Gallium nitride power device and preparation method thereof

Abstract

This application relates to the field of semiconductor technology and discloses a gallium nitride power device and its fabrication method, comprising: growing a gallium nitride epitaxial structure layer on a P+ substrate; growing a p-type gallium nitride layer on the gallium nitride epitaxial structure layer; forming a p-type gallium nitride gate region on the p-type gallium nitride layer; passivating the p-type gallium nitride gate region under a predetermined gas environment to form a functional high-resistance region, the functional high-resistance region being distributed on the sidewalls of the p-type gallium nitride gate region and on a portion of the top surface of the p-type gallium nitride gate region connected to the sidewalls; depositing a first ohmic contact metal layer and a second ohmic contact metal layer on the gallium nitride epitaxial structure layer; depositing a passivation dielectric layer on the gallium nitride epitaxial structure layer, etching the passivation dielectric layer on the p-type gallium nitride gate region, and then depositing a gate metal layer on the p-type gallium nitride gate region. This application optimizes device power consumption and improves device reliability.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a gallium nitride power device and a method for preparing the same. Background Art

[0002] In semiconductor manufacturing, gallium nitride (GaN) high electron mobility transistors (HEMTs) have gained widespread attention and practical application in power electronics and high-frequency switching applications in recent years due to the inherent advantages of the material, such as high breakdown voltage, low on-resistance, high operating frequency, and small device size. Enhancement-mode GaN HEMT devices, in particular, have become the mainstream choice due to their excellent thermal stability and long-term reliability. However, the gate leakage problem of enhancement-mode GaN HEMT devices in related technologies is particularly prominent. Gate leakage current is typically in the hundreds of microamperes to milliamperes, seriously affecting the device's driving power consumption and long-term reliability. Summary of the Invention

[0003] In view of this, the present application provides a gallium nitride power device and a preparation method thereof to solve the above-mentioned technical problems.

[0004] In a first aspect, the present invention discloses a method for preparing a gallium nitride power device, comprising:

[0005] Providing a highly doped P+ substrate, and growing a gallium nitride epitaxial structure layer on the P+ substrate;

[0006] Growing a P-type gallium nitride layer on the gallium nitride epitaxial structure layer;

[0007] After setting a gate region on the P-type gallium nitride layer, etching a non-gate region of the P-type gallium nitride layer to form a P-type gallium nitride gate region;

[0008] performing a passivation treatment on the P-type gallium nitride gate region under a set gas environment to form a functional high-resistance region, wherein the functional high-resistance region is distributed on the sidewalls of the P-type gallium nitride gate region and a portion of the top surface of the P-type gallium nitride gate region connected to the sidewalls;

[0009] Depositing a first ohmic contact metal layer and a second ohmic contact metal layer on the gallium nitride epitaxial structure layer and spaced apart from the P-type gallium nitride gate region;

[0010] A passivation dielectric layer is deposited on the gallium nitride epitaxial structure layer, and after etching the passivation dielectric layer on the P-type gallium nitride gate region, a gate metal layer is deposited on the P-type gallium nitride gate region.

[0011] In a possible example, the step of growing a gallium nitride epitaxial structure layer on the P+ substrate includes:

[0012] An aluminum nitride nucleation layer, an aluminum gallium nitride buffer layer, a gallium nitride channel layer and an aluminum gallium nitride barrier layer are sequentially grown on the P+ substrate; wherein the P-type gallium nitride gate region, the first ohmic contact metal layer, the second ohmic contact metal layer and the passivation dielectric layer are located on the aluminum gallium nitride barrier layer.

[0013] In a possible example, the first ohmic contact metal layer includes a source metal layer, and the second ohmic contact metal layer includes a drain metal layer.

[0014] In a possible example, the passivation dielectric layer covers the aluminum gallium nitride barrier layer between the first ohmic contact metal layer and the P-type gallium nitride gate region, and between the second ohmic contact metal layer and the P-type gallium nitride gate region.

[0015] In a possible example, the passivation treatment of the P-type gallium nitride gate region under a predetermined gas environment to form a functional high-resistance region includes:

[0016] forming a functional mask in a central area of ​​a top surface of the P-type gallium nitride gate region;

[0017] Passivating the P-type gallium nitride gate region with hydrogen;

[0018] The functional high resistance region is formed in the region of the P-type gallium nitride gate region not covered by the functional mask.

[0019] In a possible example, the passivation treatment of the P-type gallium nitride gate region under a predetermined gas environment to form a functional high-resistance region includes:

[0020] Passivating the P-type gallium nitride gate region with hydrogen to form an initial high-resistance region on the outer surface of the P-type gallium nitride gate region;

[0021] An initial high-resistance region at a central region of a top surface of the P-type gallium nitride gate region is etched to form the functional high-resistance region.

[0022] In a possible example, the functional high-resistance region includes a first high-resistance region and a second high-resistance region, wherein the second high-resistance region is symmetrically distributed on the sidewall of the P-type gallium nitride gate region, and the first high-resistance region is symmetrically distributed on the top surface of a portion of the P-type gallium nitride gate region connected to the sidewall.

[0023] In a possible example, the thickness of the P-type gallium nitride gate region is set to H1, the width of the P-type gallium nitride gate region is set to W1, the thickness of the first high resistance region is set to H2, and the width of the first high resistance region is set to W2, then: H2<1 / 10H1, W2<1 / 5W1.

[0024] In a possible example, after the passivation dielectric layer is deposited on the gallium nitride epitaxial structure layer, ion implantation is performed on the non-active region on the gallium nitride epitaxial structure layer to form an isolation region.

[0025] In a second aspect, the embodiments of the present application disclose a gallium nitride power device, comprising:

[0026] P+ substrate, gallium nitride epitaxial structure layer, P-type gallium nitride gate region, first ohmic contact metal layer, second ohmic contact metal layer, passivation dielectric layer and gate metal layer;

[0027] The gallium nitride epitaxial structure layer is connected to the P+ substrate, and the P-type gallium nitride gate region, the first ohmic contact metal layer, and the second ohmic contact metal layer are connected to the gallium nitride epitaxial structure layer and are arranged at intervals;

[0028] The passivation dielectric layer covers the gallium nitride epitaxial structure layer between the first ohmic contact metal layer and the P-type gallium nitride gate region, and between the second ohmic contact metal layer and the P-type gallium nitride gate region;

[0029] A functional high-resistance region is provided on the sidewall of the P-type gallium nitride gate region and on a portion of the top surface connected to the sidewall. The gate metal layer is connected to the P-type gallium nitride gate region and covers a portion of the functional high-resistance region.

[0030] In summary, compared with the prior art, the present application discloses a gallium nitride power device and a preparation method thereof, comprising growing a gallium nitride epitaxial structure layer on a P+ substrate, growing a P-type gallium nitride layer on the gallium nitride epitaxial structure layer, forming a P-type gallium nitride gate region on the P-type gallium nitride layer, passivating the P-type gallium nitride gate region under a set gas environment to form a functional high-resistance region, wherein the functional high-resistance region is distributed on the sidewalls of the P-type gallium nitride gate region and on a portion of the top surface of the P-type gallium nitride gate region connected to the sidewalls, and on the gallium nitride epitaxial structure layer. A first ohmic contact metal layer, a second ohmic contact metal layer, and a passivation dielectric layer are deposited on the structure layer. After etching the passivation dielectric layer on the P-type GaN gate region, a gate metal layer is deposited on the P-type GaN gate region. As a result, the P-type GaN gate region, based on the functional high-resistance region, can effectively block the leakage path along the sidewall and the GaN epitaxial structure layer to the source / drain, effectively suppressing gate leakage, thereby reducing leakage loss during device driving, avoiding device performance degradation caused by long-term high gate leakage, and improving the long-term reliability of the device under high-voltage and high-frequency applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 This is a flow chart of a method for preparing a gallium nitride power device according to an embodiment of the present application;

[0033] Figure 2 This is a schematic structural diagram of the first gallium nitride power device according to an embodiment of the present application;

[0034] Figure 3 This is a schematic structural diagram of a second gallium nitride power device according to an embodiment of the present application;

[0035] Figure 4 This is a schematic structural diagram of a third gallium nitride power device according to an embodiment of the present application;

[0036] Figure 5 yes Figure 4 A magnified view of point A;

[0037] Figure 6 This is a schematic structural diagram of a fourth gallium nitride power device according to an embodiment of the present application;

[0038] Figure 7 This is a schematic structural diagram of a fifth gallium nitride power device according to an embodiment of the present application;

[0039] Figure 81 is a schematic structural diagram of a sixth gallium nitride power device according to an embodiment of the present application;

[0040] Figure 9 This is a schematic structural diagram of a seventh gallium nitride power device according to an embodiment of the present application;

[0041] Figure 10 This is a schematic structural diagram of an eighth gallium nitride power device according to an embodiment of the present application;

[0042] Figure 11 This is a schematic structural diagram of the ninth gallium nitride power device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numbers in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0044] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0045] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0046] In the subsequent description, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the purpose of facilitating the description of the present application and has no specific meaning. Therefore, "module", "component" or "unit" can be used interchangeably.

[0047] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0048] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0049] Please refer to Figure 1 , and combined Figures 2 to 11 The method for preparing a gallium nitride power device according to an embodiment of the present application includes:

[0050] S101 , providing a highly doped P+ substrate 1 , and growing a gallium nitride epitaxial structure layer 2 on the P+ substrate 1 .

[0051] In a possible implementation of this application, reference Figure 2 The material for forming the P+ substrate 1 can be single crystal silicon, polycrystalline silicon, amorphous silicon or doped silicon. The material of the P+ substrate 1 can also be a SiGe substrate, a III-V group element compound substrate, a silicon carbide substrate or its stacked structure, or a silicon-on-insulator structure. It can also be a diamond substrate or other semiconductor material substrates known to those skilled in the art. For example, boron ions can be implanted into single crystal silicon to form a P-type conductive semiconductor substrate to improve the material selectivity and adaptability to the actual production environment.

[0052] In a possible implementation of the present application, a gallium nitride epitaxial structure layer 2 is grown on a P+ substrate 1, including:

[0053] An aluminum nitride nucleation layer 21 , an aluminum gallium nitride buffer layer 22 , a gallium nitride channel layer 23 and an aluminum gallium nitride barrier layer 24 are sequentially grown on the P+ substrate 1 .

[0054] It should be noted that the aluminum nitride nucleation layer 21 is located on the upper surface of the highly doped P+ substrate 1, which can provide a starting surface suitable for the epitaxial growth of gallium nitride; the aluminum gallium nitride buffer layer 22 is located on the aluminum nitride nucleation layer 21, which can be used to alleviate the lattice mismatch and stress difference between layers and improve the quality of gallium nitride crystals; the gallium nitride channel layer 23, as a key part of the gallium nitride power device, can be used for electron transport and power amplification, and the required electron flow characteristics can be achieved by setting the thickness and doping concentration; the aluminum gallium nitride barrier layer 24 is located on the gallium nitride channel layer 23, which is used to form a barrier structure for electron transport, which controls current injection and conduction when the device is in operation.

[0055] S102 , growing a P-type gallium nitride layer 30 on the gallium nitride epitaxial structure layer 2 .

[0056] In one example, the P-type GaN layer 30 can be doped with Mg (magnesium) to achieve P-type conductivity, so as to form a P-type GaN gate region of an enhancement-mode GaN power device in a subsequent process.

[0057] In one example, the P-type GaN layer 30 is formed on the AlGaN barrier layer 24 .

[0058] S103 , after setting a gate region on the P-type GaN layer 30 , etching the non-gate region of the P-type GaN layer 30 to form a P-type GaN gate region 3 .

[0059] In a possible implementation of the present application, photolithography or masking can be used to define the gate region, that is, Figure 3 The region 3a shown is then etched, and the non-gate region of the P-type GaN layer 30 is further etched. A plasma dry etching or ICP etching process may be used to ensure that the edge morphology of the P-type GaN gate region 3 is smooth.

[0060] In one example, the P-type GaN gate region 3 is formed on the AlGaN barrier layer 24 .

[0061] S104 , passivating the P-type GaN gate region 3 under a set gas environment to form a functional high-resistance region 4 , where the functional high-resistance region 4 is distributed on the sidewalls of the P-type GaN gate region 3 and a portion of the top surface of the P-type GaN gate region 3 connected to the sidewalls.

[0062] Thus, a functional high-resistance region 4 is formed on the P-type GaN gate region 3, and the functional high-resistance region 4 is used to block the leakage path from the P-type GaN gate region 3 along the sidewall and the GaN epitaxial structure layer 2 to the source / drain, thereby effectively suppressing the gate leakage of the GaN power device, reducing the leakage loss when the device is driven, avoiding the device performance degradation caused by long-term high gate leakage, and improving the long-term reliability of the GaN power device in high-voltage and high-frequency applications.

[0063] In a possible implementation of this application, reference Figure 4 、 Figure 8 and Figure 9 , passivating the P-type gallium nitride gate region 3 under a set gas environment to form a functional high-resistance region 4, including:

[0064] The P-type GaN gate region 3 is passivated with hydrogen to form an initial high-resistance region 4 a on the outer surface of the P-type GaN gate region 3 ; the initial high-resistance region 4 a in the central region 4 b of the top surface of the P-type GaN gate region 3 is etched to form a functional high-resistance region 4 .

[0065] Therefore, in a hydrogen environment, hydrogen reacts with the magnesium doping in the outer surface area of ​​the P-type GaN gate region 3, passivating the P-type characteristics of the outer surface of the P-type GaN gate region 3 to form an initial high-resistance region 4a. Then, the initial high-resistance region 4a in the central area 4b of the top surface of the P-type GaN gate region 3 is etched to form a functional high-resistance region 4 on the sidewalls of the P-type GaN gate region 3 and a portion of the top surface connected to the sidewalls, thereby achieving high resistance to the sidewalls and top surface edges of the P-type GaN gate region 3 and cutting off its leakage channel.

[0066] In a possible implementation of this application, reference Figure 10 and Figure 11 , passivating the P-type gallium nitride gate region 3 under a set gas environment to form a functional high-resistance region 4, including:

[0067] A functional mask 3 b is formed in the central area of ​​the top surface of the P-type GaN gate region 3 ; the P-type GaN gate region 3 is passivated using hydrogen; and a functional high-resistance region 4 is formed in the non-functional mask-covered area of ​​the P-type GaN gate region 3 .

[0068] Therefore, in a hydrogen environment, hydrogen can react with the magnesium doping in the non-functional mask-covered area of ​​the P-type GaN gate region 3, passivating the P-type characteristics of the P-type GaN gate region 3 and converting its local area into high resistance, that is, forming a functional high-resistance region 4 on the sidewalls of the P-type GaN gate region 3 and a portion of the top surface connected to the sidewalls, thereby achieving high resistance to the sidewalls and top surface edges of the P-type GaN gate region 3 and cutting off its leakage channel.

[0069] In a possible implementation of this application, continue to combine Figure 4 、 Figure 5 and Figure 11 The functional high-resistance region 4 includes a first high-resistance region 41 and a second high-resistance region 42. The second high-resistance region 42 is symmetrically distributed on the sidewall of the P-type gallium nitride gate region 3, and the first high-resistance region 41 is symmetrically distributed on the top surface of the portion of the P-type gallium nitride gate region 3 connected to the sidewall.

[0070] In one example, the first high resistance region 41 is opposite to the top surface of the P-type GaN gate region 3 and protrudes from the top surface of the P-type GaN gate region 3 , or the first high resistance region 41 is formed in the top surface of the P-type GaN gate region 3 .

[0071] Therefore, based on the first high-resistance region 41 and the second high-resistance region 42, high resistance is further ensured to the sidewalls and top edges of the P-type GaN gate region 3, blocking the leakage path from the P-type GaN gate region 3 along the sidewalls and the GaN epitaxial structure layer 2 to the source / drain, thereby effectively suppressing gate leakage of the GaN power device, reducing leakage loss during device driving, avoiding device performance degradation caused by long-term high gate leakage, and improving the long-term reliability of the GaN power device in high-voltage and high-frequency applications.

[0072] Furthermore, the P-type gallium nitride gate region 3 is passivated under a predetermined gas environment, including:

[0073] The P-type GaN gate region 3 is passivated using hydrogen to form an initial high-resistance region 4a on the outer surface of the P-type GaN gate region 3. The initial high-resistance region 4a in the central region 4b of the top surface of the P-type GaN gate region 3 is etched to form a first high-resistance region 41 and a second high-resistance region 42. The second high-resistance region 42 is symmetrically distributed on the sidewalls of the P-type GaN gate region 3, and the first high-resistance region 41 is symmetrically distributed on the top surface of the P-type GaN gate region 3 that is connected to the sidewalls.

[0074] On the other hand, the P-type GaN gate region 3 is passivated under a set gas environment, including: forming a functional mask 3b in the central area of ​​the top surface of the P-type GaN gate region 3; passivating the P-type GaN gate region 3 with hydrogen; and forming a first high resistance region 41 and a second high resistance region 42 in the non-functional mask-covered area of ​​the P-type GaN gate region 3, wherein the second high resistance region 42 is symmetrically distributed on the sidewalls of the P-type GaN gate region 3, and the first high resistance region 41 is symmetrically distributed on the top surface of the portion of the P-type GaN gate region 3 connected to the sidewalls.

[0075] In one example, reference Figure 5 Assuming the thickness of the P-type GaN gate region 3 to be H1, the width of the P-type GaN gate region 3 to be W1, the thickness of the first high resistance region 41 to be H2, and the width of the first high resistance region 41 to be W2, then: H2<1 / 10H1, W2<1 / 5W1.

[0076] Furthermore, the width of the second high resistance region 42 is set to W3, then: W3=H2.

[0077] That is, by defining this parameter relationship, the relative thickness and relative width of the first high-resistance region 41 are guaranteed, and the passivation dimensions of the first high-resistance region 41 and the second high-resistance region 42 are guaranteed, so that they will not excessively affect the subsequent conductivity of the P-type GaN gate region 3, and the disadvantage of excessive diffusion is also prevented, thereby ensuring the regional integrity of the P-type GaN gate region 3.

[0078] S105 , depositing a first ohmic contact metal layer 51 and a second ohmic contact metal layer 52 on the GaN epitaxial structure layer 2 , the first ohmic contact metal layer 51 and the second ohmic contact metal layer 52 being spaced apart from the P-type GaN gate region 3 .

[0079] In a possible implementation of this application, reference Figure 6 The first ohmic contact metal layer 51 includes a source metal layer, and the second ohmic contact metal layer 52 includes a drain metal layer.

[0080] Furthermore, the distance from the second ohmic contact metal layer 52 to the P-type gallium nitride gate region 3 is greater than the distance from the first ohmic contact metal layer 51 to the P-type gallium nitride gate region 3 .

[0081] The design of unequal distances between the P-type GaN gate region 3 and the source and drain metal layers prevents the P-type GaN gate region 3 from being too close to the second ohmic contact metal layer 52, thereby preventing the formation of a high electric field region between the gate and drain. This reduces the electric field strength between the two, thereby improving the device's withstand voltage performance. Furthermore, the design of a larger distance from the drain metal layer can extend the electric field diffusion path between the high voltage terminal and the P-type GaN gate region 3, avoiding excessive local electric field concentration, thereby improving the overall breakdown voltage of the device, and reducing the direct electric field coupling effect of the high drain voltage on the P-type GaN gate region 3. This reduces subsequent gate leakage current and parasitic leakage current, thereby helping to maintain low power consumption and high switching efficiency of the device. Conversely, the closer distance between the source metal layer and the P-type GaN gate region 3 facilitates rapid depletion of carriers in the channel of the GaN power device in the off state, ensuring better gate control during off-state and reducing leakage current during off-state.

[0082] Of course, in other application scenarios of the embodiment of the present application, the distances between the P-type gallium nitride gate region 3 and the source metal layer and the drain metal layer can also be set to be equal.

[0083] S106 , depositing a passivation dielectric layer 6 on the GaN epitaxial structure layer 2 , etching the passivation dielectric layer 6 on the P-type GaN gate region 3 , and then depositing a gate metal layer 7 on the P-type GaN gate region 3 .

[0084] Among them, after etching the passivation dielectric layer 6 on the P-type GaN gate region 3, the functional high-resistance region 4 on the P-type GaN gate region 3 is exposed, forming a gate window to facilitate Schottky contact between the P-type GaN gate region 3 and the gate metal layer 7.

[0085] In a possible implementation of this application, reference Figure 6 and Figure 7 The passivation dielectric layer 6 covers the aluminum gallium nitride barrier layer 24 between the first ohmic contact metal layer 51 and the P-type gallium nitride gate region 3 , and between the second ohmic contact metal layer 52 and the P-type gallium nitride gate region 3 .

[0086] Thus, the surface path between the gate region and the source / drain region of the gallium nitride power device is isolated by the passivation dielectric layer 6, thereby preventing surface conduction and the influence of external impurities.

[0087] It can be understood that the P-type GaN gate region 3 , the first ohmic contact metal layer 51 , the second ohmic contact metal layer 52 and the passivation dielectric layer 6 are located on the AlGaN barrier layer 24 .

[0088] In one example, after the passivation dielectric layer 6 is deposited on the GaN epitaxial structure layer 2 , ions are implanted into the non-active region on the GaN epitaxial structure layer 2 to form an isolation region.

[0089] Specifically, ion implantation is performed on the inactive region outside the first ohmic contact metal layer 51, the second ohmic contact metal layer 52, and the P-type gallium nitride gate region 3, thereby forming a high-resistance isolation region in the gallium nitride epitaxial structure layer 2. This enhances electrical isolation between gallium nitride power devices and the periphery of the devices, suppresses leakage current and parasitic effects, and improves device reliability.

[0090] It should be noted that the gallium nitride power device of the embodiment of the present application is an enhancement-mode GaN HEMT. The device is turned off at zero gate voltage (VGS=0), and the gate structure of the device is formed by epitaxially growing a P-type gallium nitride gate region 3 on the aluminum gallium nitride barrier layer 24 and depositing a gate metal layer 7 on the P-type gallium nitride gate region 3. This utilizes the built-in electric field of the pn junction to deplete the two-dimensional electron gas (2DEG) in the channel, thereby achieving a normally-off characteristic. The heterojunction interface between the aluminum gallium nitride barrier layer 24 and the P-type gallium nitride gate region 3 forms a high-density interface state. These interface states can serve as carrier traps or recombination centers. When a negative bias is applied to the gate, the ionization of the interface states introduces additional leakage current paths. Therefore, after designing and forming the functional high-resistance region 4, gate leakage can be effectively suppressed, thereby optimizing device power consumption and improving device reliability.

[0091] The present application also discloses a gallium nitride power device, referring to Figure 7 The gallium nitride power device is prepared by the gallium nitride power device preparation method of any of the above embodiments, including:

[0092] P+ substrate 1, gallium nitride epitaxial structure layer 2, P-type gallium nitride gate region 3, first ohmic contact metal layer 51, second ohmic contact metal layer 52, passivation dielectric layer 6 and gate metal layer 7.

[0093] In one possible implementation of the present application, the gallium nitride epitaxial structure layer 2 is connected to the P+ substrate 1, the P-type gallium nitride gate region 3, the first ohmic contact metal layer 51 and the second ohmic contact metal layer 52 are connected to the gallium nitride epitaxial structure layer 2 and are arranged at intervals; the passivation dielectric layer 6 covers the gallium nitride epitaxial structure layer 2 between the first ohmic contact metal layer 51 and the P-type gallium nitride gate region 3, and between the second ohmic contact metal layer 52 and the P-type gallium nitride gate region 3; wherein, a functional high-resistance region 4 is provided on the sidewalls of the P-type gallium nitride gate region 3 and on a portion of the top surface connected to the sidewalls, and the gate metal layer 7 is connected to the P-type gallium nitride gate region 3 and covers a portion of the functional high-resistance region 4.

[0094] In one example, the functional high-resistance region 4 includes a first high-resistance region 41 and a second high-resistance region 42 . The second high-resistance region 42 is symmetrically distributed on the sidewalls of the P-type gallium nitride gate region 3 , and the first high-resistance region 41 is symmetrically distributed on the top surface of a portion of the P-type gallium nitride gate region 3 connected to the sidewalls.

[0095] Thus, a functional high-resistance region 4 is formed on the P-type GaN gate region 3, and the functional high-resistance region 4 is used to block the leakage path from the P-type GaN gate region 3 along the sidewall and the GaN epitaxial structure layer 2 to the source / drain, thereby effectively suppressing the gate leakage of the GaN power device, reducing the leakage loss when the device is driven, avoiding the device performance degradation caused by long-term high gate leakage, and improving the long-term reliability of the GaN power device in high-voltage and high-frequency applications.

[0096] For other working principles and processes of the gallium nitride power device of this embodiment, please refer to the description of the gallium nitride power device preparation method in the above embodiment, which will not be repeated here.

[0097] The gallium nitride power device and its preparation method provided by this application are described in detail above. This article uses specific examples to illustrate the principles and implementation methods of this application. It should be noted that in this application, the descriptions of each embodiment have their own focus. For parts not detailed or recorded in one embodiment, please refer to the relevant descriptions of other embodiments.

[0098] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, all possible combinations of the various technical features in the above embodiments are not described. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, as long as there is no contradiction in the combination of these technical features, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a gallium nitride power device, characterized in that: include: Providing a highly doped P+ substrate, and growing a gallium nitride epitaxial structure layer on the P+ substrate; Growing a P-type gallium nitride layer on the gallium nitride epitaxial structure layer; After setting a gate region on the P-type gallium nitride layer, etching a non-gate region of the P-type gallium nitride layer to form a P-type gallium nitride gate region; A functional mask is formed in a central area of ​​a top surface of the P-type gallium nitride gate region, and the P-type gallium nitride gate region is passivated using hydrogen to form a functional high-resistance region in an area of ​​the P-type gallium nitride gate region not covered by the functional mask, wherein the functional high-resistance region includes a first high-resistance region and a second high-resistance region, the second high-resistance region is symmetrically distributed on a sidewall of the P-type gallium nitride gate region, and the first high-resistance region is symmetrically distributed in a portion of the top surface of the P-type gallium nitride gate region connected to the sidewall, and, assuming that the thickness of the P-type gallium nitride gate region is H1, the width of the P-type gallium nitride gate region is W1, the thickness of the first high-resistance region is H2, and the width of the first high-resistance region is W2, then: H2<1 / 10H1, W2<1 / 5W1; Depositing a first ohmic contact metal layer and a second ohmic contact metal layer on the gallium nitride epitaxial structure layer and spaced apart from the P-type gallium nitride gate region; A passivation dielectric layer is deposited on the gallium nitride epitaxial structure layer, and after etching the passivation dielectric layer on the P-type gallium nitride gate region, a gate metal layer is deposited on the P-type gallium nitride gate region.

2. The method for preparing a gallium nitride power device according to claim 1, wherein: The step of growing a gallium nitride epitaxial structure layer on the P+ substrate comprises: An aluminum nitride nucleation layer, an aluminum gallium nitride buffer layer, a gallium nitride channel layer and an aluminum gallium nitride barrier layer are sequentially grown on the P+ substrate; wherein the P-type gallium nitride gate region, the first ohmic contact metal layer, the second ohmic contact metal layer and the passivation dielectric layer are located on the aluminum gallium nitride barrier layer.

3. The method for preparing a gallium nitride power device according to claim 2, wherein: The first ohmic contact metal layer includes a source metal layer, and the second ohmic contact metal layer includes a drain metal layer.

4. The method for preparing a gallium nitride power device according to claim 2, wherein: The passivation dielectric layer covers the aluminum gallium nitride barrier layer, between the first ohmic contact metal layer and the P-type gallium nitride gate region, and between the second ohmic contact metal layer and the P-type gallium nitride gate region.

5. The method for preparing a gallium nitride power device according to claim 1, wherein: After the passivation dielectric layer is deposited on the gallium nitride epitaxial structure layer, ions are implanted into the non-active region on the gallium nitride epitaxial structure layer to form an isolation region.

6. A gallium nitride power device, characterized in that: include: P+ substrate, gallium nitride epitaxial structure layer, P-type gallium nitride gate region, first ohmic contact metal layer, second ohmic contact metal layer, passivation dielectric layer and gate metal layer; The gallium nitride epitaxial structure layer is connected to the P+ substrate, and the P-type gallium nitride gate region, the first ohmic contact metal layer, and the second ohmic contact metal layer are connected to the gallium nitride epitaxial structure layer and are arranged at intervals; The passivation dielectric layer covers the gallium nitride epitaxial structure layer between the first ohmic contact metal layer and the P-type gallium nitride gate region, and between the second ohmic contact metal layer and the P-type gallium nitride gate region; A functional high-resistance region is provided on the sidewalls of the P-type gallium nitride gate region and on a portion of the top surface connected to the sidewalls; the gate metal layer is connected to the P-type gallium nitride gate region and covers a portion of the functional high-resistance region; The functional high-resistance region includes a first high-resistance region and a second high-resistance region, the second high-resistance region is symmetrically distributed on the sidewall of the P-type gallium nitride gate region, and the first high-resistance region is symmetrically distributed in the top surface of the portion of the P-type gallium nitride gate region connected to the sidewall. Furthermore, assuming that the thickness of the P-type gallium nitride gate region is H1, the width of the P-type gallium nitride gate region is W1, the thickness of the first high-resistance region is H2, and the width of the first high-resistance region is W2, then: H2 < 1 / 10H1, W2 < 1 / 5W1.

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