Semiconductor device

Abstract

A semiconductor device includes: a first lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on a top surface of the first lower interlayer insulating layer; a first gate electrode, a second gate electrode, and a third gate electrode extending in the second horizontal direction and arranged in the first horizontal direction; a first source / drain region on the insulating pattern between the first gate electrode and the second gate electrode; a second source / drain region on the insulating pattern between the second gate electrode and the third gate electrode; a lower source / drain contact extending into the second source / drain region by vertically penetrating through the first lower interlayer insulating layer and the insulating pattern, a top surface of the lower source / drain contact being higher than a top surface of the insulating pattern; the first insulating liner layers are located on the two side walls of the lower source / drain contact; and a lower silicide layer between the second source / drain region and the lower source / drain contact.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including multi-bridge-channel field-effect transistors (MBCFETs TM ). Background Art

[0002] As a scaling technique for increasing the density of integrated circuit devices, the concept of multi-gate transistors has been proposed, in which a silicon body in the form of a fin or a nanowire is formed on a substrate and gates are formed on the surface of the silicon body.

[0003] The multi-gate transistor utilizes its three-dimensional (3D) channel, thereby allowing both easy scaling up and down. Additionally, the multi-gate transistor provides improved control of current without increasing the gate length. Furthermore, the multi-gate transistor effectively alleviates the short-channel effect (SCE), i.e., the phenomenon in which the potential of the channel region is affected by the drain voltage. Summary of the Invention

[0004] Some example embodiments of the present disclosure provide semiconductor devices capable of improving the reliability of the electrical connection between a source / drain contact disposed in a back region and a source / drain region.

[0005] However, the example embodiments of the present disclosure are not limited to those described herein. By referring to the detailed description of the present disclosure given below, the above and other example embodiments of the present disclosure will become clearer to those of ordinary skill in the art to which the present disclosure pertains.

[0006] According to an exemplary embodiment of the present disclosure, a semiconductor device may include: a first interlayer insulating layer; an insulating pattern extending along a first horizontal direction on a top surface of the first interlayer insulating layer; a first gate electrode, a second gate electrode, and a third gate electrode extending along a second horizontal direction different from the first horizontal direction on the insulating pattern, the first gate electrode, the second gate electrode, and the third gate electrode being sequentially spaced apart from each other in the first horizontal direction; a first source / drain region located between the first gate electrode and the second gate electrode on the insulating pattern; a second source / drain region located between the second gate electrode and the third gate electrode on the insulating pattern; a lower source / drain contact extending into the second source / drain region by penetrating the first interlayer insulating layer and the insulating pattern in a vertical direction, a top surface of the lower source / drain contact being higher than a top surface of the insulating pattern; a first insulating liner layer located between the lower source / drain contact and each of the first interlayer insulating layer and the insulating pattern; and a lower silicide layer located between the second source / drain region and the lower source / drain contact, the lower silicide layer being in contact with a top surface of the first insulating liner layer.

[0007] According to an exemplary embodiment of the present disclosure, a semiconductor device may include: a first interlayer insulating layer; an insulating pattern extending along a first horizontal direction on a top surface of the first interlayer insulating layer; a first plurality of nanosheets stacked on the insulating pattern at intervals in a vertical direction; a second plurality of nanosheets stacked on the insulating pattern at intervals in the vertical direction, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction; a first gate electrode extending along a second horizontal direction different from the first horizontal direction on the insulating pattern, the first gate electrode surrounding the first plurality of nanosheets; a second gate electrode extending along the second horizontal direction on the insulating pattern, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction, the second gate electrode surrounding the second plurality of nanosheets; a source / drain region located between the first gate electrode and the second gate electrode on the insulating pattern; a lower source / drain contact extending into the source / drain region by penetrating the first interlayer insulating layer and the insulating pattern in the vertical direction, a top surface of the lower source / drain contact being higher than a top surface of a lowermost nanosheet among the first plurality of nanosheets; a first insulating liner layer located between the lower source / drain contact and each of the first interlayer insulating layer and the insulating pattern; and a lower via located below the lower source / drain contact, a width of a top surface of the lower via in the first horizontal direction being greater than a width of a bottom surface of the lower source / drain contact in the first horizontal direction, at least a part of the top surface of the lower via being in contact with the first interlayer insulating layer.

[0008] According to an exemplary embodiment of the present disclosure, a semiconductor device may include: a first interlayer insulating layer; an insulating pattern extending in a first horizontal direction on a top surface of the first interlayer insulating layer; a first plurality of nanosheets stacked on the insulating pattern at intervals in a vertical direction; a second plurality of nanosheets stacked on the insulating pattern at intervals in the vertical direction, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction; a third plurality of nanosheets stacked on the insulating pattern at intervals in the vertical direction, the third plurality of nanosheets being spaced apart from the second plurality of nanosheets in the first horizontal direction; a first gate electrode extending on the insulating pattern in a second horizontal direction different from the first horizontal direction, the first gate electrode surrounding the first plurality of nanosheets; a second gate electrode extending on the insulating pattern in the second horizontal direction, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction, the second gate electrode surrounding the second plurality of nanosheets; a third gate electrode extending on the insulating pattern in the second horizontal direction, the third gate electrode being spaced apart from the second gate electrode in the first horizontal direction, the third gate electrode surrounding the third plurality of nanosheets; a first source / drain region located on the insulating pattern between the first gate electrode and the second gate electrode; a second source / drain region located on the insulating pattern between the second gate electrode and the third gate electrode; an upper interlayer insulating layer covering the first source / drain region and the second source / drain region located on the top surface of the first interlayer insulating layer; an upper source / drain contact extending into the first source / drain region by penetrating the upper interlayer insulating layer in the vertical direction; a lower source / drain contact extending into the second source / drain region by penetrating the first interlayer insulating layer and the insulating pattern in the vertical direction, a top surface of the lower source / drain contact being higher than a top surface of a lowermost nanosheet among the second plurality of nanosheets; a lower via located below the lower source / drain contact, a width of a top surface of the lower via in the first horizontal direction being greater than a width of a bottom surface of the lower source / drain contact in the first horizontal direction; a first insulating liner layer located between the lower source / drain contact and each of the first interlayer insulating layer and the insulating pattern; a second insulating liner layer contacting two sidewalls of the lower via in the first horizontal direction, the second insulating liner layer including the same material as the first insulating liner layer;and a lower silicide layer, which is located between the second source / drain region and the lower source / drain contact and is in contact with the top surface of the first insulating cushion layer;

[0009] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and according to the following description, other effects of the present disclosure will be clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become clearer by describing exemplary embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0011] Figure 1 is a layout diagram of a semiconductor device for illustrating an exemplary embodiment according to the present disclosure;

[0012] Figure 2 is Figure 1 a cross-sectional view taken along line A-A' of

[0013] Figure 3 is Figure 1 a cross-sectional view taken along line B-B' of

[0014] Figures 4 to 24 is a cross-sectional view for illustrating an intermediate step of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0015] Figure 25 is a cross-sectional view of a semiconductor device for illustrating an exemplary embodiment according to the present disclosure;

[0016] Figure 26 is a cross-sectional view of a semiconductor device for illustrating an exemplary embodiment according to the present disclosure;

[0017] Figure 27 is a cross-sectional view of a semiconductor device for illustrating an exemplary embodiment according to the present disclosure; and

[0018] Figure 28 is a cross-sectional view of a semiconductor device for illustrating an exemplary embodiment according to the present disclosure. DETAILED DESCRIPTION

[0019] Although terms such as "same", "equal", or "identical" are used in the description of the exemplary embodiments, it should be understood that there may be some inaccuracies. Therefore, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within the desired manufacturing or operating tolerance range (e.g., ±10%).

[0020] When the terms “about,” “substantially,” or “approximate” are used in this specification in relation to a numerical value, it is intended that the associated numerical value include manufacturing or operational tolerances around the stated value (e.g., ±10%). Further, when the words “about,” “substantially,” or “approximate” are used in relation to a geometric shape, it is intended that the precision of the geometric shape is not required, but rather the leeway in the shape is within the scope of the present disclosure. Further, regardless of whether a numerical value or shape is modified by “about” or “substantially,” it should be understood that these numerical values and shapes should be interpreted as including manufacturing or operational tolerances around the stated numerical value or shape (e.g., ±10%).

[0021] As used herein, a phrase such as “at least one of...” when preceding a list of elements modifies the entire list of elements and not individual elements of the list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0022] Semiconductor devices according to some example embodiments of the present disclosure are illustrated in the drawings as including a multi-bridge channel field effect transistor (MBCFET TM ) having nanosheets, but the example embodiments of the present disclosure are not limited thereto. In other example embodiments, the semiconductor device may include a fin field effect transistor (FinFET), a tunnel field effect transistor (FET), or a three-dimensional (3D) transistor having a fin-shaped patterned channel region. Further, in still other embodiments, the semiconductor device may include a bipolar junction transistor or a laterally diffused metal oxide semiconductor (LDMOS) transistor.

[0023] Hereinafter, reference will be made to Figures 1 to 3 describe semiconductor devices according to example embodiments of the present disclosure.

[0024] Figure 1 is a layout diagram for illustrating a semiconductor device according to an example embodiment of the present disclosure. Figure 2 is along Figure 1 The cross-sectional view taken along line A-A' of. Figure 3 is along Figure 1 The cross-sectional view taken along line B-B' of.

[0025] Reference Figures 1 to 3, a semiconductor device according to an exemplary embodiment of the present disclosure includes a first interlayer insulating layer 100, an insulating pattern 101, a first sacrificial pattern 103, a field insulating layer 105, a first plurality of nanosheets NW1, a second plurality of nanosheets NW2, a third plurality of nanosheets NW3, a first gate electrode G1, a second gate electrode G2, and a third gate electrode G3, a first gate spacer 111, a second gate spacer 112, and a third gate spacer 113, a first gate insulating layer 121, a second gate insulating layer 122, and a third gate insulating layer 123, a first capping pattern 131, a second capping pattern 132, and a third capping pattern 133, a first source / drain region SD1 and a second source / drain region SD2, a first etch stop layer 150, a first upper interlayer insulating layer 155, a gate contact CB, an upper source / drain contact UCA, a lower source / drain contact BCA, an upper silicide layer USL, a lower silicide layer BSL, a lower via BV, a first insulating liner 161 and a second insulating liner 162, a second etch stop layer 170, a second upper interlayer insulating layer 175, and a first via V1 and a second via V2.

[0026] The first interlayer insulating layer 100 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The low-k material may be, for example, tetraethyl orthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), tetramethoxysilane (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), Toshiba silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but the exemplary embodiments of the present disclosure are not limited thereto.

[0027] A first horizontal direction DR1 and a second horizontal direction DR2 may be defined as directions parallel to the top surface of the first interlayer insulating layer 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. A vertical direction DR3 is defined as a direction perpendicular to both the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 is defined as a direction perpendicular to the top surface of the first interlayer insulating layer 100.

[0028] The insulating pattern 101 may extend along a first horizontal direction DR1 on a top surface of the first interlayer insulating layer 100. The insulating pattern 101 may protrude from the top surface of the first interlayer insulating layer 100 in a vertical direction DR3. The insulating pattern 101 may include an insulating material. For example, the insulating pattern 101 may include the same material as the first interlayer insulating layer 100.

[0029] The field insulating layer 105 may be disposed on the top surface of the first interlayer insulating layer 100. The field insulating layer 105 may surround sidewalls of the insulating pattern 101. For example, a top surface of the insulating pattern 101 may protrude beyond a top surface of the field insulating layer 105 in the vertical direction DR3, but example embodiments of the present disclosure are not limited thereto. In other example embodiments, the top surface of the insulating pattern 101 may be formed in the same plane as the top surface of the field insulating layer 105. The field insulating layer 105 may include, for example, an oxide film, a nitride film, a oxynitride film, or a combination thereof.

[0030] The first plurality of nanosheets NW1 may be disposed on the insulating pattern 101. The first plurality of nanosheets NW1 may be disposed at an intersection of the insulating pattern 101 and the first gate electrode G1. The second plurality of nanosheets NW2 may be disposed on the insulating pattern 101. The second plurality of nanosheets NW2 may be disposed at an intersection of the insulating pattern 101 and the second gate electrode G2. The second plurality of nanosheets NW2 may be spaced apart from the first plurality of nanosheets NW1 in the first horizontal direction DR1. The third plurality of nanosheets NW3 may be disposed on the insulating pattern 101. The third plurality of nanosheets NW3 may be disposed at an intersection of the insulating pattern 101 and the third gate electrode G3. The third plurality of nanosheets NW3 may be spaced apart from the second plurality of nanosheets NW2 in the first horizontal direction DR1.

[0031] Each of the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 may include a stack of a plurality of nanosheets vertically spaced apart in the vertical direction DR3. In Figure 2 and Figure 3In [the figure], the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 are illustrated as stacks including three nanosheets stacked in the vertical direction DR3 and separated from each other, but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, each of the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 may include a stack of four or more nanosheets stacked in the vertical direction DR3 and separated from each other. For example, the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 may include silicon (Si), but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 may include silicon germanium (SiGe).

[0032] The first gate electrode G1 may extend along the second horizontal direction DR2 above the insulating pattern 101 and the field insulating layer 105. The first gate electrode G1 may surround the first plurality of nanosheets NW1. The second gate electrode G2 may extend along the second horizontal direction DR2 above the insulating pattern 101 and the field insulating layer 105. The second gate electrode G2 may surround the second plurality of nanosheets NW2. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The third gate electrode G3 may extend along the second horizontal direction DR2 above the insulating pattern 101 and the field insulating layer 105. The third gate electrode G3 may surround the third plurality of nanosheets NW3. The third gate electrode G3 may be spaced apart from the second gate electrode G2 in the first horizontal direction DR1.

[0033] The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof. The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may include a conductive metal oxide or a conductive metal nitride oxide, and may also include an oxidized form of any of the foregoing materials.

[0034] The first gate spacer 111 may extend in a second horizontal direction DR2 along two sidewalls of the first gate electrode G1 on the top surface of the topmost nanosheet among the first plurality of nanosheets NW1 and on the field insulating layer 105. The second gate spacer 112 may extend in the second horizontal direction DR2 along two sidewalls of the second gate electrode G2 on the top surface of the topmost nanosheet among the second plurality of nanosheets NW2 and on the field insulating layer 105. The third gate spacer 113 may extend in the second horizontal direction DR2 along two sidewalls of the third gate electrode G3 on the top surface of the topmost nanosheet among the third plurality of nanosheets NW3 and on the field insulating layer 105.

[0035] The first gate spacer 111, the second gate spacer 112, and the third gate spacer 113 may include at least one of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof, but the exemplary embodiments of the present disclosure are not limited thereto.

[0036] The first source / drain region SD1 may be disposed on both sides of the first gate electrode G1 on the insulating pattern 101. For example, the first source / drain region SD1 may be disposed on the insulating pattern 101 between the first gate electrode G1 and the second gate electrode G2. The second source / drain region SD2 may be disposed on both sides of the third gate electrode G3 on the insulating pattern 101. For example, the second source / drain region SD2 may be disposed on the insulating pattern 101 between the second gate electrode G2 and the third gate electrode G3.

[0037] Each of the first source / drain region SD1 and the second source / drain region SD2 may be in contact with the insulating pattern 101. The first source / drain region SD1 may be in contact with sidewalls of the first plurality of nanosheets NW1 and sidewalls of the second plurality of nanosheets NW2 in a first horizontal direction DR1. The second source / drain region SD2 may be in contact with sidewalls of the second plurality of nanosheets NW2 and sidewalls of the third plurality of nanosheets NW3 in the first horizontal direction DR1. For example, top surfaces of the first source / drain region SD1 and the second source / drain region SD2 may be formed to be higher than the top surface of the topmost nanosheet among the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3.

[0038] For example, each of the first source / drain regions SD1 and the second source / drain regions SD2 may include a first layer 141 and a second layer 142. For example, the first layer 141 may be in contact with two sidewalls of each of the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 in a first horizontal direction DR1 and a top surface of the insulating pattern 101. The second layer 142 may be disposed on the first layer 141. For example, the first layer 141 and the second layer 142 may include SiGe. For example, a concentration of germanium (Ge) in the second layer 142 may be greater than a concentration of Ge in the first layer 141.

[0039] The first sacrificial pattern 103 may be disposed under the first source / drain region SD1. The first sacrificial pattern 103 may be in contact with a bottom surface of the first source / drain region SD1. For example, the first sacrificial pattern 103 may be in contact with the first layer 141. The first sacrificial pattern 103 may extend through the insulating pattern 101 in a vertical direction DR3 into the first interlayer insulating layer 100. For example, two sidewalls of the first sacrificial pattern 103 in the first horizontal direction DR1 may be in contact with the insulating pattern 101 and the first interlayer insulating layer 100. Additionally, a bottom surface of the first sacrificial pattern 103 may be in contact with the first interlayer insulating layer 100.

[0040] The first sacrificial pattern 103 may include a material different from each of the first interlayer insulating layer 100 and the insulating pattern 101. For example, the first sacrificial pattern 103 may include SiGe. A concentration of Ge in the first sacrificial pattern 103 may be greater than a concentration of Ge in the first layer 141. In addition, a concentration of Ge in the first sacrificial pattern 103 may be less than a concentration of Ge in the second layer 142. For example, a width of the first sacrificial pattern 103 in the first horizontal direction DR1 may be less than a width of the first source / drain region SD1 in the first horizontal direction DR1.

[0041] The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the insulating pattern 101. The first gate insulating layer 121 may also be disposed between the first gate electrode G1 and the field insulating layer 105. The first gate insulating layer 121 may also be disposed between the first gate electrode G1 and the first gate spacer 111. The first gate insulating layer 121 may also be disposed between the first gate electrode G1 and the first plurality of nanosheets NW1. The first gate insulating layer 121 may also be disposed between the first gate electrode G1 and the first source / drain region SD1.

[0042] The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the insulating pattern 101. The second gate insulating layer 122 may also be disposed between the second gate electrode G2 and the field insulating layer 105. The second gate insulating layer 122 may also be disposed between the second gate electrode G2 and the second gate spacer 112. The second gate insulating layer 122 may also be disposed between the second gate electrode G2 and the second plurality of nanosheets NW2. The second gate insulating layer 122 may also be disposed between the second gate electrode G2 and each of the first source / drain region SD1 and the second source / drain region SD2.

[0043] The third gate insulating layer 123 may be disposed between the third gate electrode G3 and the insulating pattern 101. The third gate insulating layer 123 may also be disposed between the third gate electrode G3 and the field insulating layer 105. The third gate insulating layer 123 may also be disposed between the third gate electrode G3 and the third gate spacer 113. The third gate insulating layer 123 may also be disposed between the third gate electrode G3 and the third plurality of nanosheets NW3. The third gate insulating layer 123 may also be disposed between the third gate electrode G3 and the second source / drain region SD2.

[0044] Each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may be in contact with the insulating pattern 101. For example, the first gate insulating layer 121 and the second gate insulating layer 122 may be in contact with the first source / drain region SD1. Additionally, the second gate insulating layer 122 and the third gate insulating layer 123 may be in contact with the second source / drain region SD2. However, the present disclosure is not limited thereto. In some exemplary embodiments, inner spacers may be disposed between the first source / drain region SD1 and the first gate insulating layer 121 and the second gate insulating layer 122, and between the second source / drain region SD2 and the second gate insulating layer 122 and the third gate insulating layer 123. The inner spacers may include, for example, at least one of SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof.

[0045] Each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a larger dielectric constant than silicon oxide. The high-k material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0046] A semiconductor device according to some example embodiments of the present disclosure may include a negative capacitance (NC) FET using a negative capacitor. For example, each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0047] The ferroelectric material film may have a negative capacitance, while the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and have a positive capacitance, the total capacitance of the two or more capacitors may be lower than the capacitance of each of the two or more capacitors. In contrast, if at least one of the two or more capacitors has a negative capacitance, the total capacitance of the two or more capacitors may have a positive value and may be greater than the absolute value of the capacitance of each of the two or more capacitors.

[0048] If a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series, the total capacitance of the ferroelectric material film and the paraelectric material film may increase. Accordingly, the subthreshold swing (SS) of a transistor having a ferroelectric material film at room temperature may be less than about 60 mV / decade.

[0049] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

[0050] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), Si, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), Ge, scandium (Sc), strontium (Sr), or Sn. The type of dopant may vary depending on the type of material of the ferroelectric material film.

[0051] If the ferroelectric material film includes hafnium oxide, the dopant of the ferroelectric material film may include, for example, at least one of Gd, Si, Zr, Al, or Y.

[0052] If the dopant of the ferroelectric material film is Al, the ferroelectric material film may include about 3 atomic percent (at%) to about 8 at% of Al. Here, the ratio of the dopant in the ferroelectric material film may refer to the ratio of the amount of Al in the ferroelectric material film to the sum of the amounts of Hf and Al.

[0053] If the dopant of the ferroelectric material film is Si, the ferroelectric material film may include from about 2 at% to about 10 at% of Si. If the dopant of the ferroelectric material film is Y, the ferroelectric material film may include from about 2 at% to about 10 at% of Y. If the dopant of the ferroelectric material film is Gd, the ferroelectric material film may include from about 1 at% to about 7 at% of Gd. If the dopant of the ferroelectric material film is Zr, the ferroelectric material film may include from about 50 at% to about 80 at% of Zr.

[0054] The paraelectric material film may have paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide or a high-k metal oxide. The high-k metal oxide may include at least one of, for example, hafnium oxide, zirconium oxide, or aluminum oxide, but the example embodiments of the present disclosure are not limited thereto.

[0055] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide, the hafnium oxide included in the ferroelectric material film may have a crystal structure different from that of the hafnium oxide included in the paraelectric material film.

[0056] The ferroelectric material film may be thick enough to exhibit ferroelectric properties. The ferroelectric material film may have a thickness of, for example, from about 0.5 nm to about 10 nm, but the example embodiments of the present disclosure are not limited thereto. The critical thickness at which ferroelectric properties can be exhibited may vary depending on the type of ferroelectric material, and thus, the thickness of the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0057] For example, each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include a ferroelectric material film. In another example, each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include a plurality of ferroelectric material films spaced apart from each other. Each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include a stack of a plurality of ferroelectric material films and a plurality of paraelectric material films stacked alternately with the ferroelectric material films.

[0058] The first etch stop layer 150 may be disposed on sidewalls of each of the first gate spacer 111, the second gate spacer 112, and the third gate spacer 113 in a first horizontal direction DR1. The first etch stop layer 150 may also be disposed on top surfaces of the first source / drain region SD1 and the second source / drain region SD2. Although not illustrated, the first etch stop layer 150 may be disposed on sidewalls of each of the first source / drain region SD1 and the second source / drain region SD2 in a second horizontal direction DR2. For example, the first etch stop layer 150 may be conformally formed. The first etch stop layer 150 may include at least one of, for example, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

[0059] The first capping pattern 131 may extend along the second horizontal direction DR2 above each of the first gate spacer 111, the first gate insulating layer 121, and the first gate electrode G1. The second capping pattern 132 may extend along the second horizontal direction DR2 above each of the second gate spacer 112, the second gate insulating layer 122, and the second gate electrode G2. The third capping pattern 133 may extend along the second horizontal direction DR2 above each of the third gate spacer 113, the third gate insulating layer 123, and the third gate electrode G3.

[0060] For example, bottom surfaces of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133 may be in contact with the first etch stop layer 150, but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, sidewalls of each of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133 may also be in contact with the first etch stop layer 150. The first capping pattern 131, the second capping pattern 132, and the third capping pattern 133 may include at least one of, for example, SiN, SiON, SiO2, SiCN, SiOCN, or a combination thereof, but the exemplary embodiments of the present disclosure are not limited thereto.

[0061] The first interlayer insulating layer 155 may be disposed on the first etch stop layer 150. The first interlayer insulating layer 155 may be disposed on sidewalls of each of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133. The first interlayer insulating layer 155 may cover each of the first source / drain region SD1 and the second source / drain region SD2 on the field insulating layer 105. For example, a top surface of the first interlayer insulating layer 155 may be formed in a same plane as top surfaces of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133. The first interlayer insulating layer 155 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

[0062] The upper source / drain contact UCA may be disposed between the first gate electrode G1 and the second gate electrode G2. The upper source / drain contact UCA may be disposed above the first source / drain region SD1. The upper source / drain contact UCA may extend into the first source / drain region SD1 by penetrating the first interlayer insulating layer 155 and the first etch stop layer 150 in the vertical direction DR3. The upper source / drain contact UCA may be electrically connected to the first source / drain region SD1. In Figure 2 the upper source / drain contact UCA is illustrated as being formed as a single layer, but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, the upper source / drain contact UCA may be formed as a multi-layer.

[0063] For example, the top surface of the upper source / drain contact UCA may be formed on the same plane as the top surface of the first interlayer insulating layer 155, but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, the top surface of the upper source / drain contact UCA may be formed to be higher than the top surface of the first interlayer insulating layer 155. The upper source / drain contact UCA may include a conductive material.

[0064] The upper silicide layer USL may be disposed between the upper source / drain contact UCA and the first source / drain region SD1. The upper silicide layer USL may be disposed along the boundary between the upper source / drain contact UCA and the first source / drain region SD1. For example, the upper silicide layer USL may include a metal silicide material.

[0065] The gate contact CB may be located above the second gate electrode G2. The gate contact CB may be connected to the second gate electrode G2 by penetrating the second capping pattern 132 in the vertical direction DR3. In Figure 3 the gate contact CB is illustrated as being formed as a single layer, but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, the gate contact CB may be formed as a multi-layer. For example, the top surface of the gate contact CB may be formed on the same plane as the top surfaces of the upper source / drain contact UCA and the first interlayer insulating layer 155, but the exemplary embodiments of the present disclosure are not limited thereto. The gate contact CB may include a conductive material.

[0066] The lower source / drain contact BCA may be disposed between the second gate electrode G2 and the third gate electrode G3. The lower source / drain contact BCA may be disposed below the second source / drain region SD2. The lower source / drain contact BCA may extend into the second source / drain region SD2 by penetrating a part of the first interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3. The lower source / drain contact BCA may be electrically connected to the second source / drain region SD2. For example, the lower source / drain contact BCA may be formed as a single layer, but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, the lower source / drain contact BCA may be formed as a multi-layer.

[0067] For example, the top surface of the lower source / drain contact BCA may be formed to be higher than the top surface of the insulating pattern 101. Additionally, the top surface of the lower source / drain contact BCA may be formed to be higher than the top surface of the lowermost nanosheet among the second plurality of nanosheets NW2 and the third plurality of nanosheets NW3. The bottom surface of the lower source / drain contact BCA may be formed in the same plane as the bottom surface of the first sacrificial pattern 103.

[0068] For example, the width of the lower source / drain contact BCA in the first horizontal direction DR1 may be smaller than the width of the second source / drain region SD2 in the first horizontal direction DR1. The lower source / drain contact BCA may be spaced apart from each of the insulating pattern 101 and the first interlayer insulating layer 100 in the first horizontal direction DR1. That is, the lower source / drain contact BCA does not contact the insulating pattern 101 and / or the first interlayer insulating layer 100. The lower source / drain contact BCA may include a conductive material.

[0069] The lower silicide layer BSL may be disposed between the lower source / drain contact BCA and the second source / drain region SD2. The lower silicide layer BSL may be disposed along the boundary between the lower source / drain contact BCA and the second source / drain region SD2. The lower silicide layer BSL may include, for example, a metal silicide material.

[0070] The lower via BV can be disposed below the lower source / drain contact BCA. For example, the lower via BV can be disposed within the first interlayer insulating layer 100. The bottom surface of the lower via BV can be formed in the same plane as the bottom surface of the first interlayer insulating layer 100, but the exemplary embodiments of the present disclosure are not limited thereto. For example, the width of the top surface of the lower via BV in the first horizontal direction DR1 can be greater than the width of the bottom surface of the lower source / drain contact BCA in the first horizontal direction DR1. Similarly, the width of the top surface of the lower via BV in the second horizontal direction DR2 can be greater than the width of the bottom surface of the lower source / drain contact BCA in the second horizontal direction DR2. For example, the width of the lower via BV in the first horizontal direction DR1 can gradually decrease closer to the bottom surface of the lower source / drain contact BCA.

[0071] At least a portion of the top surface of the lower via BV can be in contact with the first interlayer insulating layer 100. For example, at least a portion of the top surface of the lower via BV on both sides of the lower source / drain contact BCA in the first horizontal direction DR1 can be in contact with the first interlayer insulating layer 100. For example, the lower via BV can be integrally formed with the lower source / drain contact BCA. That is, the lower via BV and the lower source / drain contact BCA can be formed by the same manufacturing process. The lower via BV can include a conductive material. The lower via BV can include the same material as the lower source / drain contact BCA.

[0072] The first insulating cushion layer 161 can be disposed between the lower source / drain contact BCA and each of the first interlayer insulating layer 100 and the insulating pattern 101. For example, the top surface of the first insulating cushion layer 161 can be formed to be lower than the top surface of the lower source / drain contact BCA. For example, the bottom surface of the first insulating cushion layer 161 can be formed in the same plane as the bottom surface of the lower source / drain contact BCA. For example, the first insulating cushion layer 161 can be in contact with the first interlayer insulating layer 100, the insulating pattern 101, and the lower source / drain contact BCA. For example, the bottom surface of the first insulating cushion layer 161 can be in contact with the top surface of the lower via BV. For example, the top surface of the first insulating cushion layer 161 can be in contact with the lower silicide layer BSL. For example, the first insulating cushion layer 161 can be conformally formed.

[0073] The second insulating liner layer 162 may be disposed on the sidewalls of the lower via BV. The second insulating liner layer 162 may be disposed between the lower via BV and the first interlayer insulating layer 100. For example, the top surface of the second insulating liner layer 162 may be formed in the same plane as the top surface of the lower via BV. Similarly, the bottom surface of the second insulating liner layer 162 may be formed in the same plane as the bottom surface of the lower via BV. For example, the second insulating liner layer 162 may be in contact with the sidewalls of the lower via BV and the first interlayer insulating layer 100. For example, the top surface of the second insulating liner layer 162 may be in contact with the first interlayer insulating layer 100.

[0074] For example, the first insulating liner layer 161 and the second insulating liner layer 162 may include the same material. The first insulating liner layer 161 and the second insulating liner layer 162 may include a material different from the first interlayer insulating layer 100 and the insulating pattern 101. The first insulating liner layer 161 and the second insulating liner layer 162 may include an insulating material. For example, the first insulating liner layer 161 and the second insulating liner layer 162 may include at least one of SiN, SiCN, SiON, or SiOCN.

[0075] The second etch stop layer 170 may be disposed on the top surfaces of the upper source / drain contact UCA, the first capping pattern 131, the second capping pattern 132, the third capping pattern 133, and the first upper interlayer insulating layer 155. In Figure 2 and Figure 3 the second etch stop layer 170 is illustrated as being formed as a single layer, but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, the second etch stop layer 170 may be formed as multiple layers. The second etch stop layer 170 may include at least one of, for example, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The second upper interlayer insulating layer 175 may be disposed on the second etch stop layer 170. The second upper interlayer insulating layer 175 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

[0076] The first via V1 may be connected to the upper source / drain contact UCA by penetrating the second upper interlayer insulating layer 175 and the second etch stop layer 170 in the vertical direction DR3. Similarly, the second via V2 may be connected to the gate contact CB by penetrating the second upper interlayer insulating layer 175 and the second etch stop layer 170 in the vertical direction DR3. In Figure 2 and Figure 3 the first via V1 and the second via V2 are illustrated as being formed as a single layer, but the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, the first via V1 and the second via V2 may be formed as multiple layers. The first via V1 and the second via V2 may include a conductive material.

[0077] In the following, reference will be made to Figures 2 to 24 describe a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0078] Figures 4 to 24 is a cross-sectional view for illustrating an intermediate step of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0079] Reference Figure 4 and Figure 5 , a substrate 10 may be provided. The substrate 10 may be a Si substrate or a silicon-on-insulator (SOI) substrate. In some exemplary embodiments, the substrate 10 may include SiGe, silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the exemplary embodiments of the present disclosure are not limited thereto.

[0080] Thereafter, a stacked structure 20 may be formed on the top surface of the substrate 10. The stacked structure 20 may include a first semiconductor layer 21 and a second semiconductor layer 22, the first semiconductor layer 21 and the second semiconductor layer 22 being stacked on the top surface of the substrate 10 and the second semiconductor layer 22 being alternating with the first semiconductor layer 21. For example, the first semiconductor layer 21 may be formed at the bottom of the stacked structure 20, and the second semiconductor layer 22 may be formed at the top of the stacked structure 20. However, the exemplary embodiments of the present disclosure are not limited thereto. In some exemplary embodiments, the first semiconductor layer 21 may be formed at the top of the stacked structure 20. The first semiconductor layer 21 may include, for example, SiGe. The second semiconductor layer 22 may include, for example, Si.

[0081] Thereafter, a portion of the stacked structure 20 may be etched. During the etching of the stacked structure 20, a portion of the substrate 10 may also be etched. Through this etching process, an active pattern 11 may be defined on the top surface of the substrate 10 below the stacked structure 20. The active pattern 11 may protrude from the top surface of the substrate 10 in the vertical direction DR3. The active pattern 11 may extend in a first horizontal direction DR1.

[0082] Thereafter, a field insulating layer 105 may be formed on the top surface of the substrate 10. The field insulating layer 105 may surround the sidewalls of the active pattern 11. For example, the top surface of the active pattern 11 may be formed to be higher than the top surface of the field insulating layer 105. Thereafter, a pad oxide layer 30 may be formed to cover the top surface of the field insulating layer 105, the exposed sidewalls of the active pattern 11, and the sidewalls and the top surface of the stacked structure 20. For example, the pad oxide layer 30 may be conformally formed. The pad oxide layer 30 may include, for example, SiO2.

[0083] Reference Figure 6 and Figure 7, on the stacked structure 20 and the field insulating layer 105, a first dummy gate DG1, a second dummy gate DG2, and a third dummy gate DG3 extending in the second horizontal direction DR2, and a first dummy capping pattern DC1, a second dummy capping pattern DC2, and a third dummy capping pattern DC3 also extending in the second horizontal direction DR2 can be formed on the pad oxide layer 30. For example, the second dummy gate DG2 can be spaced apart from the first dummy gate DG1 in the first horizontal direction DR1, and the third dummy gate DG3 can be spaced apart from the second dummy gate DG2 in the first horizontal direction DR1. The first dummy capping pattern DC1 can be disposed on the first dummy gate DG1. The second dummy capping pattern DC2 can be disposed on the second dummy gate DG2. The third dummy capping pattern DC3 can be disposed on the third dummy gate DG3.

[0084] During the formation of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, and the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3, the entire pad oxide layer 30 can be removed except for portions overlapping with the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 in the vertical direction DR3.

[0085] Thereafter, a spacer material layer SM can be formed to cover the sidewalls and top surfaces of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3, the exposed sidewalls and top surface of the stacked structure 20, and the top surface of the field insulating layer 105. For example, the spacer material layer SM can be conformally formed. The spacer material layer SM can include, for example, SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, or a combination thereof.

[0086] Reference Figure 8 , the stacked structure 20 can be etched by using the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, and the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3 as masks to form a first source / drain trench ST1 and a second source / drain trench ST2. The first source / drain trench ST1 can be formed between the first dummy gate DG1 and the second dummy gate DG2. The second source / drain trench ST2 can be formed between the second dummy gate DG2 and the third dummy gate DG3. Figure 6

[0087] ​In addition, a first sacrificial pattern trench 103T may be formed under the first source / drain trench ST1, and a second sacrificial pattern trench 104T may be formed under the second source / drain trench ST2. The first sacrificial pattern trench 103T and the second sacrificial pattern trench 104T may be formed in each of the active pattern 11 and the substrate 10. The substrate 10 may be exposed at the bottoms of the first sacrificial pattern trench 103T and the second sacrificial pattern trench 104T.

[0088] During the formation of the first source / drain trench ST1 and the second source / drain trench ST2, the spacer material layer SM formed on the top surfaces of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3, and portions of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3 may be removed. The remaining spacer material layer SM on the sidewalls of each of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, and on the sidewalls of each of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3 may be defined as a first gate spacer 111, a second gate spacer 112, and a third gate spacer 113.

[0089] For example, after the formation of the first source / drain trench ST1 and the second source / drain trench ST2, the remaining second semiconductor layer 22 under the first dummy gate DG1 on the active pattern 11 may be defined as a first plurality of nanosheets NW1. Similarly, the remaining second semiconductor layer 22 under the second dummy gate DG2 on the active pattern 11 may be defined as a second plurality of nanosheets NW2, and the remaining second semiconductor layer 22 under the third dummy gate DG3 on the active pattern 11 may be defined as a third plurality of nanosheets NW3.

[0090] Reference Figure 9 may be made to form a first sacrificial pattern 103 in the first sacrificial pattern trench 103T, and a second sacrificial pattern 104 may be formed in the second sacrificial pattern trench 104T. The top surfaces of the first sacrificial pattern 103 and the second sacrificial pattern 104 may be formed to be lower than the bottom surface of the lowermost first semiconductor layer 21. The first sacrificial pattern 103 and the second sacrificial pattern 104 may include, for example, SiGe. Thereafter, a first source / drain region SD1 may be formed in the first source / drain trench ST1, and a second source / drain region SD2 may be formed in the second source / drain trench ST2. For example, the bottom surface of the first source / drain region SD1 may be in contact with the top surface of the first sacrificial pattern 103, and the bottom surface of the second source / drain region SD2 may be in contact with the top surface of the second sacrificial pattern 104.

[0091] Each of the first source / drain region SD1 and the second source / drain region SD2 may include a first layer 141 and a second layer 142. For example, the first layer 141 may be formed along the sidewalls and the bottom surfaces of each of the first source / drain trench ST1 and the second source / drain trench ST2. The first layer 141 may be in contact with the top surfaces of the first sacrificial pattern 103 and the second sacrificial pattern 104. For example, the second layer 142 may be formed on the first layer 141 to fill the remaining portions of each of the first source / drain trench ST1 and the second source / drain trench ST2.

[0092] For example, the first layer 141 and the second layer 142 may include SiGe. The concentration of Ge in the first sacrificial pattern 103 and the second sacrificial pattern 104 may be greater than the concentration of Ge in the first layer 141. In addition, the concentration of Ge in the second layer 142 may be greater than the concentration of Ge in the first sacrificial pattern 103 and the second sacrificial pattern 104.

[0093] Reference Figure 10 , a first etch stop layer 150 may be formed on the exposed top surface of the field insulating layer 105, the exposed sidewalls of each of the first gate spacer 111, the second gate spacer 112, and the third gate spacer 113, the exposed top surfaces of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3, and the exposed surfaces of the first source / drain region SD1 and the second source / drain region SD2. Thereafter, a first upper interlayer insulating layer 155 may be formed on the first etch stop layer 150. Thereafter, the top surfaces of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 may be exposed by a planarization process.

[0094] Reference Figure 11 and Figure 12 , the first dummy gate DG1, the second dummy gate DG2, the third dummy gate DG3, the pad oxide layer 30, and the first semiconductor layer 21 may each be etched. The etched portions of the first dummy gate DG1, the pad oxide layer 30, and the first semiconductor layer 21 may be defined as the first gate trench GT1. Similarly, the etched portions of the second dummy gate DG2, the pad oxide layer 30, and the first semiconductor layer 21 may be defined as the second gate trench GT2. The etched portions of the third dummy gate DG3, the pad oxide layer 30, and the first semiconductor layer 21 may be defined as the third gate trench GT3.

[0095] Reference Figure 13 and Figure 14, a first gate insulating layer 121, a first gate electrode G1, and a first capping pattern 131 may be sequentially formed in the first gate trench GT1. Similarly, a second gate insulating layer 122, a second gate electrode G2, and a second capping pattern 132 may be sequentially formed in the second gate trench GT2, and a third gate insulating layer 123, a third gate electrode G3, and a third capping pattern 133 may be sequentially formed in the third gate trench GT3.

[0096] Reference Figure 15 and Figure 16 , an upper source / drain contact UCA may be formed on the first source / drain region SD1. The upper source / drain contact UCA may extend into the first source / drain region SD1 by penetrating the first interlayer insulating layer 155 and the first etch stop layer 150 in the vertical direction DR3. Additionally, an upper silicide layer USL may be formed between the first source / drain region SD1 and the upper source / drain contact UCA. Further, a gate contact CB may be formed that is connected to the second gate electrode G2 by penetrating the second capping pattern 132 in the vertical direction DR3.

[0097] Thereafter, a second etch stop layer 170 and a second interlayer insulating layer 175 may be sequentially formed on the top surfaces of the first interlayer insulating layer 155, the first capping pattern 131, the second capping pattern 132, the third capping pattern 133, and the upper source / drain contact UCA. Thereafter, a first via V1 may be formed that is connected to the upper source / drain contact UCA by penetrating the second etch stop layer 170 and the second interlayer insulating layer 175 in the vertical direction DR3. Similarly, a second via V2 may be formed that is connected to the gate contact CB by penetrating the second etch stop layer 170 and the second interlayer insulating layer 175 in the vertical direction DR3.

[0098] Reference Figure 17 and Figure 18 , portions of the substrate 10 and the active pattern 11 may be etched. Accordingly, portions of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123, portions of the first source / drain region SD1 and the second source / drain region SD2, portions of the field insulating layer 105, and portions of the first sacrificial pattern 103 and the second sacrificial pattern 104 may be exposed.

[0099] Reference Figure 19 and Figure 20, the first interlayer insulating layer 100 and the insulating pattern 101 may be formed in the portions where the substrate 10 and the active pattern 11 have been etched. For example, the insulating pattern 101 may be formed in the portion where the active pattern 11 has been etched. The insulating pattern 101 may be in contact with the first gate insulating layer 121, the second gate insulating layer 122, the third gate insulating layer 123, the first source / drain region SD1, the second source / drain region SD2, the field insulating layer 105, and the first sacrificial pattern 103 and the second sacrificial pattern 104. The insulating pattern 101 may surround a portion of the sidewalls of each of the first sacrificial pattern 103 and the second sacrificial pattern 104.

[0100] Additionally, the first interlayer insulating layer 100 may be formed in the portion where the substrate 10 has been etched. The first interlayer insulating layer 100 may be in contact with the field insulating layer 105 and each of the first sacrificial pattern 103 and the second sacrificial pattern 104. The first interlayer insulating layer 100 may surround a portion of the sidewalls of each of the first sacrificial pattern 103 and the second sacrificial pattern 104. The first interlayer insulating layer 100 may cover the bottom surfaces of the first sacrificial pattern 103 and the second sacrificial pattern 104.

[0101] Reference Figure 21 , the first trench T1 may be formed on the bottom surface of the second sacrificial pattern 104. For example, through the first trench T1, the bottom surface of the second sacrificial pattern 104 may be exposed. For example, the width of the top surface of the first trench T1 in the first horizontal direction DR1 may be greater than the width of the bottom surface of the second sacrificial pattern 104 in the first horizontal direction DR1.

[0102] Reference Figure 22 , the second sacrificial pattern 104 may be wet-etched through the first trench T1. The etched portion of the second sacrificial pattern 104 may be defined as the second trench T2. Through the second trench T2, the first layer 141 may be exposed. Since the concentration of Ge in the second sacrificial pattern 104 is greater than the concentration of Ge in the first layer 141, the second sacrificial pattern 104 may be selectively etched. Thus, etching of the first layer 141 during the etching of the second sacrificial pattern 104 may be alleviated or prevented.

[0103] Reference Figure 23 , the insulating liner material layer 160 may be formed on the sidewalls and the top surface of the first trench T1, the sidewalls and the top surface of the second trench T2, and the bottom surface of the first interlayer insulating layer 100. For example, the insulating liner material layer 160 may be conformally formed. For example, the insulating liner material layer 160 may include one of SiN, SiCN, SiON, and SiOCN.

[0104] Reference Figure 24, by performing an etching process, portions of the insulating liner material layer 160 formed on the top surface of the first trench T1, the top surface of the second trench T2, and the bottom surface of the first interlayer insulating layer 100 can be etched. During the etching of the portion of the insulating liner material layer 160 on the top surface of the second trench T2, the second source / drain region SD2 can also be partially etched. Thus, a third trench T3 can be formed on the top surface of the first trench T1.

[0105] For example, the top surface of the third trench T3 can be formed to be higher than the top surface of the lowermost nanosheet among the second plurality of nanosheets NW2 and the third plurality of nanosheets NW3. The portion of the insulating liner material layer 160 remaining on the sidewalls of the third trench T3 can be defined as a first insulating liner layer 161. Additionally, another portion of the insulating liner material layer 160 remaining on the sidewalls of the first trench T1 can be defined as a second insulating liner layer 162.

[0106] Reference Figure 2 and Figure 3 , a lower source / drain contact BCA can be formed in the third trench T3. The top surface of the lower source / drain contact BCA can be formed to be higher than the top surface of the lowermost nanosheet among the second plurality of nanosheets NW2 and the third plurality of nanosheets NW3. Additionally, a lower via BV can be formed in the first trench T1. The lower source / drain contact BCA and the lower via BV can be formed by the same manufacturing process. For example, the lower source / drain contact BCA and the lower via BV can be integrally formed.

[0107] Furthermore, a lower silicide layer BSL can be formed between the lower source / drain contact BCA and the second source / drain region SD2. For example, the top surface of the first insulating liner layer 161 can be in contact with the lower silicide layer BSL. In this way, a Figure 2 and Figure 3 semiconductor device can be manufactured.

[0108] The method of manufacturing a semiconductor device according to this exemplary embodiment of the present disclosure can use the second sacrificial pattern 104 as a sacrificial layer to form the lower source / drain contact BCA. By forming the concentration of Ge higher in the second sacrificial pattern 104 than in the first layer 141 of the second source / drain region SD2, the second sacrificial pattern 104 can be selectively wet-etched. Thus, etching of the first layer 141 during the wet etching of the second sacrificial pattern 104 can be reduced or prevented, thereby protecting the second source / drain region SD2. Furthermore, the method of manufacturing a semiconductor device according to this exemplary embodiment of the present disclosure can form the lower source / drain contact BCA extending into the second source / drain region SD2 by forming the first insulating liner layer 161 in the etched portion of the second sacrificial pattern 104 and then performing subsequent etching processes.

[0109] In a semiconductor device manufactured by a method of manufacturing a semiconductor device according to this exemplary embodiment of the present disclosure, a top surface of a lower source / drain contact BCA may be formed to be higher than a top surface of a lowermost nanosheet among a second plurality of nanosheets NW2 and a third plurality of nanosheets NW3. Accordingly, reliability of an electrical connection between the lower source / drain contact BCA and a second source / drain region SD2 may be enhanced. Additionally, top surfaces of respective portions of a first insulating liner layer 161 on sidewalls of the lower source / drain contact BCA may be in contact with a lower silicide layer BSL.

[0110] Hereinafter, focus will be mainly placed on differences from Figures 1 to 3 a semiconductor device of Figure 25 to describe a semiconductor device according to another exemplary embodiment of the present disclosure.

[0111] Figure 25 is a cross-sectional view for illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept.

[0112] Referring to Figure 25 , a lower source / drain contact BCA2 and a lower via BV2 may be formed as a dual film.

[0113] For example, each of the lower source / drain contact BCA2 and the lower via BV2 may include a contact barrier layer 281 and a contact fill layer 282. The contact barrier layer 281 of the lower source / drain contact BCA2 may form sidewalls and a top surface of the lower source / drain contact BCA2. The contact barrier layer 281 of the lower source / drain contact BCA2 may be in contact with each of a first insulating liner layer 161 and a lower silicide layer BSL. The contact fill layer 282 of the lower source / drain contact BCA2 may fill a space between respective portions of the contact barrier layer 281 of the lower source / drain contact BCA2.

[0114] The contact barrier layer 281 of the lower via BV2 may form portions of sidewalls and a top surface of the lower via BV2. The contact barrier layer 281 of the lower via BV2 may be in contact with a first insulating liner layer 161, a second insulating liner layer 162, and a first interlayer insulating layer 100. The contact fill layer 282 of the lower via BV2 may fill a space between respective portions of the contact barrier layer 281 of the lower via BV2.

[0115] For example, the lower source / drain contact BCA2 and the lower via BV2 can be integrally formed. The contact barrier layer 281 of the lower source / drain contact BCA2 and the contact barrier layer 281 of the lower via BV2 can be integrally formed. That is, the contact barrier layer 281 of the lower source / drain contact BCA2 and the contact barrier layer 281 of the lower via BV2 can be continuously formed. Similarly, the contact fill layer 282 of the lower source / drain contact BCA2 and the contact fill layer 282 of the lower via BV2 can be integrally formed. That is, the contact barrier layer 281 of the lower source / drain contact BCA2 and the contact barrier layer 281 of the lower via BV2 can be continuously formed.

[0116] The contact barrier layer 281 may include materials such as Ta, TaN, Ti, TiN, Ru, Co, Ni, nickel boride (NiB), W, WN, tungsten carbonitride (WCN), Zr, zirconium nitride (ZrN), V, vanadium nitride (VN), Nb, NbN, Pt, Ir, or Rh. The contact fill layer 282 may include materials such as Al, W, Co, Ru, or Mo.

[0117] Hereinafter, it will mainly focus on the differences from Figures 1 to 3 the semiconductor device of Figure 26 to describe a semiconductor device according to another exemplary embodiment of the present disclosure.

[0118] Figure 26 is a cross-sectional view for illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept.

[0119] Referring to Figure 26 , the first sacrificial pattern ( Figure 2 "103" of

[0120] Hereinafter, it will mainly focus on the differences from Figures 1 to 3 the semiconductor device of Figure 27 to describe a semiconductor device according to another exemplary embodiment of the present disclosure.

[0121] Figure 27 is a cross-sectional view for illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept.

[0122] Referring to Figure 27 , the second interlayer dielectric layer 490 may be disposed under the first interlayer dielectric layer 400, and the lower via BV may be disposed in the second interlayer dielectric layer 490.

[0123] For example, a second interlayer insulating layer 490 may be disposed on the bottom surface of the first interlayer insulating layer 400. The second interlayer insulating layer 490 may be in contact with the bottom surfaces of the first interlayer insulating layer 400 and the first sacrificial pattern 103. For example, the second interlayer insulating layer 490 may include a material different from that of the first interlayer insulating layer 400. For example, the second interlayer insulating layer 490 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

[0124] For example, the second interlayer insulating layer 490 may surround the sidewalls of the lower via BV. For example, the top surface of the second interlayer insulating layer 490 may be formed in the same plane as the top surface of the lower via BV. For example, at least a portion of the top surface of the lower via BV may be in contact with the first interlayer insulating layer 400.

[0125] Hereinafter, the focus will be mainly on the differences from Figures 1 to 3 a semiconductor device of Figure 28 to describe a semiconductor device according to another exemplary embodiment of the present disclosure.

[0126] Figure 28 is a cross-sectional view for explaining a semiconductor device according to an exemplary embodiment of the present inventive concept.

[0127] Referring to Figure 28 , a second interlayer insulating layer 590 may be disposed below the first interlayer insulating layer 500, and the lower via BV5 disposed in the second interlayer insulating layer 590 may be formed as a single film.

[0128] For example, a second interlayer insulating layer 590 may be disposed on the bottom surface of the first interlayer insulating layer 500. The second interlayer insulating layer 590 may be in contact with the bottom surface of the first interlayer insulating layer 500 and the bottom surface of the first sacrificial pattern 103. For example, the second interlayer insulating layer 590 may include a material different from that of the first interlayer insulating layer 500. For example, the second interlayer insulating layer 590 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

[0129] For example, the second interlayer insulating layer 590 may surround the sidewalls of the lower via BV5. For example, the top surface of the second interlayer insulating layer 590 may be formed in the same plane as the top surface of the lower via BV5. For example, at least a portion of the top surface of the lower via BV5 may be in contact with the first interlayer insulating layer 500. In some exemplary embodiments, the top portion of the sidewall of the lower via BV5 may be in contact with the first interlayer insulating layer 500. For example, the lower via BV5 may be formed as a single film. For example, the lower via BV5 may include a conductive material.

[0130] Although some example embodiments have been described with reference to the accompanying drawings in accordance with the technical spirit of the present disclosure, it should be understood that the present disclosure is not limited to these example embodiments. The inventive concept can be made in various different forms, and those of ordinary skill in the art will understand that the example embodiments can be implemented in other specific forms without changing the technical spirit or essential features of the inventive concept. Therefore, the above example embodiments should be considered illustrative in all respects and not restrictive.

Claims

1. A semiconductor device, the semiconductor device comprising: A first interlayer insulating layer; An insulating pattern extending along a first horizontal direction on a top surface of the first interlayer insulating layer; A first gate electrode, a second gate electrode, and a third gate electrode, the first gate electrode, the second gate electrode, and the third gate electrode extending along a second horizontal direction different from the first horizontal direction on the insulating pattern, the first gate electrode, the second gate electrode, and the third gate electrode being sequentially spaced apart from each other in the first horizontal direction; A first source / drain region located between the first gate electrode and the second gate electrode on the insulating pattern; A second source / drain region located between the second gate electrode and the third gate electrode on the insulating pattern; A lower source / drain contact extending into the second source / drain region by penetrating the first interlayer insulating layer and the insulating pattern in a vertical direction, a top surface of the lower source / drain contact being higher than a top surface of the insulating pattern; A first insulating liner layer located between the lower source / drain contact and each of the first interlayer insulating layer and the insulating pattern; And A lower silicide layer located between the second source / drain region and the lower source / drain contact, the lower silicide layer being in contact with a top surface of the first insulating liner layer.

2. The semiconductor device according to claim 1, the semiconductor device further comprising: A first plurality of nanosheets stacked at intervals of each other in the vertical direction on the insulating pattern, the first plurality of nanosheets being surrounded by the first gate electrode; A second plurality of nanosheets stacked at intervals of each other in the vertical direction on the insulating pattern, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction, the second plurality of nanosheets being surrounded by the second gate electrode; And A third plurality of nanosheets stacked at intervals of each other in the vertical direction on the insulating pattern, the third plurality of nanosheets being spaced apart from the second plurality of nanosheets in the first horizontal direction, the third plurality of nanosheets being surrounded by the third gate electrode.

3. The semiconductor device according to claim 2, wherein, The top surface of the lower source / drain contact is higher than a top surface of a lowermost nanosheet among the second plurality of nanosheets.

4. The semiconductor device according to claim 1, the semiconductor device further comprising: A lower via located below the lower source / drain contact, a width of a top surface of the lower via in the first horizontal direction being greater than a width of a bottom surface of the lower source / drain contact in the first horizontal direction, and Wherein at least a portion of the top surface of the lower via is in contact with the first interlayer insulating layer.

5. The semiconductor device according to claim 4, the semiconductor device further comprising: A second insulating liner layer, the second insulating liner layer being in contact with two sidewalls of the lower via in the first horizontal direction, the second insulating liner layer including the same material as the first insulating liner layer.

6. The semiconductor device according to claim 4, wherein, The lower via and the lower source / drain contact are respectively parts of an integral body.

7. The semiconductor device according to claim 4, the semiconductor device further comprising: A second interlayer insulating layer, the second interlayer insulating layer being located on a bottom surface of the first interlayer insulating layer, a top surface of the second interlayer insulating layer being in a same plane as the top surface of the lower via.

8. The semiconductor device according to claim 1, the semiconductor device further comprising: An interlayer insulating layer, the interlayer insulating layer covering the first source / drain region and the second source / drain region located on the top surface of the first interlayer insulating layer; And An upper source / drain contact, the upper source / drain contact extending into the first source / drain region by penetrating the interlayer insulating layer in the vertical direction.

9. The semiconductor device according to claim 1, the semiconductor device further comprising: A sacrificial pattern, the sacrificial pattern being located below the first source / drain region, two sidewalls of the sacrificial pattern in the first horizontal direction being in contact with each of the insulating pattern and the first interlayer insulating layer, the sacrificial pattern including silicon germanium.

10. The semiconductor device according to claim 9, wherein, A bottom surface of the sacrificial pattern is in a same plane as a bottom surface of the lower source / drain contact.

11. The semiconductor device according to claim 1, wherein, The lower source / drain contact is a single-film structure.

12. The semiconductor device according to claim 1, wherein, The lower source / drain contact includes a contact barrier layer and a contact fill layer, the contact barrier layer being in contact with each of the first insulating liner layer and the lower silicide layer, the contact fill layer filling a space between respective parts of the contact barrier layer.

13. A semiconductor device, the semiconductor device comprising: A first interlayer insulating layer; An insulating pattern, the insulating pattern extending along a first horizontal direction on a top surface of the first interlayer insulating layer; A first plurality of nanosheets, the first plurality of nanosheets being stacked on the insulating pattern at intervals in a vertical direction; A second plurality of nanosheets, the second plurality of nanosheets being stacked on the insulating pattern at intervals in the vertical direction, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction; A first gate electrode, the first gate electrode extending along a second horizontal direction different from the first horizontal direction on the insulating pattern, the first gate electrode surrounding the first plurality of nanosheets; A second gate electrode, the second gate electrode extending along the second horizontal direction on the insulating pattern, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction, the second gate electrode surrounding the second plurality of nanosheets; A source / drain region, the source / drain region being located between the first gate electrode and the second gate electrode on the insulating pattern; A lower source / drain contact that extends into the source / drain region by penetrating the first interlayer insulating layer and the insulating pattern in the vertical direction, and a top surface of the lower source / drain contact is higher than a top surface of the lowermost nanosheet among the first plurality of nanosheets; A first insulating cushion layer that is located between the lower source / drain contact and each of the first interlayer insulating layer and the insulating pattern; And A lower via that is located below the lower source / drain contact, a width of a top surface of the lower via in the first horizontal direction is greater than a width of a bottom surface of the lower source / drain contact in the first horizontal direction, and at least a part of the top surface of the lower via is in contact with the first interlayer insulating layer.

14. The semiconductor device according to claim 13, further comprising: A lower silicide layer that is located between the source / drain region and the lower source / drain contact, and the lower silicide layer is in contact with a top surface of the first insulating cushion layer.

15. The semiconductor device according to claim 13, further comprising: A second insulating cushion layer that is in contact with two sidewalls of the lower via in the first horizontal direction and includes the same material as the first insulating cushion layer.

16. The semiconductor device according to claim 15, wherein, A top surface of the second insulating cushion layer is located in a same plane as the top surface of the lower via.

17. The semiconductor device according to claim 13, wherein, The lower via and the lower source / drain contact are respectively parts of an integral body.

18. The semiconductor device according to claim 13, further comprising: A second interlayer insulating layer that is provided on a bottom surface of the first interlayer insulating layer, and a top surface of the second interlayer insulating layer is located in a same plane as the top surface of the lower via.

19. A semiconductor device, comprising: A first interlayer insulating layer; An insulating pattern that extends in a first horizontal direction on a top surface of the first interlayer insulating layer; A first plurality of nanosheets that are stacked on the insulating pattern at intervals in a vertical direction; A second plurality of nanosheets that are stacked on the insulating pattern at intervals in the vertical direction, and the second plurality of nanosheets are spaced apart from the first plurality of nanosheets in the first horizontal direction; A third plurality of nanosheets that are stacked on the insulating pattern at intervals in the vertical direction, and the third plurality of nanosheets are spaced apart from the second plurality of nanosheets in the first horizontal direction; A first gate electrode that extends on the insulating pattern in a second horizontal direction different from the first horizontal direction, and the first gate electrode surrounds the first plurality of nanosheets; A second gate electrode, the second gate electrode extending along the second horizontal direction on the insulating pattern, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction, the second gate electrode surrounding the second plurality of nanosheets; A third gate electrode, the third gate electrode extending along the second horizontal direction on the insulating pattern, the third gate electrode being spaced apart from the second gate electrode in the first horizontal direction, the third gate electrode surrounding the third plurality of nanosheets; A first source / drain region, the first source / drain region being located between the first gate electrode and the second gate electrode on the insulating pattern; A second source / drain region, the second source / drain region being located between the second gate electrode and the third gate electrode on the insulating pattern; An upper interlayer insulating layer, the upper interlayer insulating layer covering the first source / drain region and the second source / drain region located on the top surface of the first lower interlayer insulating layer; An upper source / drain contact, the upper source / drain contact extending into the first source / drain region by penetrating the upper interlayer insulating layer in the vertical direction; A lower source / drain contact, the lower source / drain contact extending into the second source / drain region by penetrating the first lower interlayer insulating layer and the insulating pattern in the vertical direction, the top surface of the lower source / drain contact being higher than the top surface of the lowermost nanosheet among the second plurality of nanosheets; A lower via, the lower via being located below the lower source / drain contact, the width of the top surface of the lower via in the first horizontal direction being greater than the width of the bottom surface of the lower source / drain contact in the first horizontal direction; A first insulating liner layer, the first insulating liner layer being located between the lower source / drain contact and each of the first lower interlayer insulating layer and the insulating pattern; A second insulating liner layer, the second insulating liner layer being in contact with two sidewalls of the lower via in the first horizontal direction, the second insulating liner layer including the same material as the first insulating liner layer; And A lower silicide layer, the lower silicide layer being located between the second source / drain region and the lower source / drain contact, the lower silicide layer being in contact with the top surface of the first insulating liner layer.

20. The semiconductor device according to claim 19, the semiconductor device further comprising: A sacrificial pattern, the sacrificial pattern being located below the first source / drain region, two sidewalls of the sacrificial pattern in the first horizontal direction being in contact with each of the insulating pattern and the first lower interlayer insulating layer, the sacrificial pattern including silicon germanium, Wherein, the first source / drain region includes a first layer and a second layer, the first layer being in contact with each of the first plurality of nanosheets and the second plurality of nanosheets on sidewalls in the first horizontal direction and the top surface of the sacrificial pattern, the second layer being located on the first layer, and Wherein, the concentration of germanium included in the sacrificial pattern is greater than the concentration of germanium included in the first layer.

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