Silicon carbide semiconductor device and preparation method thereof

Abstract

The invention provides a silicon carbide semiconductor device and a preparation method thereof. The device comprises a substrate; an epitaxial layer; the plurality of source region structures are located on one side, away from the substrate, of the epitaxial layer at intervals; the gate structure is located between the source region structures, the gate structure comprises a first semiconductor layer, a second semiconductor layer and a gate which are sequentially stacked in the thickness direction of the substrate, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on the side, away from the substrate, of the second semiconductor layer. The problem of low channel mobility of a silicon carbide device in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a silicon carbide semiconductor device and a method for preparing the same. Background Art

[0002] At present, there are some process and technical difficulties that prevent SiC devices from achieving theoretical performance. For example, the gate oxide channel mobility of SiC devices is low, resulting in a large proportion of channel resistance, and the switching rate of the device is difficult to increase. The main reason is that during the growth of the gate oxide, some C atoms will remain at the SiC / SiO2 interface in the form of C clusters, affecting the SiC surface, resulting in poor gate oxide quality, low channel mobility, and increased channel resistance. At this stage, the gate oxide mobility is mainly improved through N-containing element annealing, gate oxide pre-surface treatment and other process methods, but the overall improvement of gate oxide mobility is very limited. Low mobility is still one of the problems facing SiC devices.

[0003] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0004] The main purpose of the present application is to provide a silicon carbide semiconductor device and a method for preparing the same, so as to solve the problem of low channel mobility of silicon carbide devices in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a silicon carbide semiconductor device is provided, comprising: a substrate; an epitaxial layer; a plurality of source region structures, which are spaced apart and located on a side of the epitaxial layer away from the substrate; a gate structure, which is located between the source region structures, and the gate structure comprises a first semiconductor layer, a second semiconductor layer and a gate, which are stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on a side of the second semiconductor layer away from the substrate.

[0006] Optionally, the gate structure further includes: a superlattice layer, wherein the superlattice layer is located between the first semiconductor layer and the epitaxial layer.

[0007] Optionally, the material of the first semiconductor layer includes gallium nitride and gallium arsenide, the material of the second semiconductor layer includes aluminum gallium nitride and aluminum gallium arsenide, and the material of the gate includes gallium nitride and gallium arsenide.

[0008] Optionally, the source region structure includes a first doped region and a second doped region stacked in sequence along the thickness direction of the substrate. The first doped region is located on the side of the epitaxial layer away from the substrate and has a first doping type. The second doped region is located on the side of the first doped region away from the substrate and has a second doping type. The side of the first semiconductor layer away from the substrate has a first surface, and the side of the first doped region away from the substrate has a second surface. The minimum distance from the first surface to the substrate is equal to the minimum distance from the second surface to the substrate.

[0009] Optionally, the semiconductor device further includes a composite passivation layer located on the side of the source region structure and the gate structure away from the substrate. The composite passivation layer includes a stacked metal oxide layer and a non-metal oxide layer.

[0010] Optionally, the semiconductor device further includes a first lead-out portion, a second lead-out portion, and a third lead-out portion. The first lead-out portion penetrates the composite passivation layer and contacts the gate. The second lead-out portion penetrates the composite passivation layer and contacts the source region structure. The third lead-out portion contacts the substrate.

[0011] Optionally, the first lead-out portion has a first region in contact with the gate, and the second lead-out portion has a second region in contact with the source region structure. The materials of the first region and the second region include titanium-containing metal compounds.

[0012] According to another aspect of the present application, a method for manufacturing a silicon carbide semiconductor device for manufacturing the silicon carbide semiconductor device is provided. The manufacturing method includes: providing a substrate and forming an epitaxial layer on one side of the substrate; forming a plurality of spaced-apart source region structures on one side of the epitaxial layer; forming a gate structure between the plurality of source region structures. The gate structure includes a first semiconductor layer, a second semiconductor layer, and a gate stacked in sequence along the thickness direction of the substrate. A two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on the side of the second semiconductor layer away from the substrate.

[0013] Optionally, the step of forming a plurality of source region structures distributed at intervals on one side of the epitaxial layer includes: sequentially forming a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer on the substrate; performing a first implantation in the third epitaxial layer to form a preliminary first doped region; performing a second implantation in the preliminary first doped region to form a preliminary second doped region, the implantation depth of the preliminary second doped region being less than that of the preliminary first doped region; performing an etching process on the preliminary first doped region and the preliminary second doped region to form grooves in the preliminary first doped region and the preliminary second doped region, the remaining preliminary first doped region forming a first doped region, and the remaining preliminary second doped region forming a second doped region, the first doped region and the second doped region forming the source region structure.

[0014] Optionally, the step of forming the gate structure between the plurality of source region structures includes: sequentially stacking a superlattice layer, the first semiconductor layer, the second semiconductor layer, and the gate on the bottom of the groove, the gate protruding from the groove, and the superlattice layer, the first semiconductor layer, the second semiconductor layer, and the gate forming the gate structure.

[0015] Applying the technical solution of the present application, a silicon carbide semiconductor device includes a substrate, an epitaxial layer, a plurality of source region structures, and a gate structure. Among them, the plurality of source region structures are located at intervals on the side of the epitaxial layer facing away from the substrate; the gate structure is located between the source region structures, and the gate structure includes a first semiconductor layer, a second semiconductor layer, and a gate sequentially stacked along the thickness direction of the substrate. A two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on the side of the second semiconductor layer facing away from the substrate. By forming a first semiconductor layer and a second semiconductor layer between the epitaxial layer and the gate to replace the gate oxide structure in the prior art silicon carbide device, and a two-dimensional electron gas layer with extremely high electron mobility is formed at the contact interface between the first semiconductor layer and the second semiconductor layer. The electron mobility of the two-dimensional electron gas layer is 20 to 40 times higher than that of the conventional gate oxide structure. Therefore, by replacing the gate oxide structure with the two-dimensional electron gas layer for the silicon carbide device, electrons move faster in the channel under the same electric field strength, contributing a higher channel electron mobility to the silicon carbide semiconductor device and solving the problem of low channel mobility in the prior art silicon carbide device. Description of the Drawings

[0016] The specification drawings forming a part of the present application are used to provide a further understanding of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0017] Figure 1 Fig. 1 shows a schematic cross-sectional structure diagram of a first silicon carbide semiconductor device according to an embodiment of the present application;

[0018] Figure 2 shows a schematic cross-sectional structure diagram of a second silicon carbide semiconductor device according to an embodiment of the present application;

[0019] Figure 3 shows a schematic cross-sectional structure diagram of a third silicon carbide semiconductor device according to an embodiment of the present application;

[0020] Figure 4 shows a schematic flow diagram of a method for manufacturing a silicon carbide semiconductor device according to an embodiment of the present application;

[0021] Figure 5 shows Figure 4 a schematic cross-sectional structure diagram of a substrate and a matrix after forming an epitaxial layer in a method for manufacturing a silicon carbide semiconductor device;

[0022] Figure 6 shows in Figure 8 a schematic cross-sectional structure diagram of a matrix after forming a preliminary first doping region and a preliminary second doping region in an epitaxial layer formed therein;

[0023] Figure 7 shows for Figure 6 a schematic cross-sectional structure diagram of a matrix after etching treatment of a preliminary first doping region and a preliminary second doping region formed therein;

[0024] Figure 8 shows in Figure 7 a schematic cross-sectional structure diagram of a matrix after forming a superlattice layer, a first semiconductor layer, a second semiconductor layer, and a gate in a groove formed therein.

[0025] Among them, the above-mentioned drawings include the following reference numerals:

[0026] 10. Substrate; 20. Epitaxial layer; 21. First epitaxial layer; 22. Second epitaxial layer; 23. Third epitaxial layer; 30. Source region structure; 31. First doping region; 32. Second doping region; 310. Preliminary first doping region; 320. Preliminary second doping region; 40. Gate structure; 41. First semiconductor layer; 42. Second semiconductor layer; 43. Gate; 44. Two-dimensional electron gas layer; 45. Superlattice layer; 50. Composite passivation layer; 60. First lead-out portion; 61. First region; 70. Second lead-out portion; 71. Second region; 80. Third lead-out portion. Detailed implementation manners

[0027] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0028] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0029] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present invention described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as "on" another element, the element can be directly on the other element, or there may also be an intermediate element. Moreover, in the description and claims of the specification, when an element is described as "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0031] As introduced in the background art, in the prior art, the channel mobility of SiC devices is relatively low, resulting in a large proportion of channel resistance and making it difficult to improve the switching speed of the devices. The main reason is that some C atoms will remain at the SiC / SiO2 interface in the form of C clusters during the growth of the gate oxide, affecting the SiC surface, thus resulting in poor gate oxide quality, low channel mobility, and increased channel resistance. At present, the channel mobility of the gate oxide is mainly improved by processes such as N-element annealing and pre-surface treatment of the gate oxide, but the overall improvement of the gate oxide mobility is very limited. The too low mobility is still one of the problems faced by SiC devices. To solve the problem of low channel mobility of silicon carbide devices in the prior art, the embodiments of the present application provide a silicon carbide semiconductor device and a method for preparing the same.

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention.

[0033] According to the embodiments of the present application, as Figures 1 to 3As shown, a silicon carbide semiconductor device is provided, including: a substrate 10; an epitaxial layer 20; a plurality of source region structures 30, spaced apart on a side of the epitaxial layer 20 facing away from the substrate 10; a gate structure 40, located between the source region structures 30, the gate structure 40 including a first semiconductor layer 41, a second semiconductor layer 42, and a gate 43 stacked in sequence along the thickness direction of the substrate 10, a two-dimensional electron gas layer 44 being formed at an interface between the first semiconductor layer 41 and the second semiconductor layer 42, and the gate 43 being located on a side of the second semiconductor layer 42 facing away from the substrate 10.

[0034] Through the above silicon carbide semiconductor device, including a substrate, an epitaxial layer, a plurality of source region structures, and a gate structure, wherein the plurality of source region structures are spaced apart on a side of the epitaxial layer facing away from the substrate; the gate structure is located between the source region structures, the gate structure includes a first semiconductor layer, a second semiconductor layer, and a gate stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer is formed at an interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on a side of the second semiconductor layer facing away from the substrate. By forming a first semiconductor layer and a second semiconductor layer between the epitaxial layer and the gate to replace the gate oxide structure of the silicon carbide device in the prior art, and a two-dimensional electron gas layer with extremely high electron mobility is formed at the contact interface between the first semiconductor layer and the second semiconductor layer. The mobility of the two-dimensional electron gas layer is 20 to 40 times higher than that of the conventional gate oxide structure. This application is equivalent to contributing high mobility to the silicon carbide device by replacing the gate oxide structure with the two-dimensional electron gas layer, also improving the switching speed of the device and enhancing the high-frequency performance of the device. It solves the problem of low channel mobility in the silicon carbide device in the prior art.

[0035] In the above embodiment, the materials of the substrate and the epitaxial layer are both silicon carbide, which can make the device have high thermal conductivity and high breakdown field strength, and is suitable for manufacturing high-performance devices that can work in high-temperature and high-pressure environments. The thickness of the substrate can be 300 to 350 μm, and the substrate will be thinned in the subsequent process of preparing the drain lead-out part. The thickness of the thinned substrate is 150 to 200 μm, and the thickness of the epitaxial layer is 5 to 16 μm. The epitaxial layer within this range can reduce the reverse leakage current, relatively protect the position under the gate, prevent premature breakdown, and also enhance the current-carrying capacity of the device during forward conduction.

[0036] As Figure 1 shown, the epitaxial layer 20 includes a first epitaxial layer 21 and a second epitaxial layer 22, wherein: the first epitaxial layer 21 and the second epitaxial layer 22 are stacked on the substrate 10 in sequence along the thickness direction of the substrate 10, and the doping concentration of the second epitaxial layer 22 is lower than that of the first epitaxial layer 21. Adopting a double-layer epitaxial layer can enable the device to carry a higher current (at least 30% increase) during forward conduction, and at the same time, when reverse-biased, the leakage current is reduced by more than 50%, significantly improving the performance and reliability of the device and extending the service life of the device.

[0037] Specifically, the thickness of the first epitaxial layer can be 5 - 15 μm, and the doping concentration can be 9E15 - 1.5E16 cm -3 . The thickness of the second epitaxial layer can be 200 - 400 nm, and the doping concentration is in the range of 1E12 - 1E13 cm -3 , which can improve the breakdown voltage of the device. There are no specific limitations on the doping concentration and thickness of the first epitaxial layer and the second epitaxial layer. Among them, the breakdown voltage of the first epitaxial layer with a thickness of 5 μm is about 600 V, and the breakdown voltage of the second epitaxial layer with a thickness of 15 μm is about 1700 V.

[0038] In some alternative embodiments, the material of the first semiconductor layer includes gallium nitride (GaN) and gallium arsenide (GaAs), the material of the second semiconductor layer includes aluminum gallium nitride (AlGaN) and aluminum gallium arsenide (AlGaAs), and the material of the gate includes gallium nitride and gallium arsenide. Among them, when the material of the first semiconductor layer is GaN, the material of the second semiconductor layer is AlGaN, the material of the gate is GaN, and the gate has P-type doping; when the material of the first semiconductor layer is GaAs, the material of the second semiconductor layer is AlGaAs, the material of the gate is GaAs, and the gate has P-type doping. Preferably, the material of the first semiconductor layer is GaN. The lattice constants between the GaN material and the SiC material are very close (the lattice constant difference is about 3%, and the lattice constant difference of GaN epitaxially grown on Si is about 70%), which can result in fewer defects in the first semiconductor layer formed on SiC. The thickness of the first semiconductor layer can be 180 - 200 nm, the thickness of the second semiconductor layer can be 15 - 25 nm, and the thickness of the gate can be 80 - 100 nm. Setting the materials and thicknesses of the first semiconductor layer and the second semiconductor layer within the above ranges is beneficial for forming a two-dimensional electron gas layer with high mobility, thereby significantly improving the switching speed of the device, reducing the channel resistance, enhancing the high-frequency performance of the device, and at the same time reducing the gate capacitance and maintaining good electrical properties of the gate. Among them, the two-dimensional electron gas layer is formed due to the piezoelectric polarization and spontaneous polarization effects caused by the lattice mismatch between AlGaN and GaN, which generate an internal electric field at the interface.

[0039] Among them, the gate made of P-GaN can form an enhancement-mode device, and the threshold voltage value can be adjusted through the width of the gate structure and can be stably controlled within 1.8 - 2.5 V.

[0040] In some alternative embodiments, as Figure 2 shown, the gate structure further includes: a superlattice layer 45, and the superlattice layer 45 is located between the first semiconductor layer 41 and the epitaxial layer 20. The superlattice layer 45 can suppress the defects brought by the lattice mismatch of the device.

[0041] The above-mentioned superlattice layer can be formed by alternately stacking AlN material layers and GaN material layers, or by alternately stacking AlGaN material layers and GaN material layers, or by alternately stacking InGaN material layers and GaN material layers, or by alternately stacking AlInN material layers and GaN material layers. Among them, it is preferably that the superlattice layer is formed by alternately stacking AlN material layers and GaN material layers. The barrier and passivation effect of AlN is better, which can better limit the upward growth of defects. The thickness of the AlN, AlGaN, InGaN, and AlInN material layers can be 2 nm, the thickness of the GaN material layer can be 1-2 nm, and the number of layer periods is 25-30 layers, which can further optimize the electron mobility, reduce defects, and improve the stability of the device.

[0042] In some alternative embodiments, such as Figure 3 shown, the source region structure 30 includes a first doped region 31 and a second doped region 32 stacked in sequence along the thickness direction of the substrate 10. Among them, the first doped region 31 is located on the side of the epitaxial layer 20 away from the substrate 10, and the first doped region 31 has a first doping type; the second doped region 32 is located on the side of the first doped region 31 away from the substrate 10, and the second doped region 32 has a second doping type; the first semiconductor layer 41 has a first surface on the side away from the substrate 10, and the first doped region 31 has a second surface on the side away from the substrate 10. The minimum distance from the first surface to the substrate 10 is equal to the minimum distance from the second surface to the substrate 10. The first doped region 31 ensures a low contact resistance with the source electrode lead-out portion to ensure good ohmic contact, making the current transmission more smooth when the device is in the on state, and improving the conductivity and efficiency of the device. The combination of the first doped region 31 and the second doped region 32 can increase the current density, improve the ohmic contact, and reduce the contact resistance of the source region.

[0043] Specifically, the doping type of the first doped region can be P-type, the doping ion can be Al element, and the doping concentration can be 1E13~E15 cm -3 , and the doping depth can be 360~420 nm; the doping type of the second doped region can be N-type, the doping ion can be N element, and the doping concentration can be 1E13~5E14 cm -3 , and the doping depth can be 100~150 nm. This can further ensure a low contact resistance between the device and the source electrode lead-out portion to ensure good ohmic contact, making the current transmission more smooth when the device is in the on state, and improving the conductivity and efficiency of the device.

[0044] In some alternative embodiments, such as Figures 1 to 3As shown, the semiconductor device further includes a composite passivation layer 50. The composite passivation layer 50 is located on the side of the source region structure 30 and the gate structure 40 facing away from the substrate 10. The composite passivation layer 50 includes a stacked metal oxide layer and a non-metal oxide layer. The composite passivation layer 50 can reduce surface states, reduce gate leakage, and at the same time has good mechanical properties, preventing corrosion and diffusion of metal materials.

[0045] Among them, the metal oxide layer can be any one of Al2O3, HfO2, and ZrO2, and the thickness can be 2 - 3 nm. Preferably, it is Al2O3. The price of Al2O3 is cheaper, which can save costs and is better controlled in the manufacturing process. The non-metal oxide layer can be any one of a silicon dioxide layer (a silicon dioxide layer (PEOX) formed by chemical vapor deposition process) and a tetraethyl orthosilicate layer (a tetraethyl orthosilicate layer (PETEOS) formed by chemical vapor deposition process), and the thickness is 2000 - 3000 Å. By setting the composite passivation layer to the above materials and parameters, the surface state density of the device can be better reduced, the gate leakage can be reduced, so that the leakage level of the device in the off state is reduced by at least 40%, the stability of the device is improved, and the service life is extended. At the same time, it also provides additional mechanical protection and enhances the durability of the device.

[0046] In some alternative embodiments, as Figures 1 to 3 shown, the semiconductor device further includes a first lead-out portion 60, a second lead-out portion 70, and a third lead-out portion 80. Among them, the first lead-out portion 60 penetrates through the composite passivation layer 50 and contacts the gate 43, the second lead-out portion 70 penetrates through the composite passivation layer 50 and contacts the source region structure 30, and the third lead-out portion 80 contacts the substrate 10. By applying a voltage to the first lead-out portion 60, the on and off states of the device can be controlled. The second lead-out portion 70 forms an ohmic contact with the second doped region 32, which helps to reduce the contact resistance between the second lead-out portion 70 and the source region structure 30, ensures efficient current transmission, reduces energy loss, and the third lead-out portion 80 collects the charges injected from the second lead-out portion 70 and transmitted through the channel to complete the process of current flowing through the device. The thicknesses of the above-mentioned first lead-out portion, second lead-out portion, and third lead-out portion can be 50 - 100 nm. Within the above range, a lower contact resistance of the device can be better achieved.

[0047] In some alternative embodiments, as Figures 1 to 3As shown, the first lead-out portion 60 has a first region 61 in contact with the gate 43, and the second lead-out portion 70 has a second region 71 in contact with the source region structure 30. The materials of the first region 61 and the second region 71 include titanium-containing metal compounds. Among them, the titanium-containing compounds include any one of TiAlN, TiC, and TiCN. Preferably, it is TiN. TiN is easier to control during the device preparation process and has a lower resistivity, that is, the contact resistance is the smallest. The first lead-out portion 60 and the second lead-out portion 70 made of TiN material can form good contact characteristics with the semiconductor layers of GaN material and SiC material, thereby realizing low-impedance electrode connection. At the same time, TiN has high corrosion resistance and can maintain the integrity of the first lead-out portion 60 and the second lead-out portion 70 after high-temperature annealing. Among them, the first lead-out portion 60 made of TiN material can better form a Schottky contact with the gate 43 of P-GaN material to reduce gate reverse leakage. In the second lead-out portion 70 made of TiN material, Ti forms a good ohmic contact with the second doped region of SiC material.

[0048] Specifically, the working principle of the silicon carbide semiconductor device in this application is as follows:

[0049] When the gate voltage V g ≤0V, the electric field generated by the negative gate voltage will repel the electrons in the second semiconductor layer, forming a depletion layer, reducing the two-dimensional electron gas density. Finally, there is no two-dimensional electron gas layer in the channel, and the device is in the off state at this time. The reverse second epitaxial layer can reduce the device leakage in the off state;

[0050] When the gate voltage 0V<Vg<V th , at this time, under the positive gate voltage, a two-dimensional electron gas is gradually formed between the second semiconductor layer and the first semiconductor layer, but the conduction path is not completely formed, the channel resistance is large, the device is in the sub-threshold stage, and the source-drain current is small, where V th is the voltage threshold of the device in the on state;

[0051] When the gate voltage V g =V th , at this time, the two-dimensional electron gas layer in the channel is completely formed, the channel is completely opened, and electrons flow out from the source electrode through the two-dimensional electron gas layer, then pass through the first semiconductor layer, the epitaxial layer, and the substrate to the drain electrode, forming a conductive loop.

[0052] According to the embodiments of this application, as Figure 4 shown, a preparation method of a silicon carbide semiconductor device is provided for preparing the silicon carbide semiconductor device. The preparation method includes:

[0053] Step S1, providing a substrate and forming an epitaxial layer on one side of the substrate;

[0054] Specifically, the materials of the substrate and the epitaxial layer are both silicon carbide, which can make the device have high thermal conductivity and high breakdown field strength, and is suitable for manufacturing high performance that can work in high temperature and high pressure environments. The thickness of the substrate can be 300~350μm, and the substrate will be thinned in the subsequent process of preparing the drain lead-out portion. The substrate thickness after thinning is 150~200μm, and the thickness of the epitaxial layer is 5~16μm.

[0055] Step S2, forming a plurality of source region structures spaced apart from each other on one side of the epitaxial layer;

[0056] Specifically, the source region structure can form a good ohmic contact with the lead-out portion, thereby ensuring the stability and performance of the device and avoiding signal transmission problems caused by poor contact.

[0057] Step S3, forming a gate structure between the multiple source region structures, the gate structure includes a first semiconductor layer, a second semiconductor layer and a gate stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on the side of the second semiconductor layer away from the substrate.

[0058] Specifically, the material of the first semiconductor layer may include gallium nitride and gallium arsenide, the material of the second semiconductor layer may include aluminum gallium nitride and aluminum gallium arsenide, and the material of the gate may include gallium nitride and gallium arsenide. The thickness of the first semiconductor layer may be 180-200nm, the thickness of the second semiconductor layer may be 15-25nm, and the thickness of the gate may be 80-100nm. Setting the material and thickness of the first semiconductor layer and the second semiconductor layer to the above range is conducive to forming a high-mobility two-dimensional electron gas layer, thereby significantly improving the switching speed of the device and reducing the channel resistance, enhancing the high-frequency performance of the device, while reducing the gate capacitance and maintaining good electrical properties of the gate.

[0059] The silicon carbide semiconductor device prepared by the above method for preparing a silicon carbide semiconductor device includes a substrate, an epitaxial layer, a plurality of source region structures, and a gate structure. Among them, the plurality of source region structures are located on the side of the epitaxial layer facing away from the substrate at intervals; the gate structure is located between the source region structures. The gate structure includes a first semiconductor layer, a second semiconductor layer, and a gate stacked in sequence along the thickness direction of the substrate. A two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on the side of the second semiconductor layer facing away from the substrate. By forming the first semiconductor layer and the second semiconductor layer between the epitaxial layer and the gate, the gate oxide structure of the silicon carbide device in the prior art is replaced, and a two-dimensional electron gas layer with extremely high electron mobility is formed at the contact interface between the first semiconductor layer and the second semiconductor layer. The mobility of the two-dimensional electron gas layer is 20 to 40 times higher than that of the conventional gate oxide structure. This application is equivalent to contributing high mobility to the silicon carbide device by replacing the gate oxide structure with a two-dimensional electron gas layer, and solves the problem of low channel mobility in the existing silicon carbide device.

[0060] In some alternative embodiments, as Figures 5 to 7 shown, a plurality of source region structures 30 are formed at intervals on one side of the epitaxial layer, including: sequentially forming a first epitaxial layer 21, a second epitaxial layer 22, and a third epitaxial layer 23 on the substrate 10; performing a first implantation in the third epitaxial layer 23 to form a preliminary first doped region 310; performing a second implantation in the preliminary first doped region 310 to form a preliminary second doped region 320, and the implantation depth of the preliminary second doped region 320 is less than that of the preliminary first doped region 310; performing an etching process on the preliminary first doped region 310 and the preliminary second doped region 320 to form grooves in the preliminary first doped region 310 and the preliminary second doped region 320, and the remaining preliminary first doped region 310 forms a first doped region 31, and the remaining preliminary second doped region 320 forms a second doped region 32, and the first doped region 31 and the second doped region 32 form the source region structure 30.

[0061] Exemplarily, as Figure 5 shown, a first epitaxial layer 21 of SiC material is epitaxially grown on the SiC substrate 10, with a thickness of 5 to 15 μm. Then, a second epitaxial layer 22 of SiC material with low doping is epitaxially grown on the first epitaxial layer 21, with a doping concentration of 1E12 to 1E13 cm -3 , and a thickness of 200 to 400 nm, which can reduce the reverse leakage current, relatively protect the position under the gate, prevent premature breakdown, and can also enhance the current-carrying capacity during the forward conduction of the device. Finally, a third epitaxial layer 23 of SiC material is epitaxially grown, with a thickness of 360 to 420 nm, and the doping concentration is 9E15 to 1.5E16 cm -3 . As Figure 6As shown, Al elements are implanted into the third epitaxial layer in the form of ion implantation to form a preliminary first doping region 310. For the sake of implantation uniformity, multiple implantations (such as 5 - 6 times) can be adopted. The energy of ion implantation is in the range of 50 - 300 keV, and the dose is in the range of 1E13 - 1E15 cm -3 , and the implantation depth is controlled to the surface of the second epitaxial layer 22; then N elements are implanted into the surface layer by ion implantation to form an N type, implanted 2 - 4 times, the energy is in the range of 50 - 100 keV, and the dose is in the range of 1E13 - 5E14 cm -3 , and the implantation depth is controlled by the implantation energy. The implantation depth can be 100 - 150 nm. The main purpose is to make the lower surface of the second doping region align with the two-dimensional electron gas layer plane region in the subsequent process. After the implantation is completed, annealing activation is carried out, and the annealing temperature is in the range of 1650 - 1700 °C. Then a sacrificial oxygen layer of about 10 nm is formed on the formed preliminary first doping region 310, and the sacrificial oxygen layer is etched away with DHF (diluted hydrofluoric acid). The purpose is to remove the damaged SiC film layer on the surface layer by implantation. As Figure 7 shown, a photolithography process is carried out on the preliminary first doping region 310 and the preliminary second doping region 320. A photoresist (positive photoresist) with a thickness of 12000 - 15000 Å is coated, exposed and developed to form a mask plate with a specified pattern, and the exposure time is in the range of 10 - 60 s. Then an inductively coupled plasma process (ICP) etching machine is used to etch the preliminary first doping region 310 and the preliminary second doping region 320 with a fluorine-based gas (SF6 / O2), the power is 500 - 1200 W, the pressure is 5 - 10 mtorr, and the etching rate is 200 - 500 nm / min. Grooves are formed in the preliminary first doping region 310 and the preliminary second doping region 320, and the depth is generally greater than 3000 Å. The bottom of the groove is the upper surface of the second epitaxial layer 22. The above-mentioned.

[0062] Among them, the purpose of making the sacrificial oxygen layer is that during the ion implantation and high-temperature activation processes, certain lattice damage will be caused to the surface SiC material, which is extremely rough. Oxidation treatment is carried out on it to oxidize the poor SiC on the surface into SiO2, and then it is etched away. The newly exposed SiC surface is relatively smooth, making the performance of the finally formed device better.

[0063] In some alternative embodiments, as Figure 8 shown, a gate structure 40 is formed between multiple source region structures 30, including: a superlattice layer 45, a first semiconductor layer 41, a second semiconductor layer 42 and a gate 43 are laminated on the bottom of the groove in sequence, the gate 43 protrudes from the groove, and the superlattice layer 45, the first semiconductor layer 41, the second semiconductor layer 42 and the gate 43 form the gate structure 40.

[0064] Exemplarily, as Figure 8As shown, a relatively thin superlattice layer 45 with a thickness of 80 - 100 nm is grown to suppress the defects caused by lattice mismatch. Then, a first semiconductor layer 41 made of GaN and a second semiconductor layer 42 made of AlGaN are epitaxially grown. The thickness of the first semiconductor layer 41 is 180 - 200 nm, and the thickness of the second semiconductor layer 42 is 15 - 25 nm. Finally, a gate 43 made of P-GaN layer is epitaxially grown with a thickness of 80 - 100 nm. The two-dimensional electron gas layer is formed by the internal electric field generated at the interface due to the piezoelectric polarization and spontaneous polarization effects caused by the lattice mismatch between the first semiconductor layer 41 and the second semiconductor layer 42. Among them, the first semiconductor layer 41 is grown by MOCVD epitaxial equipment. The first semiconductor layer 41 is made of GaN material, and the lattice constant between it and the SiC material is very close (the lattice constant difference is about 3%, while the lattice constant difference of GaN epitaxially grown on Si is about 70%). Therefore, there are fewer defects in the first semiconductor layer 41 epitaxially grown on SiC.

[0065] After the epitaxial growth of the superlattice layer 45, the first semiconductor layer 41, the second semiconductor layer 42, and the gate 43 is completed, lithography can be performed according to the groove as an alignment mark. The thickness of the photoresist used is 12000 - 15000 Å. The specified pattern is exposed and developed, and then etched by inductively coupled plasma process (ICP) to etch away the film layer located on the source region structure 30. In the ICP process, a Cl2 / BCl3 mixed gas can be used, the radio frequency power is controlled at 60 - 100 W, and the pressure is 5 - 10 mTorr. In this way, the etching rate is slower, and the etching damage to the superlattice layer 45, the first semiconductor layer 41, the second semiconductor layer 42, and the gate is smaller. In addition, the etching rate of the SiC film layer under this condition is about 10 nm / min, and it will not over-etch the source region structure 30 after etching the first semiconductor layer 41. The etching can stop in time on the surface of the source region structure 30. After etching, the photoresist is removed and the cleaning is carried out.

[0066] After the gate structure is formed, the preparation method further includes: growing a layer of Al2O3 layer with a thickness of 2 - 3 nm on the source region structure and the gate structure by an atomic layer deposition device, aiming to passivate the surface damage caused, reduce the interface states, and then growing a layer of silicon dioxide layer (PEOX) with a thickness of 2000 - 3000 Å as the second passivation layer by chemical vapor deposition; then performing photolithography, the photoresist for photolithography is positive photoresist with a thickness of 14000 - 16000 Å, exposing and developing to form a specified pattern to form a mask plate, and the exposure time is 10 - 60 s. When etching, an Applied Materials 5200 etcher is used to etch off the PEOX layer and the Al2O3 layer, and the process parameters include: using a CF4 / BCl3 / Ar mixed gas, with a power of 400 - 600 W, a pressure of 5 - 10 mTorr, and an etching rate of 150 - 400 nm / min. The positions of the first lead-out part and the second lead-out part are prepared, and after etching, the photoresist is removed and cleaned.

[0067] After the step of etching the composite passivation layer, a TiN layer is grown as the ohmic contact layer of the source region structure 30 and the Schottky contact layer of the gate structure 40 by physical vapor deposition growth method, with a growth thickness of 50 - 100 nm. After completion, high-temperature rapid annealing is carried out at a temperature of 600 - 700 °C for 2 - 5 min, so that the formed TiN layer can form a better Schottky contact with the gate 43, reduce the gate reverse leakage, and the Ti in the formed TiN layer forms an ohmic contact with the second doped layer of the source region structure 30. Then a layer of AlCu / TiN layer is grown on the TiN layer, where the thickness of the AlCu layer is 800 - 1000 nm and the thickness of the TiN layer is 40 - 60 nm, and photolithography or etching is performed on it to etch out the morphologies of the first lead-out part 60 and the second lead-out part 70. Among them, the photoresist used in the photolithography process is positive photoresist with a thickness of 30000 - 35000 Å, and the exposure time is 20 - 80 s. The metal etching uses a North China Chuang 508 etcher, uses a Cl2 / BCl3 / Ar mixed gas, with a power of 400 - 1000 W, a pressure of 5 - 15 mTorr, and an etching rate of 200 - 600 nm / min.

[0068] Then the substrate is thinned to 150 - 200 μm, a metal Ni with a thickness of 80 - 100 nm is grown on the back of the substrate as the ohmic contact layer, and laser annealing is carried out to activate it to form the ohmic contact on the back of the device. Then C is removed, and finally a metal layer Ti / Ni / Ag is grown, where the thickness of Ti is 60 - 100 nm, the thickness of Ni is 100 - 300 nm, and the thickness of Ag is 600 - 1000 nm, for forming the third lead-out part 80.

[0069] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for preparing a silicon carbide semiconductor device of the present application will be described in detail below in conjunction with specific embodiments.

[0070] This embodiment relates to a specific method for preparing a silicon carbide semiconductor device, comprising the following steps:

[0071] Step S1: providing a substrate, and sequentially forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on one side of the substrate;

[0072] Step S2: performing a first ion implantation in the third epitaxial layer to form a preliminary first doping region, and performing a second ion implantation in the first doping region to form a preliminary second doping region;

[0073] Step S3: etching the prepared first doping region and the prepared second doping region to form grooves therein, thereby forming the first doping region and the second doping region;

[0074] Step S4: forming a superlattice layer, a first semiconductor layer, a second semiconductor layer and a gate in sequence in the groove, wherein the gate protrudes from the groove;

[0075] Step S5: Covering the gate and source region structures with a composite passivation layer;

[0076] Step S6: forming a first lead-out portion and a second lead-out portion on the composite passivation layer, wherein the first lead-out portion penetrates the composite passivation layer and contacts the gate, and the second lead-out portion penetrates the composite passivation layer and contacts the first doped region;

[0077] Step S7: thinning the substrate to form a third lead-out portion on a side of the substrate away from the first epitaxial layer.

[0078] The silicon carbide semiconductor device and the manufacturing method described above can achieve the following beneficial effects:

[0079] 1) The gate oxide structure of the silicon carbide device in the prior art is replaced by forming a first semiconductor layer and a second semiconductor layer between the epitaxial layer and the gate, and a two-dimensional electron gas layer with extremely high electron mobility is formed at the contact interface of the first semiconductor layer and the second semiconductor layer. The mobility of the two-dimensional electron gas layer is 20 to 40 times higher than that of the conventional gate oxide structure. This application is equivalent to contributing high mobility to the silicon carbide device by replacing the gate oxide structure with a two-dimensional electron gas layer, thereby solving the problem of low channel mobility of the silicon carbide device in the prior art.

[0080] 2) The channel mobility of silicon carbide semiconductor devices is improved, which also increases the switching speed of the device and enhances the high-frequency performance of the device.

[0081] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A silicon carbide semiconductor device, characterized in that, Comprising: A substrate; An epitaxial layer; A plurality of source region structures, spaced apart on a side of the epitaxial layer facing away from the substrate; A gate structure, located between the source region structures, the gate structure including a first semiconductor layer, a second semiconductor layer, and a gate stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer being formed at an interface between the first semiconductor layer and the second semiconductor layer, and the gate being located on a side of the second semiconductor layer facing away from the substrate.

2. The silicon carbide semiconductor device according to claim 1, wherein The gate structure further includes: a superlattice layer, the superlattice layer being located between the first semiconductor layer and the epitaxial layer.

3. The silicon carbide semiconductor device according to claim 1, characterized in that, The material of the first semiconductor layer includes gallium nitride and gallium arsenide, the material of the second semiconductor layer includes aluminum gallium nitride and aluminum gallium arsenide, and the material of the gate includes gallium nitride and gallium arsenide.

4. The silicon carbide semiconductor device according to claim 1, characterized in that, The source region structure includes: a first doped region and a second doped region stacked in sequence along the thickness direction of the substrate, wherein, The first doped region is located on a side of the epitaxial layer facing away from the substrate, and the first doped region has a first doping type; the second doped region is located on a side of the first doped region facing away from the substrate, and the second doped region has a second doping type; A first surface is provided on a side of the first semiconductor layer facing away from the substrate, a second surface is provided on a side of the first doped region facing away from the substrate, and the minimum distance from the first surface to the substrate is equal to the minimum distance from the second surface to the substrate.

5. The silicon carbide semiconductor device according to claim 1, wherein The semiconductor device further includes a composite passivation layer, the composite passivation layer being located on a side of the source region structure and the gate structure facing away from the substrate, and the composite passivation layer includes a stacked metal oxide layer and non-metal oxide layer.

6. The silicon carbide semiconductor device according to claim 5, characterized in that, The semiconductor device further includes a first lead-out portion, a second lead-out portion, and a third lead-out portion, wherein, The first lead-out portion penetrates through the composite passivation layer and contacts the gate, the second lead-out portion penetrates through the composite passivation layer and contacts the source region structure, and the third lead-out portion contacts the substrate.

7. The silicon carbide semiconductor device according to claim 6, wherein A first region in contact with the gate is provided in the first lead-out portion, a second region in contact with the source region structure is provided in the second lead-out portion, and the materials of the first region and the second region include titanium-containing metal compounds.

8. A method for preparing a silicon carbide semiconductor device, characterized in that For manufacturing the silicon carbide semiconductor device according to any one of claims 1 to 7, the manufacturing method includes: Providing a substrate and forming an epitaxial layer on one side of the substrate; Forming a plurality of spaced-apart source region structures on one side of the epitaxial layer; Forming a gate structure between the plurality of source region structures, the gate structure including a first semiconductor layer, a second semiconductor layer, and a gate stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer being formed at an interface between the first semiconductor layer and the second semiconductor layer, and the gate being located on a side of the second semiconductor layer facing away from the substrate.

9. The preparation method according to claim 8, wherein The step of forming a plurality of spaced-apart source region structures on one side of the epitaxial layer includes: Successively forming a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer on the substrate; Performing a first implantation in the third epitaxial layer to form a preliminary first doped region; A second implantation is performed in the preliminary first doped region to form a preliminary second doped region, and the implantation depth of the preliminary second doped region is less than that of the preliminary first doped region; The preliminary first doped region and the preliminary second doped region are etched to form grooves in the preliminary first doped region and the preliminary second doped region. The remaining preliminary first doped region forms a first doped region, and the remaining preliminary second doped region forms a second doped region. The first doped region and the second doped region form the source region structure.

10. The preparation method according to claim 9, characterized in that, The step of forming the gate structure between the plurality of source region structures includes: A superlattice layer, the first semiconductor layer, the second semiconductor layer, and the gate are sequentially stacked on the bottom of the groove. The gate protrudes from the groove, and the superlattice layer, the first semiconductor layer, the second semiconductor layer, and the gate form the gate structure.

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