Terminal structure preparation method and chip

Abstract

The invention belongs to the technical field of power devices, and provides a preparation method of a terminal structure and a chip, an N-type drift region is formed on the front surface of an N-type silicon carbide substrate, a main junction is formed on the N-type drift region, a tail end preset region of the main junction is etched to form a tail groove, so that a first roll angle of the tail groove is smaller than 16 degrees, and a second roll angle of the tail groove is smaller than 16 degrees. The second side wall of the tail trench extends to the edge of the chip, and a field limiting ring region is arranged between the first side of the tail trench and the main junction, so that the terminal length is effectively reduced under the condition of ensuring the voltage resistance of the device by combining the field limiting ring, the junction termination extension region and the trench structure only through a mask process of adding the junction termination extension region and the tail trench; and the area occupation of the chip is reduced.

Description

Technical Field

[0001] This application belongs to the technical field of power devices, and particularly relates to a preparation method and a chip for a terminal structure. Background Art

[0002] As a new generation of wide-bandgap semiconductor material, silicon carbide has excellent performance in harsh environments such as high voltage, high temperature, and high frequency. Therefore, it has broad application prospects in the fields of power electronics, rail transit, etc. However, due to the limited size of semiconductor devices, there is an electric field concentration effect at the edge of the main junction, which easily leads to premature breakdown of the device and reduces the breakdown voltage performance of the device. To alleviate this problem, it is usually necessary to set a terminal protection structure at the edge of the device. Common terminal structures include field plates, field limiting rings, junction terminal extensions, etc.

[0003] Although the traditional field limiting ring terminal structure can effectively improve the breakdown voltage of the device, it needs to introduce multiple field limiting ring circular regions, resulting in a large chip area occupied by the terminal structure and increasing the production cost. Although the junction terminal extension technology can reduce the terminal length, its efficiency of reducing the surface electric field is not high, the terminal area is still large, and it is very sensitive to the implantation dose, and the process window is small. Summary of the Invention

[0004] To solve the above technical problems, the embodiments of this application provide a preparation method and a chip for a terminal structure. By forming a tail groove in the N-type drift region and etching the tail groove so that the inclination angle of its first sidewall is less than 16°, the terminal length can be effectively reduced while ensuring the breakdown voltage, and the occupied area of the terminal can be reduced.

[0005] The first aspect of the embodiments of this application provides a preparation method for a terminal structure, and the preparation method for the terminal structure includes: Providing an N-type silicon carbide substrate and forming an N-type drift region on the front surface of the N-type silicon carbide substrate; Forming a main junction on the N-type drift region; Etching in a preset region at the end of the main junction to form a tail groove; wherein, the inclination angle of the first side of the tail groove is less than 16°, and the field limiting ring region is between the first side of the tail groove and the main junction.

[0006] In some embodiments, before etching in the preset region at the end of the main junction to form a tail groove, it further includes: Injecting P-type impurities into the field limiting ring region to form a field limiting ring structure; wherein, the field limiting ring structure includes a plurality of spaced field limiting rings; Superimposing and injecting P-type impurities into the field limiting ring region to form a junction terminal extension region; wherein, the junction terminal extension region covers the field limiting ring region and extends to the tail groove.

[0007] In some embodiments, after etching a tail groove in a preset area at the end of the main junction, the method further includes: Injecting P-type impurities into the field limiting ring area to form a field limiting ring structure; wherein, the field limiting ring structure includes a plurality of spaced field limiting rings; Superposing and injecting P-type impurities into the field limiting ring area to form a junction termination extension region; wherein, the junction termination extension region covers the field limiting ring area and extends to the tail groove.

[0008] In some embodiments, injecting P-type impurities into the field limiting ring area to form a field limiting ring structure includes: Injecting P-type impurities into a preset area in the field limiting ring area by using multiple masks and multiple doping ion implantation processes to form a plurality of spaced field limiting rings; wherein, the junction depth of the field limiting ring is 1um, and the junction concentration of the field limiting ring shows an approximately skewed distribution with the highest concentration near the interface.

[0009] In some embodiments, superposing and injecting P-type impurities into the field limiting ring area to form a junction termination extension region includes: Superposing and injecting P-type impurities into the field limiting ring area to form a junction termination extension region covering the field limiting ring area; wherein, the doping concentration of the junction termination extension region shows a box-shaped distribution.

[0010] In some embodiments, after superposing and injecting P-type impurities into the field limiting ring area to form a junction termination extension region, the method further includes: Etching an area on each field limiting ring to form a field limiting ring isolation groove, and filling an insulating dielectric material in the field limiting ring isolation groove; wherein, the depth of the field limiting ring isolation groove is less than or equal to the thickness of the junction termination extension region.

[0011] In some embodiments, after etching a tail groove in a preset area at the end of the main junction, the method further includes: Depositing an insulating dielectric material to form an insulating dielectric material layer; wherein, the insulating dielectric material layer fills the tail groove and covers the area between the end of the main junction and the edge of the chip; Forming a first electrode layer in contact with the main junction, and forming a second electrode layer on the back of the N-type silicon carbide substrate.

[0012] In some embodiments, etching a tail groove in a preset area at the end of the main junction includes: Define the tail groove region using a hard mask, and etch the tail groove region on the N-type drift region under the protection of the hard mask to form the tail trench; wherein, the first side inclination angle of the tail trench is related to the etching time, etching ion gas ratio, energy, angle of the dry etching process, and the thickness of the hard mask.

[0013] In some embodiments, etching to form a tail trench in a preset region at the end of the main junction includes: Define the tail groove region using a hard mask or photoresist, and etch the tail groove region on the N-type drift region using a wet etching process under the protection of the hard mask to form the tail trench; wherein, the first side inclination angle of the tail trench is related to the etching time, etching solution concentration, energy, and the thickness of the hard mask or photoresist.

[0014] The second aspect of the embodiments of the present application also provides a chip, including a silicon carbide power device, and the silicon carbide power device includes a terminal structure prepared by the preparation method of the terminal structure as described in any one of the above.

[0015] The beneficial effects of the embodiments of the present application: An N-type drift region is formed on the front surface of the N-type silicon carbide substrate, a main junction is formed on the N-type drift region, and a tail trench is etched in a preset region at the end of the main junction, so that the first side inclination angle of the tail trench is less than 16°, and the second side wall of the tail trench extends to the edge of the chip. Among them, the field limiting ring region is between the first side of the tail trench and the main junction. Therefore, by only adding the mask processes for the junction termination extension region and the tail trench, combining the field limiting ring, the junction termination extension region, and the trench structure, while ensuring the breakdown voltage performance of the device, the terminal length is effectively reduced, and the area occupied by the chip is reduced. Description of the Drawings

[0016] Figure 1 is a schematic flow chart of the preparation method of the terminal structure provided by the embodiments of the present application; Figure 2 is a schematic flow chart of the preparation method of the terminal structure provided by the embodiments of the present application; Figure 3 is a schematic flow chart of the preparation method of the terminal structure provided by the embodiments of the present application; Figure 4 is a schematic flow chart of the preparation method of the terminal structure provided by the embodiments of the present application; Figure 5 is a schematic flow chart of the preparation method of the terminal structure provided by the embodiments of the present application; Figure 6 is a schematic process diagram of the preparation method of the terminal structure provided by the embodiments of the present application; Figure 7It is a process schematic diagram of a preparation method of a terminal structure provided by an embodiment of the present application; Figure 8 It is a process schematic diagram of a preparation method of a terminal structure provided by an embodiment of the present application; Figure 9 It is a process schematic diagram of a preparation method of a terminal structure provided by an embodiment of the present application; Figure 10 It is a structure schematic diagram of a terminal structure prepared by a preparation method of a terminal structure provided by an embodiment of the present application; Figure 11 It is a withstand voltage schematic diagram of a silicon carbide device terminal structure and a traditional terminal structure provided by an embodiment of the present application; Figure 12 It is an electric field distribution schematic diagram of a traditional terminal structure; Figure 13 And Figure 14 It is an electric field distribution schematic diagram of a silicon carbide device terminal structure provided by an embodiment of the present application; Figure 15 It is a relationship schematic diagram between the tail groove inclination angle and the withstand voltage of a terminal structure provided by an embodiment of the present application; Figure 16 It is a relationship schematic diagram between JTE doping and withstand voltage of a terminal structure provided by an embodiment of the present application. Detailed implementation manners

[0017] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] Although the existing field limiting ring terminal structure can improve the breakdown voltage of the device, it is necessary to introduce multiple field limiting ring annular regions, resulting in a large chip area occupied by the terminal structure and increasing the production cost. Moreover, although the junction terminal extension technology can reduce the terminal length, its efficiency of reducing the surface electric field is not high, and the terminal area is still large, so the chip utilization rate cannot be effectively improved.

[0019] To solve the above technical problems, an embodiment of the present application provides a preparation method of a terminal structure. As shown in Figure 1 、 Figures 6 - 9 , the preparation method of the terminal structure in this embodiment at least includes step S100 to step S300.

[0020] In step S100, an N-type silicon carbide substrate 210 is provided, and an N-type drift region 220 is formed on the front surface of the N-type silicon carbide substrate 210.

[0021] In step S200, a main junction 310 is formed on the N-type drift region 220.

[0022] In step S300, an etching is performed on a preset region at the end of the main junction 310 to form a tail trench 710.

[0023] In this embodiment, through an etching process, an etching is performed on a preset region at the end of the main junction 310 to obtain a tail trench 710 with a first side inclination angle less than 16°. A preset field limiting ring region is provided between the first side of the tail trench 710 and the main junction 310. The junction termination extension region within the preset field limiting ring region is truncated by the tail trench 710, changing from a cylindrical junction to a planar junction, reducing electric field concentration, thereby greatly improving the breakdown voltage of the device. Under the same breakdown voltage requirement, the width of the terminal structure in this embodiment is smaller than that of the traditional field limiting ring terminal, saving the chip area.

[0024] In some embodiments, the second sidewall of the tail trench 710 extends to the chip edge.

[0025] In some embodiments, the first sidewall of the tail trench 710 is close to the preset field limiting ring region, and the first sidewall inclination angle is the angle between the first sidewall of the tail trench 710 and the horizontal plane of the N-type drift region 220. In a 1200V breakdown voltage device, a safety margin of 20% is generally required, so the actual breakdown voltage is greater than 1500V. As shown in the model simulation diagram in Figure 15 , when the angle between the first sidewall of the tail trench 710 and the horizontal plane of the N-type drift region 220 is less than 16 degrees, the breakdown voltage of the breakdown voltage device is greater than 1500V. By setting the tail trench 710 with a first side inclination angle less than 16°, the junction termination extension region within the preset field limiting ring region is truncated, changing from a cylindrical junction to a planar junction, reducing electric field concentration, thereby greatly improving the breakdown voltage of the device. Under the same breakdown voltage requirement, the width of the terminal structure in this embodiment is smaller than that of the traditional field limiting ring terminal, saving the chip area.

[0026] In some embodiments, as shown in Figure 2 , before step S300: performing an etching on a preset region at the end of the main junction 310 to form the tail trench 710, steps S410 and S420 are further included.

[0027] In step S410, a P-type impurity is implanted in the field limiting ring region to form a field limiting ring structure.

[0028] In this embodiment, as shown in Figure 6 and Figure 7 , before etching the tail trench 710, in Figure 6 and Figure 7Based on the schematic structure (a), a field limiting ring structure can be formed by implanting P-type impurities in the field limiting ring region through an ion implantation process, obtaining Figure 6 and Figure 7 the schematic structure (b) in, wherein, the main junction 310 in step S200 and the field limiting ring structure in step S410 can share the same mask, thus, one mask can be saved.

[0029] Combined with Figure 6 and Figure 7 the schematic structure (b) in, the field limiting ring structure includes a plurality of spaced field limiting rings 410, the widths of the plurality of spaced field limiting rings 410 can be determined by the pattern of the ion implantation mask, and the ion implantation depth and ion doping concentration of the plurality of spaced field limiting rings 410 can also be made different through multiple masks.

[0030] In step S420, P-type impurities are implanted in the field limiting ring region in a superposed manner to form a junction termination extension region 510.

[0031] In this embodiment, combined with Figure 6 and Figure 7 the schematic structure (c) in, a plurality of junction termination extension regions 510 cover the field limiting ring region and extend to the tail groove 710.

[0032] In some embodiments, as shown in combination with Figure 3 shown, after step S300: etching a tail groove in a preset region at the end of the main junction, steps S410 and S420 are further included.

[0033] In step S410, P-type impurities are implanted in the field limiting ring region to form a field limiting ring structure.

[0034] Combined with Figure 8 shown, based on the schematic structure (a) in Figure 8 an etching mask 602 is formed, and etching is performed under the coverage of the etching mask 602 to obtain Figure 8 the schematic structure (b) in, after the etching process of the tail groove 710 is completed, P-type impurities are implanted in the field limiting ring region through an ion implantation process to form a field limiting ring structure, obtaining Figure 8 the schematic structure (c) in, the field limiting ring structure includes a plurality of spaced field limiting rings 410.

[0035] In some embodiments, as shown in combination with Figure 8 the schematic structure (c) in, the inclination angle of the first sidewall of the tail groove 710 is less than 16°, and the second side of the tail groove 710 extends to the chip edge.

[0036] In step S420, P-type impurities are implanted in the field limiting ring region in a superposed manner to form a junction termination extension region.

[0037] In this embodiment, as shown in the schematic structure (d) in Figure 8 , the junction termination extension region 510 covers the field limiting ring region and extends to the tail groove 710.

[0038] In some embodiments, the order of step S410 and step S420 can be swapped.

[0039] In some embodiments, step S300 can also be arranged between step S410 and step S420.

[0040] In some embodiments, the JTE junction depth concentration of the field limiting ring 410 shows a typical box-like distribution.

[0041] In some embodiments, the JTE junction depth of the field limiting ring 410 is about 0.5 μm.

[0042] In some embodiments, the sidewall inclination angle of the field limiting ring 410 is less than 90°, which can reduce the electric field concentration caused by the curvature effect.

[0043] In some embodiments, the depth range of the tail groove 710 is 0.6 - 0.7 μm.

[0044] In some embodiments, the range of the second sidewall inclination angle of the tail groove 710 is between 0° and 90°.

[0045] In some embodiments, as shown in the schematic structure (d) in Figure 8 , the second sidewall inclination angle of the tail groove 710 is 0°, and the second side of the tail groove 710 extends to the chip edge.

[0046] In some embodiments, the second sidewall inclination angle of the tail groove 710 is 90°.

[0047] In some embodiments, the distance that the junction termination extension region 510 extends from the end of the main junction 310 beyond the field limiting ring 410 ranges from 15 - 20 μm.

[0048] In some embodiments, the junction termination extension region 510 (i.e., the JTE structure) can be formed by superposing and implanting P-type doping ions (such as aluminum ions, etc.) in the field limiting ring region, and the junction depth of the junction termination extension region 510 is less than or equal to three-fifths of the junction depth of the field limiting ring 410.

[0049] In some embodiments, in step S420, the junction termination extension region 510 includes a lightly doped region surrounding the main junction 310, and the doping concentration is generally 10 16 cm -3 ~10 18 cm -3 .

[0050] In some embodiments, in step S420, the doping concentration of the junction termination extension region 510 gradually decreases from the main junction 310 outward, which can be formed by multiple masks and multiple ion implantation processes, and the depth of the junction termination extension region 510 can also gradually decrease from the main junction 310 outward. When a reverse bias is applied, the depletion layer of the main junction extends laterally to the JTE region, causing the electric field distribution to "disperse" outward from the edge of the main junction, distributing the high voltage over a longer lateral distance. Moreover, by truncating the junction termination extension region 510 through the tail groove 710, the original cylindrical junction becomes a planar junction, reducing the electric field concentration, thereby significantly improving the breakdown voltage of the device. Under the same breakdown voltage requirement, the width of the terminal structure in this embodiment is smaller than that of the traditional field limiting ring terminal, saving the chip area.

[0051] In some embodiments, the depth of the junction termination extension region 510 can be gradually decreased from the main junction 310 outward by multiple P-type doping ion implantations with different energies, achieving a JTE structure with a gradually changing depth.

[0052] In some embodiments, in step S420, multiple junction termination extension regions 510 are provided on the N-type drift region 220. The multiple junction termination extension regions 510 can introduce different amounts of additional charges in different regions, further optimizing the electric field distribution and improving the breakdown voltage capability. The junction termination extension region 510 has relatively high requirements for process control, and parameters such as the dose and depth of ion implantation need to be precisely controlled to ensure that the doping concentration and width of the extension region meet the design requirements.

[0053] In some embodiments, in step S410, it can be formed by multiple P-type doping ion implantations on the N-type drift region 220, such that the junction concentration of the field limiting ring 410 shows an approximately skewed distribution, with the highest concentration near the interface.

[0054] In this embodiment, the approximately skewed distribution of the junction concentration of the field limiting ring 410 can be an asymmetric Gaussian distribution. The P-type doping ion implantation of the field limiting ring region can be performed with multiple P-type impurities, making the concentration near the surface relatively high. Ions at the edge of the mask during implantation may scatter into the area below the mask, resulting in a higher concentration near the interface than in the central region. High-temperature annealing causes the implanted ions to diffuse toward the surface and laterally, further strengthening the concentration near the interface.

[0055] In some embodiments, by performing P-type doping ion implantation on the field limiting ring region with multiple P-type impurities, the implantation concentrations of multiple field limiting rings 410 change gradually laterally or are distributed in multiple levels, which can smooth the electric field peak.

[0056] In some embodiments, the field limiting ring 410 is a P-type ring, and the junction depth of the field limiting ring 410 is about 1 μm.

[0057] In some embodiments, the P-type ring is a commonly used terminal structure in power semiconductor devices. It is a P-type ring-shaped structure with the same type of doping set near the main junction 310. Under reverse bias, the electric lines generated by the ionized acceptors in the P-type ring interact with the electric lines emitted by the ionized donors in the N region of the main junction 310, which is equivalent to introducing additional charges near the main junction 310. The electric field generated by these additional charges is opposite to the direction of the electric field of the main junction 310, thereby weakening the peak value of the electric field of the main junction 310, reducing the curvature effect of the main junction 310, expanding the depletion region width, optimizing the electric field distribution, and increasing the breakdown voltage of the device.

[0058] In some embodiments, there can be one or more P-type rings, which can be fabricated in the same process as the main junction 310. By adjusting process parameters such as the spacing, junction depth, and ion implantation concentration of the P-type ring, the breakdown voltage performance can be adjusted. The P-type ring structure design is relatively simple, the process implementation difficulty is low, and it can be formed by simultaneous diffusion with the main junction 310 without adding additional process steps.

[0059] In some embodiments, the number of P-type rings is greater than 2, and can be set to 4 or 5.

[0060] In some embodiments, the tail groove 710 is formed at the end of the JTE structure. The depth of the tail groove 710 is about 0.6 - 0.7 μm, the groove inclination angle is less than 16 degrees, and the groove is filled with an insulating medium. It can effectively reduce the terminal length while ensuring the breakdown voltage performance of the device, reducing the area occupation by about 40% - 60%. Only the mask processes for the JTE and the groove need to be added, and the process is simple and the cost is low.

[0061] Combined Figure 16 As shown, when the doping dose of the junction termination extension region 510 is between 3.5E12 - 4.0E12 cm -2 the breakdown voltage of the voltage-resistant device is greater than 1500V. By setting the angle between the first sidewall of the tail groove 710 and the horizontal plane of the N-type drift region 220 to be less than 16 degrees, a wider ion implantation range of the doping dose of the junction termination extension region 510 can be obtained, reducing the influence of the doping concentration on the breakdown voltage range of the device, which is beneficial to improving the breakdown voltage stability of the device.

[0062] In some embodiments, step S410: Injecting P-type impurities into the field limiting ring region to form a field limiting ring structure includes: Injecting P-type impurities into a preset region in the field limiting ring region using multiple masks and multiple doping ion implantation processes to form multiple spaced field limiting rings 410.

[0063] In this embodiment, the junction depth of the field limiting ring 410 is 1 μm, and the junction concentration of the field limiting ring 410 shows an approximately skewed distribution, with the highest concentration near the interface.

[0064] In some embodiments, step S420: implanting P-type impurities in a field limiting ring region to form a junction termination extension region 510 includes: implanting P-type impurities in a field limiting ring region to form a junction termination extension region 510 covering the field limiting ring region.

[0065] In this embodiment, the doping concentration of the junction termination extension region 510 is distributed in a box shape.

[0066] In some embodiments, combined Figure 4 As shown, step S410: implanting P-type impurities in the field limiting ring region to form a junction termination extension region, and then further includes: etching a region on each of the field limiting rings 410 to form a field limiting ring isolation trench 720, and filling an insulating dielectric material in the field limiting ring isolation trench 720.

[0067] In this embodiment, as Figure 10 shown, the depth of the field limiting ring isolation trench is less than or equal to the thickness of the junction termination extension region. A field limiting ring isolation trench 720 is provided on each of the field limiting rings 410, so that the shape of the vertical cross-section of the field limiting ring 410 is concave, which is beneficial to extending the length of the JTE structure between the main junction 310 and the chip edge, improving the breakdown voltage performance of the device, effectively reducing the terminal length, and reducing the area occupation of the chip.

[0068] In some embodiments, the field limiting ring isolation trench 720 and the tail trench 710 can share the same mask, and the field limiting ring isolation trench 720 can be obtained by etching the region on the field limiting ring 410 through an etching mask in the schematic structure (c) in Figure 6 、 Figure 7 、 Figure 9 . The depth of the field limiting ring isolation trench 720 is the same as the depth of the tail trench 710.

[0069] In some embodiments, combined Figure 5 As shown, step S300: after etching a tail trench in a preset region at the end of the main junction, further includes step S510 and step S520.

[0070] In step S510, an insulating dielectric material is deposited to form an insulating dielectric material layer.

[0071] In this embodiment, combined Figures 6 - 9 with the schematic structure (e) in, the insulating dielectric material layer 610 fills the tail trench 710 and covers the region between the end of the main junction and the chip edge.

[0072] In step S520, a first electrode layer 120 in contact with the main junction 310 is formed, and a second electrode layer 110 is formed on the back of the N-type silicon carbide substrate 210.

[0073] In this embodiment, combinedFigures 6 - 9 As shown in the schematic structure (f), the first electrode layer 120 can be formed on the main junction 310 by depositing an electrode material, and the second electrode layer 110 can be formed on the back surface of the N-type silicon carbide substrate 210.

[0074] In some embodiments, step S300: etching a tail groove in a preset area at the end of the main junction, includes: defining the tail groove area using a hard mask, and etching the tail groove area on the N-type drift region under the protection of the hard mask by adjusting a dry etching process to form the tail groove.

[0075] In this embodiment, in combination with Figure 6 As shown in the schematic structure (d), a tail groove 710 with a specific inclined plane angle is formed by combining a hard mask 601 with dry etching. The first side inclination angle of the tail groove 710 is related to the etching time, etching ion gas ratio, energy, angle of the dry etching process, and the thickness of the hard mask 601.

[0076] In some embodiments, step S300: etching a tail groove in a preset area at the end of the main junction, includes: defining the tail groove area using a hard mask or photoresist, and etching the tail groove area on the N-type drift region under the protection of the hard mask by using a wet etching process to form the tail groove.

[0077] In this embodiment, in combination with Figure 7 As shown in the schematic structure (d), the tail groove area is defined by a hard mask 601 or photoresist 602. Under the protection of the hard mask 601 or photoresist 602, a tail groove 710 with a specific inclined plane angle is formed by combining a wet etching process. The first side inclination angle of the tail groove 710 is related to the etching time, etching solution concentration, energy, and the thickness of the hard mask or photoresist.

[0078] In some embodiments, in combination with Figure 11 As shown, under the same EPI conditions, the breakdown voltage (BV) of a silicon carbide device with a conventional terminal structure S10 is 1586V, and a silicon carbide power device with a silicon carbide device terminal structure S20 shown in the schematic structure (f) Figures 6 - 9 has a BV of 1764V. The silicon carbide power device with the silicon carbide device terminal structure shown in the schematic structure (f) Figures 6 - 9 has a higher breakdown voltage.

[0079] In some embodiments, in combination with Figure 12 As shown, when a voltage of 1586V is applied to the first electrode layer 120, its electric field distribution is as shown in Figure 12 shown, Figures 6 - 9The peak electric field of the SiC device terminal structure shown in the schematic structure (f) is located on the right side of the 4th ring. At the same time, the left inclined plane of the trench also plays a certain pressure-bearing role. The electric field on the right side of the 4th ring is much stronger than that on the left inclined plane of the trench, indicating that there is still room for optimization and improvement in this terminal structure. The electric field between the two points shows an ideal box-shaped distribution, and the model will reach the optimal when the electric field on the right side of the 4th ring is close to that on the left inclined plane of the trench. When a voltage of 1586V is applied to the first electrode layer 120 of the SiC device with a traditional terminal structure, its electric field distribution is as Figure 12 shown, and the peak electric field of the FLRs is located on the right side of the 6th - 7th rings adjacent to the main junction. Combining the Figure 12 traditional terminal structure in, the length of the FLRs terminal except the main junction is 110μm. When a voltage of 1586V is applied, its electric field distribution is as Figure 13 and Figure 14 shown. The length except the main junction mentioned above is only 43μm. Figure 13 and Figure 14 The horizontal coordinate Y in represents the lateral distance of the terminal structure, and Figure 13 the vertical coordinate X in represents the longitudinal distance of the terminal structure. Figure 14 The vertical coordinate in represents the electric field strength. Combining Figure 13 and Figure 14 shown, Figures 6 - 9 In the SiC device terminal structure (S20) shown in the schematic structure (f), at the position of the lateral distance of 45um, the electric field on the right side of the 4th ring of its terminal structure is much stronger than that on the left inclined plane of the trench. At this time, Figures 6 - 9 the terminal length shown in the schematic structure (f) is reduced by about 60%.

[0080] The embodiment of the present application also provides a chip, including a SiC power device, and the SiC power device includes a terminal structure prepared by the preparation method of the terminal structure described in any one of the above.

[0081] In this embodiment, the chip includes a chip substrate, and one or more preparation methods of the terminal structure are provided on the substrate. The preparation method of the terminal structure can set the preparation method of the terminal structure in any one of the above embodiments on the chip substrate.

[0082] In some embodiments, the SiC power device can be any one of a SiC MOSFET, a SiC diode, and a SiC IGBT.

[0083] The SiC device terminal structure described in any one of the above embodiments can be applied to any high-voltage power device produced based on SiC materials, including but not limited to SiC MOSFETs, SiC diodes, SiC IGBTs, etc.

[0084] In a specific application embodiment, other relevant semiconductor devices can also be integrated on the chip substrate to form an integrated circuit together with the manufacturing method of the terminal structure.

[0085] In a specific application embodiment, the chip can be a switching chip or a driving chip.

[0086] Advantages of the embodiments of the present application: A field limiting ring structure including multiple field limiting rings is provided at the end of the main junction. By forming a tail groove between the field limiting ring structure and the chip edge, and setting the inclination angle of the first side wall of the tail groove to be less than 16°, the second side wall of the tail groove extends to the chip edge, and the field limiting ring region is covered by multiple junction terminal extension regions and extends to the tail groove. Thus, by combining the field limiting ring, the junction terminal extension region and the groove structure, while ensuring the breakdown voltage performance of the device, the terminal length is effectively reduced, and the area occupied by the chip is reduced.

[0087] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each doping region and device is used as an example. In actual applications, the above-mentioned functions can be allocated to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. Each doping region and device in the embodiment can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0088] In addition, the specific names of each doping region and device are only for the convenience of mutual distinction and do not limit the protection scope of the present application.

[0089] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0090] In addition, each doping region in each embodiment of the present application can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0091] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for preparing a terminal structure, characterized in that The preparation method of the terminal structure includes: Providing an N-type silicon carbide substrate and forming an N-type drift region on the front surface of the N-type silicon carbide substrate; Forming a main junction on the N-type drift region; Etching a tail groove in a preset region at the end of the main junction; wherein, the first side inclination angle of the tail groove is less than 16°, and a field limiting ring region is formed between the first side of the tail groove and the main junction.

2. The manufacturing method of the terminal structure according to claim 1, characterized in that Before etching the tail groove in the preset region at the end of the main junction, it further includes: Injecting P-type impurities into the field limiting ring region to form a field limiting ring structure; wherein, the field limiting ring structure includes a plurality of spaced field limiting rings; Superimposing and injecting P-type impurities into the field limiting ring region to form a junction termination extension region; wherein, the junction termination extension region covers the field limiting ring region and extends to the tail groove.

3. The manufacturing method of the terminal structure according to claim 1, characterized in that, After etching the tail groove in the preset region at the end of the main junction, it further includes: Injecting P-type impurities into the field limiting ring region to form a field limiting ring structure; wherein, the field limiting ring structure includes a plurality of spaced field limiting rings; Superimposing and injecting P-type impurities into the field limiting ring region to form a junction termination extension region; wherein, the junction termination extension region covers the field limiting ring region and extends to the tail groove.

4. The preparation method of the terminal structure according to claim 2 or 3, characterized in that, Injecting P-type impurities into the field limiting ring region to form a field limiting ring structure includes: Injecting P-type impurities into a preset region in the field limiting ring region by using multiple masks and multiple doping ion implantation processes to form a plurality of spaced field limiting rings; wherein, the junction depth of the field limiting ring is 1 μm, and the junction concentration of the field limiting ring shows an approximately skewed distribution, with the highest concentration near the interface.

5. The manufacturing method of the terminal structure according to claim 2 or 3, characterized in that, Superimposing and injecting P-type impurities into the field limiting ring region to form a junction termination extension region includes: Superimposing and injecting P-type impurities into the field limiting ring region to form a junction termination extension region covering the field limiting ring region; wherein, the doping concentration of the junction termination extension region shows a box-shaped distribution.

6. The preparation method of the terminal structure according to claim 2 or 3, characterized in that, After superimposing and injecting P-type impurities into the field limiting ring region to form a junction termination extension region, it further includes: Etching a field limiting ring isolation groove in the region on each field limiting ring and filling an insulating dielectric material in the field limiting ring isolation groove; wherein, the depth of the field limiting ring isolation groove is less than or equal to the thickness of the junction termination extension region.

7. The preparation method of the terminal structure according to any one of claims 1-3, characterized in that, After etching the tail groove in the preset region at the end of the main junction, it further includes: Depositing an insulating dielectric material to form an insulating dielectric material layer; wherein, the insulating dielectric material layer fills the tail groove and covers the region between the end of the main junction and the chip edge. Forming a first electrode layer in contact with the main junction and forming a second electrode layer on the back surface of the N-type silicon carbide substrate.

8. The preparation method of the terminal structure according to any one of claims 1-3, characterized in that, Etching the tail groove in the preset region at the end of the main junction includes: Defining the tail groove region by using a hard mask and adjusting the dry etching process under the protection of the hard mask to etch the tail groove region on the N-type drift region to form the tail groove; wherein, the first side inclination angle of the tail groove is related to the etching time, etching ion gas ratio, energy, angle of the dry etching process, and the thickness of the hard mask.

9. The preparation method of the terminal structure according to any one of claims 1-3, characterized in that Etching is performed in a preset area at the end of the main junction to form a tail groove, including: Defining a tail groove area using a hard mask or photoresist, and etching the tail groove area on the N-type drift region under the protection of the hard mask using a wet etching process to form the tail groove; wherein, the first side inclination angle of the tail groove is related to the etching time, etching solution concentration, energy, and the thickness of the hard mask or photoresist of the wet etching process.

10. A chip, characterized in that, It includes a silicon carbide power device, and the silicon carbide power device includes a terminal structure prepared by the preparation method of the terminal structure according to any one of claims 1-9.

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