Gallium oxide power device and preparation method thereof

Abstract

The invention discloses a gallium oxide power device and a preparation method thereof, and relates to the technical field of semiconductor devices.The gallium oxide power device comprises a first metal electrode layer, an n-type gallium oxide substrate and an n-type gallium oxide epitaxial layer which are sequentially stacked; the side, away from the n-type gallium oxide substrate, of the n-type gallium oxide epitaxial layer is of a boss structure. The gallium oxide power device further comprises a field plate structure layer, one end of which is located on a part of the mesa of the boss structure and the other end of which is suspended; the field plate structure layer comprises a dielectric layer and a second metal electrode layer which are stacked in sequence, and the dielectric layer is attached to the table top of the boss structure part; and the third metal electrode layer is positioned on the table surface of the boss structure which is not covered by the field plate structure layer and is connected with the second metal electrode layer. According to the invention, by introducing the partially suspended field plate structure layer, an extremely high electric field peak value in the dielectric layer is reduced, and breakdown in advance is avoided; meanwhile, electric field distribution of a device terminal area is further optimized, and high breakdown voltage is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a gallium oxide power device and a preparation method thereof. Background Art

[0002] Gallium oxide (Ga2O3) materials have an ultra-wide bandgap of about 4.8eV and an ultra-high critical breakdown field strength of about 8MV / cm, which makes power devices based on gallium oxide materials have a Baliga figure of merit of more than 3000, which is 4 times that of gallium nitride (GaN)-based power devices and 10 times that of silicon carbide (SiC)-based power devices, showing the huge advantages of ultra-high breakdown voltage and low conduction loss. In addition, unlike the third-generation semiconductor gallium nitride and silicon carbide materials, which can only grow substrates through the vapor phase method, gallium oxide substrate materials can be grown through the melt method, and also have the application advantages of high quality and low cost. However, gallium oxide faces the problem of difficult electric field regulation in the terminal region, which greatly limits the improvement of the device breakdown voltage. The main reason is that gallium oxide materials currently lack effective p-type doping, which makes it difficult to directly apply the mature high-voltage terminal design technology in silicon (Si) / silicon carbide-based power devices to gallium oxide power devices, resulting in significant electric field concentration in the device terminal region. Therefore, based on the unique material properties of gallium oxide, developing terminal technology and preparation processes suitable for gallium oxide power devices is of great significance to improving device performance. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a gallium oxide power device and a method for preparing the same, in order to solve the problem that the breakdown voltage of the existing gallium oxide power device needs to be further improved.

[0004] The technical solution of the present invention is as follows:

[0005] A first aspect of the present invention provides a gallium oxide power device, wherein the gallium oxide power device comprises a first metal electrode layer, an n-type gallium oxide substrate and an n-type gallium oxide epitaxial layer stacked in sequence;

[0006] A side of the n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate is a boss structure;

[0007] The gallium oxide power device further comprises:

[0008] A field plate structure layer, one end of which is located on a portion of the platform structure, and the other end is suspended; the field plate structure layer comprises a dielectric layer and a second metal electrode layer stacked in sequence, and the dielectric layer is attached to the portion of the platform structure;

[0009] A third metal electrode layer, which is located on the surface of the boss structure not covered by the field plate structure layer and is connected to the second metal electrode layer.

[0010] Optionally, the thickness of the n-type gallium oxide substrate is 50 - 650 μm;

[0011] The n-type gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 - 10 20 cm －3 ;

[0012] The thickness of the n-type gallium oxide epitaxial layer is 2 - 20 μm;

[0013] The n-type gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 - 10 17 cm －3 .

[0014] Optionally, the thickness of the dielectric layer is 50 - 500 nm;

[0015] The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, and aluminum oxide.

[0016] Optionally, the width of one end of the field plate structure layer located on a part of the surface of the boss structure is 5 - 25 μm, and the width of the suspended end of the field plate structure layer is 200 nm - 1.5 μm.

[0017] Optionally, the gallium oxide power device further includes a passivation layer;

[0018] The passivation layer is located on the uncovered surfaces of the boss structure and the field plate structure layer; or, the passivation layer is simultaneously located on the uncovered surfaces of the boss structure and the field plate structure layer, and on a part of the surface on the side of the connection end of the third metal electrode layer and the second metal electrode layer.

[0019] Optionally, the thickness of the passivation layer is 500 nm - 20 μm, and the material of the passivation layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and polyimide.

[0020] Optionally, the thickness of the first metal electrode layer is 500 nm - 2 μm, and the material of the first metal electrode layer includes at least one of Ti, Ni, Ag, Au, and Ag;

[0021] The thickness of the second metal electrode layer is 50 - 300 nm, and the material of the second metal electrode layer includes at least one of Ni, Mo, W, Au, Pt, and platinum oxide;

[0022] The thickness of the third metal electrode layer is 50 - 300 nm, and the material of the third metal electrode layer includes at least one of Ni, Mo, W, Au, Pt, and platinum oxide.

[0023] In the second aspect of the present invention, a method for manufacturing a gallium oxide power device as described above in the present invention is provided, which includes the following steps:

[0024] Provide an n-type gallium oxide substrate with an n-type gallium oxide epitaxial layer on its surface, and the side of the n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate is a convex structure;

[0025] Prepare a field plate structure layer, one end of the field plate structure layer is located on a part of the tabletop of the convex structure and the other end is suspended. The field plate structure layer includes a dielectric layer and a second metal electrode layer stacked in sequence, and the dielectric layer is attached to the part of the tabletop of the convex structure;

[0026] Prepare a third metal electrode layer, the third metal electrode layer is located on the tabletop of the convex structure not covered by the field plate structure layer and is connected to the second metal electrode layer;

[0027] Prepare a first metal electrode layer, the first metal electrode layer is located on the side of the n-type gallium oxide substrate facing away from the n-type gallium oxide epitaxial layer.

[0028] Optionally, the method for manufacturing the n-type gallium oxide epitaxial layer includes the following steps:

[0029] Provide an n-type gallium oxide substrate with a first n-type gallium oxide epitaxial layer on its surface;

[0030] By inductively coupled plasma etching method, using BCl3, Ar, and Cl2 as etching gases, etch the side of the first n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate to obtain a convex structure, and then obtain an n-type gallium oxide epitaxial layer.

[0031] Optionally, the method for manufacturing the gallium oxide power device further includes the following steps:

[0032] Prepare a passivation layer, the passivation layer is located on the surface of the convex structure and the field plate structure layer not covered, or the passivation layer is simultaneously located on the surface of the convex structure and the field plate structure layer not covered, and on a part of the surface of the connection end side of the third metal electrode layer and the second metal electrode layer.

[0033] Beneficial effects: In the present invention, the field plate structure layer is a partially suspended field plate structure layer. The non-suspended end is connected to the second metal electrode layer (i.e., the anode). That is, the field plate structure layer and the second metal electrode layer are at the same potential, which can make more electric field vector lines in the terminal region terminate on the suspended field plate, greatly reducing the peak electric field in the dielectric layer of the field plate structure layer and avoiding premature breakdown. By introducing the partially suspended field plate structure, the problem of extremely high peak electric field in the dielectric layer of the existing field plate structure terminal device is effectively solved, avoiding its premature breakdown; at the same time, the electric field distribution in the device terminal region is further optimized to achieve a high breakdown voltage. Description of the Drawings

[0034] Figure 1 It is a schematic structural diagram of a gallium oxide power device in an embodiment of the present invention.

[0035] Figure 2 It is a schematic structural diagram of a gallium oxide power device in another embodiment of the present invention.

[0036] Figure 3 It is a schematic diagram of the preparation process of a gallium oxide power device in an embodiment of the present invention, where (a) is a schematic diagram of providing an n-type gallium oxide substrate with a first n-type gallium oxide epitaxial layer on the surface, (b) is a schematic diagram of preparing a first dielectric layer, (c) is a schematic diagram of opening holes in the first dielectric layer to expose part of the first n-type gallium oxide epitaxial layer, (d) is a schematic diagram of preparing a second metal electrode layer and a third metal electrode layer, (e) is a schematic diagram of preparing a dielectric layer, (f) is a schematic diagram of preparing a boss structure, (g) is a schematic diagram of preparing a passivation layer, and (h) is a schematic diagram of preparing a first metal electrode layer.

[0037] Figure 4 It is a test result diagram of the gallium oxide power device in Example 1 and Comparative Example 1, where (a) is a two-dimensional electric field distribution simulation result diagram of the gallium oxide power device in Comparative Example 1, (b) is a two-dimensional electric field distribution simulation result diagram of the gallium oxide power device in Example 1, (c) is the surface electric field distribution curve of the gallium oxide power device in Example 1 and Comparative Example 1 in the tangent direction AA' of FIGS. (a) and (b), and (d) is the surface electric field distribution curve of the gallium oxide power device in Example 1 and Comparative Example 1 in the tangent direction BB' of FIGS. (a) and (b).

[0038] Reference numerals in the drawings:

[0039] 1. First metal electrode layer; 2. n-type gallium oxide substrate; 3. n-type gallium oxide epitaxial layer; 30. First n-type gallium oxide epitaxial layer; 4. Field plate structure layer; 40. First dielectric layer; 41. Dielectric layer; 42. Second metal electrode layer; 5. Third metal electrode layer; 6. Passivation layer. Detailed Embodiments

[0040] The present invention provides a gallium oxide power device and a method for manufacturing the same. To make the objectives, technical solutions, and effects of the present invention clearer and more definite, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] The field plate structure is a terminal technology with both simple process and remarkable effects, and many gallium oxide high-voltage terminal designs are derived therefrom. However, due to the material characteristics of gallium oxide with an ultra-high critical breakdown electric field and a high relative dielectric constant, an extremely high electric field peak will be introduced into the dielectric layer of the field plate structure, resulting in premature breakdown of the dielectric layer, thereby restricting the further increase of the breakdown voltage of the device. Based on this, an embodiment of the present invention provides a gallium oxide power device, wherein the gallium oxide power device includes a first metal electrode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3 that are sequentially stacked;

[0042] One side of the n-type gallium oxide epitaxial layer 3 facing away from the n-type gallium oxide substrate 2 is a convex structure;

[0043] The gallium oxide power device further includes:

[0044] A field plate structure layer 4, one end of the field plate structure layer 4 is located on a part of the tabletop of the convex structure, and the other end is suspended (that is, part of the field plate structure layer is suspended outside the tabletop of the convex structure); the field plate structure layer 4 includes a dielectric layer 41 and a second metal electrode layer 42 that are sequentially stacked, and the dielectric layer 41 is attached to a part of the tabletop of the convex structure;

[0045] A third metal electrode layer 5, the third metal electrode layer 5 is located on the tabletop of the convex structure not covered by the field plate structure layer and is connected to the second metal electrode layer 42.

[0046] In an embodiment of the present invention, the field plate structure layer is a partially suspended field plate structure layer, and the non-suspended end is connected to the second metal electrode layer (i.e., the anode). That is, the field plate structure layer and the second metal electrode layer are at the same potential, which can make more electric field vector lines in the terminal region cut off on the suspended field plate, greatly reducing the electric field peak in the dielectric layer of the field plate structure layer and avoiding premature breakdown. By introducing a partially suspended field plate structure, the problem of extremely high electric field peaks existing in the dielectric layer of the existing terminal device with a field plate structure is effectively solved, and its premature breakdown is avoided; at the same time, the electric field distribution in the terminal region of the device is further optimized to achieve a high breakdown voltage.

[0047] In some embodiments, the width of one end of the field plate structure layer located on the tabletop of the boss structure is 5 - 25 μm (for example, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm or 25 μm, etc.), and the width of the suspended end of the field plate structure layer is 200 nm - 1.5 μm (for example, it can be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm or 1.5 μm, etc.).

[0048] That is to say, the field plate structure layer includes two parts. Among them, one part is located on the tabletop of the boss structure, and the other part is suspended. The width a of the part of the field plate structure layer located on the tabletop of the boss structure is 5 - 25 μm, and the width of the suspended part of the field plate structure layer is 200 nm - 1.5 μm.

[0049] In some embodiments, the thickness of the n-type gallium oxide substrate is 50 - 650 μm, for example, it can be 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm or 650 μm, etc.

[0050] In some embodiments, the n-type gallium oxide substrate is a highly doped n-type gallium oxide substrate, and the doping concentration (i.e., electron concentration) is 10 18 ~10 20 cm －3 (that is, 10 18 ~10 20 per cubic centimeter).

[0051] In some embodiments, the thickness of the n-type gallium oxide epitaxial layer is 2 - 20 μm, for example, it can be 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm, etc.

[0052] In some embodiments, the n-type gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration (i.e., electron concentration) is 10 15 ~10 17 cm －3 (that is, 10 15 ~10 17 per cubic centimeter), for example, it can be 10 15 cm －3 、5×10 15cm －3 , 10 16 cm －3 , 5×10 16 cm －3 or 10 17 cm －3 wait.

[0053] The doping concentration of the n-type gallium oxide epitaxial layer is lower than the doping concentration of the n-type gallium oxide substrate.

[0054] In some embodiments, the thickness of the dielectric layer is 50 to 500 nm. For example, the thickness of the dielectric layer is 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or 500 nm.

[0055] In some embodiments, the material of the dielectric layer includes at least one of silicon oxide (SiO 2 ), silicon nitride (SiN x ) and aluminum oxide (Al 2 O 3 ), but is not limited thereto.

[0056] In some embodiments, the thickness of the first metal electrode layer is 500 nm to 2 μm, for example, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm, etc.

[0057] In some embodiments, the material of the first metal electrode layer includes at least one of Ti, Ni, Ag, Au and Ag, but is not limited thereto.

[0058] In some embodiments, the thickness of the second metal electrode layer is 50-300 nm, for example, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm.

[0059] In some embodiments, the material of the second metal electrode layer includes at least one of Ni, Mo, W, Au, Pt and platinum oxide, but is not limited thereto.

[0060] In some embodiments, the thickness of the third metal electrode layer is 50-300 nm, for example, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm.

[0061] In some embodiments, the material of the third metal electrode layer includes at least one of Ni, Mo, W, Au, Pt and platinum oxide, but is not limited thereto.

[0062] In some embodiments, the second metal electrode and the third metal electrode layer are of an integrally formed structure. In this embodiment, it can also be understood that the third metal electrode layer extends outward to the surface of the dielectric layer, and the third metal layer on the surface of the dielectric layer and the dielectric layer together form a field plate structure layer.

[0063] In some embodiments, as Figure 2 shown, the gallium oxide power device further includes a passivation layer 6;

[0064] The passivation layer 6 is located on the uncovered surfaces of the boss structure and the field plate structure layer 4; or, the passivation layer 6 is simultaneously located on the uncovered surfaces of the boss structure and the field plate structure layer 4, and on a partial surface of the connection end side of the third metal electrode layer 5 and the second metal electrode layer 42.

[0065] That is to say, for the gallium oxide power device, all or part of the third metal electrode layer is exposed through the passivation layer.

[0066] In this embodiment, as Figure 2 shown, the uncovered surfaces of the boss structure and the field plate structure layer refer to all the uncovered surfaces of the boss structure and the field plate structure layer, including the upper surface, the lower surface, and the side surface.

[0067] In some embodiments, the thickness of the passivation layer is 500 nm to 20 μm, and for example, it can be 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm, or 20 μm, etc.

[0068] In some embodiments, the material of the passivation layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and polyimide (PI), but is not limited thereto.

[0069] The embodiment of the present invention also provides a method for manufacturing the gallium oxide power device as described above in the embodiment of the present invention, which includes the following steps:

[0070] Provide an n-type gallium oxide substrate with an n-type gallium oxide epitaxial layer on its surface, and the side of the n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate is a boss structure;

[0071] Prepare a field plate structure layer, one end of the field plate structure layer is located on a partial table surface of the boss structure and the other end is suspended. The field plate structure layer includes a dielectric layer and a second metal electrode layer stacked in sequence, and the dielectric layer is attached to the partial table surface of the boss structure;

[0072] preparing a third metal electrode layer, wherein the third metal electrode layer is located on the table surface of the boss structure not covered by the field plate structure layer and is connected to the second metal electrode layer;

[0073] A first metal electrode layer is prepared, where the first metal electrode layer is located on a side of the n-type gallium oxide substrate away from the n-type gallium oxide epitaxial layer.

[0074] In the embodiment of the present invention, the terminal of the prepared gallium oxide power device is a partially suspended field plate structure layer, and the non-suspended end is connected to the second metal electrode layer (i.e., the anode), that is, the field plate structure layer and the second metal electrode layer are equipotential, which can make the electric field vector lines in the terminal area more terminated on the suspended field plate, greatly reducing the electric field peak in the dielectric layer in the field plate structure layer, and avoiding the occurrence of premature breakdown. By introducing a partially suspended field plate structure, the problem of extremely high electric field peaks in the dielectric layer of existing terminal devices with field plate structures is effectively solved, avoiding premature breakdown; at the same time, the electric field distribution in the terminal area of the device is further optimized to achieve a high breakdown voltage.

[0075] In some embodiments, Figure 3 As shown, the method for preparing the gallium oxide-based power device includes the following steps S1 to S8:

[0076] S1, such as Figure 3 As shown in (a) of FIG. 1 , an n-type gallium oxide substrate 2 having a first n-type gallium oxide epitaxial layer 30 on its surface is provided.

[0077] In this step, the thickness and doping concentration of the first n-type gallium oxide epitaxial layer are the same as those of the n-type gallium oxide epitaxial layer described above; the thickness and doping concentration of the n-type gallium oxide substrate are as described above and will not be described again here.

[0078] In an embodiment, the n-type gallium oxide substrate having the first n-type gallium oxide epitaxial layer on its surface may be firstly subjected to inorganic and organic cleaning before the subsequent steps are performed.

[0079] S2, such as Figure 3 As shown in (b) , a first dielectric layer 40 is formed on the surface of the first n-type gallium oxide epitaxial layer 30 .

[0080] In this step, the thickness and material of the first dielectric layer are the same as the thickness and material of the dielectric layer mentioned above.

[0081] In some embodiments, the first dielectric layer is formed on the surface of the first n-type gallium oxide epitaxial layer by a deposition method, including but not limited to one of plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), inductively coupled plasma chemical vapor deposition (ICPCVD), and magnetron sputtering, but not limited thereto.

[0082] S3. As shown in (b) to (c) of Figure 3 , an opening is made in the first dielectric layer 40 to expose a part of the first n-type gallium oxide epitaxial layer 30.

[0083] In this step, photolithography can be performed on the surface of the first dielectric layer, and the first dielectric layer is opened by a combination of dry and wet etching or wet etching.

[0084] S4. As shown in (d) of Figure 3 , a metal layer is formed in the opening of the first dielectric layer and on a part of the surface of the first dielectric layer 40 to obtain a second metal electrode layer 42 and a third metal electrode layer 5 respectively.

[0085] In this step, the metal layer includes at least one of Ni, Mo, W, Au, Pt, and platinum oxide, and the thickness of the metal layer is the same as that of the second metal electrode layer and the third metal electrode layer in the above text.

[0086] In some embodiments, the metal is deposited in the opening of the first dielectric layer and on a part of the surface of the first dielectric layer by electron beam evaporation or sputtering, and a patterned metal layer is formed by a lift-off process, that is, a second metal electrode layer and a third metal electrode layer are formed.

[0087] S5. As shown in (d) to (e) of Figure 3 , using the patterned metal layer (that is, the second metal electrode layer 42 and the third metal electrode layer 5) as a hard mask, self-aligning with the first dielectric layer 40, and etching by dry etching, wet etching, or a combination of dry and wet etching to form a dielectric layer 41. Then, the dielectric layer and the second metal electrode layer located on the surface of the dielectric layer together form a field plate structure layer 4.

[0088] In this step, by etching away a part of the first dielectric layer, the remaining part is the obtained dielectric layer.

[0089] S6. As shown in (e) to (f) of Figure 3 , by inductively coupled plasma etching method, using BCl3, Ar, and Cl2 as etching gases, the side of the first n-type gallium oxide epitaxial layer 30 facing away from the n-type gallium oxide substrate 2 is etched to obtain a convex structure, and then the n-type gallium oxide epitaxial layer 3 is obtained, and at the same time, one end of the field plate structure layer is suspended.

[0090] The partially suspended field plate structure introduced in the present invention does not require the introduction of additional processing steps, but only needs to optimize the gas conditions of the mesa etching process. Specifically, based on the original etching gases of boron trichloride (BCl3) and argon (Ar), chlorine gas (Cl2) is additionally introduced to increase the isotropic etching of the gallium oxide material, so as to form a partially suspended field plate structure layer while etching the mesa. In this step, after the first n-type gallium oxide epitaxial layer is etched, the remaining part is the n-type gallium oxide epitaxial layer.

[0091] In some embodiments, the boss structure is a trapezoidal boss structure (specifically, a positive boss structure).

[0092] S7. As Figure 3 shown in (g) therein, a passivation layer is formed on the surfaces of the boss structure and the field plate structure layer 4 that are not covered, or a passivation layer is simultaneously formed on the surfaces of the boss structure and the field plate structure layer 4 that are not covered and on a partial surface of the connection end side of the third metal electrode layer 5 and the second metal electrode layer 42.

[0093] In some embodiments, a passivation material layer is formed on the boss structure, the field plate structure, and the third metal electrode layer, and the passivation material layer is opened to expose a part of the second metal electrode layer located on the mesa of the boss structure that is not covered by the dielectric layer, thereby obtaining the passivation layer 6.

[0094] S8. As Figure 3 shown in (h) therein, a first metal electrode layer 1 is formed on the side of the n-type gallium oxide substrate 2 facing away from the n-type gallium oxide epitaxial layer 3.

[0095] In some embodiments, a metal (such as at least one of Ti, Ni, Ag, Au, and Ag) is deposited on the side of the n-type gallium oxide substrate facing away from the n-type gallium oxide epitaxial layer by electron beam evaporation or sputtering to form the first metal electrode layer.

[0096] In some embodiments, the first metal electrode layer includes a stacked Ti layer, Ni layer, and Ag layer, or the first metal electrode layer includes a stacked Ti layer and Au layer, or the first metal electrode layer includes a stacked Ti layer and Ag layer.

[0097] The present invention will be further described below through specific examples.

[0098] Example 1

[0099] This example provides a gallium oxide power device with a partially suspended field plate structure. As Figure 1 shown, it includes a first metal electrode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3 that are sequentially stacked.

[0100] The side of the n-type gallium oxide epitaxial layer 3 facing away from the n-type gallium oxide substrate 2 is a positive trapezoidal boss structure;

[0101] The gallium oxide power device further includes:

[0102] A field plate structure layer 4, one end of the field plate structure layer 4 is located on a part of the tabletop of the positive trapezoidal boss structure, and the other end is suspended; the field plate structure layer 4 includes a dielectric layer 41 and a second metal electrode layer 42 stacked in sequence, and the dielectric layer 41 fits the part of the tabletop of the positive trapezoidal boss structure; the width a of the part of the field plate structure layer 4 located on the positive trapezoidal boss structure is 15 μm, and the width b of the suspended part is 850 nm;

[0103] A third metal electrode layer 5, the third metal electrode layer 5 is located on the tabletop of the positive trapezoidal boss structure not covered by the field plate structure layer 4 and is connected to the second metal electrode layer 42; the second metal electrode layer 42 and the third metal electrode layer 5 are an integrally formed structure.

[0104] Among them, the thickness of the first metal electrode layer is 1 μm, and the first metal electrode layer includes a Ti layer with a thickness of 300 nm, a Ni layer with a thickness of 400 nm, and an Ag layer with a thickness of 300 nm stacked in sequence. The Ti layer is attached to the n-type gallium oxide substrate;

[0105] The thickness of the n-type gallium oxide substrate is 500 μm, and the doping concentration is 10 19 cm －3 ;

[0106] The total thickness of the n-type gallium oxide epitaxial layer is 10 μm, of which the height of the positive trapezoidal boss structure is 5 μm, and the doping concentration is 10 16 cm －3 ;

[0107] The thickness of the dielectric layer is 250 nm, and the material of the dielectric layer is SiO2;

[0108] The thickness of the second metal electrode layer is 150 nm, and the material of the second metal electrode layer is Ni;

[0109] The thickness of the third metal electrode layer is 150 nm, and the material of the third metal electrode layer is Ni.

[0110] Comparative Example 1

[0111] This comparative example provides a gallium oxide power device with a conventional field plate structure. The difference from Example 1 is only that: the field plate structure layer has no suspended part, that is, the field plate structure layer is completely located on the tabletop of the positive trapezoidal boss structure, and its width is the same as the width a in Example 1, specifically 15 μm.

[0112] In the gallium oxide power devices of Example 1 and Comparative Example 1, the simulation results of the two-dimensional electric field distribution and the surface electric field distribution curves of the two gallium oxide terminal structures are as follows Figure 4 shown. It can be seen that in Comparative Example 1, the conventional structure field plate has a significant electric field concentration effect at the junction of the field plate and the mesa, resulting in extremely high electric field peaks both in the dielectric layer and on the surface of the n-type gallium oxide epitaxial layer, making the breakdown voltage of the device relatively low. In contrast, in the terminal structure of Example 1, by introducing a partially suspended field plate structure layer, the electric field peaks in the dielectric layer and on the surface of the n-type gallium oxide epitaxial layer can be greatly suppressed, achieving a higher breakdown voltage.

[0113] Example 2

[0114] This example provides a gallium oxide power device with a partially suspended field plate structure, as shown in Figure 1 the figure, which includes a first metal electrode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3 stacked in sequence;

[0115] The side of the n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate is a positive trapezoidal convex platform structure;

[0116] The gallium oxide power device further includes:

[0117] A field plate structure layer 4, one end of the field plate structure layer 4 is located on a part of the mesa of the positive trapezoidal convex platform structure, and the other end is suspended; the field plate structure layer 4 includes a dielectric layer 41 and a second metal electrode layer 42 stacked in sequence, and the dielectric layer 41 is attached to a part of the mesa of the positive trapezoidal convex platform structure; the width a of the part of the field plate structure layer 4 located on the positive trapezoidal convex platform structure is 5 μm, and the width b of the suspended part is 1.5 μm;

[0118] A third metal electrode layer 5, the third metal electrode layer 5 is located on the mesa of the positive trapezoidal convex platform structure not covered by the field plate structure layer 4 and is connected to the second metal electrode layer 42; the second metal electrode layer 42 and the third metal electrode layer 5 are an integrally formed structure.

[0119] Among them, the thickness of the first metal electrode layer is 500 nm, and the first metal electrode layer includes a Ti layer with a thickness of 200 nm and an Au layer with a thickness of 300 nm stacked, and the Ti layer is attached to the n-type gallium oxide substrate;

[0120] The thickness of the n-type gallium oxide substrate is 50 μm, and the doping concentration is 10 18 cm －3 ;

[0121] The total thickness of the n-type gallium oxide epitaxial layer is 2 μm, of which the height of the positive trapezoidal convex platform structure is 1 μm, and the doping concentration is 10 17 cm －3 ;

[0122] The thickness of the dielectric layer is 50 nm, and the material of the dielectric layer is Al2O3;

[0123] The thickness of the second metal electrode layer is 50 nm, and the material of the second metal electrode layer is Mo;

[0124] The thickness of the third metal electrode layer is 50 nm, and the material of the third metal electrode layer is Mo.

[0125] Example 3

[0126] This example provides a gallium oxide power device with a partially suspended field plate structure, as Figure 1 shown, including a first metal electrode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3 stacked in sequence;

[0127] The side of the n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate is a positive trapezoidal convex structure;

[0128] The gallium oxide power device further includes:

[0129] A field plate structure layer 4, one end of the field plate structure layer 4 is located on a part of the tabletop of the positive trapezoidal convex structure, and the other end is suspended; the field plate structure layer 4 includes a dielectric layer 41 and a second metal electrode layer 42 stacked in sequence, and the dielectric layer 41 is attached to a part of the tabletop of the positive trapezoidal convex structure; the width a of the part of the field plate structure layer 4 located on the positive trapezoidal convex structure is 25 μm, and the width b of the suspended part is 200 nm;

[0130] A third metal electrode layer 5, the third metal electrode layer 5 is located on the tabletop of the positive trapezoidal convex structure not covered by the field plate structure layer 4 and is connected to the second metal electrode layer 42; the second metal electrode layer 42 and the third metal electrode layer 5 are an integrally formed structure.

[0131] Among them, the thickness of the first metal electrode layer is 2 μm, and the first metal electrode layer includes a Ti layer with a thickness of 1 μm and an Ag layer with a thickness of 1 μm stacked, and the Ti layer is attached to the n-type gallium oxide substrate.

[0132] The thickness of the n-type gallium oxide substrate is 650 μm, and the doping concentration is 10 20 cm －3 ;

[0133] The total thickness of the n-type gallium oxide epitaxial layer is 20 μm, of which the height of the positive trapezoidal convex structure is 10 μm, and the doping concentration is 10 15 cm －3 ;

[0134] The thickness of the dielectric layer is 500 nm, and the material of the dielectric layer is Al2O3;

[0135] The thickness of the second metal electrode layer is 300 nm, and the material of the second metal electrode layer is Pt;

[0136] The thickness of the third metal electrode layer is 300 nm, and the material of the third metal electrode layer is Pt.

[0137] It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or modifications can be made according to the above description, and all such improvements and modifications shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A gallium oxide power device, characterized in that, The gallium oxide power device includes a first metal electrode layer, an n-type gallium oxide substrate, and an n-type gallium oxide epitaxial layer that are sequentially stacked; One side of the n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate is a convex structure; The gallium oxide power device further includes: A field plate structure layer, one end of the field plate structure layer is located on a part of the tabletop of the convex structure, and the other end is suspended; the field plate structure layer includes a dielectric layer and a second metal electrode layer that are sequentially stacked, and the dielectric layer fits the part of the tabletop of the convex structure; A third metal electrode layer, the third metal electrode layer is located on the tabletop of the convex structure not covered by the field plate structure layer and is connected to the second metal electrode layer.

2. The gallium oxide power device according to claim 1, characterized in that The thickness of the n-type gallium oxide substrate is 50 - 650 μm; The n-type gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm －3 ; The thickness of the n-type gallium oxide epitaxial layer is 2 - 20 μm; The n-type gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm －3 .

3. The gallium oxide power device according to claim 1, wherein, The thickness of the dielectric layer is 50 - 500 nm; The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, and aluminum oxide.

4. The gallium oxide power device according to claim 1, characterized in that, The width of one end of the field plate structure layer located on the part of the tabletop of the convex structure is 5 - 25 μm, and the width of the suspended end of the field plate structure layer is 200 nm - 1.5 μm.

5. The gallium oxide power device according to claim 1, characterized in that, The gallium oxide power device further includes a passivation layer; The passivation layer is located on the surfaces of the convex structure and the field plate structure layer that are not covered; or, the passivation layer is simultaneously located on the surfaces of the convex structure and the field plate structure layer that are not covered, and on a part of the surface on the side of the connection end of the third metal electrode layer and the second metal electrode layer.

6. The gallium oxide power device according to claim 5, wherein The thickness of the passivation layer is 500 nm - 20 μm, and the material of the passivation layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and polyimide.

7. The gallium oxide power device according to claim 1, characterized in that The thickness of the first metal electrode layer is 500 nm - 2 μm, and the material of the first metal electrode layer includes at least one of Ti, Ni, Ag, Au, and Ag; The thickness of the second metal electrode layer is 50 - 300 nm, and the material of the second metal electrode layer includes at least one of Ni, Mo, W, Au, Pt, and platinum oxide; The thickness of the third metal electrode layer is 50 - 300 nm, and the material of the third metal electrode layer includes at least one of Ni, Mo, W, Au, Pt, and platinum oxide.

8. A method for manufacturing a gallium oxide power device according to claim 1, characterized in that, Including the following steps: Provide an n-type gallium oxide substrate with an n-type gallium oxide epitaxial layer on its surface, and one side of the n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate is a convex structure; Prepare a field plate structure layer, one end of the field plate structure layer is located on a part of the tabletop of the convex structure and the other end is suspended, the field plate structure layer includes a dielectric layer and a second metal electrode layer that are sequentially stacked, and the dielectric layer fits the part of the tabletop of the convex structure; Prepare a third metal electrode layer, the third metal electrode layer is located on the tabletop of the convex structure not covered by the field plate structure layer and is connected to the second metal electrode layer; Prepare a first metal electrode layer, and the first metal electrode layer is located on the side of the n-type gallium oxide substrate facing away from the n-type gallium oxide epitaxial layer.

9. The preparation method according to claim 8, characterized in that, The preparation method of the n-type gallium oxide epitaxial layer includes the following steps: Provide an n-type gallium oxide substrate with a first n-type gallium oxide epitaxial layer on its surface; By means of an inductively coupled plasma etching method, using BCl3, Ar, and Cl2 as etching gases, the side of the first n-type gallium oxide epitaxial layer facing away from the n-type gallium oxide substrate is etched to obtain a boss structure, and then an n-type gallium oxide epitaxial layer is obtained.

10. The preparation method according to claim 8, characterized in that, The method for preparing the gallium oxide power device further includes the following steps: A passivation layer is prepared, and the passivation layer is located on the uncovered surfaces of the boss structure and the field plate structure layer, or the passivation layer is simultaneously located on the uncovered surfaces of the boss structure and the field plate structure layer, and a partial surface on the connection end side of the third metal electrode layer and the second metal electrode layer.

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