Semiconductor metal field plate manufacturing method and semiconductor metal field plate
By forming a hole etching protective layer in the manufacturing of semiconductor metal field plates and scrubbing and removing it, the damage problem of connecting hole etching on the field plates is solved, the electrical performance and yield rate are improved, and the production process is simplified.
Patent Information
- Application Number
- CN202510728690.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-03
- Publication Date
- 2025-07-25
AI Technical Summary
The connection hole etching process of existing semiconductor metal field plates is difficult to accurately control, resulting in damage to the field plate structure and degradation of electrical properties, and low yield.
The hole etching protective layer is formed on the substrate and gate surfaces, and the hole is etched and removed by scrubbing and cleaning to ensure sufficient space at the bottom of the connection hole. Metal organic chemical vapor deposition is used to form a metal adhesive layer to avoid overetching damage.
It protects the structural integrity of the field plate, improves electrical performance and yield, simplifies the production process, and reduces the difficulty of deposition and grinding of metal adhesive layers.
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Figure CN120379325A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly to a method for manufacturing a semiconductor metal field plate and a semiconductor metal field plate. Background Art
[0002] Semiconductor metal field plates are common in the field of semiconductor chip design and manufacturing. The semiconductor metal field plate connects the internal transistors of the field plate and the metal wires on the surface of the field plate through a metal bonding layer at the connection hole (CT).
[0003] Currently, the semiconductor metal field plate forms a number of relatively large-sized connection holes by a connection hole etching process, and the connection holes respectively need to terminate at the field plate gate polysilicon, the field plate active region, and the field plate oxide layer. To avoid damage to the field plate structure during the connection hole etching process, an etching stop layer is usually used as a protective layer and pre-laid on the field plate. However, in the actual process flow, it is still difficult to control the etching stop, resulting in over-etching through the etching stop layer and damaging the field plate structure. And in order to ensure the electrical performance of the field plate, it is necessary to avoid the etching stop layer being too thick and it needs to be etched sufficiently.
[0004] The above problems pose extremely high requirements for the accuracy of the connection hole etching process, which is difficult to achieve perfectly in the actual production and preparation process of the semiconductor metal field plate, resulting in a low yield rate and being unfavorable for the production and manufacturing of semiconductor devices. Summary of the Invention
[0005] The present invention aims to provide a method for manufacturing a semiconductor metal field plate and a semiconductor metal field plate, which can protect the field plate structure from being damaged by the connection hole etching process on the basis of ensuring the electrical performance of the field plate, and solve the technical problems of high difficulty in etching the connection holes of the field plate and easy damage to the field plate.
[0006] To achieve the above object, in the first aspect of the present invention, a method for manufacturing a semiconductor metal field plate is provided, including the following steps:
[0007] Determine a substrate and form a gate on the surface of the substrate; form a metal silicide blocking layer on the surfaces of the substrate and the gate; form a hole etching protective layer on the surfaces of the substrate, the gate, and the metal silicide blocking layer; form an interlayer dielectric layer on the surfaces of the substrate, the gate, the metal silicide blocking layer, and the hole etching protective layer; perform connection hole etching on the interlayer dielectric layer to form a number of connection holes penetrating through the hole etching protective layer; wash and remove the hole etching protective layer; form a metal bonding layer in the number of connection holes.
[0008] The above semiconductor metal field plate manufacturing method forms a hole etching protection layer on the surface of the substrate, the gate, and the metal silicide barrier layer. When etching the via holes in the interlayer dielectric layer, it only needs to etch to the hole etching protection layer without damaging the rest of the field plate structure. At the same time, in order to ensure the electrical performance of the field plate, this method thoroughly removes the hole etching protection layer through a washing process. On the one hand, it can ensure that the via holes will not have a too thick remaining hole etching protection layer, which affects the electrical performance of the field plate. On the other hand, the washing process will not damage the rest of the field plate structure, fully protecting the structural integrity of the semiconductor metal field plate. In addition, after using this process to wash the hole etching protection layer, sufficient space can be left at the bottom of the via holes, thereby increasing the contact area between the metal adhesion layer formed in the via holes and the field plate structure, improving the electrical performance of the field plate.
[0009] Further, forming the metal silicide barrier layer on the surface of the substrate and the gate includes:
[0010] Depositing a first oxide structure on the surface of the substrate and the gate, and determining the barrier layer retention area of the first oxide structure;
[0011] Etching the first oxide structure to form a metal silicide barrier layer in the barrier layer retention area.
[0012] The above embodiment makes the formed metal silicide barrier layer located in the barrier layer retention area in the way of first depositing and then etching, covering part of the surfaces of the substrate and the gate, and exposing the rest of the substrate and the gate, so that the subsequent formed hole etching protection layer can respectively cover the surfaces of the substrate, the gate, and the metal silicide barrier layer, and further enables the finally formed several via holes to respectively penetrate to the surface of the substrate, the surface of the gate, and the surface of the metal silicide barrier layer to form a semiconductor metal field plate.
[0013] Further, forming the hole etching protection layer on the surfaces of the substrate, the gate, and the metal silicide barrier layer includes:
[0014] Depositing a second oxide structure on the surfaces of the substrate, the gate, and the metal silicide barrier layer, and then depositing silicon nitride on the surface of the second oxide structure to form a mixed layer;
[0015] Determining the hole etching protection area of the mixed layer;
[0016] Etching the mixed layer to form a hole etching protection layer in the hole etching protection area.
[0017] In the above-described embodiment, a second oxide and silicon nitride are first redeposited and grown on the surfaces of the substrate, the gate, and the metal silicide barrier layer to form a mixed layer; wherein, the second oxide serves as an etch stop layer for the silicon nitride. Secondly, the portion of the mixed layer to be etched with connection holes is determined and used as a hole etching protection area, and then the mixed layer outside the hole etching protection area is etched away, and the remaining mixed layer in the hole etching protection area is used as a hole etching protection layer.
[0018] Further, the etching of the mixed layer to form a hole etching protection layer in the hole etching protection area includes:
[0019] Etching the mixed layer so that the mixed layer is separated into a type-I connection hole protection layer, a type-II connection hole protection layer, and a type-III connection hole protection layer, and using the type-I connection hole protection layer, the type-II connection hole protection layer, and the type-III connection hole protection layer as the hole etching protection layer.
[0020] In the above-described embodiment, the mixed layer is etched so that the mixed layer is separated into three parts, namely a type-I connection hole protection layer, a type-II connection hole protection layer, and a type-III connection hole protection layer, and each separated connection hole protection layer corresponds to a connection hole etching position.
[0021] Further, the gate includes a polysilicon structure; the substrate includes an active region; the type-I connection hole protection layer is located on the surface of the polysilicon structure; the type-II connection hole protection layer is located on the surface of the active region; and the type-III connection hole protection layer is located on the surface of the metal silicide barrier layer.
[0022] Further, the etching of the interlayer dielectric layer to form a plurality of connection holes penetrating through the hole etching protection layer includes:
[0023] Etching the interlayer dielectric layer to form a type-I connection hole penetrating through the type-I connection hole protection layer, a type-II connection hole penetrating through the type-II connection hole protection layer, and a type-III connection hole penetrating through the type-III connection hole protection layer;
[0024] After washing away the hole etching protection layer, it further includes:
[0025] Depositing metal silicide in the type-I connection hole and the type-II connection hole, thereby forming a metal silicide layer on the surfaces of the polysilicon structure and the active region.
[0026] Specifically, depositing metal silicide in the type-I connection holes and the type-II connection holes, thereby forming a metal silicide layer on the polysilicon structure and the surface of the active region, specifically includes: depositing a metal layer in the type-I connection holes and the type-II connection holes respectively; reacting the metal layer with the polysilicon structure in the type-I connection holes and the surface of the active region in the type-II connection holes respectively through an annealing process, thereby forming a metal silicide layer on the polysilicon structure and the surface of the active region; removing the excess metal layer material in the type-I connection holes and the type-II connection holes by wet etching.
[0027] It should be noted that after etching to form the type-I connection holes penetrating through the type-I connection hole protection layer, the type-II connection holes penetrating through the type-II connection hole protection layer, and the type-III connection holes penetrating through the type-III connection hole protection layer in the above embodiments, the type-I connection hole protection layer, the type-II connection hole protection layer, and the type-III connection hole protection layer are respectively washed and removed, so that the type-I connection holes become blind holes penetrating to the surface of the polysilicon structure, the type-II connection holes become blind holes penetrating to the surface of the active region, and the type-III connection holes become blind holes penetrating to the surface of the metal silicide barrier layer, enabling the finally formed several connection holes to penetrate to the surface of the substrate, the surface of the gate, and the surface of the metal silicide barrier layer respectively.
[0028] Depositing metal silicide in the type-I connection holes and the type-II connection holes through a metal silicide process, thereby forming a metal silicide layer on the polysilicon structure and the surface of the active region, is beneficial to reducing the contact resistance at the via position.
[0029] When etching to form the type-I connection holes, the type-II connection holes, and the type-III connection holes respectively in the above embodiments, it is only necessary to etch to the type-I connection hole protection layer, the type-II connection hole protection layer, and the type-III connection hole protection layer respectively. Therefore, over-etching will not damage the gate polysilicon structure, the substrate active region, and the metal silicide barrier layer, protecting the structural integrity of the semiconductor metal field plate. Moreover, compared with the prior art, the process is simple and easy to implement in the mass production process, thereby improving the yield of the field plate. At the same time, in order to ensure the electrical performance of the field plate, in this method, the type-I connection hole protection layer, the type-II connection hole protection layer, and the type-III connection hole protection layer are thoroughly removed through a washing process. On the one hand, it can ensure that the type-I connection holes, the type-II connection holes, and the type-III connection holes will not have a too thick hole etching protection layer remaining, affecting the electrical performance of the field plate. On the other hand, the washing process will not damage the gate polysilicon structure, the substrate active region, and the metal silicide barrier layer, fully protecting the structural integrity of the semiconductor metal field plate. In addition, after washing the hole etching protection layer with this process, sufficient space can be left at the bottom of the connection hole, thereby increasing the contact area between the metal adhesion layer formed in the connection hole and the gate polysilicon structure, the substrate active region, and the metal silicide barrier layer, and improving the electrical performance of the field plate.
[0030] Further, forming an interlayer dielectric layer on the surfaces of the substrate, the gate, the metal silicide barrier layer, and the via etch protection layer includes:
[0031] Depositing a dielectric structure on the surfaces of the substrate, the gate, the metal silicide barrier layer, and the via etch protection layer;
[0032] Performing chemical mechanical polishing on the dielectric structure to form an interlayer dielectric layer.
[0033] Specifically, the dielectric structure is an oxide structure, and the interlayer dielectric layer formed by the dielectric structure is an oxide structure.
[0034] The above implementation method performs chemical mechanical polishing on the surface of the dielectric structure to make the surface of the formed interlayer dielectric layer flat, which is beneficial to subsequent via etching of the interlayer dielectric layer and forming a metal adhesion layer in several of the vias, improving the electrical performance of the field plate.
[0035] Further, removing the via etch protection layer by washing includes:
[0036] Performing wet etching on the via etch protection layer with phosphoric acid to remove the via etch protection layer by washing.
[0037] The above implementation method removes the type-I via protection layer, type-II via protection layer, and type-III via protection layer in the type-I via, type-II via, and type-III via by phosphoric acid. On the one hand, the phosphoric acid process will not damage the gate polysilicon structure, the substrate active region, and the metal silicide barrier layer, fully protecting the structural integrity of the semiconductor metal field plate. On the other hand, phosphoric acid can completely remove the via protection layer by washing without leaving an overly thick via protection layer that affects the electrical performance of the field plate.
[0038] Further, forming a metal adhesion layer in several of the vias includes:
[0039] Using metal organic chemical vapor deposition to fill a metal mixture into several of the vias;
[0040] Performing chemical mechanical polishing on the metal mixture to form a metal adhesion layer.
[0041] Preferably, in one implementation, atomic layer deposition (ALD) is selected to fill a metal mixture into several of the vias.
[0042] After removing the hole etching protection layer in the connection holes by wet etching and scrubbing in the above-described embodiment, a metal adhesion layer is grown in the connection holes by metal-organic chemical vapor deposition process. Cleverly, the residual hole etching protection layer in the connection holes is replaced with a metal adhesion layer that fully fills the connection holes by means of wet etching and physical vapor deposition (PVD), realizing the function of the connection holes in the semiconductor metal field plate; this method will neither damage the field plate structure nor leave a too thick hole etching protection layer to affect the electrical performance of the field plate, and the steps are simple and easy to implement in production, which is beneficial to improving the production yield of the semiconductor metal field plate.
[0043] The second aspect of the present invention provides a semiconductor metal field plate, which is prepared by the semiconductor metal field plate manufacturing method according to any one of the first aspects of the present invention. The semiconductor metal field plate includes a substrate, and a gate, a metal silicide barrier layer, and an interlayer dielectric layer are provided on the surface of the substrate, wherein:
[0044] The metal silicide barrier layer extends from the surface of the substrate along one side of the gate to the surface of the gate;
[0045] The interlayer dielectric layer covers the gate and the metal silicide barrier layer;
[0046] A plurality of connection holes are provided in the interlayer dielectric layer;
[0047] The plurality of connection holes respectively penetrate to the surface of the substrate, the surface of the gate, and the surface of the metal silicide barrier layer;
[0048] The plurality of connection holes are filled with a metal adhesion layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] Figure 1 is a schematic flow chart of a semiconductor metal field plate manufacturing method provided by an embodiment of the present invention;
[0050] Figure 2 is in a semiconductor metal field plate manufacturing method provided by an embodiment of the present invention;
[0051] Figure 3 is a schematic diagram of the field plate structure in the first semiconductor metal field plate manufacturing method provided by an embodiment of the present invention;
[0052] Figure 4 is a schematic diagram of the field plate structure in the second semiconductor metal field plate manufacturing method provided by an embodiment of the present invention;
[0053] Figure 5 is a schematic diagram of the field plate structure in the third semiconductor metal field plate manufacturing method provided by an embodiment of the present invention;
[0054] Figure 6It is a schematic diagram of the field plate structure in the fourth semiconductor metal field plate manufacturing method provided by the embodiments of the present invention;
[0055] Figure 7 It is a schematic diagram of the field plate structure in the fifth semiconductor metal field plate manufacturing method provided by the embodiments of the present invention;
[0056] Figure 8 It is a schematic diagram of the field plate structure in the sixth semiconductor metal field plate manufacturing method provided by the embodiments of the present invention;
[0057] Figure 9 It is a schematic diagram of the field plate structure in the seventh semiconductor metal field plate manufacturing method provided by the embodiments of the present invention;
[0058] Figure 10 It is a schematic diagram of the field plate structure in the eighth semiconductor metal field plate manufacturing method provided by the embodiments of the present invention;
[0059] Figure 11 It is a schematic diagram of the field plate structure in the ninth semiconductor metal field plate manufacturing method provided by the embodiments of the present invention;
[0060] Figure 12 It is a schematic diagram of the field plate structure in the tenth semiconductor metal field plate manufacturing method provided by the embodiments of the present invention;
[0061] Figure 13 It is a schematic diagram of the field plate structure in the eleventh semiconductor metal field plate manufacturing method provided by the embodiments of the present invention;
[0062] Wherein: 1. Substrate; 2. Gate; 21. Polysilicon structure; 22. Sidewall; 3. First oxide structure; 31. Metal silicide barrier layer; 4. Hybrid layer; 401. Second oxide structure; 402. Silicon nitride; 41. Protection layer for type I connection hole; 42. Protection layer for type II connection hole; 43. Protection layer for type III connection hole; 5. Interlayer dielectric layer; 51. Dielectric structure; 61. Type I connection hole; 611. First linear structure; 62. Type II connection hole; 621. Second linear structure; 63. Type III connection hole; 631. Third linear structure; 71. First metal silicide layer; 72. Second metal silicide layer; 8. Metal mixture; 81. First metal bonding layer; 82. Second metal bonding layer; 83. Third metal bonding layer. Detailed implementation manners
[0063] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that the following detailed description is only an exemplary description, aiming to provide further details of the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the description and claims of this application and the above drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the description and claims of this application or the above drawings are used to distinguish different objects and are not used to describe a specific order.
[0064] It should be understood that although the steps in the flowchart of the accompanying drawings are shown sequentially in the direction of the arrows, these steps are not necessarily executed sequentially in the direction of the arrows. Unless otherwise clearly stated in this article, there is no strict order restriction for the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.
[0065] Semiconductor metal field plates are common in the field of semiconductor chip design and manufacturing. The semiconductor metal field plate connects the internal transistors of the field plate and the metal wires on the surface of the field plate through a metal bonding layer at the connection hole (CT).
[0066] The existing semiconductor metal field plate structure fabricates relatively large-sized linear connection holes through a connection hole etching process, forming three typical structures: the first is a connection hole that penetrates through the field plate gate polysilicon, the second is a connection hole that penetrates through the field plate active area (AA), and the third is a linear connection hole structure that penetrates through the field plate metal silicide barrier layer. The technical difficulties are as follows: First, for the first and second connection holes, it is necessary to ensure that the connection hole etching can completely etch the contact etch stop layer (CESL), and at the same time ensure that the damage to the field plate silicide is within the allowable range; second, for the third linear connection hole structure that leads to the field plate metal silicide barrier layer, it is required to avoid etching through the metal silicide barrier layer (SAB) on the premise of etching through the etch stop layer, which has extremely high requirements for the etching process. Finally, the contact area between the field plate and the metal bonding layer in the connection hole is completely limited by the etching radius of the connection hole, which has certain limitations; if the connection hole radius is too small, the contact area at the bottom of the metal bonding layer is too small, resulting in a decline in the electrical performance of the field plate. If the connection hole radius is too large, it will increase the difficulty of the metal bonding layer deposition and chemical mechanical polishing processes.
[0067] The above problems pose extremely high requirements for the precision of the connection hole etching process, which is difficult to achieve perfectly in the actual production process of semiconductor metal field plates, resulting in a low yield rate and being unfavorable for the production and manufacturing of semiconductor devices.
[0068] To solve the above technical problems, referring to Figure 1 , the first aspect of the embodiment of the present invention provides a method for manufacturing a semiconductor metal field plate, including the following steps:
[0069] S101. Determine the substrate 1 and form a gate 2 on the surface of the substrate 1.
[0070] Specifically, referring to Figure 2 , the gate 2 is composed of a polysilicon structure 21 and sidewalls 22, and the polysilicon structure 21 is surrounded by the sidewalls 22.
[0071] S102. Form a metal silicide blocking layer 31 on the surfaces of the substrate 1 and the gate 2.
[0072] Specifically, step S102 includes:
[0073] Referring to Figure 3 , deposit a first oxide structure 3 on the surfaces of the substrate 1 and the gate 2, and determine the blocking layer retention area of the first oxide structure 3;
[0074] Referring to Figure 4 , etch the first oxide structure 3 using a dry etching and photolithography process, so as to form a metal silicide blocking layer 31 in the blocking layer retention area, and the metal silicide blocking layer 31 extends from the surface of the substrate 1 along one sidewall 22 of the gate 2 to the surface of the polysilicon structure 21.
[0075] In the above embodiment, the formed metal silicide blocking layer 31 is located in the blocking layer retention area in a manner of first deposition and then etching, covering part of the surfaces of the substrate 1 and the gate 2, and exposing the remaining parts of the substrate 1 and the gate 2, so that the subsequently formed hole etching protection layer can respectively cover the surfaces of the substrate 1, the gate 2 and the metal silicide blocking layer 31, and further enable several finally formed connection holes to respectively penetrate to the surfaces of the substrate 1, the gate 2 and the metal silicide blocking layer 31, forming a semiconductor metal field plate.
[0076] S103. Form a hole etching protection layer on the surfaces of the substrate 1, the gate 2 and the metal silicide blocking layer 31.
[0077] Specifically, step S103 includes:
[0078] Referring to Figure 5, a second oxide structure 401 is deposited on the surfaces of the substrate 1, the gate 2, and the metal silicide barrier layer 31, and then silicon nitride 402 is deposited on the surface of the second oxide structure 401 to form a hybrid layer 4;
[0079] Determine the hole etching protection area of the hybrid layer 4;
[0080] Etch the hybrid layer 4 to form a hole etching protection layer in the hole etching protection area.
[0081] In a possible embodiment, the second oxide structure 401 is silicon oxide.
[0082] Further, with reference to Figure 6 , the etching of the hybrid layer 4 to form a hole etching protection layer in the hole etching protection area includes:
[0083] Use a dry etching process to etch the hybrid layer 4 so that the hybrid layer 4 is separated into a type-I connection hole protection layer 41, a type-II connection hole protection layer 42, and a type-III connection hole protection layer 43, and use the type-I connection hole protection layer 41, the type-II connection hole protection layer 42, and the type-III connection hole protection layer 43 as the hole etching protection layer.
[0084] In the above embodiment, first, a layer of second oxide and silicon nitride 402 is redeposited and grown on the surfaces of the substrate 1, the gate 2, and the metal silicide barrier layer 31 to form a hybrid layer 4; wherein, the second oxide serves as an etching stop layer for the silicon nitride 402. Secondly, determine the part of the hybrid layer 4 to be etched with connection holes and use it as the hole etching protection area, and then etch away the hybrid layer 4 outside the hole etching protection area so that the hybrid layer 4 is separated into three parts, namely a type-I connection hole protection layer 41, a type-II connection hole protection layer 42, and a type-III connection hole protection layer 43, and each separated connection hole protection layer corresponds to a connection hole etching position.
[0085] The hybrid layer 4 in the area where the field plate and contact connection holes need to be formed is retained by dry etching to form a hole etching protection layer, and the hole etching protection layer will be replaced by a metal mixture 8 to form a metal bonding layer later. The silicon nitride 402 in the connection hole area can effectively solve the problem of insufficient contact etching in the existing process and optimize the silicide damage caused by excessive etching at the same time.
[0086] Further, with reference to Figure 6 , the gate 2 includes a polysilicon structure 21; the substrate 1 includes an active area; the type-I connection hole protection layer 41 is located on the surface of the polysilicon structure 21; the type-II connection hole protection layer 42 is located on the surface of the active area; the type-III connection hole protection layer 43 is located on the surface of the metal silicide barrier layer 31.
[0087] S104. Form an interlayer dielectric layer 5 on the surfaces of the substrate 1, the gate 2, the metal silicide barrier layer 31, and the hole etching protection layer.
[0088] Specifically, step S104 includes:
[0089] Referring to Figure 7 , deposit a dielectric structure 51 on the surfaces of the substrate 1, the gate 2, the metal silicide barrier layer 31, and the hole etching protection layer;
[0090] Referring to Figure 8 , perform chemical mechanical polishing on the dielectric structure 51 to form the interlayer dielectric layer 5.
[0091] In the above embodiment, chemical mechanical polishing is performed on the surface of the dielectric structure 51 to make the surface of the formed interlayer dielectric layer 5 flat, which is beneficial to subsequent via etching of the interlayer dielectric layer 5 and formation of a metal adhesion layer in several of the vias, improving the field plate electrical performance.
[0092] S105. Perform via etching on the interlayer dielectric layer 5 to form several vias penetrating through the hole etching protection layer.
[0093] Specifically, step S105 includes:
[0094] Referring to Figure 9 , perform via etching on the interlayer dielectric layer 5 to form a type-I via 61 penetrating through the type-I via protection layer 41, a type-II via 62 penetrating through the type-II via protection layer 42, and a type-III via 63 penetrating through the type-III via protection layer 43.
[0095] In a possible embodiment, the second oxide structure 401 is silicon oxide. The pattern is transferred to the etching position of silicon nitride 402 (SIN) from the hole etching protection layer through via etching. Due to the high etching selectivity between silicon oxide and silicon nitride 402 (SIN), and the subsequent wet etching removal of the SIN pattern, the over-etching of silicon nitride 402 has a controllable impact on the overall structure. Compared with the conventional process, the stop control of via etching is easier, and there is no need to overly worry about the impact of over-etching on the morphology of the bottom silicide, thus obtaining a greater process window advantage.
[0096] When forming the type-I connection hole 61, type-II connection hole 62, and type-III connection hole 63 through etching in the above embodiments, it is only necessary to etch to the type-I connection hole protection layer 41, type-II connection hole protection layer 42, and type-III connection hole protection layer 43 respectively. Therefore, over-etching will not damage the polysilicon structure 21 of the gate 2, the active region of the substrate 1, and the metal silicide barrier layer 31, protecting the structural integrity of the semiconductor metal field plate. Moreover, compared with the prior art process, it is simple and easy to implement in the mass production process, thereby improving the yield of the field plate. At the same time, in order to ensure the electrical performance of the field plate, in this method, the type-I connection hole protection layer 41, type-II connection hole protection layer 42, and type-III connection hole protection layer 43 are thoroughly removed through the washing process. On the one hand, it can ensure that the type-I connection hole 61, type-II connection hole 62, and type-III connection hole 63 will not have a too thick etched hole protection layer remaining, which affects the electrical performance of the field plate. On the other hand, the washing process will not damage the polysilicon structure 21 of the gate 2, the active region of the substrate 1, and the metal silicide barrier layer 31, fully protecting the structural integrity of the semiconductor metal field plate. In addition, after using this process to wash the etched hole protection layer, sufficient space can be left at the bottom of the connection hole, thereby increasing the contact area between the metal bonding layer formed in the connection hole and the polysilicon structure 21 of the gate 2, the active region of the substrate 1, and the metal silicide barrier layer 31, and improving the electrical performance of the field plate.
[0097] S106. Wash and remove the etched hole protection layer.
[0098] Specifically, step S106 includes:
[0099] Refer to Figure 9 And Figure 10 , use phosphoric acid to perform wet etching on the type-I connection hole protection layer 41, type-II connection hole protection layer 42, and type-III connection hole protection layer 43, thereby washing and removing the etched hole protection layer.
[0100] In a possible embodiment, the second oxide structure 401 is silicon oxide.
[0101] Refer to Figure 9 And Figure 10, It should be noted that after the above-described embodiments etch to form the first-type connection hole 61 penetrating through the first-type connection hole protection layer 41, the second-type connection hole 62 penetrating through the second-type connection hole protection layer 42, and the third-type connection hole 63 penetrating through the third-type connection hole protection layer 43, the first-type connection hole protection layer 41, the second-type connection hole protection layer 42, and the third-type connection hole protection layer 43 are respectively washed and removed, so that the first-type connection hole 61 becomes a blind hole penetrating to the surface of the polysilicon structure 21, the second-type connection hole 62 becomes a blind hole penetrating to the surface of the active region, and the third-type connection hole 63 becomes a blind hole penetrating to the surface of the metal silicide barrier layer 31, enabling the formed plurality of connection holes to respectively penetrate to the surface of the substrate 1, the surface of the gate 2, and the surface of the metal silicide barrier layer 31.
[0102] In the above embodiments, the first-type connection hole protection layer 41, the second-type connection hole protection layer 42, and the third-type connection hole protection layer 43 in the first-type connection hole 61, the second-type connection hole 62, and the third-type connection hole 63 are washed and removed by phosphoric acid. On the one hand, the phosphoric acid process will not damage the polysilicon structure 21 of the gate 2, the active region of the substrate 1, and the metal silicide barrier layer 31, fully protecting the structural integrity of the semiconductor metal field plate. On the other hand, phosphoric acid can thoroughly wash and remove the connection hole protection layer without leaving an overly thick connection hole protection layer that affects the electrical performance of the field plate.
[0103] Further, after the first-type connection hole protection layer 41 in the first-type connection hole 61 is washed and removed by phosphoric acid, a first linear structure 611 is formed at the bottom of the first-type connection hole 61, and the size of the first linear structure 611 depends on the size of the first-type connection hole protection layer 41. Thus, in this embodiment, by etching and retaining the first-type connection hole protection layer 41 with a larger volume in step S103, a first linear structure 611 with a larger volume can be formed in step S106, increasing the contact area between the first-type connection hole 61 and the polysilicon structure 21. While improving the electrical performance of the field plate, the first-type connection hole 61 can be set to a smaller radius, reducing the difficulty of subsequent metal adhesion layer deposition and chemical mechanical polishing processes.
[0104] Similarly, a second linear structure 621 is formed at the bottom of the type-II connection hole 62, and the size of the second linear structure 621 depends on the size of the type-II connection hole protective layer 42; a third linear structure 631 is formed at the bottom of the type-III connection hole 63, and the size of the third linear structure 631 depends on the size of the type-III connection hole protective layer 43; by etching and retaining the relatively larger type-II connection hole protective layer 42 and type-III connection hole protective layer 43 in step S103, relatively larger second linear structure 621 and third linear structure 631 are formed in step S106, increasing the contact area between the type-II connection hole 62 and the active region, as well as the contact area between the type-III connection hole 63 and the metal silicide blocking layer 31. While improving the electrical performance of the field plate, the type-II connection hole 62 and the type-III connection hole 63 can be set to have a smaller radius, reducing the difficulty of subsequent metal adhesion layer deposition and chemical mechanical polishing processes.
[0105] After washing and removing the hole etching protective layer, the method further includes:
[0106] Referring to Figure 11 depositing metal silicide in the type-I connection hole 61 and the type-II connection hole 62, thereby forming a metal silicide layer on the surface of the polysilicon structure 21 and the active region.
[0107] In the above embodiment, metal silicide is deposited in the type-I connection hole 61 and the type-II connection hole 62 through a metal silicide process, thereby forming a metal silicide layer on the surface of the polysilicon structure 21 and the active region, which is beneficial to reducing the contact resistance at the via position.
[0108] S107. Form a metal adhesion layer in several of the connection holes.
[0109] Specifically, step S107 includes:
[0110] Referring to Figure 12 , using metal organic chemical vapor deposition to fill several of the connection holes with a metal mixture 8;
[0111] Referring to Figure 13 , performing chemical mechanical polishing on the metal mixture 8, thereby forming a first metal adhesion layer 81 in the type-I connection hole 61, a second metal adhesion layer 82 in the type-II connection hole, and a third metal adhesion layer 83 in the type-III connection hole 63.
[0112] In a possible embodiment, the metal mixture 8 includes titanium (Ti), titanium nitride (TiN), and tungsten (W).
[0113] After removing the hole etching protection layer in the connection hole by wet etching and scrubbing in the above embodiments, a metal bonding layer is grown in the connection hole by metal organic chemical vapor deposition process. The residual hole etching protection layer in the connection hole is cleverly replaced by a metal bonding layer that fully fills the connection hole through wet etching and physical vapor deposition (PVD), realizing the function of the connection hole in the semiconductor metal field plate; this method will neither damage the field plate structure nor leave a too thick hole etching protection layer to affect the electrical performance of the field plate, and the steps are simple and easy to implement in production, which is beneficial to improving the preparation yield of the semiconductor metal field plate.
[0114] Referring to Figure 13 , an embodiment of the present invention further provides a semiconductor metal field plate, which is prepared by the semiconductor metal field plate manufacturing method described in any one of the embodiments of the present invention. The semiconductor metal field plate includes a substrate 1, and a gate 2, a metal silicide blocking layer 31, and an interlayer dielectric layer 5 are disposed on the surface of the substrate 1, wherein:
[0115] The gate 2 is composed of a polysilicon structure 21 and sidewalls 22, the polysilicon structure 21 is surrounded by the sidewalls 22, and the substrate 1 includes an active region;
[0116] The metal silicide blocking layer 31 extends from the surface of the substrate 1 along one side of the sidewalls 22 of the gate 2 to the surface of the polysilicon structure 21 of the gate 2;
[0117] The interlayer dielectric layer 5 covers the gate 2 and the metal silicide blocking layer 31;
[0118] A first-type connection hole 61, a second-type connection hole 62, and a third-type connection hole 63 are provided in the interlayer dielectric layer 5;
[0119] The first-type connection hole 61 is located on the surface of the polysilicon structure 21; the second-type connection hole 62 is located on the surface of the active region; the third-type connection hole 63 is located on the surface of the metal silicide blocking layer 31;
[0120] A first linear structure 611 is formed at the bottom of the first-type connection hole 61, a second linear structure 621 is formed at the bottom of the second-type connection hole 62, and a third linear structure 631 is formed at the bottom of the third-type connection hole 63;
[0121] A first metal silicide layer 71 is provided on the first linear structure 611, and a second metal silicide layer 72 is provided on the second linear structure 621;
[0122] The first-type connection hole 61 is filled with a first metal bonding layer 81, the second-type connection hole is filled with a second metal bonding layer 82, and the third-type connection hole 63 is filled with a third metal bonding layer 83.
[0123] A semiconductor metal field plate manufacturing method and a semiconductor metal field plate provided by the present invention have at least the following advantages compared with the prior art:
[0124] In the semiconductor metal field plate manufacturing method provided by the present invention, a hole etching protection layer is formed on the surfaces of the substrate 1, the gate 2, and the metal silicide barrier layer 31. When etching the connection holes in the interlayer dielectric layer 5, it only needs to be etched to the hole etching protection layer, without damaging the rest of the field plate structure. At the same time, in order to ensure the electrical performance of the field plate, this method thoroughly removes the hole etching protection layer through a washing process. On the one hand, it can ensure that there is no excessive hole etching protection layer remaining in the connection holes, which affects the electrical performance of the field plate. On the other hand, the washing process will not damage the rest of the field plate structure, fully protecting the structural integrity of the semiconductor metal field plate. In addition, after using this process to wash the hole etching protection layer, sufficient space can be left at the bottom of the connection holes, thereby increasing the contact area between the metal bonding layer formed in the connection holes and the field plate structure, and improving the electrical performance of the field plate.
[0125] The present invention cleverly replaces silicon nitride 402 (SIN) with a metal tungsten mixture by means of wet etching and physical vapor deposition (PVD). At the same time, the silicon nitride 402 can be used to increase the bottom area of the field plate connection holes (CT), thereby enhancing the electrical performance of the field plate while maintaining a small connection hole radius, and optimizing the problem of difficult connection hole etching.
[0126] The advantages of the present invention are as follows. First, the three types of connection holes only need to terminate at the silicon nitride 402 of the hole etching protection layer, significantly reducing the requirements for the etching process. Second, the size of the contact surface at the bottom of the connection holes is not limited by the connection hole radius, but depends on the reserved volume of the silicon nitride 402 before it is washed away, enabling the field plate to be larger than the existing process and applicable to higher-voltage products. Third, it can maintain a small radius of the field plate connection holes, which is more beneficial for the deposition and polishing of metal tungsten.
[0127] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), ferroelectric random access memories (FRAM), phase change memories (PCM), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logics, data processing logics based on quantum computing, etc., without limitation.
[0128] As used herein, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in this specification.
[0129] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several improvements and substitutions can be made, and these improvements and substitutions should also be regarded as the protection scope of the present invention. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims
1. A method for manufacturing a semiconductor metal field plate, characterized in that, Comprising: Determine a substrate and form a gate on the surface of the substrate; Form a metal silicide barrier layer on the surface of the substrate and the gate; Form a hole etching protection layer on the surface of the substrate, the gate and the metal silicide barrier layer; Form an interlayer dielectric layer on the surface of the substrate, the gate, the metal silicide barrier layer and the hole etching protection layer; Perform connection hole etching on the interlayer dielectric layer to form a plurality of connection holes penetrating through to the hole etching protection layer; Wash and remove the hole etching protection layer; Form a metal adhesion layer in the plurality of connection holes.
2. A method for manufacturing a semiconductor metal field plate according to claim 1, wherein, The forming a metal silicide barrier layer on the surface of the substrate and the gate includes: Deposit a first oxide structure on the surface of the substrate and the gate and determine a barrier layer retention region of the first oxide structure; Etch the first oxide structure so as to form a metal silicide barrier layer in the barrier layer retention region.
3. A method for manufacturing a semiconductor metal field plate according to claim 1, characterized in that, The forming a hole etching protection layer on the surface of the substrate, the gate and the metal silicide barrier layer includes: Deposit a second oxide structure on the surface of the substrate, the gate and the metal silicide barrier layer, and then deposit silicon nitride on the surface of the second oxide structure to form a mixed layer; Determine a hole etching protection region of the mixed layer; Etch the mixed layer so as to form a hole etching protection layer in the hole etching protection region.
4. The method for manufacturing a semiconductor metal field plate according to claim 3, wherein, The etching the mixed layer so as to form a hole etching protection layer in the hole etching protection region includes: Etch the mixed layer such that the mixed layer is separated to form a type-I connection hole protection layer, a type-II connection hole protection layer and a type-III connection hole protection layer, and use the type-I connection hole protection layer, the type-II connection hole protection layer and the type-III connection hole protection layer as the hole etching protection layer.
5. A method for manufacturing a semiconductor metal field plate according to claim 4, wherein The gate includes a polysilicon structure; the substrate includes an active region; the type-I connection hole protection layer is located on the surface of the polysilicon structure; the type-II connection hole protection layer is located on the surface of the active region; the type-III connection hole protection layer is located on the surface of the metal silicide barrier layer.
6. A method for manufacturing a semiconductor metal field plate according to claim 5, characterized in that, The performing connection hole etching on the interlayer dielectric layer to form a plurality of connection holes penetrating through to the hole etching protection layer includes: Perform connection hole etching on the interlayer dielectric layer to form a type-I connection hole penetrating through to the type-I connection hole protection layer, a type-II connection hole penetrating through to the type-II connection hole protection layer and a type-III connection hole penetrating through to the type-III connection hole protection layer; After the washing and removing of the hole etching protection layer, further included is: Deposit metal silicide in the type-I connection hole and the type-II connection hole so as to form a metal silicide layer on the surface of the polysilicon structure and the active region.
7. A method for manufacturing a semiconductor metal field plate according to claim 1, characterized in that, The forming an interlayer dielectric layer on the surface of the substrate, the gate, the metal silicide barrier layer and the hole etching protection layer includes: Deposit a dielectric structure on the surface of the substrate, the gate, the metal silicide barrier layer and the hole etching protection layer; Perform chemical mechanical polishing on the dielectric structure so as to form an interlayer dielectric layer.
8. A method for manufacturing a semiconductor metal field plate according to claim 1, characterized in that, The washing and removing of the hole etching protection layer includes: Perform wet etching on the hole etching protection layer with phosphoric acid so as to wash and remove the hole etching protection layer.
9. A method for manufacturing a semiconductor metal field plate according to claim 1, characterized in that Forming a metal bonding layer in a plurality of the connection holes includes: Using metal-organic chemical vapor deposition to fill a metal mixture into a plurality of the connection holes; Performing chemical mechanical polishing on the metal mixture to form a metal bonding layer.
10. A semiconductor metal field plate, characterized in that, Prepared by a semiconductor metal field plate manufacturing method according to any one of claims 1 to 9, the semiconductor metal field plate includes a substrate, and a gate, a metal silicide blocking layer and an interlayer dielectric layer are disposed on the surface of the substrate, wherein: The metal silicide blocking layer extends from the surface of the substrate along one side of the gate to the surface of the gate; The interlayer dielectric layer covers the gate and the metal silicide blocking layer; A plurality of connection holes are provided in the interlayer dielectric layer; A plurality of the connection holes respectively penetrate to the surface of the substrate, the surface of the gate and the surface of the metal silicide blocking layer; A metal bonding layer is filled in a plurality of the connection holes.