Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a gate insulating layer, a first gate portion, a second gate portion and a third gate portion, and a groove structure is formed on the substrate; the gate insulating layer is located on the inner wall of the groove structure, and the gate insulating layer comprises a first surface in contact with the inner wall and a second surface opposite to the first surface; the first gate part is located at the bottom of the groove structure and is in contact with the second surface; the second gate part is located on one side, away from the bottom of the groove structure, of the first gate part and has a hollow structure; the third gate part is located in the hollow structure; the work function of the second gate part is smaller than that of the first gate part and the third gate part; and the resistivity of the material adopted by the second gate part is greater than that of the materials adopted by the first gate part and the third gate part. The data retention characteristic and the data operation speed of the semiconductor device provided by the invention are improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Memory is used to store data information in electronic devices such as personal computers, workstations, computer servers, mainframes, and other computer-related devices (such as printers, scanners, and hard disk drives). The memory has data storage capabilities. A widely used random access memory cell is a dynamic random access memory (DRAM) that can be programmed to store a voltage representing one of two binary values. A DRAM cell includes a transistor and a capacitor. The gate structure in the transistor affects the data retention characteristics and data operation speed of the DRAM cell. The data retention characteristics and data operation speed of the DRAM cell in the related art cannot be taken into account at the same time. Summary of the invention

[0003] The purpose of the present application is to at least solve the problem that the data retention characteristics and data operation speed of semiconductor devices cannot be taken into account at the same time. This purpose is achieved through the following technical solutions:

[0004] The first aspect of the present application proposes a semiconductor device, which includes a substrate, a gate insulating layer, a first gate portion, a second gate portion and a third gate portion. A groove structure is formed on the substrate. The gate insulating layer is located on the inner wall of the groove structure, and the gate insulating layer includes a first surface in contact with the inner wall and a second surface opposite to the first surface. The first gate portion is located at the bottom of the groove structure and in contact with the second surface. The second gate portion is located on the side of the first gate portion away from the bottom of the groove structure, the second gate portion is in contact with the second surface, and the second gate portion has a hollow structure connected to the groove structure. The third gate portion is located on the side of the first gate portion away from the bottom of the groove structure, and is located in the hollow structure. Among them, the work function of the second gate portion is smaller than the work function of the first gate portion and the third gate portion; the resistivity of the material used for the second gate portion is greater than the resistivity of the material used for the first gate portion and the third gate portion.

[0005] The semiconductor device provided in the present application includes a substrate, a gate insulating layer, a first gate portion, a second gate portion and a third gate portion. A groove structure is formed on the substrate, and the groove structure is used to accommodate the gate and the word line, so as to bury the gate and the word line under the substrate, thereby reducing the parasitic electrostatic capacitance between the bit line and the word line, so as to improve the sensing margin, reduce the power consumption of the semiconductor device, and improve the performance of the semiconductor device. Specifically, the groove structure is located between the source region and the drain region in the semiconductor device. The gate insulating layer is located on the inner wall of the groove structure, and the gate insulating layer covers the inner wall of the groove structure to achieve isolation of the structure inside the groove structure from other structures in the semiconductor device. The gate insulating layer includes a first surface and a second surface arranged opposite to each other, the first surface is in contact with the inner wall, and the second surface is located on the side of the first surface away from the substrate. The first gate portion is located at the bottom of the groove structure and contacts the second surface, that is, the first gate portion is used to contact the channel in the semiconductor device. Since the work function of the first gate portion is relatively high, the threshold voltage of the transistor can be increased to reduce the doping concentration of the channel, thereby improving the problem of poor data retention performance caused by the reduction of the electric field at the junction; and since the resistivity of the material of the first gate portion is relatively low, the problem of low operating speed of the semiconductor device can be improved. The second gate portion is located on the side of the first gate portion away from the bottom of the groove structure, the second gate portion contacts the second surface, and the second gate portion has a hollow structure connected to the groove structure. The second gate portion is used to contact the source region and the drain region. On the one hand, since the second gate portion adopts a material with a relatively low work function, the gate-induced drain leakage current can be reduced to improve the problem of data retention performance degradation caused by the large gate-induced drain leakage current, thereby improving the data retention time of the semiconductor device; on the other hand, since the second gate portion adopts a hollow structure, and a third gate portion made of a material with a relatively low resistivity is arranged in the hollow structure, the overall resistance of the gate and the word line can be reduced, thereby improving the operating speed of the semiconductor device.

[0006] The second aspect of the present application also provides a method for preparing a semiconductor device, comprising:

[0007] Providing a substrate, and forming a groove structure on the substrate;

[0008] forming a gate insulating layer on the inner wall of the groove structure, wherein the gate insulating layer comprises a first surface in contact with the inner wall and a second surface opposite to the first surface;

[0009] forming a first gate portion at the bottom of the groove structure, the first gate portion being in contact with the second surface;

[0010] A second gate portion is formed on a side of the first gate portion away from the bottom of the groove structure, the second gate portion is in contact with the second surface, and the second gate portion has a hollow structure connected to the groove structure;

[0011] A third gate portion is formed on a side of the first gate portion facing away from the bottom of the groove structure, and the third gate portion is located within the hollow structure;

[0012] Wherein, the work function of the second gate portion is less than the work functions of the first gate portion and the third gate portion; the resistivity of the material used for the second gate portion is greater than the resistivities of the materials used for the first gate portion and the third gate portion. Description of the Drawings

[0013] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of illustrating the preferred embodiments and are not considered to be a limitation of the present application. Moreover, throughout the drawings, the same reference numerals are used to denote the same components. In the drawings:

[0014] Figure 1 is a schematic structural diagram of a semiconductor device in the related art;

[0015] Figure 2 is a schematic structural diagram of another semiconductor device in the related art;

[0016] Figure 3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

[0017] Figure 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application;

[0018] Figure 5 is a schematic structural diagram of yet another semiconductor device provided by an embodiment of the present application;

[0019] Figure 6 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0020] Figures 7 to 13 is a schematic diagram of film layer changes during the manufacturing process of a semiconductor device provided by an embodiment of the present application.

[0021] The reference numerals are as follows:

[0022] 11', Substrate; 12', Buried word line; 13', First gate; 14', Second gate; 1, Semiconductor device; 11, Substrate; 111, Groove structure; 12, Gate insulating layer; 121, First surface; 122, Second surface; 13, First gate portion; 14, Second gate portion; 140, Hollow structure; 41, Second preset surface; 15, Third gate portion; 16, Source region; 161, First preset surface; 17, Drain region; 71, Third preset surface; 18, Insulating layer; 19, Second gate material layer. Detailed implementation manners

[0023] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0024] It should be understood that the terms used herein are for the purpose of describing specific exemplary embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein may also include the plural forms. The terms "comprising", "including", "containing", and "having" are inclusive and thus specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the particular order described or illustrated, unless the order of performance is explicitly stated. It should also be understood that additional or alternative steps may be used.

[0025] Although the terms first, second, third, etc. may be used herein to describe multiple elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as "first" and "second" and other numerical terms used herein do not imply an order or sequence. Thus, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings of the exemplary embodiments.

[0026] For ease of description, spatial relative relationship terms may be used in the text to describe the relationship of one element or feature shown in the figure with respect to another element or feature. These relative relationship terms are, for example, "inside", "outside", "inner side", "outer side", "below", "beneath", "above", "over", etc. Such spatial relative relationship terms are intended to include different orientations of the device during use or operation other than the orientations depicted in the figure. For example, if the device in the figure is flipped, an element described as "below" or "beneath" other elements or features will then be oriented as "above" or "over" other elements or features. Thus, the example term "below" can include both upward and downward orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatial relative relationship descriptors used in the text are interpreted accordingly.

[0027] The fabrication of a dynamic random access memory (DRAM) cell includes the fabrication of transistors, capacitors, bit lines, and word lines. The word lines are typically connected to the gates of the transistors. One way to form the word lines is the buried word line 12' (bWL), which specifically buries the word line beneath the surface of the substrate 11'. Thereby, the parasitic capacitance (CB) between the bit line (BL) and the word line can be reduced, the sensing margin can be significantly improved, and ultimately the power consumption of the DRAM can be reduced. As Figure 1 shown, the buried word line 12' (and the gate connected to the buried word line 12') typically uses a metal material. The metal material can reduce the resistance of the word line and the gate. The metal material has a high work function, which can increase the threshold voltage (VT) of the transistor, thereby reducing the channel doping concentration. Furthermore, the problem of poor data retention performance caused by the reduction of the electric field at the junction inside the transistor can be improved. However, due to the scaling requirements of semiconductor devices, transistors with such buried word lines 12' (and the gates connected to the buried word lines 12') having a high work function are prone to an increase in gate induced drain leakage (GIDL), resulting in a decrease in the data retention performance of the DRAM.

[0028] To improve the problem of deteriorated data retention performance caused by gate induced drain leakage (GIDL), a gate with a dual function (DoubleWG, DWG) can be used in the DRAM cell to replace the gate with a single function (Single Work-function Gate, SWG). Specifically, as Figure 2 shown, the gate includes two parts with different work functions, and the two parts are stacked on top of each other in the trench of the substrate 11'. The first gate 13' with a high work function is at the bottom, and the second gate 14' with a low work function is on top. The second gate 14' contacts the source and drain of the transistor, and the first gate 13' contacts the channel of the transistor. However, with the continuous miniaturization of semiconductor devices, the volume of the gate is further reduced. Due to the high resistance of the second gate 14', the overall resistance of the gate and the buried word line (WL) surges, resulting in a decrease in the operating speed of the DRAM and making it difficult to meet the current usage requirements. Based on the research of the above problems, the present application provides a semiconductor device and a manufacturing method thereof to reduce the resistance of the gate and the word line and improve the data retention performance.

[0029] As Figure 3 , according to an embodiment of the present application, a semiconductor device 1 is proposed. The semiconductor device 1 includes a substrate 11, a gate insulating layer 12, a first gate portion 13, a second gate portion 14, and a third gate portion 15. A groove structure 111 is formed on the substrate 11. The gate insulating layer 12 is located on the inner wall of the groove structure 111. The gate insulating layer 12 includes a first surface 121 in contact with the inner wall and a second surface 122 opposite to the first surface 121. The first gate portion 13 is located at the bottom of the groove structure 111 and contacts the second surface 122. The second gate portion 14 is located on a side of the first gate portion 13 away from the bottom of the groove structure 111. The second gate portion 14 contacts the second surface 122, and the second gate portion 14 has a hollow structure 140 communicating with the groove structure 111. The third gate portion 15 is located on a side of the first gate portion 13 facing away from the bottom of the groove structure 111 and is located inside the hollow structure 140. Among them, the work function of the second gate portion 14 is less than the work functions of the first gate portion 13 and the third gate portion 15; the resistivity of the material used for the second gate portion 14 is greater than the resistivity of the materials used for the first gate portion 13 and the third gate portion 15.

[0030] The semiconductor device 1 provided in the present application includes a substrate 11, a gate insulating layer 12, a first gate portion 13, a second gate portion 14 and a third gate portion 15. A groove structure 111 is formed on the substrate 11. The groove structure 111 is used to accommodate the gate and the word line, so as to bury the gate and the word line under the substrate 11, thereby reducing the parasitic electrostatic capacitance between the bit line and the word line, so as to improve the sensing margin, reduce the power consumption of the semiconductor device 1, and improve the performance of the semiconductor device 1. Specifically, the groove structure 111 is located between the source region 16 and the drain region 17 in the semiconductor device 1. The gate insulating layer 12 is located on the inner wall of the groove structure 111, and the gate insulating layer 12 covers the inner wall of the groove structure 111 to achieve isolation of the structure in the groove structure 111 from other structures in the semiconductor device 1. The gate insulating layer 12 includes a first surface 121 and a second surface 122 arranged opposite to each other, the first surface 121 is in contact with the inner wall, and the second surface 122 is located on the side of the first surface 121 away from the substrate 11. The first gate portion 13 is located at the bottom of the groove structure 111 and contacts the second surface 122, that is, the first gate portion 13 is used to contact the channel in the semiconductor device 1. Since the work function of the first gate portion 13 is relatively high, the threshold voltage of the transistor can be increased to reduce the doping concentration of the channel, thereby improving the problem of poor data retention performance caused by the reduction of the electric field at the junction; and since the resistivity of the material of the first gate portion 13 is relatively low, the problem of low operating speed of the semiconductor device 1 can be improved. The second gate portion 14 is located on a side of the first gate portion 13 away from the bottom of the groove structure 111. The second gate portion 14 contacts the second surface 122. The second gate portion 14 has a hollow structure 140 connected to the groove structure 111. The second gate portion 14 is used to contact the source region 16 and the drain region 17. On the one hand, since the second gate portion 14 adopts a material with a lower work function, the gate-induced drain leakage current can be reduced to improve the problem of data retention performance degradation caused by a large gate-induced drain leakage current, thereby improving the data retention time of the semiconductor device 1; on the other hand, since the second gate portion 14 adopts a hollow structure, and a third gate portion 15 made of a material with a lower resistivity is arranged in the hollow structure 140, the overall resistance of the gate and the word line can be reduced, thereby improving the operating speed of the semiconductor device 1.

[0031] In the present application, the semiconductor device 1 may be a memory, specifically a dynamic random access memory (DRAM), or a transistor in a dynamic random access memory.

[0032] The gate within the groove structure 111 and the portions of the word line that contact the source region 16 and the drain region 17 in the semiconductor device 1 are formed of a material having a low work function and a relatively high resistivity, so as to improve the problem of deterioration of DRAM data transfer characteristics due to a relatively high gate-induced drain leakage current. By respectively disposing the first gate portion 13 and the third gate portion 15 formed of a material having a relatively low resistivity and a relatively high work function within the bottom of the groove structure 111 and the hollow structure 140 of the second gate portion 14, the overall resistance of the gate and the word line can be reduced, thereby improving the problem of reduced DRAM operation speed.

[0033] In the above-described embodiment, the substrate 11 can be formed of any suitable material.

[0034] Specifically, the material of the substrate 11 can include one or more of silicon oxynitride (SiON), silicon oxide (SiOx), or a high-k dielectric material.

[0035] The material of the gate insulating layer 12 can include an oxide material, specifically, it can include silicon oxide and the like.

[0036] In the above-described embodiment, the first gate portion 13, the second gate portion 14, and the third gate portion 15 together form the gate and the word line of the semiconductor device 1.

[0037] In a feasible embodiment, as Figure 3 shown, the substrate 11 further includes a source region 16 and a drain region 17. The source region 16 and the drain region 17 are located on both sides of the groove structure 111. A second gate portion 14 is disposed between the source region 16 and the third gate portion 15 and between the drain region 17 and the third gate portion 15.

[0038] In the above-described embodiment, the source region 16 and the drain region 17 are located on both sides of the groove structure 111. The portion of the substrate 11 between the source region 16 and the drain region 17 forms a channel region, that is, the channel region is located below the groove structure 111. By connecting the first gate portion 13 to the channel region structure, the second gate portion 14 is in contact with the source region 16 and the drain region 17, and the third gate portion 15 is filled within the hollow structure 140 of the second gate portion 14, the data retention characteristics of the semiconductor device 1 can be improved while the data operation speed of the semiconductor device 1 is increased.

[0039] In a feasible embodiment, as Figure 3 and Figure 4 shown, the source region 16 includes a first preset surface 161 near the bottom of the groove structure 111, the second gate portion 14 includes a second preset surface 41 near the bottom of the groove structure 111, and the drain region 17 includes a third preset surface 71 near the bottom of the groove structure 111. As Figure 4As shown, the first preset surface 161 is located on the side of the second preset surface 41 away from the bottom of the groove structure 111, or, as Figure 3 shown, the first preset surface 161 is flush with the second preset surface 41. As Figure 4 shown, the third preset surface 71 is located on the side of the second preset surface 41 away from the bottom of the groove structure 111, or, as Figure 3 shown, the third preset surface 71 is flush with the second preset surface 41.

[0040] In the above embodiments, by setting the first preset surface 161 to be located on the side of the second preset surface 41 away from the bottom of the groove structure 111, or the first preset surface 161 is flush with the second preset surface 41, the relative area contact effect between the second gate portion 14 and the source region 16 can be ensured, the probability of direct contact between the first gate portion 13 and the source region 16 is reduced, and the probability of direct contact between the third gate portion 15 and the source region 16 is reduced. By setting the third preset surface 71 to be located on the side of the second preset surface 41 away from the bottom of the groove structure 111, or the third preset surface 71 is flush with the second preset surface 41, the relative area of the contact effect between the second gate portion 14 and the drain region 17 can be ensured, the probability of direct contact between the first gate portion 13 and the drain region 17 is reduced, and the probability of direct contact between the third gate portion 15 and the drain region 17 is reduced. Since the work function of the second gate portion 14 is less than the work functions of the first gate portion 13 and the third gate portion 15, by designing the second gate portion 14 to be close to the contact with the source region 16 and the drain region 17, the gate-induced drain leakage current of the semiconductor device 1 can be reduced, thereby improving the data retention performance and reliability of the semiconductor device 1.

[0041] In a feasible embodiment, the material of the first gate portion 13 includes a metal. Specifically, the first gate portion 13 can adopt a material with low resistance and high work function such as TiN.

[0042] In a feasible embodiment, the material of the third gate portion 15 includes a metal. Specifically, the third gate portion 15 can adopt a material with low resistance and high work function such as TiN.

[0043] In a feasible embodiment, the material of the second gate portion 14 includes polysilicon. Specifically, it can be N+ polysilicon (poly-Si).

[0044] In a feasible embodiment, the materials of the first gate portion 13 and the third gate portion 15 are the same.

[0045] In the above embodiments, the materials of the first gate portion 13 and the third gate portion 15 are the same, which can reduce the number of materials used in the manufacturing process, simplify the manufacturing process, and the same materials of the first gate portion 13 and the third gate portion 15 can improve their contact characteristics, thereby improving the performance of the semiconductor device 1.

[0046] In a feasible implementation, the polysilicon is doped with doping particles, and the concentration range of the doping particles is 10^18 / cm 3 -10^20 / cm 3 .

[0047] Specifically, the second gate portion 14 can adopt a heavily doped N-type semiconductor material, and the doping particles can specifically be pentavalent elements such as phosphorus and arsenic to ensure the current transmission performance of the second gate portion 14.

[0048] In a feasible implementation, the size of the first gate portion 13 in the depth direction of the groove structure 111 is H1, and 10 nm ≤ H1 ≤ 100 nm.

[0049] Specifically, the size H1 of the first gate portion 13 in the depth direction of the groove structure 111 can specifically be: 10 nm, 20 nm, 35 nm, 49 nm, 56 nm, 82 nm, 95 nm, 100 nm, and so on.

[0050] In the above implementation, if the size of the first gate portion 13 in the depth direction of the groove structure 111 is too small, it will affect the overall resistance of the gate. If it is too large, it will cause an increase in the gate-induced drain leakage (GIDL) due to the correspondence with the source region and the drain region, resulting in deterioration of the data retention performance. When the size of the first gate portion 13 in the depth direction of the groove structure 111 is set to 10 nm - 100 nm, the overall resistance of the gate and the gate-induced drain leakage can be balanced.

[0051] In a feasible implementation, the size of the second gate portion 14 in the depth direction of the groove structure 111 is H2, 1 nm ≤ H1 ≤ 100 nm, and the size of the second gate portion 14 in the direction perpendicular to the inner wall of the groove structure 111 is D1, 1 nm ≤ D1 ≤ 50 nm.

[0052] Specifically, the size H2 of the second gate portion 14 in the depth direction of the groove structure 111 can specifically be: 1 nm, 5 nm, 8 nm, 10 nm, 20 nm, 36 nm, 47 nm, 55 nm, 83 nm, 91 nm, 100 nm, and so on.

[0053] In the above embodiments, if the dimension of the second gate portion 14 in the depth direction of the groove structure 111 is too small, it will affect the relative effect between the second gate portion 14 and the source region and the drain region, and it is easy to cause an increase in the gate-induced drain leakage (GIDL), thereby resulting in deterioration of the data retention performance. If the dimension of the second gate portion 14 in the depth direction of the groove structure 111 is too large, it will affect the overall resistance of the gate, thereby affecting the data operation speed. When the dimension of the second gate portion 14 in the depth direction of the groove structure 111 is set to 1 nm - 100 nm, the overall resistance of the gate and the gate-induced drain leakage can be taken into account.

[0054] Specifically, the dimension D1 of the second gate portion 14 in the direction perpendicular to the inner wall of the groove structure 111 can specifically be: 1 nm, 5 nm, 8 nm, 10 nm, 20 nm, 36 nm, 47 nm, 50 nm, etc.

[0055] In the above embodiments, if the dimension of the second gate portion 14 in the direction perpendicular to the inner wall of the groove structure 111 is too small, it will result in poor manufacturing yield and high manufacturing difficulty. When the yield is poor, it is easy to affect the gate-induced drain leakage. If the dimension of the second gate portion 14 in the direction perpendicular to the inner wall of the groove structure 111 is too large, it will affect the overall resistance of the gate, thereby affecting the data operation speed. When the dimension of the second gate portion 14 in the direction perpendicular to the inner wall of the groove structure 111 is set to 1 nm - 50 nm, the overall resistance of the gate and the gate-induced drain leakage can be taken into account.

[0056] In a feasible embodiment, the dimension of the third gate portion 15 in the depth direction of the groove structure 111 is H3, and 10 nm ≤ H3 ≤ 100 nm.

[0057] Specifically, the dimension H3 of the third gate portion 15 in the depth direction of the groove structure 111 can specifically be: 10 nm, 20 nm, 35 nm, 49 nm, 56 nm, 82 nm, 95 nm, 100 nm, etc.

[0058] In the above embodiments, if the dimension of the third gate portion 15 in the depth direction of the groove structure 111 is too small, it will affect the overall resistance of the gate, and its size should match the size of the hollow structure 140.

[0059] In a feasible embodiment, as Figure 5 shown, the semiconductor device 1 further includes an insulating layer 18. The insulating layer 18 is located in the groove structure 111, and the insulating layer 18 is located on the side of the second gate portion 14 and the third gate portion 15 away from the bottom of the groove structure 111.

[0060] In the above embodiments, by providing an insulating layer 18 within the groove structure 111, on one hand, the second gate portion 14 and the third gate portion 15 can be protected, and on the other hand, mutual isolation between the second gate portion 14, the third gate portion 15 and the subsequent structures located on the substrate 11 can be achieved. Moreover, by providing the insulating layer 18, the groove structure 111 can be filled, reducing the step difference on the surface of the substrate 11 at the groove structure 111.

[0061] The present application also provides a method for manufacturing a semiconductor device 1, as Figure 6 shown, including:

[0062] S200, as Figure 7 shown, provide a substrate 11 and form a groove structure 111 on the substrate 11.

[0063] Specifically, the material of the substrate 11 may include one or more of silicon oxynitride (SiON), silicon oxide (SiOx), or a high-K dielectric material.

[0064] Specifically, forming the groove structure 111 on the substrate 11 may include: etching the substrate 11 using an etching process to form the groove structure 111. Before etching, a patterned mask layer may be formed on one side surface of the substrate 11 to locate the position where the groove structure 111 is to be etched. The mask layer may be made of photoresist material. The process of forming the mask layer includes: uniformly coating a layer of photoresist on the surface of the substrate 11, exposing the photoresist using a mask plate and a light source (such as ultraviolet light or extreme ultraviolet light). Through the design of the mask plate, the shape and size of the exposed area can be controlled. The exposed photoresist is developed to remove the photoresist in the exposed area, forming a mask area and a non-mask area. The non-mask area is etched using a dry or wet etching process to transfer the photoresist pattern onto the substrate 11, thereby forming the groove structure 111.

[0065] S400, as Figure 8 shown, form a gate insulating layer 12 on the inner wall of the groove structure 111. The gate insulating layer 12 includes a first surface 121 in contact with the inner wall and a second surface 122 opposite to the first surface 121.

[0066] Specifically, the material of the gate insulating layer 12 is an oxide, and the gate insulating layer 12 can be formed on the inner wall of the groove structure 111 using an oxidation or deposition process.

[0067] Specifically, when forming the gate insulating layer 12, it can be directly formed on the inner wall of the groove structure 111, or simultaneously formed on the inner wall of the groove structure 111 and the surface of the substrate 11 close to the opening of the groove structure 111, and then the gate insulating layer 12 on the surface of the substrate 11 close to the opening of the groove structure 111 is removed through subsequent processes.

[0068] S600, as Figure 9 shown, a first gate portion 13 is formed at the bottom of the groove structure 111, and the first gate portion 13 is in contact with the second surface 122.

[0069] Specifically, as Figure 10 shown, when forming the first gate portion 13 at the bottom of the groove structure 111, the material for forming the first gate portion 13 can be filled in the groove structure 111, and part of the material for forming the first gate portion 13 is removed by an etching process, and only the part located at the bottom of the groove structure 111 is retained, thereby forming the first gate portion 13.

[0070] Specifically, the dimension of the first gate portion 13 in the depth direction of the groove structure 111 is H1, and 10 nm ≤ H1 ≤ 100 nm.

[0071] S800, as Figure 11 shown, a second gate portion 14 is formed on the side of the first gate portion 13 away from the bottom of the groove structure 111. The second gate portion 14 is in contact with the second surface 122, and the second gate portion 14 has a hollow structure 140 communicating with the groove structure 111.

[0072] Specifically, when forming the second gate portion 14, a material layer for forming the second gate portion 14 can be simultaneously formed in the groove structure 111 and on the surface of the substrate 11 close to the opening of the groove structure 111, and then the second gate material layer 19 is anisotropically etched to form the second gate portion 14.

[0073] Specifically, the dimension of the second gate portion 14 in the depth direction of the groove structure 111 is H2, and 1 nm ≤ H1 ≤ 100 nm. The dimension of the second gate portion 14 in the direction perpendicular to the inner wall of the groove structure 111 is D1, and 1 nm ≤ D1 ≤ 50 nm.

[0074] The dimension of the second gate portion 14 in the direction perpendicular to the inner wall of the groove structure 111 is the thickness of the second gate portion 14. When the second gate portion 14 is too thick, it will affect the size of the hollow space, thereby affecting the volume of the third gate portion 15. The larger the volume of the third gate portion 15, the smaller the volume of the second gate portion 14, and the smaller the total resistance of the gate. That is, the dimension of the second gate portion 14 in the direction perpendicular to the inner wall of the groove structure 111 should not be too large. At the same time, the dimension of the second electrode portion in the direction perpendicular to the inner wall of the groove structure 111 should not be too small. Otherwise, on the one hand, it is not easy to ensure the continuity of film formation, that is, the preparation yield is low. On the other hand, if the second gate portion 14 is too thin, it is not easy to reduce the gate-induced drain leakage current, resulting in poor improvement effect on the data retention characteristics of the semiconductor device 1.

[0075] S1000, such as Figure 12 As shown, a third gate portion 15 is formed on the side of the first gate portion 13 facing away from the bottom of the groove structure 111, and the third gate portion 15 is located in the hollow structure 140.

[0076] Specifically, when forming the third gate portion 15 in the groove structure 111, a material for forming the third gate portion 15 can be filled in the groove structure 111, and a etching process is used to remove part of the material for forming the third gate portion 15, only retaining the part located in the hollow structure 140, thereby forming the third gate portion 15.

[0077] Specifically, the dimension of the third gate portion 15 in the depth direction of the groove structure 111 is H3, and 10 nm ≤ H3 ≤ 100 nm.

[0078] Among them, the work function of the second gate portion 14 is less than the work functions of the first gate portion 13 and the third gate portion 15; the resistivity of the material used for the second gate portion 14 is greater than the resistivities of the materials used for the first gate portion 13 and the third gate portion 15.

[0079] In the above preparation method, a first gate portion 13 is formed at the bottom of the groove structure 111. The work function of the first gate portion 13 is relatively high and the resistivity of the material used to prepare and form the first gate portion 13 is relatively low. The first gate portion 13 is used to contact the channel region in the semiconductor device 1. A second gate portion 14 is formed at a position close to the inner wall of the groove structure 111. A hollow structure 140 is formed in the second gate portion 14, and a third gate portion 15 is formed in the hollow structure 140. The second gate portion 14 is used to be disposed opposite to the source region 16 and the drain region 17 in the semiconductor device 1. The second gate portion 14 has a low work function, so as to improve the problem of deterioration of the DRAM data transmission characteristics caused by a relatively high gate-induced drain leakage current. The third gate portion 15 has a relatively high work function and is prepared and formed by using a material with a relatively low resistivity, so as to reduce the overall resistance of the gate and the word line, thereby improving the problem of reduction of the DRAM operation speed. This preparation method is simple and has a relatively high preparation yield. The semiconductor device 1 prepared by using this preparation method can achieve both high data storage characteristics and high data operation speed, thereby comprehensively improving the performance of the semiconductor device 1.

[0080] In a feasible implementation manner, as Figure 13 shown, the preparation method of the semiconductor device 1 provided in the present application further includes: forming an insulating layer 18 on a side of the second gate portion 14 and the third gate portion 15 facing away from the bottom of the groove structure 111, and the insulating layer 18 is located in the groove structure 111.

[0081] Specifically, when forming the insulating layer 18, an insulating material layer may be deposited in the groove structure 111 and on a surface of the substrate 11 close to the opening of the groove structure 111, and the insulating material layer is patterned by an etching process, and only the part of the insulating material layer located in the groove structure 111 is retained to form the insulating layer 18, so as to fill the groove structure 111 through the insulating layer 18.

[0082] In a feasible implementation manner, as Figure 5 shown, the preparation method of the semiconductor device 1 provided in the present application further includes: forming a source region 16 and a drain region 17 on both sides of the groove structure 111 respectively.

[0083] Specifically, the source region 16 and the drain region 17 are formed by an ion implantation process, and the implantation depth does not exceed a surface of the second gate portion 14 close to the first gate portion 13, so as to improve the effect of the second gate portion 14 on reducing the gate-induced drain leakage current, thereby improving the data retention characteristics of the semiconductor device 1.

[0084] The above are only the preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a groove structure formed thereon; a gate insulating layer, located on the inner wall of the groove structure, the gate insulating layer comprising a first surface in contact with the inner wall and a second surface opposite to the first surface; A first gate portion, located at the bottom of the groove structure and in contact with the second surface; A second gate portion, located at a side of the first gate portion away from the bottom of the groove structure, the second gate portion is in contact with the second surface, and the second gate portion has a hollow structure connected to the groove structure; a third gate portion, located at a side of the first gate portion away from the bottom of the groove structure and located in the hollow structure; The work function of the second gate portion is smaller than the work functions of the first gate portion and the third gate portion; and the resistivity of the material used for the second gate portion is greater than the resistivity of the material used for the first gate portion and the third gate portion.

2. The semiconductor device according to claim 1, wherein The substrate further includes a source region and a drain region, wherein the source region and the drain region are located at two sides of the groove structure, and the second gate portion is disposed between the source region and the third gate portion and between the drain region and the third gate portion.

3. The semiconductor device according to claim 2, wherein, The source region includes a first preset surface close to the bottom of the groove structure, the second gate portion includes a second preset surface close to the bottom of the groove structure, and the drain region includes a third preset surface close to the bottom of the groove structure; The first preset surface is located on a side of the second preset surface away from the bottom of the groove structure, or the first preset surface is flush with the second preset surface; The third preset surface is located on a side of the second preset surface away from the bottom of the groove structure, or the third preset surface is flush with the second preset surface.

4. The semiconductor device according to claim 1, wherein, The material of the first gate portion includes metal; and / or, The material of the third gate portion includes metal; and / or, The material of the second gate portion includes polysilicon.

5. The semiconductor device according to claim 4, wherein The first gate portion and the third gate portion are made of the same material.

6. The semiconductor device according to claim 4, wherein The polysilicon is doped with doping particles, and the concentration range of the doping particles is 10 18 / cm 3 -10 20 / cm 3 .

7. The semiconductor device according to claim 1, wherein, The dimension of the first gate portion along the depth direction of the groove structure is H1, 10nm≤H1≤100nm; and / or, The dimension of the second gate portion along the depth direction of the groove structure is H2, 1nm≤H1≤100nm, and the dimension of the second gate portion along the direction perpendicular to the inner wall of the groove structure is D1, 1nm≤D1≤50nm; and / or, A dimension of the third gate portion along a depth direction of the groove structure is H3, and 10 nm ≤ H3 ≤ 100 nm.

8. The semiconductor device according to claim 1, wherein, The semiconductor device further includes an insulating layer, wherein the insulating layer is located in the groove structure, and the insulating layer is located on a side of the second gate portion and the third gate portion away from a bottom of the groove structure.

9. A method for manufacturing a semiconductor device, characterized in that, include: Providing a substrate, and forming a groove structure on the substrate; forming a gate insulating layer on the inner wall of the groove structure, wherein the gate insulating layer comprises a first surface in contact with the inner wall and a second surface opposite to the first surface; forming a first gate portion at the bottom of the groove structure, the first gate portion being in contact with the second surface; A second gate portion is formed on a side of the first gate portion away from the bottom of the groove structure, the second gate portion contacts the second surface, and the second gate portion has a hollow structure communicating with the groove structure; A third gate portion is formed on a side of the first gate portion facing away from the bottom of the groove structure, and the third gate portion is located within the hollow structure; Wherein, the work function of the second gate portion is less than the work functions of the first gate portion and the third gate portion; the resistivity of the material used for the second gate portion is greater than the resistivity of the materials used for the first gate portion and the third gate portion.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, It further includes forming an insulating layer on a side of the second gate portion and the third gate portion facing away from the bottom of the groove structure, and the insulating layer is located within the groove structure.

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