Semiconductor device with via-shaped cut gate structure and method of manufacturing same

Abstract

The invention relates to a semiconductor device having a via-shaped cut gate structure and a method of manufacturing the same. The embodiment of the invention provides a semiconductor device with a via-shaped cut gate structure. The via-shaped cut gate structure may be formed by a self-aligned patterning process and may minimize parasitic capacitance in the semiconductor device. In some embodiments, a protective layer is deposited over the ILD layer to implement a self-aligned patterning process. In some embodiments, the protection layer may be formed by recessing and etching the ILD layer between the gate structures and filling the recess with a dielectric layer. In some embodiments, the protective layer may include silicon nitride.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a via-shaped cut gate structure and a method of manufacturing the same. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials over a semiconductor substrate and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the Invention

[0004] According to one aspect of the present disclosure, there is provided a method including: forming a semiconductor structure including a first semiconductor fin structure and a second semiconductor fin structure extending in a first direction; a gate structure spanning the first semiconductor fin structure and the second semiconductor fin structure; a first source / drain region on the first semiconductor fin structure; a second source / drain region on the second semiconductor fin structure; and an interlayer dielectric (ILD) layer over the first source / drain region and the second source / drain region; depositing a mask layer over the semiconductor structure; forming a first opening through the mask layer, wherein the first opening extends in the first direction disposed between the first semiconductor fin structure and the second semiconductor fin structure and the first opening exposes a portion of the gate structure and the ILD layer; forming a via opening in the gate structure through the first opening in the mask layer, wherein the via opening divides the gate structure into two segments; and filling a dielectric material in the via opening to form a cut gate structure.

[0005] According to another aspect of the present disclosure, there is provided a semiconductor device including: a first semiconductor fin structure and a second semiconductor fin structure extending in a first direction; and a gate structure spanning the first semiconductor fin structure and the second semiconductor fin structure, wherein the gate structure includes: a first gate segment disposed over the first semiconductor fin structure; a second gate segment disposed over the second semiconductor fin structure; a cut gate structure disposed between the first gate segment and the second gate segment; a first gate sidewall spacer; and a second gate sidewall spacer, wherein the cut gate structure is disposed between the first gate sidewall spacer and the second gate sidewall spacer.

[0006] According to yet another aspect of the present disclosure, there is provided a semiconductor device including: a first gate structure; a second gate structure parallel to the first gate structure; a first source / drain region formed between the first gate structure and the second gate structure; a second source / drain region formed between the first gate structure and the second gate structure; a source / drain contact feature in contact with the first source / drain region and the second source / drain region; a first cut gate structure disposed in the first gate structure; a second cut gate structure disposed in the second gate structure; a first dielectric layer disposed between the source / drain contact feature and the first cut gate structure; and a second dielectric layer disposed between the source / drain contact feature and the second cut gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure may be best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 2 to 10 、 Figures 10A to 10D 、 Figure 11 、 Figure 12 、 Figures 12A to 12D 、 Figure 13 、 Figures 13A to 13D 、 Figures 14A to 14D 、 Figure 15 、 and Figures 15A to 15D schematically illustrates various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 16 is a schematic diagram of a semiconductor device according to the present disclosure including a cut gate structure.

[0011] Figure 17 、 Figures 18A to 18C to Figures 29A to 29C schematically illustrates various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 30A to 30C to Figures 33A to 33C schematically illustrates various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 34 、 Figures 34A to 34B 、 Figure 35 、 Figures 35A to 35B 、 Figure 36 、Figures 36A to 36B , Figure 37 , Figures 37A to 37B and Figures 38A to 38B schematically illustrate various stages of fabricating a semiconductor device in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific instances of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, spatially relative terms (such as, "beneath", "below", "lower", "above", "on", "top", "upper", etc.) may be used herein to facilitate describing one element or feature shown in the figures relative to another (one or more) element or (one or more) feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] The foregoing generally outlines some aspects of the embodiments described in the present disclosure. Although some of the embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and / or other devices, such as planar FETs, finFETs, horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, and other suitable devices. Those of ordinary skill in the art will readily appreciate other modifications that may be made within the scope of the present disclosure. Further, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein. The (one or more) source / drain regions may refer to the source or the drain individually or jointly, depending on the context. In the present disclosure, source / drain refers to the source and / or the drain. The source and the drain may be used interchangeably.

[0017] The fins can be patterned by any suitable method. For example, one or more lithography processes (including double-patterning or multi-patterning processes) can be used to pattern the fins. Generally, double-patterning or multi-patterning processes combine lithography processes and self-alignment processes, thereby allowing the generation of patterns with, for example, pitches smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0018] When fabricating field-effect transistors, in modern complementary metal-oxide-semiconductor (CMOS) technology, gate patterning (such as the cut polycrystalline silicon (CPO) process and the cut metal gate (CMG) process) is typically used to form circuits. As device dimensions decrease, dielectric refill after the patterning process may result in significant parasitic capacitance that is detrimental to AC applications.

[0019] Embodiments of the present disclosure provide a semiconductor device having a via-shaped cut gate structure. The via-shaped cut gate structure can be formed by a self-alignment patterning process and can minimize parasitic capacitance in the semiconductor device. In some embodiments, a protective layer is deposited over the ILD layer to enable the self-alignment patterning process. In some embodiments, the protective layer can be formed by recess-etching the ILD layer between the gate structures and filling the recesses with a dielectric layer. In some embodiments, the protective layer can include silicon nitride.

[0020] Figure 1 is a flowchart of a method 100 for manufacturing a semiconductor device 200 according to an embodiment of the present disclosure. Figures 2 to 13 Schematically illustrates various stages of manufacturing an exemplary semiconductor device 200 according to an embodiment of the present disclosure. Specifically, the semiconductor device 200 can be manufactured according to Figure 1 method 100.

[0021] At operation 102 of method 100, a plurality of fin structures are formed on a substrate on which a semiconductor device is to be formed, as Figure 2 shown, Figure 2 is a schematic perspective view of the semiconductor device 200. A substrate 202 is provided on which the semiconductor device 200 is to be formed. The substrate 202 can include a single-crystalline semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 202 can include various doping configurations, depending on the circuit design. At Figure 2In this case, the substrate 202 includes a p-doped region (or p-well) 204a and an n-doped region (or n-well) 204b. One or more n-type devices (e.g., nFETs) will be formed above and / or within the p-well 204a. One or more p-type devices (e.g., pFETs) will be formed above and / or within the n-well 204b. Figure 2 It is shown that the p-well 204a is in a doped local region of the doped substrate, which is not restrictive. In other embodiments, the p-well 204a and the n-well 204b may be separated by one or more insulators (e.g., STI).

[0022] A semiconductor stack including alternating first semiconductor layers 206a and second semiconductor layers 208a is formed above the p-well 204a to facilitate the formation of a nanosheet channel in a multi-gate n-type device (e.g., a nanosheet channel nFET). The first semiconductor layer 206a and the second semiconductor layer 208a have different compositions. In some embodiments, the two semiconductor layers 206a and 208a provide different oxidation rates and / or different etching selectivities. In a subsequent manufacturing stage, portions of the second semiconductor layer 208a form the nanosheet channel in the multi-gate device. Three first semiconductor layers 206a and three second semiconductor layers 208a are alternately arranged, as Figure 2 shown as an example. More or fewer semiconductor layers 206a and 208a may be included, depending on the desired number of channels in the semiconductor device to be formed. In some embodiments, the number of semiconductor layers 206a and 208a is between 1 and 10.

[0023] In some embodiments, the first semiconductor layer 206a may include silicon germanium (SiGe). The first semiconductor layer 206a may be a SiGe layer including more than 25% molar ratio of Ge. For example, the first semiconductor layer 206a may be a SiGe layer including Ge in the range of 25% to 50% molar ratio. The second semiconductor layer 208a may include silicon. In some embodiments, the second semiconductor layer 208a may be an undoped Si layer. Alternatively, the second semiconductor layer 208a may be a Ge layer. The second semiconductor layer 208a may include an n-type dopant, such as phosphorus (P), arsenic (As), etc.

[0024] Similarly, a semiconductor stack including alternating third semiconductor layers 206b and fourth semiconductor layers 208b is formed above the n-well 204b to facilitate the formation of a nanosheet channel in a multi-gate p-type device, such as a nanosheet channel PMOS.

[0025] In some embodiments, the third semiconductor layer 206b may include silicon germanium (SiGe). The third semiconductor layer 206b may be a SiGe layer including more than 25% molar ratio of Ge. For example, the third semiconductor layer 206b may be a SiGe layer including Ge with a molar ratio in the range between 25% and 50%. The fourth semiconductor layer 208b may include silicon, Ge, compound semiconductors (such as SiC, GeAs, GaP, InP, InAs, and / or InSb), alloy semiconductors (SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or a combination of the foregoing. In some embodiments, the fourth semiconductor layer 208b may be a Ge layer. The fourth semiconductor layer 208b may include a p-type dopant, such as boron, etc. In some embodiments, in the following process, the materials of the interposer 206a and 206b may be replaced with silicon oxide or silicon nitride.

[0026] The semiconductor layers 206a, 206b, 208a, 208b may be formed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. Patterning techniques may be used to separately form the semiconductor stack on the n-well 204b and the p-well 204a.

[0027] Then, fin structures 210a, 210b (collectively 210) are formed by etching the semiconductor stack and a part of the underlying n-well 204b, p-well 204a respectively, as Figure 2 shown. The fin structures 210a, 210b are substantially parallel and separated by the trench 205. Although the fin structures 210a, 210b of the nanosheet FET device are shown in the semiconductor device 200, the embodiments of the present disclosure are also applicable to planar FETs, Fin-FETs, horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, and other suitable devices.

[0028] At operation 104, a sacrificial gate structure 214 is formed on the fin structures 210a, 210b and on the isolation layer 212, as Figure 3 shown, Figure 3It is a schematic diagram of a semiconductor device 200. An isolation layer 212 is filled in the trench 215 between the fin structures 210a and 210b, and then it is etched back below the semiconductor stack of the fin structures 210a and 210b. The isolation layer 212 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 212 can include silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectric, a combination of the foregoing items. In some embodiments, the isolation layer 212 is formed by an appropriate deposition process to cover the fin structures 210a and 210b to fill the trench 205 between the fin structures 210a and 210b, and then an appropriate anisotropic etching process is used to etch the recessed isolation layer 212 to expose the active portions of the fin structures 210a and 210b. As Figure 3 shown, after operation 104, the isolation layer 212 fills the bottom of the trench 205 between the fin structures 210. Specifically, the stack of semiconductor layers 206a, 206b, 208a, and 208b extends above the top surface of the isolation layer 212.

[0029] A sacrificial gate structure 214 is formed above the isolation layer 212 and around the exposed portions of the fin structures 210a and 210b. The sacrificial gate structure 214 is formed above the portions of the fin structures 210a and 210b that will become the channel regions. A trench 215 is formed between adjacent sacrificial gate structures 214. The sacrificial gate structure 214 is substantially perpendicular to the fin structures 210.

[0030] A sacrificial gate dielectric layer 218 can be conformally formed above the fin structures 210a and 210b and the isolation layer 212. In some embodiments, the sacrificial gate dielectric layer 218 can be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, an FCVD process, an ALD process, a PVD process, or other suitable processes. The sacrificial gate dielectric layer 218 can include one or more layers of dielectric materials, such as SiO2, SiN, high-k dielectric materials, and / or other suitable dielectric materials.

[0031] A sacrificial gate electrode layer 220 can be deposited blanketly on the sacrificial gate dielectric layer 218. The sacrificial gate electrode layer 220 includes silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in the range between about 42 nm and about 200 nm. In some embodiments, a planarization operation is performed on the sacrificial gate electrode layer 220. The sacrificial gate electrode layer 220 can be deposited by CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes.

[0032] Subsequently, a liner layer 222 and a mask layer 224 are formed over the sacrificial gate electrode layer 220. The liner layer 222 may include silicon nitride. The mask layer 224 may include silicon oxide. Next, a process sequence including patterning and etching is performed on the mask layer 224, the liner layer 222, the sacrificial gate electrode layer 220, and the sacrificial gate dielectric layer 218 to form the sacrificial gate structure 214. Portions of the sacrificial gate electrode layer 220 and the sacrificial gate dielectric layer 218 are removed in sequence using the pattern formed in the mask layer 224 to form the sacrificial gate structure 214.

[0033] At operation 106, a gate sidewall spacer 216 is formed over the semiconductor device 200, as Figure 4 shown, Figure 4 which is a schematic perspective view of the semiconductor device 200. After forming the sacrificial gate structure 214, the gate sidewall spacer 216 can be deposited over the semiconductor device 200 by blanket depositing one or more insulating materials. Even though Figure 4 only one layer is shown in

[0034] FIG. 2, the gate sidewall spacer 216 can include two or more layers of dielectric materials. In some embodiments, the gate sidewall spacer 216 can include one or more insulating materials. The gate sidewall spacer 216 can include a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, and combinations of the foregoing.

[0034] In operation 108, the fin structures 210 not covered by the sacrificial gate structure 214 are etched to expose the well portions of each fin structure 210, thereby forming source / drain recesses 234, as Figure 5 shown. In some embodiments, appropriate dry etching and / or wet etching can be used to etch back the semiconductor layers 206, 208 together or separately. After recessing the fin structures 210, a portion of the fin sidewall spacer 216f may remain. The height of the remaining fin sidewall spacer 216f can be used to control the shape of the subsequently formed epitaxial source / drain regions.

[0035] After the recessed etched fin structure 210, an internal spacer 232 is formed through the source / drain recess 234. To form the internal spacer 232, the semiconductor layer 206 under the gate sidewall spacer 216g is selectively etched along the horizontal direction (or x-direction) from the semiconductor layer 208 to form a spacer cavity. In some embodiments, the semiconductor layer 206 can be selectively etched by using a wet etchant (such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution). After forming the spacer cavity, an internal spacer 232 is formed in the spacer cavity by conformally depositing an insulating layer and then partially removing the insulating layer. The insulating layer can be formed by ALD or any other suitable method. A subsequent etching process removes most of the insulating layer except the insulating layer inside the cavity, thus producing the internal spacer 232.

[0036] At operation 110, epitaxial source / drain regions 236, 238 are formed, as Figure 6 shown, Figure 6 is a schematic perspective view of the semiconductor device 200. In some embodiments, the epitaxial source / drain regions 236, 238 can be used for different types of devices and can be formed individually using a patterning process.

[0037] In some embodiments, an epitaxial source / drain region 236 for an N-type device is formed from the exposed surface of the fin structure 210b. The epitaxial source / drain region 236 for an n-type device can include one or more layers of Si, SiP, SiC, and SiCP. The epitaxial source / drain region 236 also includes an N-type dopant, such as phosphorus (P), arsenic (As), etc. In some embodiments, the epitaxial source / drain region 236 can be a Si layer including a phosphorus (P) dopant. Figure 6 The epitaxial source / drain region 236 shown in has a hexagonal shape. However, according to the design, the epitaxial source / drain region 236 can be other shapes. The epitaxial source / drain region 236 can be formed by any suitable method (such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique).

[0038] The epitaxial source / drain regions 238 can be used for P-type devices. The epitaxial source / drain regions 238 can be formed by any suitable method (e.g., by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique). In some embodiments, the epitaxial source / drain regions 238 for p-type devices can include one or more layers of Si, SiGe, Ge with p-type dopants (e.g., boron (B)) for p-type devices (e.g., pFETs). In some embodiments, the epitaxial source / drain regions 238 can be SiGe materials including boron as a dopant. The formation order of the epitaxial source / drain for NMOS and PMOS can be interchangeable, depending on the requirements of the process. According to the design of the thin film scheme, the shape of the epitaxial source / drain can be different for NMOS and PMOS.

[0039] At operation 112, a contact etch stop layer (CESL) 240 and an interlayer dielectric (ILD) layer 242 are conformally formed over the semiconductor device 200, as Figure 7 shown, Figure 7 is a schematic perspective view of the semiconductor device 200.

[0040] The CESL 240 is formed over the exposed surface of the semiconductor device 200. The CESL 240 is formed over the epitaxial source / drain regions 236, 238, the gate sidewall spacers 216g, the fin sidewall spacers 216f, and the isolation layer 212. The CESL 240 can include Si3N4, SiON, SiCN, or any other suitable material, and can be formed by CVD, PVD, or ALD.

[0041] The ILD layer 242 is formed over the contact etch stop layer 240. The material of the ILD layer 242 includes compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials (e.g., polymers) can be used for the ILD layer 242. In some embodiments, the ILD layer 242 can be formed by flowable CVD (FCV). The ILD layer 242 and the CESL layer 240 protect the epitaxial source / drain regions 236, 238 during the removal of the sacrificial gate structure 214. In some embodiments, after depositing the ILD layer 242, a planarization process can be performed to expose the sacrificial gate structure 214.

[0042] In operation 114, an etching process is performed to selectively etch the top surface 242t of the ILD layer 242 to be lower than the top surface 240t of the CESL 240 and the top surface 216t of the gate sidewall spacer 216, as Figure 8 shown, Figure 8is a schematic perspective view of semiconductor device 200. The ILD layer 242 can be recessed using any suitable etching process (e.g., dry etching, wet etching, reactive ion etching, chemical oxide removal, dry chemical cleaning process, etc.). In some embodiments, a dry etching process (e.g., dry etching using an etchant such as NH3 / HF) or a plasma dry etching process using a fluorine-based chemical such as CF4, SF6, CH2F2, CHF3, and / or C2F6 is used to etch the ILD layer 242. After operation 114, a recess is formed over the ILD layer 242 to allow a protective cap to be formed thereon in a subsequent process.

[0043] In operation 116, a protective cap 226 is formed over the top surface 242t of the ILD layer 242, as Figure 9 shown. Figure 9 is a schematic perspective view of semiconductor device 200. The protective cap 226 can be formed by depositing a protective layer over the ILD layer 242 and the sacrificial gate structure 214 and then performing a planarization process to expose the sacrificial gate structure 214. The protective cap 226 is disposed over the top surface 242t of the ILD layer 242 and between the sacrificial gate structures 214. The protective cap 226 contacts the top surface 242t of the ILD layer 242 and the CESL 240 on the gate sidewall spacers 216g. As Figure 9 shown, after the protective cap 226 is formed, the ILD layer 242 is covered for subsequent processes.

[0044] The protective cap 226 can be formed of a material that has an etching selectivity with respect to the subsequently formed gate structure. In some embodiments, the protective cap 226 can include a nitrogen-containing material that has an etching selectivity with respect to metal materials, metal oxide materials. In some embodiments, the protective cap 226 is formed of a nitride, such as silicon nitride.

[0045] The protective cap 226 has a thickness H in the z direction 226 . In some embodiments, the thickness H 226 is in the range between about 5 nm and about 20 nm. A thickness less than 5 nm may not be sufficient to protect the ILD layer 242 during subsequent processes. A thickness greater than 20 nm may increase the aspect ratio of the gate structure during the replacement gate process without increasing the protection benefit.

[0046] At operation 118, a replacement gate structure 252 is formed, as Figure 10 , Figures 10A - Figures 10D shown. Figure 10 is a perspective view of semiconductor device 200. Figure 10A , Figure 10B , Figure 10C and 10Dare cross-sectional views of semiconductor device 200 along lines A-A, B-B, C-C, and D-D. It should be noted that in Figure 10 two replacement gate structures 252 are shown straddling two semiconductor fin structures 210, while in Figures 10A - Figures 10D four replacement gate structures 252 are shown straddling four semiconductor fin structures 210.

[0047] In some embodiments, a dry etch, a wet etch, or a combination thereof is used to remove the sacrificial gate dielectric layer 218 and the sacrificial gate electrode layer 220. The semiconductor layers 206a, 206b are exposed and then removed, creating a gate cavity around the nanosheets of semiconductor layers 208a, 208b. Then, the replacement gate structure 252 is filled in the gate cavity. The replacement gate structure 252 may include a gate dielectric layer 244 and a gate electrode layer 246.

[0048] A gate dielectric layer 244 is formed on the exposed surface in the gate cavity. The gate dielectric layer 244 may have different compositions and dimensions for N-type and P-type devices and is formed separately using a patterned mask layer and different deposition recipes. The gate dielectric layer 244 may include one or more dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations of the foregoing. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titania, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations of the foregoing. The gate dielectric layer 244 may be formed by CVD, ALD, or any suitable method.

[0049] A gate electrode layer 246 is formed on the gate dielectric layer 244 to fill the gate cavity. The gate electrode layer 246 may include one or more conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations of the foregoing. In some embodiments, the gate electrode layer 246 may be formed by CVD, ALD, electroplating, or other suitable methods.

[0050] After forming the gate electrode layer 246, a planarization process (such as a CMP process) is performed to remove the over-deposited gate electrode material and expose the protection cap 226.

[0051] In operation 120, a mask layer 254 is deposited over the replacement gate structure 252 and the protection cap 226, as Figure 11 shown, Figure 11is a perspective view of semiconductor device 200. Mask layer 254 is configured to form a cut metal gate structure using a hard mask layer. In some embodiments, mask layer 254 is a dielectric layer, such as silicon nitride. In other embodiments, mask layer 254 may include a semiconductor layer, such as amorphous silicon.

[0052] In operation 122, a patterning process is performed to form a cut gate pattern 256 in mask layer 254, as Figure 12 and Figures 12A to 12D shown. Figure 12 is a perspective view of semiconductor device 200. Figure 12A 、 Figure 12B 、 Figure 12C and 12D are cross-sectional views of semiconductor device 200 along lines A-A, B-B, C-C, and D-D, respectively.

[0053] The cut gate pattern 256 can be formed in the mask layer 254 by depositing and patterning a photoresist layer (such as a three-layer photoresist (not shown)) over the mask layer 254, and etching the mask layer 254 through the photoresist layer.

[0054] In some embodiments, the cut gate pattern 256 may include one or more elongated openings formed between semiconductor fin structures 210 to expose one or more replacement gate structures 252 across the semiconductor fin structures 210. As Figure 12 and Figure 12C shown, above the replacement gate structure 252, the openings of the cut gate pattern 256 are disposed between two semiconductor channel layer stacks 208 of two semiconductor fin structures 210 and expose the replacement gate structure 252. Accordingly, as Figure 12D shown, the openings of the cut gate pattern 256 are disposed between two adjacent source / drain regions 236 / 238, aligned with the ILD layer 242, and expose the capping layer 226 above the ILD layer 242. In Figure 12B , the openings of the cut gate pattern 256 expose one or more replacement gate structures 252 to be cut, the capping layers 226 on both sides of and between the exposed replacement gate structures 252, the gate sidewall spacers 216 and CESL 240 between the replacement gate structures 252 and the capping layers 226.

[0055] In operation 124, a cut gate opening 258 is formed in the replacement gate structure 252, as Figure 13 and Figures 13A to 13D shown. Figure 13 is a perspective view of semiconductor device 200. Figure 13A 、 Figure 13B 、 Figure 13C and13D These are cross-sectional views of the semiconductor device 200 along lines A-A, B-B, C-C, and D-D, respectively.

[0056] A cut gate opening 258 is formed by using a cut gate pattern 256 formed in a mask layer 254 through a self-aligned etching process. As Figure 13B and Figure 13C shown, the cut gate opening 258 is formed as a via that passes through the replacement gate structure 252 and into the isolation layer 212. In some embodiments, one or more etching processes may be performed to selectively remove the gate electrode layer 246 and the gate dielectric layer 244 exposed by the cut gate pattern 256, where the protective cap 226, the CESL 240, and the gate sidewall spacers 216 are substantially unaffected.

[0057] Although the cut gate pattern 256 is an elongated opening that spans one or more replacement gate structures 252 and exposes the gate sidewall spacers 216 located on both sides of and between the replacement gate structures 252, the cut gate opening 258 extending from the cut gate pattern 256 is a via opening that extends within the replacement gate structure 252 and between the gate sidewall spacers 216. The cut gate opening 258 cuts the corresponding gate electrode layer 246 and gate dielectric layer 244 into segments within the replacement gate structure 252, as Figure 13C shown, while the ILD layer 242 under the opening of the cut gate pattern 256 remains, as Figure 13B and Figure 13D shown.

[0058] As Figure 13B shown, the cut gate opening 258 is formed between the gate sidewall spacers 216. In other words, the cut gate opening 258 does not extend in the X direction through the gate sidewall spacers 216. In some embodiments, the cut gate opening 258 has a width W in the x direction 258 .

[0059] As Figure 13C shown, the cut gate opening 258 cuts through the gate electrode layer 246 and the gate dielectric layer 244 and cuts into the isolation layer 212. In some embodiments, the cut gate opening 258 has a length L in the y direction 258 . In some embodiments, the length L 258 is in the range between about 5 nm and about 20 nm. A length less than about 5 nm may not be sufficient to provide electrical isolation between the gate electrode layers 246 on opposite sides of the cut gate opening 258. A length greater than 20 nm may affect the structural integrity of the adjacent semiconductor channel layers 208. The depth of the cut gate opening 258 extending into the isolation layer 212 in the z direction is D 258 . In some embodiments, the depth D258 In the range between about 5 nm and about 70 nm. Substantial recesses (D 258 ) are typically obtained on the STI to avoid any metal remaining in the cut gate trenches. In some embodiments, the maximum value of D 258 is less than the thickness of the STI, so the well structure under the STI will not be damaged by the cut gate process.

[0060] In some embodiments, one or more etching processes can be used to form the cut gate opening 258. In some embodiments, the etching process can use an etching chemistry configured to selectively remove the metal material in the gate electrode layer 246, the oxide layer in the gate dielectric layer 244, and the nitrogen-containing material in the protective cap 226. In some embodiments, the etching chemistry is also selected to have a minimal impact on the gate sidewall spacers 216 and the CESL 240. In some embodiments, the etching chemistry can include chlorine-containing gases (such as SiCl4, BCl3, Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (such as HBr and / or CHBr3), iodine-containing gases, or any suitable gas, or a combination of the foregoing. In some embodiments, the etching process can be a plasma process.

[0061] In operation 126, the cut gate structure 260 is formed by depositing a dielectric fill material, as Figures 14A to 14D shown. The dielectric fill material can include any suitable dielectric material. In some embodiments, the dielectric fill material can include one or more low-k dielectric materials to provide electrical isolation between segments of the gate electrode layer 246 and provide sufficient mechanical strength to provide structural integrity in the replacement gate structure 252. In some embodiments, the cut gate structure 260 can include silicon nitride, silicon oxide, or a combination thereof.

[0062] As Figures 14A to 14D shown, the cut gate structure 260 is a via structure that is confined within the gate sidewall spacers 216 and does not extend into the ILD layer 242. By confining the cut gate structure 260 within the replacement gate structure 252, embodiments of the present disclosure avoid forming a dielectric structure between adjacent epitaxial source / drain regions 236 / 238 and minimize the parasitic capacitance within the semiconductor device 200.

[0063] The cut gate structure 260 cuts through the gate electrode layer 246 and the gate dielectric layer 244 and cuts into the isolation layer 212. In some embodiments, the cut gate structure 260 has a width W 260 . The width W 260equal to or greater than the distance between the gate sidewall spacers 216 in the x - direction. In some embodiments, the cut - gate structure 260 has a length L in the y - direction 260 .

[0064] In some embodiments, the length L 260 is in the range between about 5 nm and about 20 nm. A length less than about 5 nm may not be sufficient to provide electrical isolation between the gate electrode layers 246 on opposite sides of the cut - gate structure 260. A length greater than 20 nm may affect the structural integrity of the adjacent semiconductor channel layers 208. In some embodiments, for devices that require high density (such as SRAMs and ring oscillators), the length L of the cut - gate structure 260 in the Y - direction 260 is about 80% to about 90% of the length L between two adjacent semiconductor fin structures 210 210 . The depth D to which the cut - gate structure 260 extends into the isolation layer 212 in the z - direction 260 . In some embodiments, the depth D 260 is in the range between about 5 nm and about 20 nm.

[0065] In operation 128, source / drain contact features 266 and gate contact features 268 are formed, as Figure 15 and Figures 15A to 15D shown. Figure 15 is a schematic plan view of the semiconductor device 200. For clarity, Figure 15 various dielectric materials are not shown. Figure 15A , Figure 15B , Figure 15C and Figure 15D are cross - sectional views of the semiconductor device 200 along lines A - A, B - B, C - C, and D - D in Figure 15 respectively.

[0066] After depositing the dielectric fill material, a planarization process can be performed to expose the gate electrode layer 246 and the ILD layer 242 for subsequent processes. The protective cap 226 is removed during the planarization process. In some embodiments, an etch - stop layer 262 and an ILD layer 264 can then be deposited over the gate electrode layer 246 and the ILD layer 242.

[0067] To form the source / drain contact feature 266, contact holes may be formed through the ILD layer 242, the CESL 240 to expose the epitaxial source / drain regions 236, 238, and then filled with a conductive material. Appropriate lithography and etching techniques are used to form the contact holes through the layers. After forming the contact holes, a silicide layer (not shown) is selectively formed on the surfaces of the epitaxial source / drain regions 236, 238 exposed by the contact holes. The silicide layer can be formed by depositing a metal source layer to cover the exposed surfaces including the exposed surfaces of the epitaxial source / drain regions 236, 238, and performing a rapid thermal annealing process. In some embodiments, the metal source layer includes a metal layer selected from W, Co, Ni, Ti, Mo, and Ta, or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. After forming the metal source layer, a rapid thermal annealing process is performed. During the rapid annealing process, the portion of the metal source layer over the epitaxial source / drain regions 236, 238 reacts with silicon in the epitaxial source / drain regions 236, 238 to form a silicide layer. Then, the unreacted portion of the metal source layer is removed. In some embodiments, the silicide layer includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.

[0068] After forming the silicide layer 248, a conductive material is deposited to fill the contact holes and form the source / drain contact feature 266. Optionally, a barrier layer may be formed in the contact holes before forming the source / drain contact feature 266. In some embodiments, a conductive material layer for the gate contact may be formed by CVD, PVD, electroplating, ALD, or other suitable techniques. In some embodiments, the conductive material for the source / drain contact feature 250 includes TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Co, Cu, Ag, Al, Zn, Ca, Au, Mg, Mo, Cr, etc. Subsequently, a CMP process is performed to remove the portion of the conductive material layer above the top surface of the ILD layer 264.

[0069] Similarly, to form the gate contact feature 268, contact holes may be formed through the ILD layer 264 and the etch stop layer 262 to expose the gate electrode layer 246, and then filled with a conductive material.

[0070] Embodiments of the present disclosure provide a method for forming a via-shaped cut gate structure that is located within the gate sidewall spacers of each gate structure, does not extend into the ILD layer, and does not extend between adjacent source / drain regions. A via-shaped cut gate structure can be facilitated by adding a protective cap over the ILD layer and without changing the circuit design or mask pattern used in a conventional linear cut gate structure.

[0071] As Figure 15 and Figure 15D shown, the cut gate structure 260 is a via feature that is disposed within the gate sidewall spacer 216 and does not extend between adjacent source / drain regions 236 / 238, thus minimizing the parasitic capacitance between adjacent source / drain regions 236 / 238.

[0072] As Figure 15 and Figure 15B shown, since the cut gate structure 260 does not extend into the ILD layer 242 between adjacent source / drain regions 236 / 238, source / drain contact features 266 can be formed across adjacent source / drain regions 236 / 238 without being complicated by additional dielectric material, increasing the contact area between the source / drain contact features 266 and the source / drain regions 236 / 238.

[0073] Figure 16 is a schematic plan view of an SRAM (static random access memory) device including a via-shaped cut gate structure 260 according to the present disclosure. The via-shaped cut gate structure 260 allows the ILD layer to remain between the source / drain regions adjacent to the via-shaped cut gate structure 260, marked as rectangles. The ILD layer retained between the cut gate structures 260 minimizes the parasitic capacitance in the SRAM device.

[0074] The via-shaped cut gate structure according to the present disclosure can be incorporated into any suitable semiconductor device to reduce parasitic capacitance and improve product performance. For example, the via-shaped cut gate structure can be formed together with the following devices: FinFET devices, GAA or FinFET devices with or without hybrid fins, GAA or FinFET devices with SAC (self-aligned capping layer in the gate structure).

[0075] Figure 17 , Figures 18A to 18C and Figures 29A to 29C schematically shows a semiconductor device 300 according to the present disclosure. The semiconductor device 300 is a FinFET device with hybrid fins. In some embodiments, the semiconductor device 300 includes a via-shaped cut gate structure formed over the hybrid fins. The semiconductor device 300 can be manufactured according to method 100.

[0076] Figure 17 is a schematic plan view of a semiconductor device 300. As Figure 17 shown, the semiconductor device 300 includes a semiconductor fin structure 310 formed along the x direction and a gate structure 352 formed along the y direction. Dielectric fins 308 are formed between the semiconductor fin structures 310. Source / drain regions 338 are formed from the semiconductor fin structures 310. A via-shaped cut gate structure 360 is formed in the gate structure 352. In some embodiments, the via-shaped cut gate structure 360 is formed above the intersection of the gate structure 352 and the dielectric fins 308.

[0077] Figures 18A to 18C to Figures 29A to 29C schematically show the semiconductor device at different manufacturing stages. Figures 18A to 29A 、 Figures 18B to 29B and Figures 18C to 29C are cross-sectional views of the semiconductor device 300 along lines A-A, B-B, and C-C in Figure 17 respectively.

[0078] Figures 18A to 18C schematically shows the semiconductor device 300 after operation 112. In operation 102, a semiconductor fin structure 310 is formed on a semiconductor substrate 302. An isolation region 312 is formed around the semiconductor fin structure 310. Dielectric fins 308 or hybrid fins extend from the isolation region 312. The dielectric fins 308 can be formed of one or more dielectric materials and are parallel to the semiconductor fin structures 310. In operation 104, a sacrificial gate dielectric layer 318 and a sacrificial gate electrode layer 320 are formed to span the fin structure 310 and the dielectric fins 308. In operation 106, gate sidewall spacers 316 are formed on the sidewalls of the sacrificial gate structure. In operation 108, the semiconductor fin structure 310 not covered by the sacrificial gate structure is back-etched, and source / drain regions 338 are formed therein. In operation 112, a CESL 340 is deposited on the source / drain regions 338, the dielectric fins 308, and the gate sidewall spacers 316. Then an ILD layer 342 is deposited on the CESL 340. Then a planarization process is performed to expose the ILD layer 342 and the sacrificial gate electrode layer 320.

[0079] Figures 19A to 19C schematically shows the semiconductor device 300 after operation 114, where the ILD layer 342 is back-etched to a level below the sacrificial gate electrode layer 320.

[0080] Figures 20A to 20C and Figures 21A to 21CSchematically shows the semiconductor device 300 after operation 116, wherein a protective material is deposited over the ILD layer 342 and then planarized to form a protective cap 326 over the ILD layer 342.

[0081] Figures 22A to 22C , Figures 23A to 23C and Figures 24A to 24C Schematically shows the semiconductor device 300 after operation 118, wherein a replacement gate structure 352 is formed. A gate dielectric layer 344 is deposited over the semiconductor fin structure 310 and the dielectric fin 308, and a gate electrode layer 346 is deposited over the gate dielectric layer 344.

[0082] Figures 25A to 25C Schematically shows the semiconductor device 300 after operation 120, wherein a mask layer 354 is deposited over the protective cap 326 and the gate structure 352.

[0083] Figures 26A to 26C Schematically shows the semiconductor device 300 during operation 122 (when a three-layer photoresist layer is deposited over the hard mask layer 354 to form a cut metal gate pattern in the hard mask layer 354).

[0084] Figures 27A to 27C Schematically shows the semiconductor device 300 after operation 124, wherein the cut gate opening 358 uses the cut gate pattern 356 in the mask layer 354. The cut gate opening 358 is formed by a self-aligned etching process using the cut gate pattern 356 formed in the mask layer 354.

[0085] The cut gate pattern 356 may include one or more elongated openings over the dielectric fin 308. The cut gate pattern 356 exposes one or more replacement gate structures 352 and the protective cap 326.

[0086] The cut gate opening 358 is a via formed to pass through the replacement gate structure 352 and into the dielectric fin 308. In some embodiments, one or more etching processes may be performed to selectively remove the gate electrode layer 346 and the gate dielectric layer 344 exposed by the cut gate pattern 356, wherein the protective cap 326, the CESL 340, and the gate sidewall spacers 316 are substantially unaffected. The cut gate opening 358 is a via opening extending between the gate sidewall spacers 316 within the replacement gate structure 352. The cut gate opening 358 cuts the corresponding gate electrode layer 346 and the gate dielectric layer 344 into segments within the replacement gate structure 352, as Figure 27C shown, while the ILD layer 324 under the opening of the cut gate pattern 356 remains. As Figure 27BAs shown, a cut gate opening 358 is formed between the gate sidewall spacers 316. In other words, the cut gate opening 358 does not extend through the gate sidewall spacers 316 in the X direction.

[0087] Figures 28A to 28C Semiconductor device 300 after operation 126 is schematically shown, where the cut gate opening 358 is filled with a dielectric material to form a cut gate structure 360. In some embodiments, the cut gate structure 360 may include silicon nitride, silicon oxide, or a combination thereof.

[0088] The cut gate structure 360 is a via structure that is confined within the gate sidewall spacers 316 and does not extend into the ILD layer 342. The cut gate structure 360 cuts through the gate electrode layer 346 and the gate dielectric layer 344 and cuts into the dielectric fin 308. In some embodiments, the cut gate structure 360 has a width in the x direction. The width of the cut gate structure 360 is equal to the distance between the gate sidewall spacers 316 in the x direction. In some embodiments, the cut gate structure 360 has a length in the y direction. In some embodiments, the length of the cut gate structure 360 is in the range between about 5 nm and about 20 nm. A length less than about 5 nm may not be sufficient to provide electrical isolation between the gate electrode layers 346 on opposite sides of the cut gate structure 360. A length greater than 20 nm may affect the structural integrity of adjacent semiconductor fin structures 310. In some embodiments, the length of the cut gate structure 360 in the Y direction is about 20% to about 90% of the length L between two adjacent semiconductor fin structures 310. The depth to which the cut gate structure 360 extends into the dielectric fin 308 in the z direction is D 310 of about 20% to about 90%. The depth D to which the cut gate structure 360 extends into the dielectric fin 308 in the z direction is D 360 . In some embodiments, the depth D 360 is in the range between about 3 nm and about 70 nm (which depends on the material of the dummy fin. Generally, the bottom of D 360 should be above the STI so that the well structure below the STI is not damaged by the cut gate process.)

[0089] By confining the cut gate structure 360 within the replacement gate structure 352, embodiments of the present disclosure avoid forming a dielectric structure between adjacent epitaxial source / drain regions 338 and minimize the parasitic capacitance within the semiconductor device 300.

[0090] Figures 29A to 29CSchematically illustrated is the semiconductor device 300 after operation 128, wherein source / drain contact features 366 are formed. After depositing a dielectric fill material, a planarization process may be performed to expose the gate electrode layer 346 and the ILD layer 342 for subsequent processes. The protective cap 326 is removed during the planarization process. In some embodiments, an ILD layer 364 may then be deposited over the gate electrode layer 346 and the ILD layer 342.

[0091] Figures 30A to 30C to Figures 33A to 33C Schematically illustrated are semiconductor devices 300a at different manufacturing stages. The semiconductor device 300a is similar to the semiconductor device 300 described above, but the semiconductor device 300a includes a SAC layer 348 formed over the gate structure 352. Figures 30A to 33A 、 Figures 30B to 33B and Figures 30C to 33C are cross-sectional views of the semiconductor device 300 taken along lines A-A, B-B, and C-C in Figure 17 respectively.

[0092] Figures 30A to 30C Schematically illustrated is the semiconductor device 300a after operation 118, wherein a replacement gate structure 352 is formed. In operation 118, a gate dielectric layer 344 is deposited over the semiconductor fin structure 310 and the dielectric fin 308, and a gate electrode layer 346 is deposited over the gate dielectric layer 344. A planarization process may be performed after depositing the gate electrode layer 346 to expose the protective cap 326. The gate electrode layer and the gate structure 352 are selectively recessed to form a self-aligned cap (SAC) recess. Then a dielectric material for the SAC layer 348 is deposited. The SAC layer 348 may be deposited by any suitable process (such as CVD, PECVD, or a suitable deposition process). The dielectric material for the SAC layer 348 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, or a suitable dielectric material. Then a hard mask layer 354 is deposited over the SAC layer 348.

[0093] Figures 31A to 31C Schematically illustrated is the semiconductor device 300a during operation 122 (when a three-layer photoresist layer is deposited over the hard mask layer 354 to form a cut metal gate pattern in the hard mask layer 354).

[0094] Figures 32A to 32CThe semiconductor device 300a is schematically shown after operation 124, wherein a cut gate opening 358 is formed using a cut gate pattern 356 in the mask layer 354. The cut gate opening 358 is formed by a self-aligned etching process using the cut gate pattern 356 formed in the mask layer 354. The cut gate opening 358 is a via opening formed through the SAC layer 348, the gate electrode layer 346, the gate dielectric layer 344, and into the dielectric fin 308.

[0095] Figures 33A to 33C The semiconductor device 300a is schematically illustrated after operation 126, wherein the cut gate opening 358 is filled with a dielectric material to form a cut gate structure 360. In some embodiments, the cut gate structure 360 may include silicon nitride, silicon oxide, or a combination thereof.

[0096] The cut gate structure 360 is a via structure confined within the gate sidewall spacer 316 and does not extend into the ILD layer 342. The cut gate structure 360 cuts through the SAC layer 348, the gate electrode layer 346, and the gate dielectric layer 344 and into the dielectric fin 308.

[0097] In some embodiments, the via-shaped cut gate structure according to the present disclosure can also be used in a cut polysilicon gate process, i.e., the cut gate structure is formed before forming a replacement structure. During the cut polysilicon gate process, a portion of the sacrificial gate structure (i.e., the polysilicon layer) is selectively removed from the ILD layer without using a protective cap. The cut polysilicon gate process according to the present disclosure uses method 100 by omitting operations 112, 114, 116 and performing operation 118 after operation 126. Figure 34 , Figures 34A to 34B , Figure 35 , Figures 35A to 35B , Figure 36 , Figures 36A to 36B , Figure 37 , Figures 37A to 37B as well as Figures 38A to 38B The semiconductor device 300b is shown at various stages of fabrication. The semiconductor device 300a is similar to the semiconductor device 300 described above, but the semiconductor device 300b includes a via-shaped cut gate structure 360b formed during a cut polysilicon gate process.

[0098] Figure 34 , Figures 34A to 34B The semiconductor device 300 b is schematically illustrated after operation 112 . Figure 34 is a schematic perspective view of a semiconductor device 300 b . Figure 34A is a cross-sectional view of the semiconductor device 300 b along the dielectric fin 308 .Figure 34B is a cross-sectional view of semiconductor device 300b along the gate structure. In operation 112, CESL 340 is deposited over source / drain regions 338, gate sidewall spacers 316, isolation regions 312, and dielectric fins 308.

[0099] After operation 112, operation 120 is performed to deposit mask layer 354 over sacrificial gate layers 320, 318, and ILD layer 342, as Figure 34 shown. Figure 34 、 Figures 34A to 34B Also shown is a three-layer photoresist layer deposited over hard mask layer 354 to form a cut metal gate pattern in hard mask layer 354.

[0100] Figure 35 、 Figures 35A to 35B Schematically shows semiconductor device 300b after operation 122, where cut gate opening 358 uses the cut gate pattern 356 in mask layer 354. Cut gate opening 358 is formed by a self-aligned etching process using the cut gate pattern 356 formed in mask layer 354. The cut gate pattern 356 can include one or more elongated openings over dielectric fin 308. The cut gate pattern 356 exposes one or more sacrificial gate structures, namely sacrificial gate electrode layer 320 and ILD layer 342.

[0101] Figure 36 、 Figures 36A to 36B Schematically shows semiconductor device 300b after operation 124, where cut gate opening 358 uses the cut gate pattern 356 in mask layer 354. Cut gate opening 358 is formed by a self-aligned etching process using the cut gate pattern 356 formed in mask layer 354. In some embodiments, a dry etching process selectively removes the exposed sacrificial gate electrode layer 320 and sacrificial gate dielectric layer 318, while the exposed ILD layer 342 is substantially unaffected. In some embodiments, operation 124 can be an etching process using an etching chemical that includes an etchant with added O2 or CO2 (e.g., a Cl2 or HBr-based chemical).

[0102] Figure 37 、 Figures 37A to 37B Schematically shows semiconductor device 300b after operation 126, where cut gate opening 358 is filled with a dielectric material to form cut gate structure 360b. In some embodiments, cut gate structure 360 can include silicon nitride, silicon oxide, or a combination thereof.

[0103] After operation 126, a replacement gate process (e.g., operation 118) is performed to form a gate dielectric layer 344 and a replacement gate electrode layer 346. Figures 38A to 38B A semiconductor device 300b after the replacement gate process is schematically shown. As Figure 38B shown, the cut gate structure 360b is a via structure that is confined within the gate sidewall spacers 316 and does not extend into the ILD layer 342. The cut gate structure 360b is in contact with the gate dielectric layer 344. The cut gate structure 360b is a via-shaped dielectric structure defined by the gate sidewall spacers 316 and the gate dielectric layer 344. In some embodiments, the cut gate structure 306b may extend into the dielectric fins 308 (if present) or into the isolation region 312 (when the dielectric fins 30 are absent).

[0104] The various embodiments or examples described herein provide several advantages over the prior art. Embodiments of the present disclosure provide a semiconductor device having a via-shaped cut gate structure that is defined within sidewall spacers in a gate structure. Because the via-shaped cut gate structure does not extend between adjacent source / drain regions, the parasitic capacitance formed between the source / drain regions is minimized. The via-shaped cut gate structure can be fabricated using existing circuit designs and is thus easily adopted.

[0105] Some embodiments of the present disclosure provide a method that includes: forming a semiconductor structure that includes: a first semiconductor fin structure and a second semiconductor fin structure extending in a first direction; a gate structure spanning the first semiconductor fin structure and the second semiconductor fin structure; a first source / drain region on the first semiconductor fin structure; a second source / drain region on the second semiconductor fin structure; and an ILD (interlayer dielectric) layer over the first source / drain region and the second source / drain region; depositing a mask layer over the semiconductor structure; forming a first opening through the mask layer, wherein the first opening extends in the first direction disposed between the first semiconductor fin structure and the second semiconductor fin structure and the first opening exposes a portion of the gate structure and the ILD layer; forming a via opening in the gate structure through the first opening in the mask layer, wherein the via opening divides the gate structure into two segments; and filling the via opening with a dielectric material to form a cut gate structure.

[0106] Some embodiments of the present disclosure provide a semiconductor device, the semiconductor device including: a first semiconductor fin structure and a second semiconductor fin structure extending in a first direction; and a gate structure spanning the first semiconductor fin structure and the second semiconductor fin structure, wherein the gate structure includes: a first gate segment disposed over the first semiconductor fin structure; a second gate segment disposed over the second semiconductor fin structure; a cut gate structure disposed between the first gate segment and the second gate segment; a first gate sidewall spacer; and a second gate sidewall spacer, wherein the cut gate structure is disposed between the first gate sidewall spacer and the second gate sidewall spacer.

[0107] Some embodiments of the present disclosure provide a semiconductor device, the semiconductor device including: a first gate structure; a second gate structure parallel to the first gate structure; a first source / drain region formed between the first gate structure and the second gate structure; a second source / drain region formed between the first gate structure and the second gate structure; a source / drain contact feature in contact with the first source / drain region and the second source / drain region; a first cut gate structure disposed in the first gate structure; a second cut gate structure disposed in the second gate structure; a first dielectric layer disposed between the source / drain contact feature and the first cut gate structure; and a second dielectric layer disposed between the source / drain contact feature and the second cut gate structure.

[0108] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0109] Example 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor structure, the semiconductor structure including: a first semiconductor fin structure and a second semiconductor fin structure extending in a first direction; a gate structure spanning the first semiconductor fin structure and the second semiconductor fin structure; a first source / drain region on the first semiconductor fin structure; a second source / drain region on the second semiconductor fin structure; and an interlayer dielectric ILD layer over the first source / drain region and the second source / drain region; depositing a mask layer over the semiconductor structure; forming a first opening through the mask layer, wherein the first opening extends in the first direction disposed between the first semiconductor fin structure and the second semiconductor fin structure, and the first opening exposes the gate structure and a portion of the ILD layer; forming a via opening in the gate structure through the first opening in the mask layer, wherein the via opening divides the gate structure into two segments; filling the via opening with a dielectric material to form a cut gate structure.

[0110] Example 2. The method according to Example 1, wherein the semiconductor structure further includes a first gate sidewall spacer and a second gate sidewall spacer disposed on sidewalls of the gate structure, and the cut gate structure contacts the first gate sidewall spacer and the second gate sidewall spacer.

[0111] Example 3. The method according to Example 1, further comprising: forming a protective cap over the ILD layer before depositing the mask layer.

[0112] Example 4. The method according to Example 3, wherein forming the protective cap includes: recessing the ILD layer to a level lower than the gate structure; depositing a protective material over the semiconductor structure; and planarizing the semiconductor structure to expose the gate structure.

[0113] Example 5. The method according to Example 4, wherein the protective material is a nitrogen-containing dielectric material.

[0114] Example 6. The method according to Example 3, further comprising: planarizing the semiconductor structure to remove the protective cap after filling the via opening with the dielectric material.

[0115] Example 7. The method according to Example 1, after filling the via opening with the dielectric material, further comprising: removing the two segments of the gate structure to expose the first semiconductor fin structure and the second semiconductor fin structure; depositing a replacement gate dielectric layer on the first semiconductor fin structure and the second semiconductor fin structure; and depositing a replacement gate electrode layer on the replacement gate dielectric layer.

[0116] Example 8. The method according to Example 1, wherein the semiconductor structure further includes a dielectric fin disposed between the first semiconductor fin structure and the second semiconductor fin structure, and the via opening extends into the dielectric fin.

[0117] Example 9. The method according to Example 1, wherein the semiconductor structure further includes an isolation layer disposed under the gate structure, and the via opening extends into the isolation layer.

[0118] Example 10. A semiconductor device, comprising: a first semiconductor fin structure and a second semiconductor fin structure extending in a first direction; and a gate structure spanning the first semiconductor fin structure and the second semiconductor fin structure, wherein the gate structure includes: a first gate segment disposed over the first semiconductor fin structure; a second gate segment disposed over the second semiconductor fin structure; a cut gate structure disposed between the first gate segment and the second gate segment; a first gate sidewall spacer; and a second gate sidewall spacer, wherein the cut gate structure is disposed between the first gate sidewall spacer and the second gate sidewall spacer.

[0119] Example 11. The semiconductor device according to Example 10, further comprising: a dielectric fin disposed between the first semiconductor fin structure and the second semiconductor fin structure, wherein the gate structure is disposed over the dielectric fin, and the cut gate structure extends into the dielectric fin.

[0120] Example 12. The semiconductor device according to Example 10, further comprising: an isolation layer disposed around the first semiconductor fin structure and the second semiconductor fin structure, wherein the gate structure is disposed over the isolation layer, and the cut gate structure extends into the isolation layer.

[0121] Example 13. The semiconductor device according to Example 10, further comprising: a first source / drain region on the first semiconductor fin structure; a second source / drain region on the second semiconductor fin structure; and an interlayer dielectric ILD layer over the first source / drain region and the second source / drain region, wherein the first gate sidewall spacer is disposed between the ILD layer and the cut gate structure.

[0122] Example 14. The semiconductor device according to Example 13, further comprising: a contact etch stop layer disposed between the ILD layer and the first gate sidewall spacer.

[0123] Example 15. The semiconductor device according to Example 10, wherein the first gate segment includes: a gate dielectric layer; and a gate electrode layer, wherein the gate electrode layer is in contact with the cut gate structure.

[0124] Example 16. The semiconductor device according to Example 10, wherein the first gate segment includes: a gate dielectric layer; and a gate electrode layer, wherein the gate dielectric layer is disposed between the gate electrode layer and the cut gate structure.

[0125] Example 17. A semiconductor device includes: a first gate structure; a second gate structure parallel to the first gate structure; a first source / drain region formed between the first gate structure and the second gate structure; a second source / drain region formed between the first gate structure and the second gate structure; a source / drain contact feature in contact with the first source / drain region and the second source / drain region; a first cut gate structure disposed in the first gate structure; a second cut gate structure disposed in the second gate structure; a first dielectric layer disposed between the source / drain contact feature and the first cut gate structure; and a second dielectric layer disposed between the source / drain contact feature and the second cut gate structure.

[0126] Example 18. The semiconductor device according to Example 17, wherein the first dielectric layer includes a first gate sidewall spacer in contact with the first gate structure.

[0127] Example 19. The semiconductor device according to Example 18, wherein the first dielectric layer further includes a contact etch stop layer in contact with the first source / drain region and the second source / drain region.

[0128] Example 20. The semiconductor device according to Example 19, further includes an isolation layer, wherein the first gate structure is disposed on the isolation layer, and the first cut gate structure extends into the isolation layer.

Claims

1. A method of manufacturing a semiconductor device, comprising: Forming a semiconductor structure, the semiconductor structure comprising: A first semiconductor fin structure and a second semiconductor fin structure extending in a first direction; A gate structure spanning the first semiconductor fin structure and the second semiconductor fin structure; A first source / drain region on the first semiconductor fin structure; A second source / drain region on the second semiconductor fin structure; and An interlayer dielectric (ILD) layer over the first source / drain region and the second source / drain region; Depositing a mask layer over the semiconductor structure; Forming a first opening through the mask layer, wherein the first opening extends in the first direction disposed between the first semiconductor fin structure and the second semiconductor fin structure, and the first opening exposes the gate structure and a portion of the ILD layer; Forming a via opening in the gate structure through the first opening in the mask layer, wherein the via opening divides the gate structure into two segments; Filling the via opening with a dielectric material to form a cut gate structure.

2. The method according to claim 1, wherein The semiconductor structure further includes a first gate sidewall spacer and a second gate sidewall spacer disposed on sidewalls of the gate structure, and the cut gate structure contacts the first gate sidewall spacer and the second gate sidewall spacer.

3. The method according to claim 1 further comprises: Forming a protective cap over the ILD layer before depositing the mask layer.

4. The method according to claim 3, wherein Forming the protective cap includes: Recessing the ILD layer to a level lower than the gate structure; Depositing a protective material over the semiconductor structure; and Planarizing the semiconductor structure to expose the gate structure.

5. The method according to claim 4, wherein, The protective material is a nitrogen-containing dielectric material.

6. The method according to claim 3, further comprising: After filling the via opening with the dielectric material, planarize the semiconductor structure to remove the protective cap.

7. The method according to claim 1, after filling the via opening with the dielectric material, further comprising: Removing the two segments of the gate structure to expose the first semiconductor fin structure and the second semiconductor fin structure; Depositing a replacement gate dielectric layer on the first semiconductor fin structure and the second semiconductor fin structure; And Depositing a replacement gate electrode layer on the replacement gate dielectric layer.

8. The method according to claim 1, wherein The semiconductor structure further includes a dielectric fin disposed between the first semiconductor fin structure and the second semiconductor fin structure, and the via opening extends into the dielectric fin.

9. A semiconductor device, comprising: A first semiconductor fin structure and a second semiconductor fin structure extending in a first direction; And A gate structure spanning the first semiconductor fin structure and the second semiconductor fin structure, wherein the gate structure includes: A first gate segment disposed over the first semiconductor fin structure; A second gate segment disposed over the second semiconductor fin structure; A cut gate structure disposed between the first gate segment and the second gate segment; A first gate sidewall spacer; and A second gate sidewall spacer, wherein the cut gate structure is disposed between the first gate sidewall spacer and the second gate sidewall spacer.

10. A semiconductor device, comprising: A first gate structure; A second gate structure, parallel to the first gate structure; A first source / drain region formed between the first gate structure and the second gate structure; A second source / drain region formed between the first gate structure and the second gate structure; A source / drain contact feature in contact with the first source / drain region and the second source / drain region; A first cut gate structure disposed in the first gate structure; A second cut gate structure disposed in the second gate structure; A first dielectric layer disposed between the source / drain contact feature and the first cut gate structure; And A second dielectric layer disposed between the source / drain contact feature and the second cut gate structure.

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