Semiconductor element

Abstract

The invention discloses a semiconductor element, which mainly comprises a substrate having a first planar region, a second planar region arranged beside the first planar region, a non-planar region arranged between the first planar region and the second planar region, a first pedestal arranged in the first planar region, a second pedestal arranged in the second planar region, and a plurality of bumps arranged in the non-planar region, wherein the bumps have different heights, the top surface of the first base is flush with the top surface of the second base, the bump top surfaces are lower than the top surface of the first base, and the height of the bumps close to the first planar region is greater than the height of the bumps close to the non-planar region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having bumps of different heights disposed beside a planar region. Background Art

[0002] With the current level of semiconductor technology, the industry has been able to integrate control circuits, memories, low-voltage operating circuits, high-voltage operating circuits, and components on a single chip simultaneously, thereby reducing costs and improving operating efficiency at the same time. Among them, high-voltage components such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT), and lateral-diffusion metal-oxide-semiconductor (LDMOS) fabricated in the chip are more commonly used because of their better power switching efficiency. As is known to those skilled in the art, the aforementioned high-voltage components are often required to be able to withstand a higher breakdown voltage and operate at a lower resistance value.

[0003] In addition, as the device size continues to shrink, the development of existing planar field-effect transistor devices has faced limitations in manufacturing processes. To overcome the manufacturing process limitations, it has become the current mainstream development trend to replace planar transistor devices with non-planar field-effect transistor devices, such as fin field effect transistor (Fin FET) devices. Since the three-dimensional structure of the fin field effect transistor device can increase the contact area between the gate and the fin structure, the control of the gate over the carrier channel region can be further increased, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small-size devices and suppressing the short channel effect (SCE). Moreover, since the fin field effect transistor device will have a wider channel width at the same gate length, a doubled drain drive current can be obtained. Furthermore, the threshold voltage of the transistor device can also be adjusted by adjusting the work function of the gate.

[0004] However, as the device size continues to shrink, there are still many challenges in the integration of current high-voltage devices and low-voltage devices such as fin field-effect transistors, such as the control of leakage current and breakdown voltage. Therefore, how to improve the architectures of existing high-voltage and low-voltage devices has become an important topic today. Summary of the Invention

[0005] An embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate having a first planar region, a second planar region disposed beside the first planar region, a non-planar region disposed between the first planar region and the second planar region, a first pedestal disposed on the first planar region, a second pedestal disposed on the second planar region, and a plurality of bumps disposed in the non-planar region, wherein the bumps have different heights, the top surface of the first pedestal is flush with the top surface of the second pedestal, the top surfaces of the bumps are lower than the top surface of the first pedestal, and the height of the bumps closer to the first planar region is greater than the height of the bumps closer to the non-planar region.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate having a first planar region and a non-planar region, a plurality of bumps disposed in the non-planar region, and a plurality of dummy fin structures disposed beside the bumps in the non-planar region. Brief Description of the Drawings

[0007] Figures 1 to 4 Schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0008] Figures 5 to 11 Schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0009] Description of Reference Signs

[0010] 12: Substrate

[0011] 14: Planar Region

[0012] 16: Planar Region

[0013] 18: Non-Planar Region

[0014] 20: Pedestal

[0015] 22: Pedestal

[0016] 24: Fin Structure

[0017] 26: Patterning Mask

[0018] 28: Bump

[0019] 30: Bump

[0020] 32: Bump

[0021] 36: ODL

[0022] 38: SHB layer

[0023] 40: Patterning photoresist

[0024] 42: Bump

[0025] 44: Bump

[0026] 46: Shallow trench isolation

[0027] 48: Gate dielectric layer

[0028] 50: Gate electrode

[0029] 52: Gate structure

[0030] 54: Spacer

[0031] 56: Source / drain region Detailed implementation manner

[0032] Please refer to Figures 1 to 4 , Figure 1 and Figure 3 is a top view of manufacturing a semiconductor device according to an embodiment of the present invention, Figure 2 is Figure 1 a schematic diagram of a method for manufacturing a semiconductor device along the tangent line AA' in Figure 4 is Figure 3 a schematic diagram of a method for manufacturing a semiconductor device along the tangent line BB' in Figures 1 to 2 As shown, first, a substrate 12 is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which two planar regions 14, 16 and a non-planar region 18 are defined between the planar regions. Each of the planar regions 14, 16 can be used in subsequent manufacturing processes to fabricate high-voltage components and / or medium-voltage components based on planar field-effect transistors, while the non-planar region 18 is preferably used to fabricate a non-planar device structure, such as a dummy fin structure for improving the overall device balance.

[0033] Then, pedestals 20 and 22 are respectively formed on the substrate 12 of the planar regions 14 and 16, and a plurality of fin structures 24 are formed on the substrate 12 of the non-planar region 18. According to a preferred embodiment of the present invention, the pedestals 20 and 22 and / or the fin structures 24 can be fabricated by the sidewall image transfer (SIT) technique. The process generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, through photolithography and etching manufacturing processes, a plurality of equally spaced and equally wide patterned sacrificial layers or mandrels are formed on the substrate, and their individual appearances are strip-shaped. Then, deposition and etching manufacturing processes are sequentially performed to form spacer walls on the sidewalls of each patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching manufacturing process is performed under the coverage of the spacer walls, so that the pattern formed by the spacer walls is transferred into the substrate.

[0034] In addition, the formation method of the pedestals 20 and 22 and / or the fin structures 24 may also include first forming a patterned mask (not shown) on the substrate 12, and then through an etching manufacturing process, transferring the pattern of the patterned mask into the substrate 12 to form the pedestals 20 and 22 and / or the fin structures 24. Additionally, the formation method of the pedestals 20 and 22 and / or the fin structures 24 can also be to first fabricate a patterned hard mask layer (not shown) on the substrate 12, and use an epitaxial manufacturing process to grow a semiconductor layer containing, for example, silicon germanium on the substrate 12 exposed by the patterned hard mask layer, and this semiconductor layer can serve as the corresponding pedestals and / or fin structures 24. These embodiments of forming the pedestals 20 and 22 and the fin structures 24 are all within the scope covered by the present invention. Since the pedestals 20 and 22 and the fin structures 24 are all formed in the same manufacturing process, the top surfaces of the pedestals 20 and 22 are preferably flush with the top surfaces of the fin structures 24.

[0035] It should be noted that after forming the pedestals 20 and 22 and the fin structures 24, from Figure 1Looking at it, the bases 20, 22 are preferably arranged in the planar regions 14, 16 on both sides in a rectangular shape in a top-down view, for example, while the fin-like structure 24 extends in a strip shape along the X direction in a top-down view in the non-planar region 18 between the two planar regions 14, 16. Then, a patterned mask 26 can be formed to cover the planar regions 14, 16, where the patterned mask 26 has an opening exposing all the fin-like structures 24 in the non-planar region 18. In this embodiment, the patterned mask 26 can include a multi-layer mask composed of an organic dielectric layer (ODL) 36, a silicon-containing hard mask and anti-reflective (SHB) layer 38, and a patterned photoresist 40.

[0036] Subsequently, as Figures 2 to 4 shown, a fin cut manufacturing process is performed. For example, the fin-like structures 24 in the non-planar region 18 between the two planar regions 14, 16 can be removed by etching using the patterned mask 26 as a mask, and then the patterned mask 26 is removed. It should be noted that since the patterned mask 26 near the non-planar region 18 and away from the non-planar region 18 preferably has a height difference. For example, the top surface of the patterned mask 26 near the non-planar region 18 is generally slightly lower than the top surface of the patterned mask 26 away from the non-planar region 18. Therefore, when using the patterned mask 26 to etch and remove the fin-like structures 24 in the non-planar region 18, it is preferably to remove only most of the fin-like structures 24, so that the remaining fin-like structures 24 form bumps 28, 30, 32 with different heights on the substrate 12 of the non-planar region 18.

[0037] Looking at the details, each fin-like structure 24 originally extending along the X direction in the non-planar region 18 can form multiple bumps after being etched by the fin cut manufacturing process. For example, three bumps 28, 30, 32 are arranged along the X or Y direction, and the top surfaces of all the bumps 28, 30, 32 are lower than the top surfaces of the bases 20, 22 in the planar regions 14, 16 on both sides. For example, the height or top surface of each bump 28, 30, 32 can be less than one-half, one-third, one-fourth, or less than one-fifth of the total height of the bases 20, 22. In addition, in this embodiment, the heights of the bumps 28, 32 near the planar regions 14, 16 are preferably slightly greater than the height of the bump 30 near the non-planar region 18, or more specifically, the heights of the bumps 28, 32 near the planar regions 14, 16 are preferably greater than the height of the bump 30 in the middle of the non-planar region 18.

[0038] Taking the three bumps 28, 30, and 32 provided in the non-planar region 18 in this embodiment as an example, the height of the bump 28 near the left planar region 14 and the height of the bump 32 near the right planar region 16 are preferably greater than the height of the bump 30 near the non-planar region 18 (i.e., the bump 30 provided in the middle of the two planar regions 14, 16 or the non-planar region 18), and the height of the bump 28 near the left planar region 14 can be approximately equal to the height of the bump 32 near the right planar region 16. In other words, there are two heights in total for the three bumps 28, 30, and 32 provided in the non-planar region 18 in this embodiment, and the height of the bump 28 near the left planar region 14 and the height of the bump 32 near the right planar region 16 are preferably greater than the height of the bump 30 near the center of the non-planar region 18.

[0039] It should be noted that although this embodiment takes the example of setting three bumps 28, 30, and 32 in the non-planar region 18, it is not limited thereto. According to other embodiments of the present invention, after each fin structure 24 in the non-planar region 18 is etched by the fin structure cutting manufacturing process, multiple bumps, such as three or more bumps, can be formed, such as four, five, or more than six bumps. Among them, the height of the bumps near the two planar regions 14, 16 is preferably greater than the height of the bump near the center of the non-planar region 18. For example, if there are four bumps in the non-planar region 18, the height of the two bumps near the two planar regions 14, 16 can be greater than the height of the two bumps near the center of the non-planar region 18; if there are five bumps in the non-planar regions 14, 16, the height of the two bumps near the two planar regions 14, 16 can be greater than the height of the three bumps near the center of the non-planar region 18 or the height of the four bumps near the two planar regions 14, 16 can be greater than the height of the one bump near the center of the non-planar region 18. These variations are all within the scope covered by the present invention.

[0040] It should also be noted that although this embodiment sets two planar regions 14, 16 and a non-planar region 18 between the planar regions 14, 16 on the substrate 12, it is not limited thereto. According to other embodiments of the present invention, only one planar region and a non-planar region can be provided beside the planar region. A pedestal is provided in the planar region, and the aforementioned bumps with different heights are provided in the non-planar region. Moreover, the height of the bumps near the planar region is preferably slightly greater than the height of the bumps near the non-planar region. This variation is also within the scope covered by the present invention.

[0041] Please continue to refer to Figures 5 to 11 , Figures 5 to 11 which is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 5 and Figure 8 are top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention, Figure 6 is Figure 5 a schematic cross-sectional view of manufacturing a semiconductor device along the tangent CC' in Figure 7 isFigure 5 A schematic cross-sectional view of a semiconductor device fabricated along the tangent DD'. Figure 9 is Figure 8 A schematic cross-sectional view of a semiconductor device fabricated along the tangent EE'. Figure 10 is Figure 8 A schematic cross-sectional view of a semiconductor device fabricated along the tangent FF', and Figure 11 is Figure 10 A schematic view of a method for fabricating a semiconductor device.

[0042] As Figures 5 to 7 shown, in the present invention, a pedestal 20, 22 can be formed on the substrate 12 in the planar regions 14, 16 and a plurality of fin structures 24 can be formed on the substrate 12 in the non-planar region 18 according to the foregoing fabrication process. Then, a patterned mask 26 is formed to cover the planar regions 14, 16 and a part of the fin structures 24 in the non-planar region 18. The patterned mask 26 has at least one opening exposing a part of the fin structures 24 in the non-planar region 18. Similar to the foregoing embodiment, the patterned mask 26 can include a multi-layer mask composed of an organic dielectric layer (ODL) 36, a silicon-containing hard mask and anti-reflective (SHB) layer 38, and a patterned photoresist 40.

[0043] Subsequently, as Figures 8 to 10 shown, a fin structure cutting fabrication process is performed. For example, the patterned mask 26 can be used as a mask to etch away a part of the fin structures 24 in the non-planar region 18 between the two planar regions 14, 16. It should be noted that, compared with the fin structure cutting fabrication process in the foregoing embodiment, which removes all the fin structures 24 in the non-planar region 18 from a top view and makes all the remaining fin structures 24 form bumps, in this embodiment, only a part of the fin structures 24 in the non-planar region 18 are removed to reduce their height and convert them into a plurality of bumps 28, 30, 32, 42, 44.

[0044] In other words, at this stage, when removing the fin structures 24 in the non-planar region 18 using the patterned mask 26 as a mask, it is preferable to dispose the patterned mask 26 on the planar regions 14 and 16 on both sides and on a part of the fin structures 24 in the non-planar region 18. Then, using the patterned mask 26, the fin structures 24 in the non-planar region 18 that are not covered by the patterned mask 26 are removed by etching to reduce their height and form bumps with different heights. The remaining fin structures 24 that are not etched into bumps become dummy fin structures, and their top surfaces are preferably flush with the top surfaces of the pedestals 20 and 22 in the planar regions 14 and 16. Different from the subsequent formation of transistor elements such as gate structures and source / drain regions on the pedestals 20 and 22 in the planar regions 14 and 16 during the transistor manufacturing process, no transistor elements are preferably formed on the dummy fin structures in the non-planar region 18.

[0045] In addition, it should be noted that Figure 6 from the cross-sectional angle of Figure 9 since there are no pedestals on both sides of the fin structure 24, the patterned mask 26 disposed on both sides of the fin structure 24 preferably has no height difference. Thus, the bumps 30, 42, and 44 formed after removing a part of the fin structure 24 preferably have the same height.

[0046] If from Figure 7 the cross-sectional angle of Figure 2 as in the foregoing Figure 10 embodiment, since the patterned mask 26 near and far from the non-planar region 18 preferably has a height difference, for example, the top surface of the patterned mask 26 near the non-planar region 18 is generally slightly lower than the top surface of the patterned mask 26 far from the non-planar region 18. Therefore, after using the patterned mask 26 to etch and remove a part of the fin structure 24 in the non-planar region 18, the remaining fin structures 24 preferably form bumps 28, 30, and 32 with different heights on the substrate 12 in the non-planar region 18. In addition, the number and height variations of the bumps formed in the non-planar region 18 in this embodiment can be referred to the foregoing embodiment, and will not be elaborated herein.

[0047] After that, as Figure 11As shown, a shallow trench isolation 46 made of silicon oxide can be selectively formed on the bumps 28, 30, 32 and surround each pedestal 20, 22, and then subsequent transistor manufacturing processes can be carried out according to the requirements of the manufacturing process. For example, a gate structure 52 composed of a gate dielectric layer 48 and a gate electrode 50 can be formed on each pedestal 20, 22 in the planar regions 14, 16 respectively. A spacer 54 is beside the gate structure 52, and source / drain regions 56 are disposed in the pedestals 20, 22 beside the spacer 54. The shallow trench isolation 46 and the gate dielectric layer 48 can include silicon oxide, the gate electrode 50 can include polysilicon, the spacer 54 can include silicon oxide or silicon nitride, and the source / drain regions 56 can include N-type or P-type dopants according to the type of transistor to be fabricated. Since the standard planar transistor manufacturing process is well-known in the art, it will not be described in detail here.

[0048] Generally speaking, when integrating high-voltage and / or medium-voltage components composed of planar field-effect transistors and low-voltage components composed of non-planar components such as fin field-effect transistors, a plurality of dummy fin structures are usually provided between adjacent non-planar regions to improve the overall balance of the components. In order to make the planar regions closer to each other and reduce the required area of the overall chip, the present invention preferably uses an etching method to remove all or part of the fin structures between the planar regions during the fin structure cutting manufacturing process, so that the remaining fin structures form bumps with different heights. According to a preferred embodiment of the present invention, the heights of the bumps 28, 32 close to the planar regions 14, 16 are preferably slightly greater than the height of the bump 30 close to the non-planar region 18, or more specifically, the heights of the bumps 28, 32 close to the planar regions 14, 16 are preferably greater than the height of the bump 30 in the middle of the non-planar region 18.

[0049] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate comprising a first planar region and a non-planar region; and A plurality of bumps disposed in the non-planar region, wherein the plurality of bumps have different heights.

2. The semiconductor device according to claim 1, further comprising: A second planar region disposed beside the first planar region, wherein the non-planar region is disposed between the first planar region and the second planar region.

3. The semiconductor device according to claim 2, further comprising: A first pedestal disposed on the first planar region; A second pedestal disposed on the second planar region; and The plurality of bumps disposed in the non-planar region.

4. The semiconductor device according to claim 3, wherein the top surface of the first pedestal is flush with the top surface of the second pedestal.

5. The semiconductor device according to claim 3, wherein the top surfaces of the plurality of bumps are lower than the top surface of the first pedestal.

6. The semiconductor device according to claim 1, wherein the top surfaces of the plurality of bumps are lower than the top surface of the second pedestal.

7. The semiconductor device according to claim 1, wherein the heights of the plurality of bumps closer to the first planar region are greater than the heights of the plurality of bumps closer to the non-planar region.

8. The semiconductor device according to claim 1, wherein the heights of the plurality of bumps closer to the first planar region are greater than the heights of the plurality of bumps at the exact middle of the non-planar region.

9. A semiconductor device, characterized in that, Comprising: A substrate comprising a first planar region and a non-planar region; A plurality of bumps disposed in the non-planar region; and A plurality of dummy fin structures disposed beside the plurality of bumps in the non-planar region.

10. The semiconductor device according to claim 9, further comprising: A second planar region disposed beside the first planar region, wherein the non-planar region is disposed between the first planar region and the second planar region.

11. The semiconductor device according to claim 9, further comprising: A first pedestal disposed on the first planar region; A second pedestal disposed on the second planar region; and The plurality of bumps and the plurality of dummy fin structures are disposed in the non-planar region.

12. The semiconductor device according to claim 11, wherein the top surface of the first pedestal is flush with the top surfaces of the plurality of dummy fin structures.

13. The semiconductor device according to claim 11, wherein the top surfaces of the plurality of bumps are lower than the top surface of the first pedestal.

14. The semiconductor device according to claim 9, wherein the top surfaces of the plurality of bumps are lower than the top surfaces of the plurality of dummy fin structures.

15. The semiconductor device according to claim 9, wherein the plurality of bumps have different heights.

16. The semiconductor device according to claim 9, wherein the heights of the plurality of bumps closer to the first planar region are greater than the heights of the plurality of bumps closer to the non-planar region.

17. The semiconductor device according to claim 9, wherein the heights of the plurality of bumps closer to the first planar region are greater than the heights of the plurality of bumps at the exact middle of the non-planar region.

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