Semiconductor device

Abstract

A semiconductor device includes: a first active pattern including a first lower pattern and a first sheet pattern spaced apart from the first lower pattern in a first direction; a first gate structure including a first inner gate between the first lower pattern and a lowermost one of the first sheet patterns and between each pair of adjacent first sheet patterns, the first inner gate extending in a second direction intersecting the first direction, each of the first inner gates includes a first gate electrode and a first gate insulating film; a first source / drain pattern on the first lower pattern and connected to the first sheet pattern; a first inner spacer between the first source / drain pattern and the first inner gate; and a first nitrogen accumulation region within the first inner spacer.

Description

Technical Field

[0001] The disclosed example embodiments relate to semiconductor devices. Background Art

[0002] As one of scaling techniques for increasing the density of semiconductor devices, multi-gate transistors have been proposed. A multi-gate transistor can be produced by forming a multi-channel active pattern (or silicon body) in the shape of a fin or a nanowire on a substrate and then forming a gate on the surface of the multi-channel active pattern.

[0003] Since a three-dimensional (3D) channel is utilized, a multi-gate transistor can be more easily scaled. In addition, a multi-gate transistor can improve current control ability without increasing its gate length. Further, a multi-gate transistor can effectively suppress the short-channel effect (SCE), in which the potential in a channel region is affected by a drain voltage.

[0004] When the pitch size of a semiconductor device is reduced, a reduction in parasitic capacitance is required to ensure electrical stability between contacts within the semiconductor device.

[0005] The information disclosed in this background art section has been known or derived by the inventors before or during the process of implementing the embodiments of the present application, or is technical information obtained during the process of implementing the embodiments. Therefore, the information disclosed in this background art section may include information that does not form the prior art known to the public. Summary of the Invention

[0006] One or more example embodiments provide a semiconductor device that can improve device performance and reliability.

[0007] Additional aspects will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by practice of the presented embodiments.

[0008] According to an aspect of an example embodiment, a semiconductor device may include: a first active pattern including a first lower pattern and a first fin pattern, the first fin pattern being spaced apart from the first lower pattern in a first direction; a first gate structure including a first inner gate, the first inner gate being between the first lower pattern and the lowest first fin pattern among the first fin patterns and between each pair of adjacent first fin patterns, the first inner gate extending in a second direction intersecting the first direction, wherein each of the first inner gates includes a first gate electrode and a first gate insulating film; a first source / drain pattern on the first lower pattern and connected to the first fin pattern; a first inner spacer between the first source / drain pattern and the first inner gate; and a first nitrogen accumulation region within the first inner spacer, wherein each of the first inner gates may have a first surface, a second surface, and sidewalls, the second surface being opposite the first surface in the first direction, the sidewalls connecting the first surface and the second surface, and the first nitrogen accumulation region may extend along the sidewalls of the first inner gate.

[0009] According to an aspect of an example embodiment, a semiconductor device may include: a first active pattern including a first lower pattern and a first fin pattern, the first fin pattern being spaced apart from the first lower pattern in a first direction; a first gate structure including a first inner gate, the first inner gate being between the first lower pattern and the lowest first fin pattern among the first fin patterns and between each pair of adjacent first fin patterns, the first inner gate extending in a second direction intersecting the first direction, wherein each of the first inner gates includes a first gate electrode and a first gate insulating film; a first source / drain pattern on the first lower pattern, including doped n-type impurities, and connected to the first fin pattern; a first inner spacer between the first source / drain pattern and the first inner gate; and a first nitrogen accumulation region extending along the boundary between the first source / drain pattern and the first inner spacer and along the boundary between the first inner gate and the first fin pattern.

[0010] According to one aspect of an exemplary embodiment, a semiconductor device may include: a first active pattern including a first lower pattern and a first fin pattern, the first fin pattern being spaced apart from the first lower pattern in a first direction; a first gate structure including a first inner gate, the first inner gate being between the first lower pattern and the lowest first fin pattern among the first fin patterns and between each pair of adjacent first fin patterns, the first inner gate extending in a second direction intersecting the first direction, wherein each of the first inner gates includes a first gate electrode and a first gate insulating film; a first source / drain pattern on the first lower pattern and connected to the first fin pattern; a first inner spacer between the first source / drain pattern and the first inner gate; a second active pattern including a second lower pattern and a second fin pattern, the second fin pattern being spaced apart from the second lower pattern in the first direction; a second gate structure including a second inner gate, the second inner gate being between the second lower pattern and the lowest second fin pattern among the second fin patterns and between each pair of adjacent second fin patterns, the second inner gate extending in the second direction; a second source / drain pattern on the second lower pattern and connected to the second fin pattern; a second inner spacer between the second source / drain pattern and the second inner gate; a first nitrogen accumulation region within the first inner spacer; and a second nitrogen accumulation region within the second inner spacer, wherein, in a third direction intersecting the first direction and the second direction, the length of at least one first fin pattern having a first height among the first fin patterns is greater than the length of at least one second fin pattern having the first height among the second fin patterns.

[0011] However, aspects of the present disclosure are not limited to those set forth herein. By referring to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become clearer to those of ordinary skill in the art to which the present disclosure pertains. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features, and advantages of specific exemplary embodiments of the present disclosure will become clearer from the following description taken in conjunction with the drawings.

[0013] Figure 1 is a view showing a semiconductor device according to one or more embodiments.

[0014] Figure 2 is a cross-sectional view taken along line A-A of Figure 1 according to one or more embodiments.

[0015] Figure 3 is a cross-sectional view taken along line B-B of Figure 1 according to one or more embodiments.

[0016] Figure 4 is a cross-sectional view taken along line C-C of Figure 1 according to one or more embodiments.

[0017] Figure 5 is a magnified cross-sectional view of portion P according to one or more embodiments Figure 2 of

[0018] Figure 6 is a magnified cross-sectional view of portion Q according to one or more embodiments Figure 3 of

[0019] Figure 7 is a diagram showing the nitrogen (N) concentration along "scan line 1" and "scan line 2" according to one or more embodiments Figure 5 of

[0020] Figure 8 is a diagram showing a semiconductor device according to one or more embodiments

[0021] Figure 9 is a diagram showing the nitrogen (N) concentration along "scan line 1" and "scan line 2" according to one or more embodiments Figure 8 of

[0022] Figure 10 and Figure 11 is a diagram showing a semiconductor device according to one or more embodiments

[0023] Figure 12 and Figure 13 is a diagram showing a semiconductor device according to one or more embodiments

[0024] Figure 14 is a diagram showing a semiconductor device according to one or more embodiments

[0025] Figure 15 is a diagram showing the nitrogen (N) concentration along "scan line 1" and "scan line 2" according to one or more embodiments Figure 14 of

[0026] Figure 16 and Figure 17 is a diagram showing a semiconductor device according to one or more embodiments

[0027] Figure 18 and Figure 19 is a diagram showing a semiconductor device according to one or more embodiments

[0028] Figure 20 is a diagram showing a semiconductor device according to one or more embodiments

[0029] Figures 21 to 39 is a diagram showing the operations of a method of manufacturing a semiconductor device according to one or more embodiments Detailed Implementation Modes

[0030] Hereinafter, the disclosed exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and their redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and thus, the disclosure is not limited thereto and can be implemented in various other forms.

[0031] As used herein, expressions such as "at least one of..." modify the entire list of elements when following the list of elements, rather than modifying each individual element of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0032] It will be understood that when an element or layer is referred to as being "on", "above", "over", "under", "below", "beneath", "connected to", or "coupled to" another element or layer, the element or layer can be directly on, above, over, under, below, beneath, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "above", "over", "under", "below", "beneath", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0033] A semiconductor device according to one or more embodiments may include transistors based on two-dimensional (2D) materials and their heterostructures. Additionally, a semiconductor device according to one or more embodiments may further include bipolar junction transistors, laterally diffused metal oxide semiconductor (LDMOS) transistors, and the like.

[0034] Hereinafter, reference will be made to Figures 1 to 7 describe a semiconductor device according to one or more embodiments.

[0035] Figure 1 is a diagram showing a semiconductor device according to one or more embodiments. Figure 2 is a cross-sectional view taken along line A-A according to one or more embodiments Figure 1 of. Figure 3 is a cross-sectional view taken along line B-B according to one or more embodiments Figure 1 of. Figure 4 is a cross-sectional view taken along line C-C according to one or more embodiments Figure 1 of. Figure 5 is a magnified cross-sectional view of part P according to one or more embodiments Figure 2 of. Figure 6 is a partial view according to one or more embodimentsFigure 3 An enlarged cross-sectional view of a portion Q. Figure 7 is a schematic graph showing the nitrogen (N) concentration along Figure 5 "Scan line 1" and "Scan line 2" according to one or more embodiments.

[0036] Along Figure 1 A cross-sectional view taken along each second gate electrode 220 in the second direction D2 may be similar to Figure 4 .

[0037] Referring to Figures 1 to 7 , a semiconductor device according to one or more embodiments may include a first active pattern AP1, a second active pattern AP2, a plurality of first gate electrodes 120, a plurality of second gate electrodes 220, a first inner spacer 135, a second inner spacer 235, a first source / drain pattern 150, a second source / drain pattern 250, and a first nitrogen build-up region 135N1.

[0038] The substrate 100 may include a first region I and a second region II. For example, the first region I and the second region II may be adjacent regions. For example, one of the second gate electrodes 220 in the second region II may be the first gate electrode 120 in the first region I. Alternatively, the first region I and the second region II may be separate regions.

[0039] The first region I and the second region II may be a logic region, a static random access memory (RAM) (SRAM) region, or an input / output (I / O) region. For example, the first region I and the second region II may be regions that perform the same function. Alternatively, the first region I and the second region II may be regions that perform different functions.

[0040] The first region I and the second region II may be regions in which transistors of different conductivity types are formed. For example, the first region I may be a region in which N-type metal oxide semiconductor (MOS) (NMOS) transistors are formed. The second region II may be a region in which P-type MOS (PMOS) transistors are formed.

[0041] The substrate 100 may be a bulk silicon or silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be a silicon substrate, or include other materials (e.g., silicon germanium (SiGe), SiGe-on-insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide), but the embodiments are not limited thereto.

[0042] The first active pattern AP1, a plurality of first gate electrodes 120, first inner spacers 135, and first source / drain patterns 150 may be disposed in a first region I of the substrate 100. The second active pattern AP2, a plurality of second gate electrodes 220, second inner spacers 235, and second source / drain patterns 250 may be disposed in a second region II of the substrate 100.

[0043] The first active pattern AP1 and the second active pattern AP2 may be disposed on the substrate 100. The first active pattern AP1 and the second active pattern AP2 may extend in a first direction D1.

[0044] Optionally, one of the first active pattern AP1 and the second active pattern AP2 may extend in the first direction D1, and the other active pattern may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 will be described hereinafter as both extending in the first direction D1.

[0045] The first active pattern AP1 and the second active pattern AP2 may be multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1. The second active pattern AP2 may include a second lower pattern BP2 and a plurality of second sheet patterns NS2.

[0046] The first lower pattern BP1 may protrude from the substrate 100. The first lower pattern BP1 may extend in the first direction D1. Similarly, the second lower pattern BP2 may protrude from the substrate 100. The second lower pattern BP2 may also extend in the first direction D1.

[0047] The first sheet pattern NS1 may be disposed on an upper surface BP1_US of the first lower pattern BP1. The first sheet pattern NS1 may be spaced apart from the first lower pattern BP1 in a third direction D3. The first sheet patterns NS1 may be spaced apart from each other in the third direction D3.

[0048] The second sheet pattern NS2 may be disposed on an upper surface BP2_US of the second lower pattern BP2. The second sheet pattern NS2 may be spaced apart from the second lower pattern BP2 in the third direction D3. The second sheet patterns NS2 may be spaced apart from each other in the third direction D3.

[0049] Each of the first sheet patterns NS1 may include an upper surface NS1_US and a lower surface NS1_BS. The upper surface NS1_US of the first sheet pattern NS1 may be opposite to the lower surface NS1_BS of the first sheet pattern NS1 in the third direction D3.

[0050] Each of the second pattern NS2 may include an upper surface NS2_US and a lower surface NS2_BS. The upper surface NS2_US of the second pattern NS2 may be opposite to the lower surface NS2_BS of the second pattern NS2 in a third direction D3. The third direction D3 may be a direction intersecting both the first direction D1 and the second direction D2. For example, the third direction D3 may be the thickness direction of the substrate 100. The first direction D1 may be a direction intersecting the second direction D2.

[0051] Three first pattern NS1 and three second pattern NS2 are shown as being disposed in the third direction D3, but the embodiments are not limited thereto.

[0052] Each of the first lower pattern BP1 and the second lower pattern BP2 may be formed by etching a part of the substrate 100, or may include an epitaxial layer grown from the substrate 100. Each of the first lower pattern BP1 and the second lower pattern BP2 may include silicon or germanium, which are elemental semiconductor materials. Additionally, each of the first lower pattern BP1 and the second lower pattern BP2 may include a compound semiconductor (such as a group-IV-IV compound semiconductor or a group-III-V compound semiconductor).

[0053] The group-IV-IV compound semiconductor may include, for example, a binary compound, a ternary compound, or a quaternary compound containing at least two elements among carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping a binary compound, a ternary compound, or a quaternary compound with a group-IV element.

[0054] The group-III-V compound semiconductor may include, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group-III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as group-V elements.

[0055] The first pattern NS1 and the second pattern NS2 may include Si or Ge as elemental semiconductor materials, or a group-IV-IV or group-III-V compound semiconductor. The first pattern NS1 may include the same material or a different material from the first lower pattern BP1. Similarly, the second pattern NS2 may include the same material or a different material from the second lower pattern BP2.

[0056] In one or more embodiments, both the first lower pattern BP1 and the second lower pattern BP2 may be Si lower patterns including Si, and both the first pattern NS1 and the second pattern NS2 may be Si pattern sheets including Si.

[0057] The width of the first pattern NS1 in the second direction D2 may increase or decrease proportionally to the width of the upper surface BP1_US of the first lower pattern BP1 in the second direction D2. Similarly, the width of the second pattern NS2 in the second direction D2 may increase or decrease proportionally to the width of the upper surface BP2_US of the second lower pattern BP2 in the second direction D2.

[0058] The first pattern NS1 stacked in the third direction D3 is shown to have the same width, and the second pattern NS2 stacked in the third direction D3 is shown to have the same width. However, the embodiments are not limited thereto. Optionally, the width of the first pattern NS1 stacked in the third direction D3 in the second direction D2 may decrease as the first pattern NS1 moves away from the first lower pattern BP1. The same description may also apply to the second pattern NS2.

[0059] The width of the first active pattern AP1 in the second direction D2 is shown to be the same as the width of the second active pattern AP2 in the second direction D2, but the embodiments are not limited thereto. By reference, the width of the first active pattern AP1 in the second direction D2 may correspond to the width of the upper surface BP1_US of the first lower pattern BP1 in the second direction D2.

[0060] The field insulating film 105 may be formed on the substrate 100. The field insulating film 105 may be disposed on the sidewalls of the first lower pattern BP1. The field insulating film 105 may not be disposed on the upper surface BP1_US of the first lower pattern BP1.

[0061] For example, the field insulating film 105 may generally cover the sidewalls of the first lower pattern BP1. Optionally, the field insulating film 105 may only cover a portion of the sidewalls of the first lower pattern BP1, in which case a portion of the first lower pattern BP1 may protrude above the upper surface of the field insulating film 105 in the third direction D3.

[0062] Each of the first patterns NS1 may be disposed above the upper surface of the field insulating film 105, and the same description may also apply to the relationship between the field insulating film 105 and the second pattern NS2.

[0063] The field insulating film 105 may include, for example, an oxide film, a nitride film, a nitroxide film, or a combination thereof. The field insulating film 105 is shown as a single film, but the embodiments are not limited thereto.

[0064] A plurality of first gate structures GS1 may be disposed on a substrate 100. Each of the first gate structures GS1 may extend in a second direction D2. The first gate structures GS1 may be spaced apart from each other in a first direction D1. The first gate structures GS1 may be adjacent to each other in the first direction D1. For example, the first gate structures GS1 may be disposed on both sides of a first source / drain pattern 150 in the first direction D1.

[0065] The first gate structure GS1 may be disposed on a first active pattern AP1. The first gate structure GS1 may intersect the first active pattern AP1. The first gate structure GS1 may intersect a first lower pattern BP1. The first gate structure GS1 may surround each of a first fin pattern NS1.

[0066] The first gate structure GS1 may include a first gate electrode 120 and a first gate insulating film 130.

[0067] The first gate structure GS1 may include a plurality of first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1). The plurality of first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1) may be disposed between each pair of first fin patterns NS1 adjacent to each other in a third direction D3, and between the first lower pattern BP1 and the lowermost first fin pattern NS1 among the first fin patterns NS1. The first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1) may be disposed in the third direction D3 between an upper surface BP1_US of the first lower pattern BP1 and a lower surface NS1_BS of the lowermost first fin pattern NS1 among the first fin patterns NS1, and between an upper surface NS1_US of a first fin pattern NS1 and a lower surface NS1_BS of an adjacent first fin pattern NS1 facing the upper surface NS1_US of the first fin pattern NS1.

[0068] The number of the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1) may be proportional to the number of first fin patterns NS1 included in the active pattern AP1. For example, the number of the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1) may be the same as the number of the first fin patterns NS1. Since the first active pattern AP1 includes a plurality of first fin patterns NS1, the first gate structure GS1 may include a plurality of first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1).

[0069] The first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1) may contact the upper surface BP1_US of the first lower pattern BP1, the upper surface NS1_US of the first fin pattern NS1, and the lower surface NS1_BS of the first fin pattern NS1.

[0070] A case where there are three first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1) will be described below.

[0071] Each of the first gate structures GS1 may include a first sub-inner gate INT1_GS1, a second sub-inner gate INT2_GS1, and a third sub-inner gate INT3_GS1. In each of the first gate structures GS1, the first sub-inner gate INT1_GS1, the second sub-inner gate INT2_GS1, and the third sub-inner gate INT3_GS1 may be sequentially disposed on the first lower pattern BP1.

[0072] The third sub-inner gate INT3_GS1 may be disposed between the first lower pattern BP1 and the lowermost first sheet pattern NS1 among the first sheet patterns NS1. The third sub-inner gate INT3_GS1 may be disposed at the lowest position among the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1). The third sub-inner gate INT3_GS1 may be the lowermost first inner gate. The third sub-inner gate INT3_GS1 may contact the upper surface BP1_US of the first lower pattern BP1.

[0073] The first sub-inner gate INT1_GS1 and the second sub-inner gate INT2_GS1 may be disposed between each pair of first sheet patterns NS1 adjacent in the third direction D3. The first sub-inner gate INT1_GS1 may be disposed at the highest position among the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1). The first sub-inner gate INT1_GS1 may be the uppermost first inner gate. The first sub-inner gate INT1_GS1 may contact the lower surface NS1_BS of the uppermost first sheet pattern NS1. The second sub-inner gate INT2_GS1 may be disposed between the first sub-inner gate INT1_GS1 and the third sub-inner gate INT3_GS1.

[0074] The first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1) may include a first gate electrode 120 and a first gate insulating film 130, and the first gate electrode 120 and the first gate insulating film 130 are disposed between each pair of adjacent first sheet patterns NS1, and between the first lower pattern BP1 and the lowermost first sheet pattern NS1 among the first sheet patterns NS1.

[0075] Each of the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1) may include a first surface INT1_US, a second surface INT1_BS, and a sidewall INT1_SW. The first surface INT1_US and the second surface INT1_BS face each other in a third direction D3, and the sidewall INT1_SW connects the first surface INT1_US and the second surface INT1_BS. The first surface INT1_US of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1) may face the lower surface NS1_BS of the first fin pattern NS1. The second surface INT1_BS of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1) may face the upper surface NS1_US of the first fin pattern NS1 or the upper surface BP1_US of the first lower pattern BP1.

[0076] A plurality of second gate structures GS2 may be disposed on the substrate 100. Each of the second gate structures GS2 may extend in a second direction D2. The second gate structures GS2 may be spaced apart from each other in a first direction D1. The second gate structures GS2 may be adjacent to each other in the first direction D1. For example, the second gate structures GS2 may be disposed on both sides of the second source / drain pattern 250 in the first direction D1.

[0077] The second gate structure GS2 may be disposed on the second active pattern AP2. The second gate structure GS2 may intersect the second active pattern AP2. The second gate structure GS2 may intersect the second lower pattern BP2. The second gate structure GS2 may surround each of the second fin patterns NS2.

[0078] The second gate structure GS2 may include a second gate electrode 220 and a second gate insulating film 230.

[0079] The second gate structure GS2 may include a plurality of second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2) disposed between each pair of second fin patterns NS2 adjacent to each other in the third direction D3, and between the second lower pattern BP2 and the lowermost second fin pattern NS2 among the second fin patterns NS2. The second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2) may contact the upper surface BP2_US of the second lower pattern BP2, and the upper surface NS2_US and the lower surface NS2_BS of the second fin pattern NS2.

[0080] Each of the second gate structures GS2 may include a fourth sub-inner gate INT1_GS2, a fifth sub-inner gate INT2_GS2, and a sixth sub-inner gate INT3_GS2. The sixth sub-inner gate INT3_GS2 may be disposed between the second lower pattern BP2 and the lowermost second sheet pattern NS2 among the second sheet patterns NS2. The sixth sub-inner gate INT3_GS2 may be the lowermost second inner gate. The fourth sub-inner gate INT1_GS2 may be disposed at the highest position among the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2). The fourth sub-inner gate INT1_GS2 may be the uppermost second inner gate. The fifth sub-inner gate INT2_GS2 may be disposed between the fourth sub-inner gate INT1_GS2 and the sixth sub-inner gate INT3_GS2.

[0081] The second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2) may include a second gate electrode 220 and a second gate insulating film 230, which are disposed between each pair of adjacent second sheet patterns NS2, and between the second lower pattern BP2 and the lowermost second sheet pattern NS2 among the second sheet patterns NS2.

[0082] Each of the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2) may include a first surface INT2_US, a second surface INT2_BS, and a sidewall INT2_SW. The first surface INT2_US and the second surface INT2_BS face each other in a third direction D3, and the sidewall INT2_SW connects the first surface INT2_US and the second surface INT2_BS. The first surface INT2_US of the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2) may face the lower surface NS2_BS of the second sheet pattern NS2. The second surface INT2_BS of the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2) may face the upper surface NS2_US of the second sheet pattern NS2 or the upper surface BP2_US of the second lower pattern BP2.

[0083] When the first active pattern AP1 and the second active pattern AP2 extend in different directions, the direction in which the second gate structure GS2 extends is different from the direction in which the first gate structure GS1 extends. For example, when the first active pattern AP1 extends in a first direction D1 and the second active pattern AP2 extends in a second direction D2, the first gate structure GS1 may extend in the first direction D1, and the second gate structure GS2 may extend in the second direction D2.

[0084] The first gate electrode 120 may be disposed on the first lower pattern BP1. The first gate electrode 120 may intersect the first lower pattern BP1. The first gate electrode 120 may surround the first fin pattern NS1. Portions of the first gate electrode 120 may be disposed between each pair of adjacent first fin patterns NS1, and between the first lower pattern BP1 and the lowermost first fin pattern NS1 among the first fin patterns NS1.

[0085] The second gate electrode 220 may be disposed on the second lower pattern BP2. The second gate electrode 220 may intersect the second lower pattern BP2. Portions of the second gate electrode 220 may be disposed between each pair of adjacent second fin patterns NS2, and between the second lower pattern BP2 and the lowermost second fin pattern NS2 among the second fin patterns NS2. Although not shown, the second gate electrode 220 may surround the second fin pattern NS2.

[0086] Each pair of adjacent first gate electrodes 120 in the first direction D1 may be spaced apart by a first distance. Similarly, each pair of adjacent second gate electrodes 220 in the first direction D1 may be spaced apart by a second distance. For example, the distance by which the first gate electrodes 120 are spaced apart in the first direction D1 may be the same as the distance by which the second gate electrodes 220 are spaced apart in the first direction D1.

[0087] For example, the distance in the first direction D1 between two first gate electrodes 120 between which the first source / drain pattern 150 is disposed may correspond to the distance between the opposing sidewalls in the first direction D1 of the two first gate electrodes 120 between which the first source / drain pattern 150 is disposed.

[0088] For example, the length W1 of the first fin pattern NS1 in the first direction D1 may be equal to or greater than the length W2 of the second fin pattern NS2 in the first direction D1. In one or more embodiments, the length W1 of the first fin pattern NS1 may be greater than the length W2 of the second fin pattern NS2.

[0089] The lengths W1 and W2 may be compared for each pair of the first fin pattern NS1 and the second fin pattern NS2 at the same height or level. That is, in some examples where the lengths of the fin patterns are compared at the same height or level, the length W1 may correspond to the second first fin pattern NS1 from the first lower pattern BP1, and the length W2 may correspond to the second second fin pattern NS2 from the second lower pattern BP2.

[0090] The length W1 of the first fin pattern NS1 may be measured, for example, at the midpoint between the opposing upper surface NS1_US and lower surface NS1_BS of each of the first fin pattern NS1 in the third direction D3.

[0091] For example, according to the shapes of the first source / drain groove 150R and the second source / drain groove 250R, the length W1 of the first pattern NS1 may be different from the length W2 of the second pattern NS2.

[0092] In one or more embodiments, the thicknesses of the first gate spacer 140 and the second gate spacer 240 in the first direction D1 may vary according to the order in which the first source / drain groove 150R and the second source / drain groove 250R are formed. In this case, according to the thicknesses of the first gate spacer 140 and the second gate spacer 240 in the first direction D1, the length W1 of the first pattern NS1 may be different from the length W2 of the second pattern NS2.

[0093] The first gate electrode 120 and the second gate electrode 220 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrode 120 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), Al, copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but the embodiments are not limited thereto. The conductive metal oxides and the conductive metal oxynitrides may include the oxidized forms of the foregoing materials, but the embodiments are not limited thereto.

[0094] The first gate electrode 120 may be disposed on both sides of the first source / drain pattern 150 to be described later. The first gate structure GS1 may be disposed on both sides of the first source / drain pattern 150 in the first direction D1.

[0095] For example, both of the two first gate electrodes 120 on both sides of each of the first source / drain patterns 150 may be normal gate electrodes serving as the gates of the transistors. Alternatively, one of the two first gate electrodes 120 may be a normal gate electrode, and the other first gate electrode 120 may be a dummy gate electrode.

[0096] The second gate electrode 220 may be disposed on both sides of the second source / drain pattern 250. The second gate structure GS2 may be disposed on both sides of the second source / drain pattern 250 in the first direction D1.

[0097] For example, both of the two second gate electrodes 220 on both sides of each of the second source / drain patterns 250 may be normal gate electrodes serving as gates of transistors. Alternatively, one of the two second gate electrodes 220 may be a normal gate electrode, and the other second gate electrode 220 may be a dummy gate electrode.

[0098] The first gate insulating film 130 may extend along the upper surface of the field insulating film 105 and the upper surface BP1_US of the first lower pattern BP1. The first gate insulating film 130 may surround a plurality of first fin patterns NS1. The first gate insulating film 130 may be disposed along the outer periphery of the first fin pattern NS1. The first gate electrode 120 may be disposed on the first gate insulating film 130. The first gate insulating film 130 may be disposed between the first gate electrode 120 and the first fin pattern NS1. A portion of the first gate insulating film 130 may be disposed between each pair of first fin patterns NS1 in the third direction D3, and between the first lower pattern BP1 and the lowermost first fin pattern NS1 among the first fin patterns NS1.

[0099] The first gate insulating film 130 may include a first gate interface insulating film 131 and a first gate high-k insulating film 132. The first gate high-k insulating film 132 may be disposed between the first gate interface insulating film 131 and the first gate electrode 120.

[0100] Referring to Figure 5 , the first gate interface insulating film 131 may be disposed between the first fin pattern NS1 and the first gate high-k insulating film 132.

[0101] The first gate interface insulating film 131 may extend along the upper surface BP1_US of the first lower pattern BP1. The first gate interface insulating film 131 may be disposed along the outer periphery of the first fin pattern NS1.

[0102] The first gate interface insulating film 131 may not extend along the upper surface of the field insulating film 105. The first gate interface insulating film 131 may not extend along the boundary between the first inner spacer 135 and the first gate high-k insulating film 132. The first gate interface insulating film 131 may not extend along the sidewall of the first gate spacer 140 to be described later.

[0103] However, depending on how the first gate interface insulating film 131 is formed, the first gate interface insulating film 131 may extend along the upper surface of the field insulating film 105 and along the sidewalls of the first gate spacer 140. The first gate interface insulating film 131 may extend along the boundary between the first inner spacer 135 and the first gate high-k insulating film 132.

[0104] The first gate high-k insulating film 132 may extend along the upper surface of the field insulating film 105 and the upper surface BP1_US of the first lower pattern BP1. The first gate high-k insulating film 132 may extend along the first inner spacer 135. The first gate high-k insulating film 132 may be disposed along the outer periphery of the first sheet pattern NS1. The first gate high-k insulating film 132 may extend along the sidewalls of the first gate spacer 140 which will be described later.

[0105] The description of the second gate insulating film 230 is similar to that of the first gate insulating film 130, and thus, the second gate insulating film 230 will be briefly described below.

[0106] The second gate electrode 220 may be disposed on the second gate insulating film 230. The second gate insulating film 230 may be disposed between the second gate electrode 220 and the second sheet pattern NS2.

[0107] The second gate insulating film 230 may include a second gate interface insulating film 231 and a second gate high-k insulating film 232. The second gate high-k insulating film 232 may be disposed between the second gate interface insulating film 231 and the second gate electrode 220.

[0108] The first gate interface insulating film 131 and the second gate interface insulating film 231 may include at least one of silicon oxide, silicon germanium oxide, and germanium oxide. The first gate interface insulating film 131 and the second gate interface insulating film 231 may further include at least one of boron (B), P, C, As, Sb, and bismuth (Bi), but the embodiments are not limited thereto.

[0109] The first gate high-k insulating film 132 and the second gate high-k insulating film 232 may include at least one of, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0110] A semiconductor device according to one or more embodiments may include a negative capacitance (NC) field effect transistor (FET) utilizing a negative capacitor. For example, the first gate high-k insulating film 132 and / or the second gate high-k insulating film 232 may include a ferroelectric material film having ferroelectric properties. In another example, the first gate high-k insulating film 132 and / or the second gate high-k insulating film 232 may include both a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0111] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series, and each of the capacitors has a positive capacitance, the total capacitance of the capacitors is reduced compared to the capacitance of each of the capacitors. Conversely, if at least one of the capacitors has a negative capacitance, the total capacitance of the capacitors may have a positive value and may be greater than the absolute value of the capacitance of each of the capacitors.

[0112] When a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series, the total capacitance of the ferroelectric material film and the paraelectric material film may increase. Utilizing this capacitance increase, a transistor including the ferroelectric material film may have a subthreshold swing (SS) of 60 millivolts per decade (mV / decade) or less at room temperature.

[0113] The ferroelectric material film may have ferroelectric properties. For example, the ferroelectric material film may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanate. Hafnium zirconium oxide may be, for example, a material obtained by doping hafnium oxide with zirconium (Zr). Optionally, hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

[0114] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), Si, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), Ge, scandium (Sc), strontium (Sr), and Sn. The type of dopant included in the ferroelectric material film may vary according to the type of ferroelectric material included in the ferroelectric material film.

[0115] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include at least one of Gd, Si, Zr, Al, and Y.

[0116] In an example where the dopant is Al, the ferroelectric material film may contain 3 to 8 atomic percent (at%) of Al. The ratio of the dopant may be the ratio of Al to the sum of Hf and Al.

[0117] In an example where the dopant is Si, the ferroelectric material film may contain 2 to 10 at% of Si. In an example where the dopant is Y, the ferroelectric material film may contain 2 to 10 at% of Y. If the dopant is Gd, the ferroelectric material film may contain 1 to 7 at% of Gd. In an example where the dopant is Zr, the ferroelectric material film may contain 50 to 80 at% of Zr.

[0118] The paraelectric material film may have paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide and high-k metal oxides. The high-k metal oxides may include at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but the embodiments are not limited thereto.

[0119] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, if both the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of hafnium oxide in the ferroelectric material film may be different from the crystal structure of hafnium oxide in the paraelectric material film.

[0120] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. For example, the thickness of the ferroelectric material film may be 0.5 to 10 nanometers (nm), but the embodiments are not limited thereto. Since the critical thickness for exhibiting ferroelectric properties may vary from one ferroelectric material to another, the thickness of the ferroelectric material film may vary depending on the material of the ferroelectric material film.

[0121] For example, the first gate high-k insulating film 132 and / or the second gate high-k insulating film 232 may include a single ferroelectric material film. Alternatively, the first gate high-k insulating film 132 and / or the second gate high-k insulating film 232 may include a plurality of ferroelectric material films spaced apart from each other. The first gate high-k insulating film 132 and / or the second gate high-k insulating film 232 may have a layered film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked on each other.

[0122] The first gate spacer 140 may be disposed on the sidewalls of the first gate electrode 120. The first gate spacer 140 may not be disposed between the first lower pattern BP1 and the lowermost first sheet pattern NS1 among the first sheet patterns NS1, and may not be disposed between each pair of the first sheet patterns NS1 adjacent to each other in the third direction D3.

[0123] The second gate spacer 240 may be disposed on the sidewalls of the second gate electrode 220. The second gate spacer 240 may not be disposed between the second lower pattern BP2 and the lowermost second sheet pattern NS2 among the second sheet patterns NS2, and may not be disposed between each pair of the second sheet patterns NS2 adjacent to each other in the third direction D3.

[0124] The first gate spacer 140 and the second gate spacer 240 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), SiOC, and combinations thereof. The first gate spacer 140 and the second gate spacer 240 are shown as a single film, but the embodiments are not limited thereto.

[0125] The first gate capping pattern 145 may be disposed on the first gate electrode 120 and the first gate spacer 140. Similarly, the second gate capping pattern 245 may be disposed on the second gate electrode 220 and the second gate spacer 240. The upper surfaces of the first gate capping pattern 145 and the second gate capping pattern 245 may be disposed in the same plane as the upper surface of the first interlayer insulating film 190.

[0126] Optionally, the first gate capping pattern 145 may be disposed between the first gate spacers 140, and the second gate capping pattern 245 may be disposed between the second gate spacers 240.

[0127] The first gate capping pattern 145 and the second gate capping pattern 245 may include at least one of, for example, SiN, SiON, silicon carbonitride (SiCN), SiOCN, and combinations thereof. The first gate capping pattern 145 and the second gate capping pattern 245 may include a material having an etching selectivity with respect to the first interlayer insulating film 190.

[0128] Optionally, the first gate capping pattern 145 may not be disposed on the first gate electrode 120. The second gate capping pattern 245 may not be disposed on the second gate electrode 220.

[0129] The first source / drain pattern 150 may be disposed on the first active pattern AP1. The first source / drain pattern 150 may be disposed on the first lower pattern BP1. The first source / drain pattern 150 may be connected to the first sheet pattern NS1. The first source / drain pattern 150 may contact the first sheet pattern NS1.

[0130] The first source / drain pattern 150 may be disposed on the side of the first gate structure GS1. The first source / drain pattern 150 may be disposed between each pair of adjacent first gate structures GS1 in the first direction D1. For example, the first source / drain pattern 150 may be disposed on both sides of the first gate structure GS1. Optionally, the first source / drain pattern 150 may be disposed on one side of each of the first gate structures GS1, rather than on the other side.

[0131] The second source / drain pattern 250 may be disposed on the second active pattern AP2. The second source / drain pattern 250 may be disposed on the second lower pattern BP2. The second source / drain pattern 250 may be connected to the second sheet pattern NS2. The second source / drain pattern 250 may contact the second sheet pattern NS2.

[0132] The second source / drain pattern 250 may be disposed on the side surfaces of the second gate structure GS2. The second source / drain pattern 250 may be disposed between each pair of adjacent second gate structures GS2 in the first direction D1. For example, the second source / drain pattern 250 may be disposed on both sides of the second gate structure GS2. Optionally, the second source / drain pattern 250 may be disposed on one side of each of the second gate structures GS2 and not on the other side.

[0133] The first source / drain pattern 150 and the second source / drain pattern 250 may be included as the source / drain of a transistor that uses the first sheet pattern NS1 and the second sheet pattern NS2 as the channel region.

[0134] The first source / drain pattern 150 may be disposed within the first source / drain recess 150R. The second source / drain pattern 250 may be disposed within the second source / drain recess 250R. The first source / drain recess 150R and the second source / drain recess 250R extend in the third direction D3. The first source / drain recess 150R may be defined between each pair of adjacent first gate structures GS1 in the first direction D1. The second source / drain recess 250R may be defined between each pair of adjacent second gate structures GS2 in the second direction D2.

[0135] The sidewall of the second source / drain recess 250R may have a wavy form. The second source / drain recess 250R may include a plurality of width expansion regions ( Figure 24 "250R_ER"). Each of the width expansion regions 250R_ER may have a portion where its width in the first direction D1 increases as the distance from the upper surface BP2_US of the second lower pattern BP2 increases and a portion where its width in the first direction D1 decreases as the distance from the upper surface BP2_US of the second lower pattern BP2 increases.

[0136] Unlike the sidewall of the second source / drain recess 250R, the sidewall of the first source / drain recess 150R may not have a wavy form. Optionally, the sidewall of the second source / drain recess 250R may not have a wavy form. The sidewall of the first source / drain recess 150R may have a wavy form.

[0137] The lower surface of the first source / drain groove 150R may be defined by the first lower pattern BP1. The lower surface of the second source / drain groove 250R may be defined by the second lower pattern BP2.

[0138] The first source / drain pattern 150 and the second source / drain pattern 250 may include an epitaxial pattern. The first source / drain pattern 150 and the second source / drain pattern 250 may include a semiconductor material.

[0139] The first source / drain pattern 150 and the second source / drain pattern 250 may include, for example, an elemental semiconductor material (such as Si or Ge). Additionally, the first source / drain pattern 150 and the second source / drain pattern 250 may include a binary compound, a ternary compound, or a compound doped with a Group IV element that contains at least two of C, Si, Ge, and Sn. For example, the first source / drain pattern 150 and the second source / drain pattern 250 may include materials such as Si, SiGe, or silicon carbide (SiC), but the embodiments are not limited thereto.

[0140] The first source / drain pattern 150 and the second source / drain pattern 250 may include impurities doped into the semiconductor material. The first source / drain pattern 150 may include n-type impurities. For example, the n-type impurities may include at least one of P, As, Sb, and Bi. The second source / drain pattern 250 may include p-type impurities. For example, the p-type impurities may include at least one of B and Ga.

[0141] The first source / drain pattern 150 and the second source / drain pattern 250 are shown as a single film, but the embodiments are not limited thereto.

[0142] The first inner spacer 135 may be disposed between each pair of first sheet patterns NS1 adjacent in the third direction D3, and between the lowermost first sheet pattern NS1 in the first sheet patterns NS1 and the first lower pattern BP1. The first inner spacer 135 may be disposed between the first source / drain pattern 150 and the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1).

[0143] For example, the first inner spacer 135 may contact the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1). The first inner spacer 135 may contact the first gate insulating film 130 included in the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1). The first inner spacer 135 may contact the first source / drain pattern 150.

[0144] Each of the first inner spacers 135 may include a first surface 135US and a second surface 135BS, the first surface 135US and the second surface 135BS facing each other in a third direction D3, and each of the first inner spacers 135 may further include a first sidewall 135SW1 and a second sidewall 135SW2, the first sidewall 135SW1 and the second sidewall 135SW2 connecting the first surface 135US and the second surface 135BS. The first sidewall 135SW1 of the first inner spacer 135 may face the second sidewall 135SW2 of the first inner spacer 135 in a first direction D1.

[0145] The first surface 135US and the second surface 135BS of the first inner spacer 135 may contact the first sheet pattern NS1 or the first lower pattern BP1. The first sidewall 135SW1 of the first inner spacer 135 may face the first source / drain pattern 150. The first sidewall 135SW1 of the first inner spacer 135 may be a boundary between the first inner spacer 135 and the first source / drain pattern 150. The second sidewall 135SW2 of the first inner spacer 135 may face the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1). The second sidewall 135SW2 of the first inner spacer 135 may be a boundary between the first inner spacer 135 and the first inner gates (INT1_GS1, INT2_GS1, and INT3_GS1).

[0146] In a cross-sectional view, the first sidewall 135SW1 of the first inner spacer 135 may be flat, and the second sidewall 135SW2 of the first inner spacer 135 may have a concave shape. However, the embodiments are not limited thereto.

[0147] The second inner spacers 235 may be disposed between each pair of second sheet patterns NS2 adjacent in the third direction D3, and disposed between the lowermost second sheet pattern NS2 in the second sheet patterns NS2 and the second lower pattern BP2. The second inner spacers 235 may be disposed between the second source / drain patterns 250 and the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2).

[0148] For example, the second inner spacers 235 may contact the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2). The second inner spacers 235 may contact the second gate insulating films 230 included in the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2). The second inner spacers 235 may contact the second source / drain patterns 250.

[0149] Each of the second inner spacers 235 may include a first surface 235US and a second surface 235BS, the first surface 235US and the second surface 235BS facing each other in a third direction D3, and each of the second inner spacers 235 may further include a first sidewall 235SW1 and a second sidewall 235SW2, the first sidewall 235SW1 and the second sidewall 235SW2 connecting the first surface 235US and the second surface 235BS. The first sidewall 235SW1 of the second inner spacer 235 may face the second sidewall 235SW2 of the second inner spacer 235 in a first direction D1.

[0150] The first surface 235US and the second surface 235BS of the second inner spacer 235 may contact the second sheet pattern NS2 or the second lower pattern BP2. The first sidewall 235SW1 of the second inner spacer 235 may face the second source / drain pattern 250. The first sidewall 235SW1 of the second inner spacer 235 may be a boundary between the second inner spacer 235 and the second source / drain pattern 250. The second sidewall 235SW2 of the second inner spacer 235 may face the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2). The second sidewall 235SW2 of the second inner spacer 235 may be a boundary between the second inner spacer 235 and the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2).

[0151] In a cross-sectional view, the first sidewall 235SW1 of the second inner spacer 235 may have a concave shape, and the second sidewall 235SW2 of the second inner spacer 235 may have a concave shape, but the embodiments are not limited thereto.

[0152] For example, the thickness t1 of the first inner spacer 135 in the first direction D1 may be smaller than the thickness t2 of the second inner spacer 235 in the first direction D1. Alternatively, the thickness t1 of the first inner spacer 135 may be the same as the thickness t2 of the second inner spacer 235. For example, the thickness t1 of the first inner spacer 135 may be measured with respect to the midpoint between the first surface 135US and the second surface 135BS of each of the first inner spacers 135.

[0153] The first inner spacer 135 and the second inner spacer 235 may include an insulating material. For example, the first inner spacer 135 and the second inner spacer 235 may include silicon oxide.

[0154] The first nitrogen accumulation region 135N1 may extend along the boundary between the first source / drain pattern 150 and the first inner spacer 135. The first nitrogen accumulation region 135N1 may extend along the boundary between the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1) and the first sheet pattern NS1. The first nitrogen accumulation region 135N1 may extend along the boundary between the first lower pattern BP1 and the third sub-inner gate INT3_GS1. In Figure 2 and Figure 5 the first nitrogen accumulation region 135N1 may be formed around the outer periphery of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1).

[0155] The first nitrogen accumulation region 135N1 may include a vertical portion 135N1_V and a horizontal portion 135N1_L.

[0156] The vertical portion 135N1_V of the first nitrogen accumulation region 135N1 may extend along the boundary between the first source / drain pattern 150 and the first inner spacer 135. For example, the vertical portion 135N1_V of the first nitrogen accumulation region 135N1 may extend along the first sidewall 135SW1 of the first inner spacer 135. The vertical portion 135N1_V of the first nitrogen accumulation region 135N1 may extend along the sidewall INT1_SW of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1).

[0157] The horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may extend along the boundary between the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1) and the first sheet pattern NS1. The horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may extend along the boundary between the first lower pattern BP1 and the third sub-inner gate INT3_GS1. The horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may extend along the first surface INT1_US of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1) and the first surface 135US of the first inner spacer 135. The horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may extend along the second surface INT1_BS of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1) and the second surface 135BS of the first inner spacer 135.

[0158] The vertical portion 135N1_V of the first nitrogen accumulation region 135N1 may be formed within the first source / drain pattern 150. The vertical portion 135N1_V of the first nitrogen accumulation region 135N1 may correspond to the region within the first source / drain pattern 150 where N is accumulated. The horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may be formed within the first spacer pattern NS1. The horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may correspond to the region within the first spacer pattern NS1 where N is accumulated. The horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may be formed within the first bottom pattern BP1.

[0159] The region where N is accumulated may represent a region having a higher concentration of N (per cubic meter ( / cm 3 )) than the surrounding regions, but the N concentration may not be zero in other regions.

[0160] In Figure 5 , the horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 is shown as being continuously formed along the surface of the first spacer pattern NS1, but the embodiment is not limited thereto. For example, the horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may include both a region having a higher concentration of N accumulated and a region having a lower concentration of N accumulated. In another example, the horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 may include both a region having N accumulated and a region having no N accumulated. The region having no N accumulated may not necessarily indicate that the N concentration is 0, and may appear to have no N due to the detection limit of the detection device.

[0161] For example, the N concentration may be higher in the vertical portion 135N1_V of the first nitrogen accumulation region 135N1 than in the horizontal portion 135N1_L of the first nitrogen accumulation region 135N1. In Figure 7 , the absence of an N peak within the first inner spacer 135 does not necessarily mean that there is no N within the first inner spacer 135.

[0162] The N accumulated on the surface of the first spacer pattern NS1 may be used as a fixed charge. Since the first spacer pattern NS1 is used as the channel region of the NMOS transistor, the N constructed on the surface of the first spacer pattern NS1 may adjust the threshold voltage of the transistor and may enhance the performance of the NMOS transistor.

[0163] In Figure 3 and Figure 6In [the figure], the nitrogen accumulation region may not be formed around the outer periphery of the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2). In other words, the nitrogen accumulation region may not be formed along the boundary between the second source / drain pattern 250 and the second inner spacer 235. The nitrogen accumulation region may not be formed along the boundary between the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2) and the second sheet pattern NS2.

[0164] If N accumulates on the surface of the second sheet pattern NS2, the accumulated N may deteriorate the operating characteristics of the PMOS transistor. However, since no N accumulates at the boundary between the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2) and the second sheet pattern NS2, the performance degradation of the PMOS transistor can be prevented.

[0165] The source / drain etch stop film 185 may be disposed on the sidewalls of the first gate spacer 140 and on the upper surface of the first source / drain pattern 150. The source / drain etch stop film 185 may be disposed on the sidewalls of the second gate spacer 240 and on the upper surface of the second source / drain pattern 250. The source / drain etch stop film 185 may be disposed on the upper surface of the field insulating film 105.

[0166] The source / drain etch stop film 185 may include a material having an etch selectivity with respect to the first interlayer insulating film 190, which will be described later. The source / drain etch stop film 185 may include at least one of, for example, SiN, SiON, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof.

[0167] The first interlayer insulating film 190 may be disposed on the source / drain etch stop film 185. The first interlayer insulating film 190 may be disposed on the first source / drain pattern 150 and the second source / drain pattern 250. The first interlayer insulating film 190 may not cover the upper surfaces of the first gate capping pattern 145 and the second gate capping pattern 245.

[0168] The first interlayer insulating film 190 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k materials. The low-k materials may include, for example, tetraethyl orthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), Tonen SilaZen (TOSZ), fluorided silicate glass (FSG), polyimide nanofoam (such as, polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but the embodiments are not limited thereto.

[0169] The first source / drain contact 180 may be disposed on the first source / drain pattern 150. The first source / drain contact 180 may be connected to the first source / drain pattern 150. The first source / drain contact 180 may be connected to the first source / drain pattern 150 through the first interlayer insulating film 190 and the source / drain etch stop film 185.

[0170] The second source / drain contact 280 may be disposed on the second source / drain pattern 250. The second source / drain contact 280 may be connected to the second source / drain pattern 250.

[0171] The first metal silicide layer (or, the first metal silicide film) 155 may further be disposed between the first source / drain contact 180 and the first source / drain pattern 150. The second metal silicide layer (or, the second metal silicide film) 255 may further be disposed between the second source / drain contact 280 and the second source / drain pattern 250.

[0172] The first source / drain contact 180 and the second source / drain contact 280 are shown as a single film, but the embodiments are not limited thereto. The first source / drain contact 180 and the second source / drain contact 280 may include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material. The 2D material may be a metal material and / or a semiconductor material. The 2D material may include 2D allotropes or compounds, for example, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), but the embodiments are not limited thereto. That is, these 2D materials are merely examples, and thus, the embodiments are not limited thereto.

[0173] The first metal silicide film 155 and the second metal silicide film 255 may include metal silicide.

[0174] The second interlayer insulating film 191 may be disposed on the first interlayer insulating film 190. The second interlayer insulating film 191 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0175] The wiring structure 205 may be disposed within the second interlayer insulating film 191. The wiring structure 205 may be connected to both the first source / drain contact 180 and the second source / drain contact 280. The wiring structure 205 may include a wiring line 207 and a wiring via 206.

[0176] The wiring line 207 and the wiring via 206 are shown as being different from each other, but the embodiments are not limited thereto. That is, for example, the wiring via 206 may be formed, and the wiring line 207 may be formed. In another example, the wiring via 206 and the wiring line 207 may be formed simultaneously.

[0177] The wiring line 207 and the wiring via 206 are shown as a single film, but the embodiments are not limited thereto. The wiring line 207 and the wiring via 206 may include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material.

[0178] Figure 8 is a view showing a semiconductor device according to one or more embodiments. Figure 9 is a view showing along Figure 8 "Scan line 1" and "Scan line 2" of nitrogen (N) concentration. For convenience, the differences from the embodiments already described with reference to Figures 1 to 7 will be described hereinafter, and the repeated description of the same or similar aspects above may be omitted. Figure 8 and Figure 9 embodiments, and the repeated description of the same or similar aspects above may be omitted.

[0179] Specifically, Figure 8 is an enlarged cross-sectional view of an example corresponding to part P of Figure 2 , and Figure 9 is a graph showing the N concentration along Figure 8 "Scan line 1" and "Scan line 2".

[0180] Referring to Figure 8 and Figure 9 , according to one or more embodiments, the semiconductor device may further include a second nitrogen accumulation region 135N2, and the second nitrogen accumulation region 135N2 is disposed within the first spacer 135.

[0181] The second nitrogen accumulation region 135N2 may be a region within the first inner spacer 135 where N is accumulated. The second nitrogen accumulation region 135N2 may extend along the sidewall INT1_SW of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1). The second nitrogen accumulation region 135N2 may have a bracket shape (e.g., a "[" or "(" shape), but the embodiments are not limited thereto.

[0182] The second nitrogen accumulation region 135N2 may be spaced apart from the first nitrogen accumulation region 135N1. The second nitrogen accumulation region 135N2 may be disposed within the region defined by the first nitrogen accumulation region 135N1.

[0183] The second nitrogen accumulation region 135N2 may be spaced apart from the horizontal portion 135N1_L of the first nitrogen accumulation region 135N1 in the third direction D3. The second nitrogen accumulation region 135N2 may be spaced apart from the vertical portion 135N1_V of the first nitrogen accumulation region 135N1 in the first direction D1. The second nitrogen accumulation region 135N2 may be closer to the first gate electrode 120 than the vertical portion 135N1_V of the first nitrogen accumulation region 135N1.

[0184] In Figure 9 it is shown that the N concentration is higher in the vertical portion 135N1_V of the first nitrogen accumulation region 135N1 than in the second nitrogen accumulation region 135N2, but the embodiments are not limited thereto.

[0185] The first inner spacer 135 may include a first sub-spacer pattern 135A and a second sub-spacer pattern 135B. The first sub-spacer pattern 135A may be disposed between the second sub-spacer pattern 135B and the first source / drain pattern 150. The first sub-spacer pattern 135A and the second sub-spacer pattern 135B may be divided by the second nitrogen accumulation region 135N2.

[0186] The first sub-spacer pattern 135A may include silicon oxide. The second sub-spacer pattern 135B may also include silicon oxide, but the embodiments are not limited thereto.

[0187] Figure 10 and Figure 11 are diagrams showing semiconductor devices according to one or more embodiments. For convenience, the differences from the embodiments already described with reference to Figures 1 to 9 will be described hereinafter, and the repeated description of the same or similar aspects above may be omitted. Figure 10 and Figure 11 The embodiments of

[0188] Specifically, Figure 10 and Figure 11 may correspond to Figure 2An enlarged cross-sectional view of an example of part P.

[0189] Referring to Figure 10 , the first nitrogen accumulation region 135N1 may not be disposed along the boundary between the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1) and the first sheet pattern NS1.

[0190] The first nitrogen accumulation region 135N1 may not be formed along the first surface INT1_US of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1), and may not be formed along the first surface 135US of the first inner spacer 135. The first nitrogen accumulation region NS1 may not be formed along the second surface INT1_BS of the first inner gate (INT1_GS1, INT2_GS1, and INT3_GS1), and may not be formed along the second surface 135BS of the first inner spacer 135.

[0191] The first nitrogen accumulation region 135N1 may include a vertical portion 135N1_V and may not include a horizontal portion (e.g., horizontal portion 135N1_L). The second nitrogen accumulation region 135N2 may be disposed within the first inner spacer 135.

[0192] Referring to Figure 11 , the first nitrogen accumulation region 135N1 may not be disposed along the boundary between the first source / drain pattern 150 and the first inner spacer 135.

[0193] The first nitrogen accumulation region 135N1 may not be formed along the first sidewall 135SW1 of the first inner spacer 135.

[0194] The first nitrogen accumulation region 135N1 may include a horizontal portion 135N1_L and may not include a vertical portion (e.g., vertical portion 135N1_V). The second nitrogen accumulation region 135N2 may be disposed within the first inner spacer 135.

[0195] Figure 12 and Figure 13 are diagrams showing a semiconductor device according to one or more embodiments. For convenience, the differences from the embodiments already described with reference to Figures 1 to 11 will be described below, and repeated descriptions of the same or similar aspects above may be omitted. Figure 12 and Figure 13 of the embodiments, and repeated descriptions of the same or similar aspects above may be omitted.

[0196] Specifically, Figure 12 and Figure 13 correspond to Figure 3 An enlarged cross-sectional view of an example of part Q.

[0197] Referring to Figure 12and Figure 13 According to one or more embodiments, a semiconductor device may further include a fourth nitrogen accumulation region 235N2 disposed within the second inner spacer 235.

[0198] The fourth nitrogen accumulation region 235N2 may be a region within the second inner spacer 235 where N is accumulated. The fourth nitrogen accumulation region 235N2 may extend along the sidewall INT2_SW of the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2). The fourth nitrogen accumulation region 235N2 may have a bracket shape (e.g., a "[" or "(" shape), but the embodiments are not limited thereto.

[0199] The fourth nitrogen accumulation region 235N2 may be spaced apart from the second source / drain pattern 250. The fourth nitrogen accumulation region 235N2 may be spaced apart from the second sheet pattern NS2 in the third direction D3.

[0200] The second inner spacer 235 may include a third sub-spacer pattern 235A and a fourth sub-spacer pattern 235B. The third sub-spacer pattern 235A may be disposed between the fourth sub-spacer pattern 235B and the second source / drain pattern 250. The third sub-spacer pattern 235A and the fourth sub-spacer pattern 235B may be divided by the fourth nitrogen accumulation region 235N2.

[0201] The third sub-spacer pattern 235A may include silicon oxide. The fourth sub-spacer pattern 235B may also include silicon oxide, but the embodiments are not limited thereto.

[0202] In Figure 12 , the nitrogen accumulation region may not be disposed along the boundary between the second source / drain pattern 250 and the second inner spacer 235. The nitrogen accumulation region may not be formed along the first sidewall 235SW1 of the second inner spacer 235.

[0203] In Figure 13 , according to one or more embodiments, a semiconductor device may further include a third nitrogen accumulation region 235N1 disposed along the boundary between the second source / drain pattern 250 and the second inner spacer 235.

[0204] The third nitrogen accumulation region 235N1 may extend along the first sidewall 235SW1 of the second inner spacer 235. The third nitrogen accumulation region 235N1 may extend along the sidewall INT2_SW of the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2).

[0205] The third nitrogen accumulation region 235N1 may be formed within the second source / drain pattern 250. The third nitrogen accumulation region 235N1 may be a region within the second source / drain pattern 250 where N is accumulated.

[0206] The third nitrogen accumulation region 235N1 may not be formed along the first surface INT2_US of the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2), and may not be formed along the first surface 235US of the second inner spacer 235. The third nitrogen accumulation region 235N1 may not be formed along the second surface INT2_BS of the second inner gate 235, and may not be formed along the second surface 235BS of the second inner spacer 235. In one embodiment, the third nitrogen accumulation region 235N1 may extend along the boundary between the second source / drain pattern 250 and the second inner spacer 235 and along the boundary between the second inner gate (INT1_GS2, INT2_GS2, and INT3_GS2) and the second sheet pattern NS2.

[0207] The fourth nitrogen accumulation region 235N2 may be spaced apart from the third nitrogen accumulation region 235N1 in the first direction D1. The fourth nitrogen accumulation region 235N2 may be closer to the second gate electrode 220 than the third nitrogen accumulation region 235N1.

[0208] Figure 14 is a diagram showing a semiconductor device according to one or more embodiments. Figure 15 is a diagram showing the nitrogen (N) concentration along Figure 14 "scan line 1" and "scan line 2" according to one or more embodiments. For convenience, the differences from the embodiments already described with reference to Figures 1 to 13 will be mainly described hereinafter, and the repeated description of the same or similar aspects above may be omitted. Figure 14 and Figure 15 embodiments, and the repeated description of the same or similar aspects above may be omitted.

[0209] Specifically, Figure 14 is an enlarged cross-sectional view of an example of a portion P that may correspond to Figure 2 and Figure 15 is a graph showing the N concentration along Figure 14 "scan line 1" and "scan line 2".

[0210] The following description of the first inner spacer 135 may be directly applicable to Figure 12 and Figure 13 the second inner spacer 235.

[0211] Referring to Figure 14 and Figure 15 , the first inner spacer 135 may further include a fifth sub-spacer pattern 135C.

[0212] The fifth sub-spacer pattern 135C may be disposed between the first sub-spacer pattern 135A and the second sub-spacer pattern 135B. The first sub-spacer pattern 135A may be disposed between the fifth sub-spacer pattern 135C and the first source / drain pattern 150. The fifth sub-spacer pattern 135C may separate the first sub-spacer pattern 135A and the second sub-spacer pattern 135B.

[0213] The fifth sub-spacer pattern 135C may include a material different from that of the first sub-spacer pattern 135A and the second sub-spacer pattern 135B. The fifth sub-spacer pattern 135C may include, for example, polysilicon.

[0214] When the second nitrogen accumulation region 135N2 is disposed within the first inner spacer 135, the second nitrogen accumulation region 135N2 may be disposed within the fifth sub-spacer pattern 135C. The second nitrogen accumulation region 135N2 may be a region where N is accumulated within the fifth sub-spacer pattern 135C.

[0215] For example, the second nitrogen accumulation region 135N2 may extend along the boundary between the first sub-spacer pattern 135A and the fifth sub-spacer pattern 135C. If the thickness of the fifth sub-spacer pattern 135C is sufficient, the second nitrogen accumulation region 135N2 may be formed closer to the boundary between the first sub-spacer pattern 135A and the fifth sub-spacer pattern 135C than the boundary between the third sub-spacer pattern 135B and the fifth sub-spacer pattern 135C.

[0216] Figure 16 and Figure 17 are diagrams showing a semiconductor device according to one or more embodiments. Figure 18 and Figure 19 are diagrams showing a semiconductor device according to one or more embodiments. Figure 20 is a diagram showing a semiconductor device according to one or more embodiments. For convenience, the embodiments will be described hereinafter focusing on the differences from the embodiments already described with reference to Figures 1 to 15 and the repeated description of the same or similar aspects above may be omitted. Figures 16 to 20 of the embodiments, and the repeated description of the same or similar aspects above may be omitted.

[0217] Specifically, Figure 17 and Figure 19 are respectively enlarged cross-sectional views of examples of portions Q that may correspond to Figure 16 and Figure 18 of the embodiments.

[0218] Referring to Figure 16 and Figure 17 , the first sidewall 235SW1 of the second inner spacer 235 may be flat.

[0219] The second sidewall 235SW2 of the second inner spacer 235 is shown to have a concave shape, but the embodiment is not limited thereto.

[0220] Referring Figure 18 and Figure 19 , the first sidewall 235SW1 of the second inner spacer 235 may have a concave shape.

[0221] The second sidewall 235SW2 of the second inner spacer 235 may have a concave shape.

[0222] Referring Figure 20 , the second source / drain pattern 250 may contact the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2).

[0223] The second source / drain pattern 250 may contact the second gate insulating film 230 included in the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2). The second inner spacer 235 may not be disposed between the second source / drain pattern 250 and the second inner gates (INT1_GS2, INT2_GS2, and INT3_GS2).

[0224] Figures 21 to 39 is a diagram showing operations of a method of manufacturing a semiconductor device according to one or more embodiments.

[0225] Referring Figure 21 and Figure 22 , a first lower pattern BP1 and an upper pattern structure U_AP may be formed on the substrate 100.

[0226] A second lower pattern BP2 and an upper pattern structure U_AP may be formed on the substrate 100.

[0227] The first lower pattern BP1 and the second lower pattern BP2 may be extended in the first direction D1. The upper pattern structure U_AP may be disposed on both the first lower pattern BP1 and the second lower pattern BP2.

[0228] The upper pattern structure U_AP may include a sacrificial pattern SC_L and an active pattern ACT_L, and the sacrificial pattern SC_L and the active pattern ACT_L may be alternately stacked. The sacrificial pattern SC_L and the active pattern ACT_L may be alternately stacked on each of the first lower pattern BP1 and the second lower pattern BP2.

[0229] For example, the sacrificial pattern SC_L may include a SiGe film. The active pattern ACT_L may include a Si layer.

[0230] Thereafter, a first dummy gate structure extending in a second direction D2 may be formed on the first bottom pattern BP1 and the upper pattern structure U_AP. A second dummy gate structure extending in the second direction D2 may be formed on the second bottom pattern BP2 and the upper pattern structure U_AP.

[0231] The first dummy gate structure may include a first dummy gate insulating film 130p, a first dummy gate electrode 120p, and a first dummy gate capping film 120_HM. The second dummy gate structure may include a second dummy gate insulating film 230p, a second dummy gate electrode 220p, and a second dummy gate capping film 220_HM.

[0232] The first dummy gate insulating film 130p and the second dummy gate insulating film 230p may include, for example, silicon oxide, but the embodiments are not limited thereto. The first dummy gate electrode 120p and the second dummy gate electrode 220p may include, for example, polysilicon, but the embodiments are not limited thereto. The first dummy gate capping film 120_HM and the second dummy gate capping film 220_HM may include, for example, silicon nitride, but the embodiments are not limited thereto.

[0233] Referring Figure 23 and Figure 24 , a second front gate spacer 240p may be formed on sidewalls of the second dummy gate electrode 220p.

[0234] Using the second dummy gate electrode 220p and the second front gate spacer 240p as a mask, a second source / drain recess 250R may be formed in the upper pattern structure U_AP.

[0235] A portion of the second source / drain recess 250R may be formed in the second bottom pattern BP2. A lower surface of the second source / drain recess 250R may be defined by the second bottom pattern BP2.

[0236] As Figure 23 shown, after forming the second source / drain recess 250R, the sacrificial pattern SC_L may be additionally etched. Accordingly, a width expansion region 250R_ER of the second source / drain recess 250R may be formed.

[0237] The second source / drain recess 250R may include a plurality of width expansion regions 250R_ER. Sidewalls of the second source / drain recess 250R may have a wavy form. However, fabricating the second source / drain recess 250R including a plurality of width expansion regions 250R_ER is not limited to the above description.

[0238] As Figure 24 shown, subsequent steps of a method of manufacturing a semiconductor device according to one or more embodiments may be performed after the step of forming the width expansion region 250R_ER. Optionally, as Figure 23As shown, subsequent steps of a method of manufacturing a semiconductor device according to one or more embodiments may be performed after the step of forming the second source / drain recess 250R.

[0239] Referring to Figure 25 , a second source / drain pattern 250 may be formed on the second lower pattern BP2.

[0240] A second source / drain pattern 250 may be formed within the second source / drain recess 250R. The second source / drain pattern 250 may fill the second source / drain recess 250R.

[0241] Referring to Figure 26 , a first pre-gate spacer 140p may be formed on the sidewalls of the first dummy gate electrode 120p.

[0242] Using the first dummy gate electrode 120p and the first pre-gate spacer 140p as masks, a first source / drain recess 150R may be formed within the upper pattern structure U_AP.

[0243] A portion of the first source / drain recess 150R may be formed within the first lower pattern BP1. The lower surface of the first source / drain recess 150R may be defined by the first lower pattern BP1.

[0244] Referring to Figure 27 , a first source / drain pattern 150 may be formed on the first lower pattern BP1.

[0245] A first source / drain pattern 150 may be formed within the first source / drain recess 150R. The first source / drain pattern 150 may fill the first source / drain recess 150R.

[0246] Optionally, the first source / drain pattern 150 may be formed first, and then the second source / drain pattern 250 may be formed.

[0247] Referring to Figure 28 and Figure 29 , a source / drain etch stop film 185 and a first interlayer insulating film 190 may be formed on the first source / drain pattern 150 and the second source / drain pattern 250.

[0248] Thereafter, the upper surfaces of the first dummy gate electrode 120p and the second dummy gate electrode 220p may be exposed by removing a portion of the first interlayer insulating film 190 and by removing a portion of the source / drain etch stop film 185, the first dummy gate capping film 120_HM, and the second dummy gate capping film 220_HM. During the exposure of the upper surfaces of the first dummy gate electrode 120p and the second dummy gate electrode 220p, a first gate spacer 140 and a second gate spacer 240 may be formed.

[0249] will be hereinafter referred to Figures 30 to 37 to describe the formation of the first inner spacer ( Figure 2 "135"). For example, during the formation of the first inner spacer 135 in the first region I, the second inner spacer ( Figure 3 "235") may also be formed in the second region II. Optionally, the first inner spacer 124 may be formed in the first region I, and then, the second inner spacer 235 may be formed in the second region II using the method to be hereinafter referred to Figures 30 to 37 .

[0250] Referring to Figure 30 , by removing the first dummy gate insulating film 130p and the first dummy gate electrode 120p, the upper pattern structure U_AP can be exposed between the first gate spacers 140.

[0251] Thereafter, the first sheet pattern NS1 can be formed by removing the sacrificial pattern SC_L. The first sheet pattern NS1 can be connected to the first source / drain pattern 150. Thus, the first active pattern ( Figure 2 "AP1") including the first lower pattern BP1 and the first sheet pattern NS1 can be formed.

[0252] In addition, the gate trench 120t can be formed between the first gate spacers 140 by removing the sacrificial pattern SC_L. As a result of removing the sacrificial pattern SC_L, a part of the first source / drain pattern 150 can be exposed.

[0253] The gate trench 120t can include a plurality of inner gate trenches 120INT_t. The inner gate trenches 120INT_t can be defined between each pair of the first sheet patterns NS1 adjacent in the third direction D3 and between the first lower pattern BP1 and the lowermost first sheet pattern NS1 among the first sheet patterns NS1. In a cross-sectional view, the inner gate trenches 120INT_t can expose a part of the first source / drain pattern 150. Referring to Figure 32 , the inner gate trenches 120INT_t can be defined by the first sheet pattern NS1 and the first source / drain pattern 150. The inner gate trenches 120INT_t can be defined by the first lower pattern BP1, the first sheet pattern NS1, and the first source / drain pattern 150.

[0254] Referring to Figure 31 and Figure 32 , the first inner spacer material layer 135P1, the second inner spacer material layer 135P2, and the third inner spacer material layer 135P3 can be formed in the gate trench 120t.

[0255] The first inner spacer material layer 135P1 may extend along the sidewall of the first gate spacer 140 and the upper surface of the first interlayer insulating film 190. The first inner spacer material layer 135P1 may be formed along both the upper and lower surfaces of each of the first source / drain pattern 150 and the first fin pattern NS1 exposed by the inner gate trench 120INT_t.

[0256] The first inner spacer material layer 135P1 may be formed using, for example, atomic layer deposition (ALD). The first inner spacer material layer 135P1 may include, for example, silicon oxide.

[0257] Within the inner gate trench 120INT_t in which the first inner spacer material layer 135P1 is formed, the thickness of the first inner spacer material layer 135P1 may be smaller on the surface of the first fin pattern NS1 than on the first source / drain pattern 150 (in other words, the thickness of the first inner spacer material layer 135P1 on the surface of the first fin pattern NS1 may be smaller than the thickness of the first inner spacer material layer 135P1 on the first source / drain pattern 150). In a cross-sectional view, the length of the first fin pattern NS1 exposed by the inner gate trench 120INT_t may be greater than the length of the first source / drain pattern 150 exposed by the inner gate trench 120INT_t. Due to these geometric differences, the thickness of the first inner spacer material layer 135P1 on the surface of the first fin pattern NS1 may be different from the thickness of the first inner spacer material layer 135P1 on the first source / drain pattern 150.

[0258] Referring again to Figure 5 and Figure 6 , the length W1 of the first fin pattern NS1 in the first direction D1 may be greater than or equal to the length W2 of the second fin pattern NS2 in the first direction D1. In one or more embodiments, the length W1 of the first fin pattern NS1 is greater than the length W2 of the second fin pattern NS2. If the first inner spacer material layer 135P1 is formed simultaneously in both the first region I and the second region II, the first inner spacer material layer 135P1 may be thinner on the first fin pattern NS1 than on the second fin pattern NS2. Due to the lengths of the first fin pattern NS1 and the second fin pattern NS2, the thickness of the first inner spacer material layer 135P1 may be smaller on the first source / drain pattern 150 than on the second source / drain pattern 250.

[0259] A second inner spacer material layer 135P2 may be formed on the first inner spacer material layer 135P1. The second inner spacer material layer 135P2 may be formed along the contour of the first inner spacer material layer 135P1.

[0260] The second inner spacer material layer 135P2 may be formed, for example, by ALD. The second inner spacer material layer 135P2 may include, for example, polysilicon, but embodiments are not limited thereto. The second inner spacer material layer 135P2 may include one of, for example, polycrystalline SiGe, polycrystalline Ge, amorphous Si, amorphous SiGe, and amorphous Ge.

[0261] In the inner gate trench 120INT_t in which the second inner spacer material layer 135P2 is formed, the thickness of the second inner spacer material layer 135P2 may be smaller on the surface of the first sheet pattern NS1 than on the first source / drain pattern 150.

[0262] Similar to what has been described in connection with the first inner spacer material layer 135P1, if the second inner spacer material layer 135P2 is formed simultaneously in both the first region I and the second region II, the second inner spacer material layer 135P2 may be thinner on the first sheet pattern NS1 than on the second sheet pattern NS2. In addition, the thickness of the second inner spacer material layer 135P2 may be smaller on the first source / drain pattern 150 than on the second source / drain pattern 250.

[0263] A third inner spacer material layer 135P3 may be formed on the second inner spacer material layer 135P2. The third inner spacer material layer 135P3 may be formed along the contour of the second inner spacer material layer 135P2.

[0264] The third inner spacer material layer 135P3 may be formed, for example, by ALD. The third inner spacer material layer 135P3 may include, for example, an insulating material containing Si and N. For example, the third inner spacer material layer 135P3 may include at least one of SiN, SiON, SiOCN, and SiCN, but embodiments are not limited thereto.

[0265] Refer to Figures 33 to 35 , the second inner spacer material layer 135P2 and the third inner spacer material layer 135P3 may be oxidized using the oxidation process 50.

[0266] Therefore, the front inner spacer material layer 135P may be formed along the sidewall of the first gate spacer 140 and the upper surface of the first interlayer insulating film 190. The front inner spacer material layer 135P may be formed along both the upper and lower surfaces of each of the first source / drain pattern 150 and the first sheet pattern NS1 exposed by the inner gate trench 120INT_t. The front inner spacer material layer 135P may include Figure 31 and Figure 32 the first inner spacer material layer 135P1 of Figure 31 and Figure 32 the oxidized second inner spacer material layer 135P2 of Figure 31 and Figure 32The third inner spacer material layer 135P3 after oxidation.

[0267] Referring to Figure 34 , the second inner spacer material layer 135P2 and the third inner spacer material layer 135P3 can generally be oxidized.

[0268] Referring to Figure 35 , the third inner spacer material layer 135P3 can be oxidized, but part of the second inner spacer material layer 135P2 can be made non-oxidized. The non-oxidized portion of the second inner spacer material layer 135P2 can be retained within the front inner spacer material layer 135P as the residual spacer material layer 135P2_R.

[0269] Due to the geometric differences described above with reference to Figure 32 and Figure 33 , the thickness of the oxidized portion on the surface of the first fin pattern NS1 can be different from the thickness of the oxidized portion on the first source / drain pattern 150. The thickness of the oxidized portions of the second inner spacer material layer 135P2 and the third inner spacer material layer 135P3 on the surface of the first fin pattern NS1 can be less than the thickness of the oxidized portions of the second inner spacer material layer 135P2 and the third inner spacer material layer 135P3 on the first source / drain pattern 150.

[0270] When the second inner spacer material layer 135P2 and the third inner spacer material layer 135P3 are oxidized, the N included in the third inner spacer material layer 135P3 can diffuse toward the first fin pattern NS1 and the first source / drain pattern 150. Thus, the first nitrogen accumulation region 135N1 can be formed.

[0271] A second nitrogen accumulation region ( Figure 34 “135N2” of Figure 35 ) can be formed within the front inner spacer material layer 135P of Figure 8 or within the residual spacer material layer 135P2_R of

[0272] In Figure 31 and Figure 32In [the structure], the thickness of the first inner spacer material layer 135P1 may be smaller on the first pattern NS1 than on the second pattern NS2. The thickness of the second inner spacer material layer 135P2 may be smaller on the first pattern NS1 than on the second pattern NS2. The thicknesses of the first inner spacer material layer 135P1 and the second inner spacer material layer 135P2 may be larger on the second pattern NS2 than on the first pattern NS1. For example, when the second inner spacer material layer 135P2 and the third inner spacer material layer 135P3 are oxidized, N included in the third inner spacer material layer 135P3 may not diffuse toward the surface of the second pattern NS2. Optionally, during the oxidation of the second inner spacer material layer 135P2 and the third inner spacer material layer 135P3, a smaller amount of N may diffuse toward the surface of the second pattern NS2 than toward the surface of the first pattern NS1.

[0273] Referring to Figure 36 and Figure 37 , the first inner spacer 135 may be formed by removing a portion of the front inner spacer material layer 135P.

[0274] The first inner spacer 135 may be formed on the first source / drain pattern 150. The first inner spacer 135 may be formed between each pair of the first patterns NS1 adjacent in the third direction D3 and between the lowermost first pattern NS1 in the first patterns NS1 and the first lower pattern BP1. During the formation of the first inner spacer 135, portions of the front inner spacer material layer 135P on the upper and lower surfaces of each of the first patterns NS1 may be removed. During the formation of the first inner spacer 135, portions of the front inner spacer material layer 135P on the sidewalls of the first gate spacer 140 and on the upper surface of the first interlayer insulating film 190 may be removed.

[0275] Optionally, when removing portions of the front inner spacer material layer 135P on the upper and lower surfaces of each of the first patterns NS1, at least a portion of the first nitrogen accumulation region 135N1 formed within the first pattern NS1 may also be removed.

[0276] Referring to Figure 38 and Figure 39 , the first gate insulating film 130 may be formed along the sidewalls of the first gate spacer 140 and the upper surface of the first interlayer insulating film 190.

[0277] The first gate insulating film 130 may be formed along the upper and lower surfaces of each of the first inner spacer 135 and the first pattern NS1 exposed by the inner gate trench 120INT_t.

[0278] During the formation of the first gate insulating film 130, the first inner spacer 135 may be exposed to an oxidation process. If the first inner spacer 135 is continuously exposed to the oxidation process, then Figure 35 the residual spacer material layer 135P2_R of

[0279] may also be oxidized to become silicon oxide. Thereafter, referring again to Figure 2 , the first gate electrode 120 may be formed in the gate trench 120t and the inner gate trench 120INT_t. Additionally, the first gate cap pattern 145 may be formed.

[0280] Each embodiment provided in the above description does not exclude being associated with one or more features of another example or another embodiment that is also provided herein or not provided herein but consistent with the disclosure.

[0281] Although the disclosure has been specifically shown and described with reference to the disclosed embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A first active pattern, including a first lower pattern and a first fin pattern, the first fin pattern being spaced apart from the first lower pattern in a first direction; A first gate structure, including a first inner gate, the first inner gate being between the first lower pattern and the lowermost first fin pattern among the first fin patterns and between each pair of adjacent first fin patterns, the first inner gate extending in a second direction intersecting the first direction, wherein each of the first inner gates includes a first gate electrode and a first gate insulating film; A first source / drain pattern, on the first lower pattern and connected to the first fin pattern; A first inner spacer, between the first source / drain pattern and the first inner gate; and A first nitrogen accumulation region, within the first inner spacer, wherein each of the first inner gates has a first surface, a second surface, and sidewalls, the second surface being opposite to the first surface in the first direction, the sidewalls connecting the first surface and the second surface, and wherein the first nitrogen accumulation region extends along the sidewalls of the first inner gate.

2. The semiconductor device according to claim 1, further comprising: A second nitrogen accumulation region, extending along the boundary between the first inner spacer and the first source / drain pattern.

3. The semiconductor device according to claim 2, wherein, The second nitrogen accumulation region includes: A vertical portion, extending along the boundary between the first inner spacer and the first source / drain pattern; and A horizontal portion, extending along the first surface and the second surface of the first inner gate.

4. The semiconductor device according to claim 2, wherein, The second nitrogen accumulation region does not extend along each boundary between the first inner gate and the first fin pattern.

5. The semiconductor device according to claim 1, further comprising: A second nitrogen accumulation region, respectively extending along the boundary between the first inner gate and the first fin pattern, wherein the second nitrogen accumulation region does not extend along each boundary between the first inner spacer and the first source / drain pattern.

6. The semiconductor device according to claim 5, wherein, The first nitrogen accumulation region is spaced apart from the second nitrogen accumulation region in the first direction.

7. The semiconductor device according to claim 1, further comprising: A second active pattern, including a second lower pattern and a second fin pattern, the second fin pattern being spaced apart from the second lower pattern in the first direction; A second gate structure, including a second inner gate, the second inner gate being between the second lower pattern and the lowermost second fin pattern among the second fin patterns and between each pair of adjacent second fin patterns; A second source / drain pattern, on the second lower pattern and connected to the second fin pattern; and A second inner spacer, between the second source / drain pattern and the second inner gate, wherein no nitrogen accumulation region is formed along the outer periphery of the second inner gate.

8. The semiconductor device according to claim 7, wherein In a third direction intersecting the first direction and the second direction, the thickness of the first inner spacer is less than or equal to the thickness of the second inner spacer.

9. The semiconductor device according to claim 1, further comprising: A second active pattern, including a second lower pattern and a second fin pattern, the second fin pattern being spaced apart from the second lower pattern in the first direction; A second gate structure, including a second inner gate, the second inner gate being between the second lower pattern and the lowermost second fin pattern among the second fin patterns and between each pair of adjacent second fin patterns; A second source / drain pattern, on the second lower pattern and connected to the second fin pattern; A second inner spacer, between the second source / drain pattern and the second inner gate; and A second nitrogen accumulation region, extending along the boundary between the second source / drain pattern and the second inner spacer and along the boundary between the second inner gate and the second fin pattern.

10. The semiconductor device according to claim 1, further comprising: A second active pattern, including a second lower pattern and a second fin pattern, the second fin pattern being spaced apart from the second lower pattern in a first direction; A second gate structure, including a second inner gate, the second inner gate being between the second lower pattern and the lowermost second fin pattern among the second fin patterns and between each pair of adjacent second fin patterns; and A second source / drain pattern, on the second lower pattern and connected to the second fin pattern, wherein the second source / drain pattern contacts the second inner gate.

11. The semiconductor device according to any one of claims 1 to 10, wherein, The first inner spacer includes a first sub-spacer pattern and a second sub-spacer pattern, wherein the first sub-spacer pattern is between the second sub-spacer pattern and the first source / drain pattern, wherein the first sub-spacer pattern and the second sub-spacer pattern include different materials, and wherein the first nitrogen accumulation region extends along the boundary between the first sub-spacer pattern and the second sub-spacer pattern.

12. The semiconductor device according to claim 11, wherein, The second sub-spacer pattern includes polysilicon.

13. The semiconductor device according to claim 11, wherein, The first inner spacer further includes a third sub-spacer pattern, wherein the second sub-spacer pattern is between the first sub-spacer pattern and the third sub-spacer pattern, and wherein the third sub-spacer pattern includes a material different from that of the second sub-spacer pattern.

14. A semiconductor device, comprising: A first active pattern, including a first lower pattern and a first fin pattern, the first fin pattern being spaced apart from the first lower pattern in a first direction; A first gate structure, including a first inner gate, the first inner gate being between the first lower pattern and the lowermost first fin pattern among the first fin patterns and between each pair of adjacent first fin patterns, the first inner gate extending in a second direction intersecting the first direction, wherein each of the first inner gates includes a first gate electrode and a first gate insulating film; A first source / drain pattern, on the first lower pattern, including a doped n-type impurity and connected to the first fin pattern; A first inner spacer, between the first source / drain pattern and the first inner gate; and A first nitrogen accumulation region, extending along the boundary between the first source / drain pattern and the first inner spacer and along the boundary between the first inner gate and the first fin pattern.

15. The semiconductor device according to claim 14, further comprising: A second nitrogen accumulation region, within the first inner spacer, wherein the first nitrogen accumulation region is spaced apart from the second nitrogen accumulation region in a third direction, the third direction intersecting the first direction and the second direction.

16. The semiconductor device according to claim 14, further comprising: A second active pattern, including a second lower pattern and a second fin pattern, the second fin pattern being spaced apart from the second lower pattern in a first direction; A second gate structure, including a second inner gate, the second inner gate being between the second lower pattern and the lowermost second fin pattern among the second fin patterns and between each pair of adjacent second fin patterns; A second source / drain pattern, on the second lower pattern, includes doped p-type impurities and is connected to the second fin pattern; and a second inner spacer, between the second source / drain pattern and the second inner gate, wherein no nitrogen accumulation region is formed along the outer periphery of the second inner gate.

17. The semiconductor device according to claim 14, further comprising: a second active pattern, including a second lower pattern and a second fin pattern, the second fin pattern being spaced apart from the second lower pattern in a first direction; a second gate structure, including a second inner gate, the second inner gate being between the second lower pattern and the lowermost second fin pattern among the second fin patterns and between each pair of adjacent second fin patterns; a second source / drain pattern, on the second lower pattern, includes doped p-type impurities and is connected to the second fin pattern; a second inner spacer, between the second source / drain pattern and the second inner gate; and a second nitrogen accumulation region, within the second inner spacer and extending along the sidewall of the second inner gate.

18. The semiconductor device according to claim 17, further comprising: a third nitrogen accumulation region, extending along the boundary between the second inner spacer and the second source / drain pattern.

19. The semiconductor device according to claim 18, wherein, The third nitrogen accumulation region does not extend along the boundary between the second inner gate and the second fin pattern.

20. A semiconductor device, comprising: a first active pattern, including a first lower pattern and a first fin pattern, the first fin pattern being spaced apart from the first lower pattern in a first direction; a first gate structure, including a first inner gate, the first inner gate being between the first lower pattern and the lowermost first fin pattern among the first fin patterns and between each pair of adjacent first fin patterns, the first inner gate extending in a second direction intersecting the first direction, wherein each of the first inner gates includes a first gate electrode and a first gate insulating film; a first source / drain pattern, on the first lower pattern and connected to the first fin pattern; a first inner spacer, between the first source / drain pattern and the first inner gate; a second active pattern, including a second lower pattern and a second fin pattern, the second fin pattern being spaced apart from the second lower pattern in the first direction; a second gate structure, including a second inner gate, the second inner gate being between the second lower pattern and the lowermost second fin pattern among the second fin patterns and between each pair of adjacent second fin patterns, the second inner gate extending in the second direction; a second source / drain pattern, on the second lower pattern and connected to the second fin pattern; a second inner spacer, between the second source / drain pattern and the second inner gate; a first nitrogen accumulation region, within the first inner spacer; and a second nitrogen accumulation region, within the second inner spacer, wherein, in a third direction intersecting the first direction and the second direction, the length of at least one first fin pattern having a first height among the first fin patterns is greater than the length of at least one second fin pattern having the first height among the second fin patterns.

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