Thin film transistor, pixel structure and manufacturing method of thin film transistor

Abstract

The invention discloses a thin film transistor, a pixel structure and a manufacturing method of the thin film transistor. The thin film transistor comprises a substrate, a grid electrode, a semiconductor layer and a grid electrode insulating layer. The gate is disposed on the substrate having a top surface and a side surface. The semiconductor layer is disposed on the substrate and includes a drain region, a channel region and a source region, and the gate overlaps the channel region. The gate insulating layer is arranged between the semiconductor layer and the gate, and the upper surface profile of the gate insulating layer is provided with a first surface, a second surface, a third surface and a fourth surface which are arranged in sequence to form a groove. The first surface overlaps the top surface, the second surface and the third surface overlap the side surface, and the fourth surface overlaps the substrate. The thickness of the gate insulating layer on the first surface is smaller than that of the second surface, and the thickness of the gate insulating layer increases gradually from the third surface to the fourth surface.

Description

Technical Field

[0001] The present invention relates to a semiconductor element, a circuit structure, and a method for manufacturing a semiconductor element, and particularly to a thin film transistor, a pixel structure, and a method for manufacturing a thin film transistor. Background Art

[0002] With the innovation of display technologies, the requirements for the brightness, performance, and resolution of display panels have gradually increased. Among them, displays using self-emitting elements (such as micro light-emitting diodes) have gradually become the focus of research and development by relevant manufacturers because they do not require a backlight module and have advantages such as high brightness and high contrast.

[0003] However, self-emitting elements are driven by thin film transistors on an active array substrate. If the light-emitting element is a current-driven element, the thin film transistor also needs to provide a large current. For example, in order to meet the high-current requirements of micro light-emitting diodes (micro LEDs), thin film transistors are also required to have better high electron mobility, lower critical dimension requirements, lower resistive capacitive delay, and large storage capacitance. However, the performance of current thin film transistors still needs to be improved. Summary of the Invention

[0004] The present invention provides a thin film transistor that can provide a high current gain and has good electrical properties.

[0005] The present invention provides a pixel structure that can meet the high-current requirements of self-emitting elements, and the self-emitting elements have high brightness and uniformity, and can improve the resolution, contrast, and brightness of the display screen when used in a display.

[0006] The present invention provides a method for manufacturing a thin film transistor, which can improve the production yield of the thin film transistor.

[0007] An embodiment of the present invention provides a thin film transistor, including a substrate, a first gate, a first semiconductor layer, and a first gate insulating layer. The first gate is disposed on the substrate and has a top surface and a side surface. The first semiconductor layer is disposed on the substrate and includes a drain region, a channel region, and a source region, and the first gate overlaps the channel region. The first gate insulating layer is disposed between the first semiconductor layer and the first gate, and the upper surface profile of the first gate insulating layer has a first surface, a second surface, a third surface, and a fourth surface arranged in sequence to form a groove. The first surface overlaps the top surface, the second surface and the third surface overlap the side surface, and the fourth surface overlaps the substrate. The thickness of the first gate insulating layer on the first surface is less than the thickness of the second surface, and the thickness of the first gate insulating layer increases from the third surface to the fourth surface.

[0008] An embodiment of the present invention provides a pixel structure, including a self-luminous element and a plurality of thin film transistors. At least one of these thin film transistors has the structure of the aforementioned thin film transistor. At least one of these thin film transistors is electrically connected to the self-luminous element, and the self-luminous element includes at least one of a micro light-emitting diode, a submillimeter light-emitting diode, and an organic light-emitting diode.

[0009] An embodiment of the present invention provides a method for manufacturing a thin film transistor, including forming a gate on a substrate, having a top surface and a side surface connected to the top surface; forming a gate insulating layer on the gate. Etching the gate insulating layer to make the upper surface profile of the gate insulating layer have a first surface, a second surface, a third surface, and a fourth surface arranged in sequence to form a groove. Forming a semiconductor layer, with the gate insulating layer disposed between the semiconductor layer and the gate, wherein the first surface overlaps the top surface, the second surface and the third surface overlap the side surface, and the fourth surface overlaps the substrate. The thickness of the gate insulating layer at the first surface is less than that at the second surface, and the thickness of the gate insulating layer increases from the third surface to the fourth surface.

[0010] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0011] Figure 1A It is a cross-sectional schematic diagram of a thin film transistor according to an embodiment of the present invention;

[0012] Figure 1B For Figure 1A An enlarged schematic diagram of region A1;

[0013] Figure 1C For Figure 1A A top view schematic diagram of a partial structure of the thin film transistor;

[0014] Figure 2A And Figure 2B It is a cross-sectional schematic diagram of a partial structure of a thin film transistor of a comparative example and an embodiment of the present invention;

[0015] Figures 3A to 3E It is a cross-sectional schematic diagram of a partial manufacturing process of a thin film transistor according to an embodiment of the present invention;

[0016] Figure 4 It is a circuit diagram of a pixel structure according to an embodiment of the present invention;

[0017] Figures 5A to 5C It is a cross-sectional schematic diagram of thin film transistors according to multiple embodiments of the present invention;

[0018] Figure 6A It is a cross-sectional schematic diagram of a thin film transistor according to an embodiment of the present invention;

[0019] Figure 6B is Figure 6A an enlarged schematic view of region A2;

[0020] Figure 7 is a cross-sectional schematic view of a thin film transistor according to an embodiment of the present invention;

[0021] Figure 8 is a cross-sectional schematic view of a partial region of a pixel structure according to an embodiment of the present invention.

[0022] Symbol description:

[0023] 1, 1A, 1B, 1C, 1D, 1E, T: thin film transistors

[0024] 10: pixel structure

[0025] 100: substrate

[0026] 110A: first gate

[0027] 110B: second gate

[0028] 110C: third gate

[0029] 111A: top surface

[0030] 112A: side surface

[0031] 120A: first semiconductor layer

[0032] 120B: second semiconductor layer

[0033] 121A: first source region

[0034] 121B: second source region

[0035] 1211A, 1211B: first lightly doped region

[0036] 1212A, 1212B, HD1: first heavily doped region

[0037] 122A: first channel region

[0038] 122B: second channel region

[0039] 123A: first drain region

[0040] 123B: second drain region

[0041] 1231A, 1231B: second lightly doped region

[0042] 1232A, 1232B, HD2: second heavily doped region

[0043] 130A: First gate insulating layer

[0044] 130B: Second gate insulating layer

[0045] 130C: Third gate insulating layer

[0046] 131A: First sub-layer

[0047] 132A: Second sub-layer

[0048] 140: Buffer layer

[0049] 150, 151: Insulating layer

[0050] 160: Barrier layer

[0051] 170: Planarization layer

[0052] 180: Dielectric layer

[0053] A1, A2: Region

[0054] CA: Concave structure

[0055] Cst: Capacitance

[0056] D: Drain

[0057] D1, D1’, D2, D2’, D3, D3’,D31, D32, D33, D34, D35, D4, D110, D120,D132, D150: Thickness

[0058] Data: Data voltage

[0059] DG: Depth

[0060] DIS: Disconnected region

[0061] exL: Extended plane

[0062] EM: Emission signal

[0063] F1: First surface

[0064] F2: Second surface

[0065] F3: Third surface

[0066] F4: Fourth surface

[0067] G: Gate

[0068] GL1, GL: Gate insulating layer

[0069] GR1, GR2: Groove

[0070] HD3: Third heavily doped region

[0071] I1, I2: Boundary

[0072] LDA, LDB: Lightly doped region

[0073] M1, M2, M3: Metal layer

[0074] OVDD: High voltage

[0075] PR: Photoresist layer

[0076] S: Source

[0077] S1: First scan signal

[0078] S2: Second scan signal

[0079] SA1, SB1: First side

[0080] SA2, SB2: Second side

[0081] SM: Semiconductor layer

[0082] T1: First transistor

[0083] T2: Second transistor

[0084] T3: Third transistor

[0085] T4: Fourth transistor

[0086] T5: Fifth transistor

[0087] T6: Sixth transistor

[0088] T7: Seventh transistor

[0089] THA1, THA2, THB1, THB2: Via hole

[0090] Vn: First reference voltage

[0091] Vp: Second reference voltage

[0092] X, Y, Z: Direction Detailed implementation manners

[0093] Reference will now be made in detail to the exemplary embodiments of the present invention. Examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0094] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, no intervening element is present. As used herein, "connected" can refer to physical and / or electrical connection. Furthermore, "electrically connected" or "coupled" can mean that other elements exist between two elements.

[0095] As used herein, "about", "approximately", or "substantially" include the stated value and an average within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art, taking into account the particular quantities of the measurements being discussed and the errors associated with the measurements (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, "about", "approximately", or "substantially" as used herein can be selected with respect to optical properties, etching properties, or other properties to choose a more acceptable deviation range or standard deviation, rather than using one standard deviation for all properties.

[0096] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this invention, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0097] Figure 1A A cross-sectional schematic view of a thin film transistor according to an embodiment of the present invention. Figure 1B is Figure 1A An enlarged schematic view of region A1. Figure 1C is Figure 1A A top view schematic of a partial structure of the thin film transistor. Please refer to Figure 1A , the thin film transistor 1 includes a substrate 100, a first gate 110A, a second gate 110B, a first semiconductor layer 120A, a second semiconductor layer 120B, a first gate insulating layer 130A, a second gate insulating layer 130B, a buffer layer 140, an insulating layer 150, a barrier layer 160, a source S, and a drain D.

[0098] In this embodiment, the material of the substrate 100 can be glass, quartz, organic polymer, light-impermeable / reflection material (e.g., conductive material, wafer (chip), ceramic, or other applicable materials), or other applicable materials. It should be noted that, unless otherwise specifically stated hereinafter, the direction Z can be the normal direction of the substrate 100 or can represent the direction of the thickness of each film layer, and the plane where the direction X and the direction Y are located can be the plane of the substrate 100.

[0099] The first gate 110A has a top surface 111A and a side surface 112A. The side surface 112A can have a gradually changing thickness. For example, as it increases in the direction Y, the film thickness of the side surface 112A gradually decreases in the direction Z. On the other hand, based on the consideration of conductivity, the first gate 110A, the second gate 110B, the source S, and the drain D generally use metal materials. However, the present invention is not limited thereto. According to other embodiments, the first gate 110A, the second gate 110B, the source S, and the drain D can also use other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials. The present invention is not limited thereto.

[0100] The first semiconductor layer 120A is disposed on the substrate 100. Further, in this embodiment, the first semiconductor layer 120A is disposed on the first gate 110A. In addition, the first semiconductor layer 120A includes a first source region 121A, a first channel region 122A, and a first drain region 123A, and the first gate 110A overlaps the first channel region 122A. Similarly, the second semiconductor layer 120B is disposed on the substrate 100. In addition, the second semiconductor layer 120B includes a second source region 121B, a second channel region 122B, and a second drain region 123B, and the second channel region 122B overlaps the first gate 110A. In this embodiment, the first semiconductor layer 120A and the second semiconductor layer 120B are semiconductor materials such as polysilicon thin films, and include doping regions with different carrier doping concentrations (described hereinafter), but the present invention is not limited thereto.

[0101] On the other hand, the first gate insulating layer 130A is disposed between the first semiconductor layer 120A and the first gate 110A. In this embodiment, the material of the first gate insulating layer 130A is preferably an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials). The materials of the second gate insulating layer 130B and the insulating layer 150 may be the same as or different from the material of the first gate insulating layer 130A, and the present invention is not limited thereto. In addition, in this embodiment, the first gate insulating layer 130A may include a first sub-layer 131A and a second sub-layer 132A, and the first sub-layer 131A is disposed between the first gate 110A and the second sub-layer 132A. The material of the first sub-layer 131A may be the same as or different from the material of the second sub-layer 132A. In some embodiments, the second sub-layer 132A may serve as another buffer layer, but the present invention is not limited thereto. In other embodiments, the first gate insulating layer 130A may be only a single-layer structure or stacked by more other sub-layers.

[0102] Please refer to Figure 1A and Figure 1B simultaneously. It is worth mentioning that the contour of the upper surface of the first gate insulating layer 130A facing away from the first gate 110A (or it can also be understood as the surface contour of the second sub-layer 132A away from the first gate 110A in the Z direction) has a first surface F1, a second surface F2, a third surface F3, and a fourth surface F4 arranged in sequence to form a groove GR1. The first surface F1 overlaps the top surface 111A, the second surface F2 and the third surface F3 overlap the side surface 112A, and the fourth surface F4 overlaps the substrate 100 but does not overlap the first gate 110A. In addition, the thickness D1 of the first gate insulating layer 130A on the first surface F1 is less than the thickness D2 of the second surface F2, and the thickness of the first gate insulating layer 130A increases from the third surface F3 to the fourth surface F4. It should be noted that the definitions of the thicknesses D1 to D4 here are the film thicknesses of the first gate insulating layer 130A at different positions in the Z direction. For example, the thickness D1 may be the vertical distance from the upper surface of the second sub-layer 132A facing away from the first gate 110A to the top surface 111A, or may substantially be the thickness D132; the thickness D2 may be the vertical distance from the second surface F2 of the groove GR1 to the side surface 112A; the thickness D3 may be the vertical distance from the third surface F3 of the groove GR1 to the side surface 112A; the thickness D4 may be the vertical distance from the fourth surface F4 of the groove GR1 to the lower surface of the first sub-layer 131A. Or, from another perspective, the lower surface of the first gate 110A has an extended plane exL in the Y direction, and the thickness D4 may also be defined as the vertical distance between the fourth surface F4 and the extended plane exL.

[0103] Specifically, during the fabrication process of the first gate 110A and the first gate insulating layer 130A, the thickness of the first gate insulating layer 130A can be first reduced through an etching process. By utilizing the different properties of the materials of the first gate 110A and the first gate insulating layer 130A, the thickness of the first gate insulating layer 130A above the top surface 111A is different from the thickness of the first gate insulating layer 130A above the side surface 112A. Thus, the thickness D1 (or thickness D132) of the first gate insulating layer 130A can be reduced, and a groove GR1 overlapping the side surface 112A is formed on the upper surface of the first gate insulating layer 130A. As a result, the first semiconductor layer 120A above the first gate 110A can be formed on a relatively flat surface, and the risk of the first semiconductor layer 120A breaking and causing transistor failure can be reduced. In other words, the yield and electrical properties of the thin film transistor 1 can be improved.

[0104] It is worth mentioning that in an embodiment where the first sub-layer 131A and the second sub-layer 132A are made of different materials, a boundary can be observed between the first sub-layer 131A and the second sub-layer 132A under a measuring instrument (such as a Scanning Electron Microscope, SEM). Further, it can be that the second sub-layer 132A is set after etching the first sub-layer 131A. Therefore, it can be observed that the first sub-layer 131A covers the side surface 112A of the first gate 110A, and a concave structure CA is formed at the side surface 112A of the first gate 110A by the first sub-layer 131A, and the concave structure CA overlaps the groove GR1 (as Figure 1B shown).

[0105] In addition, during the etching process, the first sub-layer 131A above the first gate 110A can be completely etched, so that a part (or all) of the top surface 111A is not covered by the first sub-layer 131A. That is to say, the second sub-layer 132A can contact a part (or all) of the top surface 111A of the first gate 110A, contact the concave structure CA of the first sub-layer 131A, and contact the upper surface of the first sub-layer 131A that does not overlap the first gate 110A. Of course, the present invention is not limited to this. In other embodiments not shown, the first sub-layer 131A can also cover the top surface 111A.

[0106] Figure 2A and Figure 2B is a cross-sectional schematic diagram of a partial structure of a thin film transistor of a comparative example and an embodiment of the present invention. Please first refer to Figure 2A, the figure shows the result of successive stacking of each film layer without etching a groove. In this case, directly depositing the gate insulating layer GL1 and the gate insulating layer GL will result in a relatively large step difference formed by the gate insulating layer GL1 and the gate insulating layer GL. Before forming the semiconductor layer SM, the amorphous silicon material of the semiconductor layer SM needs to be subjected to excimer laser annealing (ELA) to form low-temperature polycrystalline silicon (LTPS). At this time, the material of the molten semiconductor layer SM is easily affected by gravity and surface unevenness and breaks (for example, a breakage area DIS is formed), resulting in a decrease in the yield of the thin film transistor or even failure. In addition, if no groove is etched, in the direction from the top surface of the thin film transistor to the outside of the thin film transistor, the film thickness of the gate insulating layer will first increase at the inclined surface and then return to the original thickness. For example, the thickness D1' of the gate insulating layer GL at the top surface of the gate G is about 3104 (Å); the thickness D2' of the gate insulating layer GL at the inclined surface of the gate G is about 3680 (Å); the thickness D3' of the gate insulating layer GL in the area outside the gate G is about 3104 (Å) (which can also be understood as the distance from the upper surface of the gate insulating layer GL to the upper surface of the gate insulating layer GL1). Further, in the case where no groove is etched, the thickness of the gate insulating layer GL above the side surface of the gate G will remain a certain value.

[0107] Table 1

[0108]

[0109] Table 1 lists the film thickness and change trend of the first gate insulating layer 130A at different positions. Please also refer to Figure 2B and Table 1. The figure shows the result of successive stacking of each film layer with a groove GR1 etched. In this embodiment, the thickness D1 (about 1438 (Å)) of the first gate insulating layer 130A on the first surface F1 is less than the thickness D2 (about 1560 (Å)) of the first gate insulating layer 130A on the second surface F2. And the thickness D3 (about 1483 (Å)) of the first gate insulating layer 130A on the third surface F3 is less than the thickness D2. On the other hand, on the third surface F3 and the fourth surface F4 of the groove GR1, the thickness of the first gate insulating layer 130A (for example, from the thickness D3, the thicknesses D31~D34 to the thickness D4) increases from the third surface F3 to the fourth surface F4. When the first gate insulating layer 130A does not overlap with the first gate 110A, the thickness of the first gate insulating layer 130A will remain a certain value. That is to say, in this embodiment, in the negative Y direction, the change trend of the thickness of the first gate insulating layer 130A above the side surface 112A is gradually increasing.

[0110] As described above, in some embodiments, the groove GR1 may have an appropriate depth. For example, the depth DG of the groove GR1 may be greater than 0 micrometers and less than half of the thickness D110 of the first gate 110A. In some embodiments, the depth DG of the groove GR1 may be less than the maximum thickness D120 of the second semiconductor layer 120B. On the other hand, since the thickness of the first gate insulating layer 130A may be relatively low, the film thickness of the first gate 110A may be relatively large to have good conductivity and maintain the flatness of the upper surface of the first gate insulating layer 130A. For example, in some embodiments, the thickness D110 of the first gate 110A may be greater than 1000 (Å).

[0111] Please refer again to Figure 1A and Figure 1B , the barrier layer 160 of the thin film transistor 1 may be disposed on the second gate insulating layer 130B and cover and contact the second gate 110B. The barrier layer 160 is, for example, an inorganic barrier passivation layer (IOBP) formed of an inorganic material, which is used for surface treatment and can protect the underlying components or layers (such as the second gate 110B) from being corroded and contaminated by the etching solution during the manufacturing process. In addition, the insulating layer 150 is disposed between the second semiconductor layer 120B and the first gate 110A to electrically isolate the first gate 110A and the second semiconductor layer 120B. Additionally, since the film thickness of the first gate insulating layer 130A is further reduced through the etching manufacturing process, the thickness D150 of the insulating layer 150 may be greater than the thickness D132 of the first gate insulating layer 130A on the top surface 111A.

[0112] Please continue to refer to Figure 1A , on the other hand, the first source region 121A of the first semiconductor layer 120A may include a first lightly doped region 1211A and a first heavily doped region 1212A, and the first drain region 123A may include a second lightly doped region 1231A and a second heavily doped region 1232A. Further, in the Y direction, the first lightly doped region 1211A is disposed between the first heavily doped region 1212A and the first channel region 122A, the first channel region 122A is disposed between the first lightly doped region 1211A and the second lightly doped region 1231A, the second lightly doped region 1231A is disposed between the first channel region 122A and the second heavily doped region 1232A, and there is a boundary I1 between the first lightly doped region 1211A and the first channel region 122A, and there is a boundary I2 between the first channel region 122A and the second lightly doped region 1231A.

[0113] Specifically, the doping concentrations of the first lightly doped region 1211A and the first heavily doped region 1212A can be selectively different (for example: the doping concentration of the first lightly doped region 1211A is less than that of the first heavily doped region 1212A), but the present invention is not limited thereto. It should be noted that, in fact, the boundaries I1 and I2 are not visible, and the boundaries I1 and I2 are virtual boundaries between two regions with different doping concentrations. For example, the doping concentrations of the first lightly doped region 1211A and the first channel region 122A can be analyzed using an instrument, and the position where the doping concentration changes rapidly is the location of the virtual boundary (i.e., the boundary I1).

[0114] Similarly, the second source region 121B of the second semiconductor layer 120B can include a first lightly doped region 1211B and a first heavily doped region 1212B, and the second drain region 123B can include a second lightly doped region 1231B and a second heavily doped region 1232B. Further, in the Y direction, the first lightly doped region 1211B is disposed between the first heavily doped region 1212B and the second channel region 122B, the second channel region 122B is disposed between the first lightly doped region 1211B and the second lightly doped region 1231B, the second lightly doped region 1231B is disposed between the second channel region 122B and the second heavily doped region 1232B, and the second channel region 122B and the first lightly doped region 1211B also have a boundary I1, and the second channel region 122B and the second lightly doped region 1231B also have a boundary I2. The configuration relationship of the doped regions of the second semiconductor layer 120B can be the same as that of the first semiconductor layer 120A, and will not be elaborated herein.

[0115] Figure 1C For Figure 1A a top view schematic diagram of a partial structure of a thin film transistor. Please refer to Figure 1A and Figure 1C On the other hand, the second gate insulating layer 130B is disposed on the first semiconductor layer 120A, and the second gate 110B is disposed on the second gate insulating layer 130B. Specifically, in this embodiment, the second gate insulating layer 130B is disposed between the second gate 110B and the first semiconductor layer 120A. In addition, the buffer layer 140 is disposed between the substrate 100 and the second semiconductor layer 120B, and the second semiconductor layer 120B is disposed between the substrate 100 and the first gate 110A. In this embodiment, the material of the buffer layer 140 can be an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination of the above, to facilitate the epitaxy or growth of the film layers above the buffer layer 140 (for example, the growth of the second semiconductor layer 120B).

[0116] On the other hand, in the present embodiment, the drain D can be directly electrically connected to the first side SA1 of the first semiconductor layer 120A and the first side SB1 of the second semiconductor layer 120B. The source S can be directly electrically connected to the second side SA2 of the first semiconductor layer 120A and the second side SB2 of the second semiconductor layer 120B, and the first side SA1 and the second side SA2 of the first semiconductor layer 120A can be two sides opposite to each other in the direction Y, and the first side SB1 and the second side SB2 of the second semiconductor layer 120B can be two sides opposite to each other in the direction Y.

[0117] Specifically, the drain D can be directly electrically connected to the first drain region 123A of the first semiconductor layer 120A through the through hole THA1 penetrating the barrier layer 160 and the second gate insulating layer 130B, and can be directly electrically connected to the second drain region 123B of the second semiconductor layer 120B through the through hole THB1 penetrating the barrier layer 160, the second gate insulating layer 130B, the first gate insulating layer 130A and the insulating layer 150. Similarly, the source S can be directly electrically connected to the first source region 121A of the first semiconductor layer 120A through the through hole THA2 penetrating the barrier layer 160 and the second gate insulating layer 130B, and can be directly electrically connected to the second source region 121B of the second semiconductor layer 120B through the through hole THB2 penetrating the barrier layer 160, the second gate insulating layer 130B, the first gate insulating layer 130A and the insulating layer 150. In other words, the thin film transistor 1 can also be a multi-channel type thin film transistor (Multi-channel TFT) connected to each other, whereby the on-current flowing through the thin film transistor 1 can be effectively increased.

[0118] Figures 3A to 3E It is a cross-sectional schematic diagram of a partial manufacturing process of a thin film transistor according to an embodiment of the present invention. Please first refer to Figure 3A , first, a substrate 100 is provided, and a buffer layer 140, a second semiconductor layer 120B, an insulating layer 150 and a first gate 110A are sequentially formed on the substrate 100. The first gate 110A has a top surface 111A and a side surface 112A connected thereto. The method for forming the above-mentioned each film layer can be physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), and is formed by using a photolithography manufacturing process. The present invention is not limited thereto. It should be noted that in Figure 3A only the first gate 110A and a part of the insulating layer 150 are schematically drawn, and the relative relationship of the above-mentioned each element can be referred to the foregoing Figures 1A to 1C structure, which will not be elaborated here.

[0119] Referring again to Figure 3B , a gate insulating layer is then formed on the first gate 110A. For example, the method of the previous components can be used to directly form an inorganic insulating material on the insulating layer 150 and the first gate 110A to form the first sub-layer 131A described above. It should be noted that in the embodiment where the gate insulating layer is a single-layer insulating layer, the same insulating material can also be deposited on the insulating layer 150 and the first gate 110A only in this step, and the present invention is not limited thereto.

[0120] Refer to Figure 3C , and then the gate insulating layer is etched. For example, a photoresist layer PR can be first formed on the first sub-layer 131A by using coating or spinning, as well as baking and developing processes. The photoresist layer PR can be patterned so that the portion of the first sub-layer 131A overlapping with the first gate 110A is not covered by the photoresist layer PR. Then referring again to Figure 3D , an etching process is performed on the first sub-layer 131A so that the first sub-layer 131A exposes a part of the top surface 111A and a part of the side surface 112A. The etching process can be wet etching or dry etching, and the present invention is not limited thereto. For example, the etching rate of the etching solution for the first sub-layer 131A and the first gate 110A can be different, so that the portion of the first sub-layer 131A adjacent to the side surface 112A and not covered by the photoresist layer PR is eroded more to form a concave structure CA adjacent to the side surface 112A. At this point, the thickness of the first sub-layer 131A (or can be understood as a part of the first gate insulating layer 130A) is reduced.

[0121] Then referring again to Figure 3E, a second sub-layer 132A can be formed on the first sub-layer 131A to form the first gate insulating layer 130A. And since the first sub-layer 131A has a concave structure CA, after the second sub-layer 132A is formed, the upper surface of the first gate insulating layer 130A (i.e., the surface of the second sub-layer 132A facing away from the first sub-layer 131A) can have a first surface F1, a second surface F2, a third surface F3, and a fourth surface F4 arranged in sequence to form a groove GR1. The groove GR1 can be located on opposite two side surfaces 112A of the first gate 110A in the Y direction. And a first semiconductor layer 120A is formed, with the second sub-layer 132A disposed between the first semiconductor layer 120A and the first gate 110A. Thus far, the setting of the first gate insulating layer 130A and the first semiconductor layer 120A described above is preliminarily completed. For relevant features and descriptions, reference can be made to the foregoing paragraphs and will not be elaborated here. Since the thickness of the first gate insulating layer 130A is reduced and planarized, the step difference on the upper surface of the first gate insulating layer 130A can be alleviated, and the first semiconductor layer 120A can be formed on a relatively flat surface, indirectly improving the production yield of the first semiconductor layer 120A and the thin-film transistor 1.

[0122] It must be noted here that in the following embodiments, the component numbers and some contents of the foregoing embodiments are adopted, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the foregoing embodiments and will not be repeated in the following embodiments.

[0123] Figure 4 is a circuit diagram of a pixel structure according to an embodiment of the present invention. Please refer to Figure 4, the pixel structure 10 includes a capacitor Cst, a light-emitting element LED, and first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7. In this embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors, but the present invention is not limited thereto. In other embodiments, the first transistor T1 to the seventh transistor T7 may be N-type transistors. The light-emitting element LED has an anode terminal and a cathode terminal that receives the low voltage OVSS of the system. The light-emitting element LED is, for example, at least one of a micro light-emitting diode, a submillimeter light-emitting diode, and an organic light-emitting diode. The capacitor Cst has an A terminal and a B terminal. The A terminal is electrically connected to the fourth transistor T4 and the fifth transistor T5, and the B terminal is electrically connected to the third transistor T3 and the sixth transistor T6. That is to say, the pixel structure 10 is a 7T1C architecture. In other embodiments, the pixel structure may be a 2T1C architecture, a 3T1C architecture, a 3T2C architecture, a 4T1C architecture, a 4T2C architecture, a 5T1C architecture, a 5T2C architecture, a 6T1C architecture, a 6T2C architecture, a 7T2C architecture, or any possible pixel structure to drive the light-emitting element LED, and the present invention is not limited thereto.

[0124] The source of the first transistor T1 is electrically connected between the second transistor T2 and the third transistor T3, for example, electrically connected to the drain of the third transistor T3 and the source of the second transistor T2. The gate of the first transistor T1 may receive the first scan signal S1, and the drain of the first transistor T1 may receive the first reference voltage Vn.

[0125] The source of the second transistor T2 may be electrically connected to the drain of the third transistor T3, and the drain of the second transistor T2 may be electrically connected between the sixth transistor T6 and the seventh transistor T7, for example, the drain of the sixth transistor T6 is electrically connected to the drain of the sixth transistor T6 and the source of the seventh transistor T7. The source of the third transistor T3 is electrically connected to the B terminal of the capacitor Cst. The gates of the second transistor T2 and the third transistor T3 may receive the second scan signal S2. Specifically, the first scan signal S1 and the second scan signal S2 may be respectively transmitted by different scan lines (not shown) in the display. The first scan signal S1 and the second scan signal S2 are, for example, voltage signals with the same waveform, the same intensity but different phases to drive the corresponding transistors in different timings respectively, and the present invention is not limited thereto.

[0126] Please continue to refer to Figure 4, the source of the fourth transistor T4 receives the data voltage Data, the drain of the fourth transistor T4 is electrically connected to the A terminal of the capacitor Cst, and the gate of the fourth transistor T4 receives the second scan signal S2. The source of the fifth transistor T5 receives the second reference voltage Vp, and the drain of the fifth transistor T5 is electrically connected to the A terminal of the capacitor Cst. The data voltage Data can be transmitted by a data line (not shown) in a display, so the three terminals of the source, gate, and drain of the fourth transistor T4 can be directly electrically connected to the data line, scan line, and the fifth transistor T5 respectively. In other words, the fourth transistor T4 can also be defined as a switching thin-film transistor, but the present invention is not limited thereto.

[0127] The source of the sixth transistor T6 receives the system high voltage OVDD, the drain of the sixth transistor T6 is electrically connected to the source of the seventh transistor T7, and the gate of the sixth transistor T6 is electrically connected to the B terminal of the capacitor Cst. The source of the seventh transistor T7 can be directly electrically connected to the drain of the sixth transistor T6, the drain of the seventh transistor T7 is electrically connected to the anodic terminal of the light-emitting element LED, and the gate of the seventh transistor T7 receives the light-emitting signal EM.

[0128] The pixel structure 10 can operate sequentially in a first period, a second period, and a third period, where the second period includes a preset time t1. The preset time t1 follows the first period (i.e., at the beginning of the second period) and is less than the second period. During the first period, the first transistor T1 receives the first scan signal S1 and is in the conducting state, and the second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and seventh transistor T7 are in the cut-off state; during the second period, the second transistor T2, third transistor T3, and fourth transistor T4 receive the second scan signal S2 and are in the conducting state, and the first transistor T1 remains in the conducting state during the preset time t1 of the second period; during the third period, the first transistor T1, second transistor T2, third transistor T3, and fourth transistor T4 are in the cut-off state.

[0129] When in the first time period, the first transistor T1 receives the first scan signal S1 and is in the on state. Therefore, the signal of the first reference voltage Vn can be transmitted to the source of the first transistor T1. When at the preset time t1 in the second time period, the second transistor T2, the third transistor T3, and the fourth transistor T4 are in the on state. Therefore, the signal of the data voltage Data can be transmitted to the A end of the capacitor Cst, and the first reference voltage Vn can be transmitted to the B end of the capacitor Cst. Then when the pixel structure 10 is within the second time period and at a time other than the preset time t1, the first transistor T1 is in the off state, but the second transistor T2, the third transistor T3, and the fourth transistor T4 are still in the on state. At this time, the potential of the gate of the sixth transistor T6 is equal to the high voltage OVDD minus the threshold voltage Vth, that is, (OVDD - Vth).

[0130] When in the third time period, the second transistor T2, the third transistor T3, and the fourth transistor T4 are in the off state, and the fifth transistor T5 and the seventh transistor T7 receive the light-emitting signal EM and are in the on state. At this time, the potential of the A end of the capacitor Cst changes from the data voltage Data to the second reference voltage Vp, and the change amount is expressed as (Vp - Data). Therefore, the potential of the B end of the capacitor Cst will change from (OVDD - Vth) in the second time period to (OVDD - Vth)+(Vp - Data). According to the following transistor current (Id) relationship formula (1): Id = K(Vs - Vg - |Vth|) 2 ; where K is a constant related to the transistor structure, Vg is the transistor gate voltage, which is (OVDD - Vth)+(Vp - Data) for the sixth transistor T6; Vs is the source terminal voltage, which is the high voltage OVDD for the sixth transistor T6. Substituting the value of the high voltage OVDD into Vs in formula (1), and substituting the value of (OVDD - Vth)+(Vp - Data) into Vg in formula (1), we can get Id = K(Data - Vp) 2 Since the light-emitting element LED is driven by the current (i.e., Id) flowing through when the sixth transistor T6 is on, the sixth transistor T6 can also be defined as the driving thin-film transistor. And the current (i.e., Id) flowing through the seventh transistor T7 enables the light-emitting element LED to emit light, so the seventh transistor T7 can also be defined as the light-emitting thin-film transistor.

[0131] As described above, it can also be known from Equation (1) and the derivation that the brightness of the light-emitting element LED will not be affected by the threshold voltage Vth of the sixth transistor T6, so that the display using the pixel structure 10 can have uniform brightness. In addition, in the pixel structure 10, since the current flowing through the sixth transistor T6 and the seventh transistor T7 is relatively large, at least one of the sixth transistor T6 and the seventh transistor T7 can be fabricated using the thin-film transistor 1 of this embodiment. In this way, it can have advantages such as high current gain, reduced cross voltage, and high current supply. When the light-emitting element LED is a micro light-emitting diode, it can exhibit the advantage of high brightness and maintain good stability.

[0132] Figures 5A to 5C is a cross-sectional schematic diagram of the thin-film transistors of multiple embodiments of the present invention. Please refer to Figure 5A , the thin-film transistor 1A is similar to the aforementioned thin-film transistor 1. The main difference is that in the Z direction, the thin-film transistor 1A may sequentially include a buffer layer 140, a second semiconductor layer 120B, an insulating layer 150, a first gate 110A, a first gate insulating layer 130A, and a second gate insulating layer 130B from the substrate 100 to the barrier layer 160, and the second gate 110B is not provided.

[0133] Please refer to Figure 5B , the thin-film transistor 1B is similar to the aforementioned thin-film transistor 1. The main difference is that in the Z direction, the thin-film transistor 1B may sequentially include a buffer layer 140, an insulating layer 150, a first gate insulating layer 130A, a first semiconductor layer 120A, a second gate insulating layer 130B, and a second gate 110B from the substrate 100 to the barrier layer 160, and the first gate 110A and the second semiconductor layer 120B are not provided.

[0134] Please refer to Figure 5C again, the thin-film transistor 1C is similar to the aforementioned thin-film transistor 1. The main difference is that in the Z direction, the thin-film transistor 1C may sequentially include a buffer layer 140, an insulating layer 150, a first sub-layer 131A, a first gate 110A, a second sub-layer 132A, a first semiconductor layer 120A, a second gate insulating layer 130B, and a second gate 110B from the substrate 100 to the barrier layer 160, and the second semiconductor layer 120B is not provided. In other words, the thin-film transistor 1C can be a double-gate thin-film transistor. Although not shown in the Figures 5B to 5C embodiment, a groove GR1 structure as shown in Figure 1B can also be formed at the side of the first gate insulating layer 130A with respect to the first gate 110A. The relevant content can be referred to the previous paragraphs and will not be elaborated here.

[0135] Among the above thin film transistors 1A to 1C, they can all be provided in the same pixel structure 10 and applied to different types of transistors. For example, in Figure 4 the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can all adopt the architecture of the thin film transistor 1B and be designed above the film layer, while the sixth transistor T6 and the seventh transistor T7 can both be the architecture of the thin film transistor 1A and be designed below the film layer. In addition to being able to design the sixth transistor T6 and the seventh transistor T7 into a larger size architecture to meet their high current supply requirements, the architecture of different transistors in different film layers can also effectively reduce the occupied area of the pixel structure 10 on the substrate 100. When the pixel structure 10 is applied to a display panel (not shown), it can also improve the pixel density (PPI) and resolution of the display panel. Of course, the present invention is not limited thereto.

[0136] Figure 6A It is a cross-sectional schematic diagram of a thin film transistor according to an embodiment of the present invention. Figure 6B It is Figure 6A an enlarged schematic diagram of region A2. Please first refer to Figure 6A , the thin film transistor 1D is similar to the aforementioned thin film transistor 1. The main difference is that: the thin film transistor 1D further includes an insulating layer 151 disposed between the second gate 110B and the second semiconductor layer 120B, and the second gate 110B is disposed between the first semiconductor layer 120A and the second semiconductor layer 120B. On the other hand, the thin film transistor 1D further includes a third gate 110C and a third gate insulating layer 130C. The third gate 110C is disposed on the second semiconductor layer 120B and overlaps the second channel region 122B, and the third gate insulating layer 130C is disposed between the third gate 110C and the second semiconductor layer 120B to electrically isolate the two.

[0137] In detail, the thin film transistor 1D may include a buffer layer 140, a first gate 110A, a first gate insulating layer 130A, a first semiconductor layer 120A, a second gate insulating layer 130B, a second gate 110B, an insulating layer 150, an insulating layer 151, a second semiconductor layer 120B and a third gate insulating layer 130BC in order from the substrate 100 to the barrier layer 160 in the direction Z. In this embodiment, the first semiconductor layer 120A and the second semiconductor layer 120B of the thin film transistor 1D may be electrically controlled by two gates, and it can also be understood that the thin film transistor 1D includes two dual-gate transistors. In other embodiments, the first gate 110A may be used as a routing for other functions to increase the layout flexibility of the circuit. For example, in some embodiments, the first gate 110A may be used as a shielding layer to provide an electrostatic shielding (ESD) function. According to design requirements, in some embodiments, the first gate 110A may or may not accept a potential (e.g., floating, ground potential, serving as a common electrode (vcom), source or drain), and be connected to an external circuit through internal wiring (not shown) at other locations in the thin film transistor 1D, but the present invention is not limited to this.

[0138] Please continue to refer to Figure 6B , the insulating layer 151 may also have a profile similar to the first gate insulating layer 130A. Further, the first semiconductor layer 120A, the insulating layer 150 and the insulating layer 151 may all adopt the planarization process similar to the first gate insulating layer 130A to reduce the step difference, so that the upper surface of the insulating layer 151 (i.e., the surface of the insulating layer 151 away from the first gate 110A) may also have a groove GR2, and the position of the groove GR2 may overlap the position of the groove GR1, and have the aforementioned Figure 1B In other words, the second semiconductor layer 120B above the insulating layer 151 and the first semiconductor layer 120A above the second sub-layer 132A can be formed on a relatively flat surface to improve the electrical properties and yield of the thin film transistor 1D, and the thickness of the first gate 110A and the second gate 110B does not need to be reduced to maintain good conductivity. The relevant content can be referred to the above paragraphs and will not be repeated here.

[0139] Figure 7 FIG. 1 is a cross-sectional diagram of a thin film transistor according to an embodiment of the present invention. Figure 7, the thin film transistor 1E is similar to the aforementioned thin film transistor 1, and its main difference lies in that: in the thin film transistor 1E, the heavily doped region of the first semiconductor layer 120A extends into the projection of the second gate 110B, and the heavily doped region of the second semiconductor layer 120B extends into the projection of the first gate 110A. Specifically, the first source region 121A of the first semiconductor layer 120A may include a first heavily doped region HD1A and a second heavily doped region HD2A, and the first drain region 123A may include a lightly doped region LDA and a third heavily doped region HD3A. Further, in the Y direction, the first heavily doped region HD1A is disposed between the second heavily doped region HD2A and the first channel region 122A, the first channel region 122A is disposed between the first heavily doped region HD1A and the lightly doped region LDA, the lightly doped region LDA is disposed between the first channel region 122A and the third heavily doped region HD3A, and the first channel region 122A and the lightly doped region LDA have a boundary I2, and the first channel region 122A and the first heavily doped region HD1A have a boundary I1. And the length of the first heavily doped region HD1A extends in the Y direction such that in the Z direction, the first heavily doped region HD1A and the second gate 110B overlap.

[0140] Specifically, the doping concentrations of the first heavily doped region HD1A and the second heavily doped region HD2A can be selectively different (for example: the doping concentration of the first heavily doped region HD1A is higher than that of the second heavily doped region HD2A), but the present invention is not limited thereto. As described above, the boundaries I1 and I2 are invisible, and the boundaries I1 and I2 are virtual boundaries of two regions with different doping concentrations. By reducing the length of the first channel region 122A in the Y direction (i.e., the horizontal distance between the boundaries I1 and I2 in the Y direction), a carrier channel with a shorter length can be fabricated, which can increase the on-current flowing through the thin film transistor 1E, so that when the thin film transistor 1E is applied to components that require high current, good electrical properties can be provided.

[0141] Similarly, the second source region 121B of the second semiconductor layer 120B may include a first heavily doped region HD1B and a second heavily doped region HD2B, and the second drain region 123B may include a lightly doped region LDB and a third heavily doped region HD3B. Further, in the Y direction, the first heavily doped region HD1B is disposed between the second heavily doped region HD2B and the second channel region 122B, the second channel region 122B is disposed between the first heavily doped region HD1B and the lightly doped region LDB, the lightly doped region LDB is disposed between the second channel region 122B and the third heavily doped region HD3B, and there is also a boundary I2 between the second channel region 122B and the lightly doped region LDB, and there is also a boundary I1 between the second channel region 122B and the first heavily doped region HD1B. And the length of the first heavily doped region HD1B extends in the Y direction such that in the Z direction, the first heavily doped region HD1B and the first gate 110A overlap. The configuration relationship of the doped regions of the second semiconductor layer 120B may be the same as that of the first semiconductor layer 120A. Therefore, the second semiconductor layer 120B may also have similar characteristics and effects as the first semiconductor layer 120A, which will not be elaborated here.

[0142] Figure 8 A cross-sectional schematic diagram of a partial region of a pixel structure according to an embodiment of the present invention. Please refer to Figure 8 , other film layers may also be included above the pixel structure 10, such as a planarization layer 170 and a dielectric layer 180. The dielectric layer 180 may be disposed between the third gate insulating layer 130C and the planarization layer 170, and the planarization layer 170 may be disposed between the dielectric layer 180 and the barrier layer 160. On the other hand, the thin film transistor T may have a similar architecture to the aforementioned thin film transistors 1A to 1D, which will not be elaborated here. It is worth mentioning that in Figure 8 , the first gate 110A, the second gate 110B, and the third gate 110C in the thin film transistor T may be connected in series with each other. On the other hand, the thin film transistor T may be electrically connected to a capacitor Cst. The capacitor Cst may have a metal layer M1, a metal layer M2, and a metal layer M3, and form an internal structure of the capacitor Cst via the buffer layer 140, the first gate insulating layer 130A, and the second gate insulating layer 130B.

[0143] In summary, during the preparation process of the thin film transistor of the present invention, since the topography of the gate insulating layer above the gate is flattened, while maintaining a certain thickness of the gate metal layer to have better electrical performance, the step difference formed by the upper gate insulating layer can also be reduced, or the upper surface of the gate insulating layer can be relatively flat. Therefore, the semiconductor layer on the upper surface of the gate insulating layer can also grow on a relatively flat surface, reducing the probability of disconnection of the semiconductor layer during the manufacturing process, and further improving the performance and manufacturing yield of the thin film transistor.

[0144] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended claims.

Claims

1. A thin film transistor, comprising: A substrate; A first gate disposed on the substrate, having a top surface and a side surface connected to the top surface; A first semiconductor layer disposed on the substrate, the first semiconductor layer including a first drain region, a first channel region, and a first source region, and the first gate overlapping the first channel region; and A first gate insulating layer disposed between the first semiconductor layer and the first gate, an upper surface profile of the first gate insulating layer having a first surface, a second surface, a third surface, and a fourth surface arranged in sequence to form a groove, Wherein the first surface overlaps the top surface, the second surface and the third surface overlap the side surface, and the fourth surface overlaps the substrate, Wherein a thickness of the first gate insulating layer at the first surface is less than a thickness of the second surface, and a thickness of the first gate insulating layer increases from the third surface to the fourth surface.

2. The thin film transistor according to claim 1, further comprising: A second gate insulating layer disposed on the first semiconductor layer; And A second gate disposed on the second gate insulating layer.

3. The thin film transistor according to claim 2, further comprising: A second semiconductor layer disposed on the substrate, wherein the second semiconductor layer includes a second drain region, a second channel region, and a second source region, and the second channel region overlaps the first gate.

4. The thin film transistor according to claim 3, further comprising: A buffer layer disposed between the substrate and the second semiconductor layer, wherein the second semiconductor layer is disposed between the substrate and the first gate.

5. The thin film transistor according to claim 4, further comprising: An insulating layer disposed between the second semiconductor layer and the first gate, wherein a thickness of the insulating layer is greater than a thickness of the first gate insulating layer at the top surface.

6. The thin film transistor according to claim 3, further comprising: An insulating layer disposed between the second gate and the second semiconductor layer, wherein the second gate is disposed between the first semiconductor layer and the second semiconductor layer.

7. The thin film transistor according to claim 6, further comprising: A third gate disposed on the second semiconductor layer and overlapping the second channel region; And A third gate insulating layer disposed between the third gate and the second semiconductor layer.

8. The thin film transistor according to claim 7, wherein the first gate, the second gate, and the third gate are connected in series with each other.

9. The thin film transistor according to claim 1, wherein a depth of the groove is greater than 0 micrometers and less than half of a thickness of the first gate.

10. The thin film transistor according to claim 1, wherein a thickness of the first gate is greater than 1000 angstroms (Å).

11. The thin film transistor according to claim 3, wherein a depth of the groove is less than a maximum thickness of the second semiconductor layer.

12. The thin film transistor according to claim 3, further comprising: A drain directly electrically connecting a first side of the first semiconductor layer and a first side of the second semiconductor layer; And A source electrode is directly electrically connected to a second side of the first semiconductor layer and a second side of the second semiconductor layer, wherein a first side and the second side of the first semiconductor layer are opposite to each other, and a first side and the second side of the second semiconductor layer are opposite to each other.

13. The thin film transistor as claimed in claim 1, wherein the first gate insulating layer comprises a first sub-layer and a second sub-layer, and the first sub-layer is disposed between the first gate and the second sub-layer.

14. The thin film transistor as claimed in claim 13, wherein the first sub-layer covers the side surface of the first gate, and the first sub-layer forms a recessed structure at the side surface of the first gate, and the recessed structure overlaps with the groove.

15. The thin film transistor as claimed in claim 14, wherein the second sub-layer contacts a part of the top surface of the first gate, the recessed structure, and an upper surface of the first sub-layer.

16. The thin film transistor as claimed in claim 1, wherein the first semiconductor layer has a first heavily doped region, a second heavily doped region, a third heavily doped region, and a lightly doped region, wherein the first heavily doped region is disposed between the second heavily doped region and the first channel region, the first channel region is disposed between the first heavily doped region and the lightly doped region, the lightly doped region is disposed between the first channel region and the third heavily doped region, and the first channel region and the lightly doped region have a boundary.

17. The thin film transistor as claimed in claim 3, wherein the second semiconductor layer has a first heavily doped region, a second heavily doped region, a third heavily doped region, and a lightly doped region, wherein the first heavily doped region is disposed between the second heavily doped region and the second channel region, the second channel region is disposed between the first heavily doped region and the lightly doped region, the lightly doped region is disposed between the second channel region and the third heavily doped region, and the channel region and the lightly doped region have a boundary.

18. A pixel structure, comprising: a self-emitting element; and a plurality of thin film transistors, at least one of the thin film transistors having a structure of the thin film transistor as claimed in claim 1, wherein at least one of the thin film transistors is electrically connected to the self-emitting element, and the self-emitting element comprises at least one of a micro light emitting diode, a submillimeter light emitting diode, and an organic light emitting diode.

19. The pixel structure as claimed in claim 18, wherein at least one of the thin film transistors is a driving thin film transistor or a light emitting thin film transistor.

20. The pixel structure as claimed in claim 18, wherein at least another one of the thin film transistors is a switching thin film transistor, and three terminals of the switching thin film transistor are respectively electrically connected to a data line, a scanning line, and at least one of the thin film transistors.

21. A method for manufacturing a thin film transistor, comprising: forming a gate on a substrate, having a top surface and a side surface connected to the top surface; forming a gate insulating layer on the gate; etching the gate insulating layer to make an upper surface profile of the gate insulating layer have a first surface, a second surface, a third surface, and a fourth surface arranged in sequence to form a groove; and Form a semiconductor layer, with the gate insulating layer disposed between the semiconductor layer and the gate, where the first surface overlaps the top surface, the second and third surfaces overlap the side surfaces, and the fourth surface overlaps the substrate. Wherein the thickness of the gate insulating layer at the first surface is less than that at the second surface, and the thickness of the gate insulating layer increases from the third surface towards the fourth surface.

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