Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The semiconductor device includes a substrate, a first well, a second well and an isolation structure. The substrate has a first conductivity type. The first well and the second well have a second conductivity type different from the first conductivity type and are disposed in the substrate. The isolation structure is disposed between the first well and the second well. The isolation structure comprises a third well, a fourth well and a first doped region. The third well has a first conductivity type and includes a first portion and a second portion. The fourth well has a second conductivity type and is disposed between the first portion and the second portion of the third well. The first doped region has a first conductivity type and is disposed in the fourth well.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including an isolation structure and a method for forming the same. Background Art

[0002] Current high-voltage integrated circuits (HVICs) can be used to drive high-current components such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs). Since they are cost-effective and easily compatible with other processes, HVICs are often used in power control systems to simultaneously drive high-voltage and low-voltage components with different operating voltages.

[0003] The HVIC includes a high-side circuit located in a high-side region and a low-side circuit located in a low-side region, and the high-side circuit and the low-side circuit are connected by a level shifter.

[0004] However, in an HVIC, due to insufficient electrical isolation between components, there may be a phenomenon of uneven charge distribution, resulting in problems such as excessive leakage current and insufficient punch-through resistance. Therefore, although existing semiconductor devices and methods for forming the same have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor devices and methods for forming the same. Summary of the Invention

[0005] The present disclosure improves the electrical isolation characteristics between a level shifter and a high-voltage junction termination by providing an isolation structure between a first well and a second well. Therefore, the present disclosure can improve the charge distribution to increase the breakdown voltage, reduce the leakage current, improve the punch-through resistance, improve the reliability, and / or improve the process margin.

[0006] For example, in a cross-sectional view, by disposing an N-type element (e.g., a fourth well) between two adjacent P-type elements (e.g., a first part and a second part of a third well), and disposing a P-type doped region (e.g., a first doped region) in the N-type element, a plurality of P-N junctions are provided to enhance the depletion effect, thereby improving the electrical isolation characteristics in a high voltage difference region. For example, in a cross-sectional view, by disposing a P-type doped region (e.g., a first doped region) having a different doping concentration from the P-type elements between two adjacent P-type elements (e.g., a first part and a second part of a third well), sufficient electrical isolation characteristics are provided and the process margin is enhanced in a middle voltage difference region. For example, in a cross-sectional view, the third well may further include a third part, and the third part is connected to the first part and the second part to provide sufficient electrical isolation characteristics and simplify the process in a low voltage difference region.

[0007] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first well, a second well, and an isolation structure. The substrate has a first conductivity type. The first well and the second well have a second conductivity type different from the first conductivity type and are disposed in the substrate. The isolation structure is disposed between the first well and the second well. The isolation structure includes a third well, a fourth well, and a first doped region. The third well has the first conductivity type and includes a first part and a second part. The fourth well has the second conductivity type and is disposed between the first part and the second part of the third well. The first doped region has the first conductivity type and is disposed in the fourth well.

[0008] In some embodiments, the present disclosure provides a method for forming a semiconductor device. The method for forming a semiconductor device includes providing a substrate having a first conductivity type. Forming a first well and a second well having a second conductivity type different from the first conductivity type in the substrate. Forming an isolation structure between the first well and the second well. The isolation structure includes a third well, a fourth well, and a first doped region. The third well has the first conductivity type and includes a first part and a second part. The fourth well has the second conductivity type and is disposed between the first part and the second part of the third well. The first doped region has the first conductivity type and is disposed in the fourth well.

[0009] The semiconductor device and the method for forming the same according to the present disclosure can be applied to various types of electronic devices and the methods for forming the same. To make the components and advantages of the present disclosure more obvious and understandable, various embodiments are specifically exemplified below and described in detail with the accompanying drawings as follows. Description of the Drawings

[0010] When read in conjunction with the drawings, the present disclosure can be more fully understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.

[0011] Figure 1 is a top view schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 is a perspective schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 3 and Figure 4 are respectively cross-sectional schematic diagrams of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 5 is a perspective schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 7 is a perspective schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0017] Reference Numerals

[0018] 1, 2, 3: Semiconductor Device

[0019] 100: Substrate

[0020] 102, 103, 104: First Buried Layer

[0021] 106, 108: Second Buried Layer

[0022] 112: First Well

[0023] 114: Second Well

[0024] 116: Fourth Well

[0025] 120: Third Well

[0026] 122: First Portion

[0027] 123: Third Portion

[0028] 124: Second Portion

[0029] 126: Well

[0030] 130: Gate Electrode

[0031] 142: First Doped Region

[0032] 142P: Protrusion

[0033] 144, 146, 156: Doped region

[0034] 152: Second doped region

[0035] 154: Third doped region

[0036] 200: Isolation layer

[0037] 300: Dielectric layer

[0038] 302, 304: Contact

[0039] A - A’, B - B’, C - C’: Line segment

[0040] D1: First direction

[0041] D2: Second direction

[0042] D3: Third direction

[0043] HVJT: High - voltage junction termination

[0044] HVR: High - end region

[0045] IR: Intermediate region

[0046] ISO: Isolation structure

[0047] LS: Level shifter

[0048] LVR: Low - end region

[0049] s1: First distance

[0050] s2: Second distance

[0051] V A , V A’ , V A” , V B , V B’ , V C , V C’ : Voltage

[0052] w: Total width

[0053] w122, w123, w124, w142: Width

[0054] w1: First side width

[0055] w2: Second side width Detailed implementation mode

[0056] The semiconductor devices of the embodiments in the present disclosure will be described in detail below. It should be understood that the following descriptions provide many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for simply and clearly describing some embodiments of the present disclosure. Of course, these are only for illustration and not for limiting the present disclosure. In addition, similar and / or corresponding element symbols may be used in different embodiments to label similar and / or corresponding elements to clearly describe the present disclosure. However, the use of these similar and / or corresponding element symbols is only for simply and clearly describing some embodiments of the present disclosure, and does not represent any association between the different embodiments and / or structures discussed.

[0057] It should be understood that relative terms may be used in the embodiments, for example, "lower" or "bottom" or "higher" or "top", to describe the relative relationship of one element in the figure to another element. It can be understood that if the device in the figure is flipped upside down, the element described on the "lower" side will become the element on the "higher" side. The embodiments of the present disclosure can be understood in conjunction with the figures, and the figures of the present disclosure are also regarded as part of the disclosure description.

[0058] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, it may include the case where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, when the first material layer is directly on the second material layer, it means that the first material layer is in direct contact with the second material layer.

[0059] In addition, it should be understood that the ordinal numbers such as "first", "second", etc. used in the specification and claims are used to modify elements, and they do not themselves intend to imply that the element (or elements) has any previous ordinal number, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish an element with a certain name from another element with the same name. The same terms may not be used in the claims and the specification. For example, the first element in the specification may be the second element in the claim.

[0060] In some embodiments of the present disclosure, terms related to joining and connection, such as "connect", "interconnect", "bond", etc., unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures disposed between these two structures. And these terms related to connection and joining may also include cases where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect means of electrical connection.

[0061] In this document, terms such as "approximate", "about", and "substantially" generally mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meanings of "approximate", "about", and "substantially" may still be implied even without specific mention of "approximate", "about", or "substantially". The term "ranging from a first value to a second value" or "the first value - the second value" means that the range includes the first value, the second value, and other values therebetween. Furthermore, there may be a certain error between any two values or directions being compared. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

[0062] It should be understood that throughout the specification and claims of the present disclosure, certain terms are used to refer to specific elements. Those skilled in the art should understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish elements that have the same function but different names. In the following specification and claims, words such as "comprise", "contain", and "have" are open-ended terms, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the description of the present disclosure uses the terms "include", "contain", and / or "have", it specifies the existence of corresponding components, regions, steps, operations, and / or elements, but does not exclude the existence of one or more corresponding components, regions, steps, operations, and / or elements.

[0063] It should be understood that, without departing from the spirit of the present disclosure, in the following examples, components in multiple different embodiments can be replaced, reorganized, and combined to complete other embodiments. As long as the components between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily combined and used.

[0064] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, if defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0065] In this disclosure, each direction is not limited to the three axes of a rectangular coordinate system such as the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For the sake of convenience of description, hereinafter, the X-axis direction is the first direction D1 (length direction), the Y-axis direction is the second direction D2 (width direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the three-dimensional schematic diagram described herein is a schematic diagram that simultaneously shows the XY plane (the plane formed by the first direction D1 and the second direction D2) and the XZ plane (the plane formed by the first direction D1 and the third direction D3). In some embodiments, the schematic diagram described herein is for observing the XY plane, and the cross-sectional schematic diagram described herein is for observing the XZ plane. In some embodiments, the normal direction of the substrate described herein is the third direction D3.

[0066] Refer to Figure 1 , which is a top view schematic diagram of the semiconductor device 1 according to an embodiment of this disclosure. For the sake of convenience of description, some elements are omitted. As Figure 1 shown, in some embodiments, the semiconductor device 1 may include a low-voltage region LVR, a high-voltage region HVR, and an intermediary region IR between the low-voltage region LVR and the high-voltage region HVR. In some embodiments, low-voltage components and high-voltage components may be provided in the low-voltage region LVR and the high-voltage region HVR, respectively.

[0067] As Figure 1As shown, in some embodiments, a high-voltage junction terminal (HVJT) can be formed in the intermediate region (IR), and the HVJT can surround the high-voltage region (HVR) to enhance the breakdown voltage capability of the HVR. In some embodiments, a level shifter (LS) can be formed in the IR, and the LS can be electrically connected to the low-voltage region (LVR) and the HVR to achieve the function of level shifting. For example, the LS can include an N-type level shifter as a boosting type level shifter, such as an N-type laterally diffused metal oxide semiconductor (NLDMOS), to raise the level. In some embodiments, an isolation structure (ISO) can be formed in the IR, and the ISO can be interposed between the HVJT and the LS to electrically isolate the LS from other components. Accordingly, the present disclosure improves the electrical isolation characteristics between the LS and other components by adjusting the ISO.

[0068] Referring to Figure 2 , which is a perspective schematic view of a semiconductor device 1 according to an embodiment of the present disclosure. For ease of illustration, some elements are omitted. As Figure 2 shown, in some embodiments, a substrate 100 of a first conductivity type is provided. In some embodiments, the substrate 100 can include a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate. In some embodiments, the substrate 100 can include a wafer, such as a silicon wafer. Generally, an SOI substrate can include a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like, to provide an insulating layer on a silicon or glass substrate. In some embodiments, the substrate can include a multi-substrate or a gradient substrate.

[0069] In some embodiments, the substrate 100 can include an elemental semiconductor, which includes silicon, germanium, their analogs, or a combination thereof; the substrate 100 can include a compound semiconductor, which includes: silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, their analogs, or a combination thereof; the substrate 100 can include an alloy semiconductor, which includes: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, their analogs, or a combination thereof, but the present disclosure is not limited thereto.

[0070] In some embodiments, the first conduction type and the second conduction type can be adjusted according to electrical requirements. In some embodiments, the doping concentration, the doping depth, and the size of the doping region can also be adjusted according to electrical requirements. In some embodiments, the first conduction type can be one of P-type or N-type, and the second conduction type can be the other of P-type or N-type. For ease of description, hereinafter, the first conduction type can be P-type, and the second conduction type can be N-type, but the present disclosure is not limited thereto.

[0071] As Figure 2 shown, in some embodiments, first buried layers 102 and 104 can be formed in substrate 100, and the first buried layers 102 and 104 can have the first conduction type, that is, P-type. In some embodiments, second buried layers 106 and 108 can be disposed in substrate 100, and the second buried layers 106 and 108 can have the second conduction type, that is, N-type. In some embodiments, the first buried layers 102 and 104 and / or the second buried layers 106 and 108 can be formed in substrate 100 by processes such as ion implantation process, diffusion process, drive-in process, similar processes or combinations thereof, but the present disclosure is not limited thereto. Additionally, the implanted dopants can be further activated by a rapid thermal annealing (RTA) process. In some embodiments, the dopant can be a P-type dopant such as boron (B), or an N-type dopant such as phosphorus (P), and the corresponding dopant can be selected according to the conduction type. In some embodiments, the second buried layers 106 and 108 can help improve the breakdown voltage capability of the level shifter LS. In some embodiments, the second buried layers 106 and 108 can be omitted.

[0072] In some embodiments, an epitaxial layer (not shown) can be further formed on substrate 100. In some embodiments, the epitaxial layer can cover the top surfaces of the first buried layers 102 and 104 and the second buried layers 106 and 108. In some embodiments, after the step of forming the epitaxial layer on substrate 100, by performing the aforementioned diffusion process, drive-in process, and / or rapid thermal annealing process, the first buried layers 102 and 104 and the second buried layers 106 and 108 disposed in substrate 100 can be further disposed into the epitaxial layer to change the doping profiles of the first buried layers 102 and 104 and the second buried layers 106 and 108.

[0073] As Figure 2As shown, in some embodiments, a first well 112 and a second well 114 having a second conductivity type (N-type) different from the first conductivity type may be formed in a substrate 100. In some embodiments, the first well 112 and / or the second well 114 may be formed by performing the foregoing ion implantation, diffusion process, thermal drive-in process, and / or rapid thermal annealing process. In some embodiments, the first well 112 and / or the second well 114 may be formed substantially in the same process track, or may be formed in different process tracks. In some embodiments, the first well 112 may be located in the intermediate region IR, and the second well 114 may be located in the high-end region HVR. In some embodiments, the doping concentrations of the first well 112 and the second well 114 may be lower than the doping concentrations of the second buried layers 106 and 108.

[0074] As Figure 2 shown, in some embodiments, a third well 120 having a first conductivity type (P-type) may be formed in the substrate 100. In some embodiments, the third well 120 may include a first portion 122 and a second portion 124, and a part of the first portion 122 and a part of the second portion 124 may be arranged parallel to each other. In some embodiments, the third well 120 may be formed by performing the foregoing ion implantation, diffusion process, thermal drive-in process, and / or rapid thermal annealing process. As Figure 2 shown, in some embodiments, the third well 120 may further include a third portion 123 physically connected to the first portion 122 and the second portion 124. In some embodiments, the third portion 123 may directly contact the first portion 122 and the second portion 124. In some embodiments, since the first portion 122, the second portion 124, and the third portion 123 may be parts of the third well 120 respectively or may form the third well 120, the first portion 122, the second portion 124, and the third portion 123 may have substantially the same doping concentration.

[0075] As Figure 2 shown, in some embodiments, a fourth well 116 having a second conductivity type (N-type) different from the first conductivity type may be formed in the substrate 100, and the fourth well 116 may be located between the first well 112 and the second well 114. In some embodiments, the fourth well 116 may be formed by performing the foregoing ion implantation, diffusion process, thermal drive-in process, and / or rapid thermal annealing process. In some embodiments, the fourth well 116 may be located in the intermediate region IR. In some embodiments, the fourth well 116 and the first well 112 and the second well 114 may be formed substantially in the same process track, or may be formed in different process tracks. In other words, the first well 112, the second well 114, and the fourth well 116 may have substantially the same or different doping concentrations.

[0076] In some embodiments, the fourth well 116 may be between the first well 112 and the second well 114. In some embodiments, the fourth well 116 may be disposed between the first portion 122 and the second portion 124 of the third well 120. In some embodiments, at least three sides of the fourth well 116 are surrounded by the third well 120. In some embodiments, the first portion 122 of the third well 120 may be located between the first well 112 and the fourth well 116, and the second portion 124 of the third well 120 may be located between the second well 114 and the fourth well 116. In some embodiments, the first portion 122 and the second portion 124 of the third well 120 directly contact the fourth well 116. In some embodiments, the third portion 123 of the third well 120 is spaced apart from the fourth well 116 by a distance.

[0077] As Figure 2 shown, in some embodiments, a well 126 of the first conductivity type (P-type) may be further formed in the substrate 100. In some embodiments, the well 126 may be disposed in the low voltage region LVR. In some embodiments, the well 126 may be formed by performing the aforementioned ion implantation, diffusion process, thermal drive-in process, and / or rapid thermal annealing process. In some embodiments, the well 126 and the third well 120 may be formed substantially in the same process step, or may be formed in different process steps. In some embodiments, the doping concentration of the well 126 may be greater than the doping concentration of the third well 120.

[0078] As Figure 2 shown, in some embodiments, the active regions of the semiconductor device are defined on the substrate 100, and the isolation layer 200 is formed according to the positions of the active regions. In some embodiments, the isolation layer 200 may be formed on the substrate 100. In some embodiments, the isolation layer 200 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, analogs thereof, or combinations thereof, but the present disclosure is not limited thereto. For example, the isolation layer 200 may include a field oxide. In some embodiments, the isolation layer 200 may be formed by local oxidation of silicon (LOCOS) formed by thermal oxidation.

[0079] As Figure 2As shown, in some embodiments, a gate electrode 130 may be formed on a substrate 100. In some embodiments, the gate electrode 130 may be disposed on both the low - voltage region LVR and the intermediate region IR. In some embodiments, a portion of the gate electrode 130 may be disposed on the isolation layer 200. In some embodiments, the gate electrode 130 may include amorphous silicon, polysilicon, metal, metal nitride, conductive metal oxide, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the gate electrode 130 may be formed by a chemical vapor deposition (CVD) process, sputtering, resistance - heating evaporation, electron - beam evaporation, the like, or a combination thereof.

[0080] As Figure 2 shown, in some embodiments, a first doped region 142 having a first conductivity type (P) may be formed in the fourth well 116. In some embodiments, the first doped region 142 may be formed by performing the foregoing ion implantation, diffusion process, thermal drive - in process, and / or rapid thermal annealing process. In some embodiments, doped regions 144, 146 having a first conductivity type (P) may be further formed in the well 126. In some embodiments, the doped regions 144, 146 may be electrically connected to each other. In some embodiments, the doped regions 144, 146 may be grounded. In some embodiments, the doped regions 144, 146 and the first doped region 142 may be formed substantially in the same process step, or may be formed in different process steps. In some embodiments, the doping concentration of the first doped region 142, the doped regions 144, 146 may be greater than the doping concentration of the well 126.

[0081] As Figure 2 shown, in some embodiments, a second doped region 152 having a second conductivity type (N) and a third doped region 154 may be respectively formed in the first well 112 and the second well 114. In some embodiments, the doping concentration of the second doped region 152 and the third doped region 154 may be greater than the doping concentration of the first well 112 and the second well 114. As Figure 2 shown, in some embodiments, a doped region 156 having a second conductivity type (N) may be further formed in the well 126. In some embodiments, the doped region 156 and the second doped region 152 and the third doped region 154 may be formed substantially in the same process step, or may be formed in different process steps. In some embodiments, the doped region 156 may serve as the source of the level shifter LS, and the second doped region 152 may serve as the drain of the level shifter LS.

[0082] As Figure 2As shown, in some embodiments, in the third direction D3, the bottom surface of the first doped region 142 and the bottom surface of the fourth well 116 may be spaced apart by a distance. Accordingly, the first doped region 142 can enhance the breakdown voltage resistance. In some embodiments, in the first direction D1, one side surface of the first doped region 142 and the first portion 122 of the third well 120 may be spaced apart by a distance, and the other side surface of the first doped region 142 and the second portion 124 of the third well 120 may be spaced apart by a distance. In some embodiments, depending on the dimensional relationship between the first portion 122, the second portion 124, and the first doped region 142, the doping concentration of the first doped region 142 may be greater than, less than, or equal to the doping concentrations of the first portion 122 and the second portion 124.

[0083] As Figure 2 shown, in some embodiments, in the second direction D2, the first portion 122 of the third well 120 may have a width w122, the second portion 124 of the third well 120 may have a width w124, and the first doped region 142 may have a width w142. In some embodiments, the width w122 may be substantially the same as the width w124, and the width w122 and the width w124 may be greater than the width w142. In this embodiment, the doping concentration of the first doped region 142 may be less than the doping concentrations of the first portion 122 and the second portion 124.

[0084] As Figure 2 shown, in some embodiments, in the second direction D2, the first portion 122 of the third well 120, the second portion 124 of the third well 120, and the fourth well 116 may have a total width w, the third portion 123 may have a width w123, and the total width w may be greater than the width w123. In some embodiments, the ratio of the width w123 to the total width w (width w123 / total width w) may be between 0.1 and 0.8. For example, the ratio of the width w123 to the total width w may be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, or any value between the foregoing values or any range of values composed of any of the foregoing values, but the present disclosure is not limited thereto.

[0085] As Figure 2As shown, in some embodiments, the first part 122 and the second part 124 of the third well 120 may extend along the first direction D1 and in a direction opposite to the second direction D2. In some embodiments, the first part 122 and the second part 124 of the third well 120 may have a pair of bent shapes parallel to each other. In some embodiments, the third part 123 of the third well 120 may extend along the first direction D1. In some embodiments, the third well 120 may have a Y shape, a fork shape, a shape with at least two branch parts, or other similar shapes, but the present disclosure is not limited thereto. In some embodiments, the fourth well 116 may be disposed between at least two branch parts of the third well 120. In some embodiments, the third part 123 of the third well 120 may have a linear shape, an elongated shape, a trapezoidal shape, a stepped shape, a convex shape, or other similar shapes, but the present disclosure is not limited thereto. In some embodiments, the fourth well 116 may extend along the first direction D1 and in a direction opposite to the second direction D2. In some embodiments, the fourth well 116 may include a pair of bent parts parallel to each other, and a first doping region 142 is inserted in the pair of bent parts.

[0086] As Figure 2 shown, in some embodiments, the end of the first part 122 of the third well 120 near the low-end region LVR and the end of the second part 124 of the third well 120 near the low-end region LVR may be spaced apart from the third doping region 154 by a first distance s1. In some embodiments, the first part 122 and the second part 124 of the third well 120 may be closer to the low-end region LVR than the third doping region 154. As Figure 2 shown, in some embodiments, the end of the fourth well 116 and the end of the first doping region 142 may be substantially flush. In some embodiments, the end of the fourth well 116 near the low-end region LVR and the end of the first doping region 142 near the low-end region LVR may be spaced apart from the third doping region 154 by a second distance s2. In some embodiments, the fourth well 116 and the first doping region 142 may be closer to the low-end region LVR than the third doping region 154. In some embodiments, the first distance s1 may be greater than the second distance s2.

[0087] As Figure 2 shown, the region intercepted along the line segment A-A' may be shown as a high voltage difference region. Specifically, the line segment A-A' may span from the level shifter LS across the isolation structure ISO and the high-voltage junction terminal HVJT to the high-end region HVR, and thus has a relatively high voltage value and a relatively high voltage difference value. In some embodiments, the voltage V A and the voltage V A’The pick-up voltages for the second doped region 152 and the third doped region 154 respectively. Herein, the pick-up voltage in an element or a region represents a potential that is the same as the potential of the element or the region.

[0088] In some embodiments, for example, the voltage V A can be 600 volts (V), and the voltage V A’ can be 620 volts, and the voltage V A and the voltage V A’ can have a voltage difference of 20 volts. In a high voltage difference region, in order to improve the charge distribution to increase the breakdown voltage, reduce the leakage current, increase the breakdown resistance and / or increase the reliability, the present disclosure provides a P-N-P-N-P isolation structure ISO including alternately arranged P-type elements and N-type elements. Wherein, a first portion 122 of the third well 120 can form a P-N junction with the fourth well 116 to form a depletion region. A portion (e.g., the left portion) of the fourth well 116 can form an N-P junction with the first doped region 142 to form a depletion region. The first doped region 142 can form a P-N junction with another portion (e.g., the right portion) of the fourth well 116 to form a depletion region. The fourth well 116 can form an N-P junction with a second portion 124 of the third well 120 to form a depletion region. Accordingly, a P-N-P-N-P isolation structure ISO can be formed between the first well 112 and the second well 114, and the charge distribution can be improved by the formed plurality of depletion regions.

[0089] Furthermore, the first well 112 can further form an N-P junction with the first portion 122 of the third well 120 to form a depletion region. The second portion 124 of the third well 120 can further form a P-N junction with the second well 114 to form a depletion region. In addition, since the first buried layer 102 can be in direct contact with the first portion 122 of the third well 120, the first buried layer 102 can further increase the P-type concentration. Since the first buried layer 104 can be in direct contact with the second portion 124 of the third well 120, the first buried layer 104 can also further increase the P-type concentration. Accordingly, the charge distribution can be improved by adjusting the doping concentrations and sizes of the first well 112, the second well 114, the third well 120, the fourth well 116, the first doped region 142, the first buried layers 102 and 104.

[0090] As Figure 2 shown, since the voltages provided at different positions of the third doped region 154 are the same, the voltage V A’ and the voltage V A”May be substantially the same, and a P-N-P-N-P isolation structure ISO may be provided in the region intercepted along line segment A-A". In other words, in the region where the third doping region 154 surrounds the level shifter LS, a P-N-P-N-P isolation structure ISO is formed to enhance the electrical isolation characteristics. For example, the P-N-P-N-P isolation structure ISO may be provided in a sector-like or rectangle-like region surrounded by line segment A-A', line segment A-A", and the third doping region 154 to enhance the electrical isolation characteristics in the high voltage difference region.

[0091] As Figure 2 shown, the region intercepted along line segment B-B' may be shown as a low voltage difference region. Specifically, line segment B-B' spans from the level shifter LS across the isolation structure ISO to the high voltage junction terminal HVJT, and thus has a relatively low voltage value and a relatively low voltage difference. In some embodiments, voltage V B and voltage V B’ may be the pick-up voltages of the first well 112 and the second well 114 respectively. In some embodiments, voltage V B may be less than voltage V A， and voltage V B’ may be less than voltage V A’ . In some embodiments, for example, voltage V B may be 10 volts (V), voltage V B’ may be 20 volts, and the voltage difference between voltage V B and voltage V B’ is 10 volts. In the low voltage difference region, in order to improve the charge distribution to enhance the breakdown voltage, reduce the leakage current, enhance the breakdown resistance, enhance the reliability and / or enhance the process margin, the present disclosure provides a single P-type isolation structure ISO with a simple structure. Among them, a N-P junction is formed between the first well 112 and the third part 123 of the third well 120, and a depletion region is formed. A N-P junction is formed between the second well 114 and the third part 123 of the third well 120, and a depletion region is formed. Accordingly, a single P-type isolation structure ISO can be formed between the first well 112 and the second well 114, and the charge distribution can be improved by the formed multiple depletion regions. Among them, since the structure of the third part 123 of the third well 120 is simple, the process margin can be enhanced.

[0092] Referring to Figure 3 , which is a cross-sectional schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure. Among them, Figure 3 shows the cross-section intercepted along line segment A-A' as shown in Figure 2 . As Figure 3As shown, in some embodiments, the first buried layer 102 may be disposed between the first portion 122 of the third well 120 and the substrate 100, and the first buried layer 104 may be disposed between the second portion 124 of the third well 120 and the substrate 100. In some embodiments, the second buried layer 106 may be disposed between the first well 112 and the substrate 100, and the second buried layer 108 may be disposed between the second well 114 and the substrate 100. In some embodiments, the isolation structure ISO may be interposed between the second doped region 152 and the third doped region 154. In other words, the first portion 122 and the second portion 124 of the third well 120 and the fourth well 116 may be interposed between the second doped region 152 and the third doped region 154. Thus, in the cross-sectional view, between the second doped region 152 and the third doped region 154, there may be an isolation structure ISO including a double P well.

[0093] As Figure 3 shown, in some embodiments, a dielectric layer 300 may be further formed on the isolation layer 200. In some embodiments, the dielectric layer 300 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, analogs thereof, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the dielectric layer 300 may serve as an interlayer dielectric layer. As Figure 3 shown, in some embodiments, a contact 302 electrically connected to the second doped region 152 may be formed, and the contact 302 may penetrate the dielectric layer 300. In some embodiments, a contact 304 electrically connected to the third doped region 154 may be formed, and the contact 304 may penetrate the dielectric layer 300. In some embodiments, the contact 302 and the contact 304 may be electrically connected to each other with an external load or an external resistor.

[0094] Referring Figure 4 to Figure 4 which is a cross-sectional schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure. Wherein, Figure 2 shows a cross-section taken along the line B-B' as shown. In some embodiments, a first buried layer 103 may be further disposed between the third portion 123 of the third well 120 and the substrate 100. In some embodiments, the material and formation method of the first buried layer 103 may be the same as or different from those of the first buried layers 102 and 104. In some embodiments, the first buried layer 103 and the first buried layers 102 and 104 may be formed in substantially the same process step, or may be formed in different process steps. In some embodiments, there may be substantially no interface between the first buried layer 102, 103, and 104, and they may be integrally formed as the same component. Thus, in the cross-sectional view, between the first well 112 and the second well 114, there may be an isolation structure ISO including a P strip.

[0095] Therefore, the isolation structure ISO of the semiconductor device 1 disclosed herein may include a P-N-P-N-P isolation structure and a single P-type isolation structure.

[0096] Hereinafter, the same or similar element symbols or descriptions are omitted.

[0097] Referring to Figure 5 , which is a perspective view of a semiconductor device 2 according to an embodiment of the present disclosure. In some embodiments, in a direction opposite to the first direction D1, the first doped region 142 may have a protruding portion 142P protruding from the fourth well 116. In some embodiments, compared with the end of the fourth well 116, the end of the first doped region 142 may be closer to the low voltage region LVR. Accordingly, the electrical isolation characteristics at the line segment C-C' can be improved and the process margin for forming the first doped region 142 can be improved.

[0098] As Figure 5 shown, the region intercepted along the line segment C-C' may be shown as a middle voltage difference region. Specifically, the line segment C-C' extends from the level shifter LS across the isolation structure ISO to the high voltage junction terminal HVJT, and compared with the line segment B-B', the line segment C-C' may be farther from the low voltage region LVR, so it may have a middle voltage value and a middle voltage difference. In some embodiments, the voltage V C and the voltage V C’ may be the pick-up voltages of the first well 112 and the second well 114 respectively. In some embodiments, the voltage V C may be greater than the voltage V B and less than the voltage V A， and the voltage V C’ may be greater than the voltage V B’ and less than the voltage V A’ . In some embodiments, for example, the voltage V c may be 435 volts (V), and the voltage V c’ may be 450 volts, and the voltage difference between the voltage V c and the voltage V c’ is 15 volts. And in the middle voltage difference region, in order to improve the charge distribution, the present disclosure provides a P-P - -P isolation structure ISO with P-type elements having different doping concentrations to increase the breakdown voltage, reduce the leakage current, improve the breakdown resistance, improve the reliability and / or improve the process margin.

[0099] Among them, in the embodiment where the doping concentration of the first doped region 142 as described above is less than that of the third well 120, the first part 122 of the third well 120 and the protruding portion 142P of the first doped region 142 form a P-P -junction, and the protruding portion 142P of the first doped region 142 forms a P - -P junction with the second portion 124 of the third well 120. Accordingly, a P-P - -P isolation structure ISO can be formed between the first well 112 and the second well 114 to improve the charge distribution and enhance the breakdown resistance. Furthermore, the first well 112 and the first portion 122 of the third well 120 form an N-P junction to form a depletion region. The second portion 124 of the third well 120 and the second well 114 form a P-N junction to form a depletion region. Accordingly, the charge distribution can be improved by the plurality of depletion regions formed. In addition, since the protruding portion 142P can protrude from the third well 120, the process margin for forming the protruding portion 142P can be enhanced.

[0100] Referring to Figure 6 , which is a cross-sectional schematic diagram of a semiconductor device 2 according to an embodiment of the present disclosure. Among them, Figure 6 shows a cross-section taken along the line C-C' shown in Figure 5 . As Figure 6 shown, since the first portion 122, the second portion 124, and the first doped region 142 with different doping concentrations are disposed between the first well 112 and the second well 114, the electrical isolation characteristics of the isolation structure ISO can be enhanced.

[0101] Therefore, the isolation structure ISO of the semiconductor device 2 of the present disclosure may include a P-N-P-N-P isolation structure, a P-P--P isolation structure, and a single P-type isolation structure arranged in sequence.

[0102] Referring to Figure 7 , which is a three-dimensional schematic diagram of a semiconductor device 3 according to an embodiment of the present disclosure. As Figure 7 shown, in some embodiments, the third portion 123 of the third well 120 may have a width that decreases along a direction opposite to the first direction D1 (for example, as Figure 1The width w123 shown). For example, the reduced width can be a linearly reduced width, a stepwise reduced width, or a width reduced in other ways. In some embodiments, the third portion 123 of the third well 120 can have a first side connected to the first portion 122 and the second portion 124 and a second side opposite the first side. Among them, the first side and the second side are opposite to each other in the first direction D1. In some embodiments, the first side width w1 of the first side of the third portion 123 of the third well 120 can be greater than the second side width w2 of the second side of the third portion 123 of the third well 120. In other words, the first side width w1 can be the width of the third portion 123 adjacent to the high-voltage region HVR, and the second side width w2 can be the width of the third portion 123 adjacent to the low-voltage region LVR. Therefore, the width of the third portion 123 adjacent to the low-voltage region LVR can be smaller than the width of the third portion 123 adjacent to the high-voltage region HVR. Accordingly, the width of the third portion 123 of the third well 120 can be adjusted according to different pressure differences. For example, a narrower third portion 123 is provided in a relatively low-pressure region (or low-pressure difference region), and a wider third portion 123 is provided in a relatively high-pressure region (or high-pressure difference region) to adjust the charge distribution.

[0103] Therefore, the isolation structure ISO of the semiconductor device 3 disclosed herein can include a P-N-P-N-P isolation structure, a P-P - -P isolation structure, and a single P-type isolation structure with different widths arranged in sequence.

[0104] In some embodiments, a further process can be performed on any one of the semiconductor devices 1 to 3 to form a high-voltage integrated circuit (HVIC). In some embodiments, the semiconductor devices 1 to 3 disclosed herein can be used in any combination. In some embodiments, the top view of the semiconductor device can be combined with the cross-sectional view of the semiconductor device arbitrarily.

[0105] Accordingly, the isolation structure of the semiconductor device disclosed herein can simultaneously include isolation structures with different junction structures to correspond to adjusting the electric field distribution in regions with different pressure differences. In a high-pressure difference region, a first portion, a second portion, a fourth well, and a first doping region are provided herein to form a P-N-P-N-P isolation structure including alternately arranged P-type elements and N-type elements. In a medium-pressure difference region, a first portion, a second portion, and a first doping region are provided herein to form a P-P --P isolation structure. In the low voltage difference region, the present disclosure forms a single P-type isolation structure by having a third part. Therefore, the present disclosure can improve the electrical isolation characteristics between components. For example, the electrical isolation characteristics are improved by creating a depletion region in the isolation structure. Furthermore, the present disclosure can improve the charge distribution to balance the charges, thereby increasing the breakdown voltage, reducing the leakage current, increasing the breakdown resistance, increasing the reliability, and / or increasing the process margin.

[0106] The protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps in the specific embodiments described in the specification. Any person skilled in the art in the relevant technical field can understand the processes, machines, manufactures, compositions of matter, devices, methods, and steps developed currently or in the future from the disclosed content of the present disclosure. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the protection scope of the present disclosure includes the aforementioned processes, machines, manufactures, compositions of matter, devices, methods, and steps. Any embodiment or claim of the present disclosure does not have to achieve all the purposes, advantages, and / or features described in the present disclosure.

[0107] The above outlines several embodiments so that those skilled in the art in the relevant technical field of the present disclosure can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art in the relevant technical field of the present disclosure should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art in the relevant technical field of the present disclosure should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate having a first conductivity type; A first well and a second well having a second conductivity type different from the first conductivity type and disposed in the substrate; And An isolation structure disposed between the first well and the second well, comprising: A third well having the first conductivity type and including a first portion and a second portion; A fourth well having the second conductivity type and disposed between the first portion and the second portion of the third well; and A first doped region having the first conductivity type and disposed in the fourth well.

2. The semiconductor device according to claim 1, wherein, Further comprising: A first buried layer having the first conductivity type disposed between the first portion of the third well and the substrate and between the second portion of the third well and the substrate.

3. The semiconductor device according to claim 1, wherein Further comprising: A second buried layer having the second conductivity type disposed between the first well and the substrate and between the second well and the substrate.

4. The semiconductor device according to claim 1, characterized in that, Further comprising: A second doped region having the second conductivity type disposed in the first well; and A third doped region having the second conductivity type disposed in the second well.

5. The semiconductor device according to claim 4, wherein, The isolation structure is between the second doped region and the third doped region.

6. The semiconductor device according to claim 1, wherein, The third well further comprises: A third portion connecting the first portion and the second portion, wherein the third portion of the third well is spaced apart from the fourth well by a distance.

7. The semiconductor device according to claim 6, wherein, In a top view, the total width of the first portion of the third well, the second portion of the third well, and the fourth well is greater than the width of the third portion of the third well.

8. The semiconductor device according to claim 6, wherein, In a top view, the third portion has a first side connected to the first portion and the second portion and a second side opposite the first side, and a first side width of the first side is greater than a second side width of the second side.

9. The semiconductor device according to claim 1, wherein, In a top view, the first doped region has a protruding portion protruding from the fourth well.

10. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate having a first conductivity type; Forming a first well and a second well having a second conductivity type different from the first conductivity type in the substrate; And Forming an isolation structure between the first well and the second well, wherein the isolation structure comprises: A third well having the first conductivity type and including a first portion and a second portion; A fourth well having the second conductivity type and disposed between the first portion and the second portion of the third well; and A first doped region having the first conductivity type and disposed in the fourth well.

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