Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a substrate; forming a fuse wire material layer on the substrate, etching the fuse wire material layer to form a fusing part of the fuse wire structure, leading-out areas located at the two ends of the fusing part and auxiliary structures located at the two sides of the fusing part, and forming grooves between the auxiliary structures and the fusing part; and forming a dielectric material layer to fill the groove so as to form a gap in the groove. The auxiliary structures are formed on the two sides of the fusing part of the fuse structure, the gap is formed between the fusing part and the auxiliary structures, the gap serves as a buffer space, the fusing uniformity of the fuse can be improved, damage and influence on surrounding devices when the fuse bursts are weakened, and the safety of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the continuous development of semiconductor technology, the electrically programmable fuse structure (E-fuse) is widely used in the field of integrated circuits and is an important part of integrated circuits. It is generally used for purposes such as circuit and data protection. The polysilicon fuse that is blown by a large current is a relatively common fuse structure.

[0003] With the continuous improvement of chip integration, the influence of process defects is also increasing. Using the fuse programming mechanism, defective chips can be quickly adjusted and replaced, which can effectively improve the product yield and reliability. The polysilicon fuse is composed of a polysilicon layer and a metal silicide layer in parallel, and its programming mechanisms include electromigration and thermal fusing. The electromigration mechanism is that the metal atoms of the metal silicide migrate along the crystal grains from the cathode to the anode under the action of a large number of electrons, and atomic accumulation is likely to form a "bulge" at the anode, which may affect the surrounding devices. The thermal fusing mechanism is to heat the fuse and cause an irreversible phase change to increase the resistance value. When a large current is injected in a short time, the polysilicon fuse is prone to local overheating and fuse bursting, which may cause irreversible damage or contamination to the surrounding devices. Summary of the Invention

[0004] Based on this, in view of the problems in the above background art, it is necessary to provide a semiconductor device and a method for manufacturing the same, which can at least improve the uniformity of fuse fusing and weaken the damage and influence on the surrounding devices when the fuse bursts, and improve the safety of the semiconductor device.

[0005] To achieve the above object and other related objects, one aspect of the present application provides a method for manufacturing a semiconductor device, including the following steps:

[0006] Provide a substrate;

[0007] Form a fuse material layer on the substrate, and etch the fuse material layer to form a fusing portion of the fuse structure, lead-out regions located at both ends of the fusing portion, and auxiliary structures located on both sides of the fusing portion. A groove is formed between the auxiliary structure and the fusing portion;

[0008] Form a dielectric material layer to fill the groove to form a void in the groove.

[0009] In one embodiment, the width of the groove is equal to the distance Δx between the auxiliary structure and the fusing portion, the depth of the groove is equal to the thickness H of the fusing portion, and the width of the groove is less than the depth of the groove.

[0010] In one embodiment, a gas-phase deposition process is performed to form a dielectric material layer, and the gas-phase deposition process includes at least one of a high-density plasma chemical vapor deposition process, a high aspect ratio chemical vapor deposition process, and a flowing chemical vapor deposition process.

[0011] In one embodiment, the aspect ratio of the trench exceeds the filling limit of the gas-phase deposition process to form a void in the trench:

[0012] When the high-density plasma chemical vapor deposition process is used, Δx < H;

[0013] When the high aspect ratio chemical vapor deposition process is used, Δx < H;

[0014] When the flowing chemical vapor deposition process is used, Δx < H.

[0015] In one embodiment, the lead-out region includes a first lead-out region and a second lead-out region that are respectively located at both ends of the fuse portion in a first direction, and the lead-out region is connected to the fuse portion; the auxiliary structure includes a first auxiliary structure and a second auxiliary structure that are respectively located on both sides of the fuse portion in a second direction, the auxiliary structure is separated from the fuse portion, and the auxiliary structure is separated from the lead-out region.

[0016] In one embodiment, the auxiliary structure includes an integral structure, or the auxiliary structure is composed of a plurality of separated sub-auxiliary structures.

[0017] In one embodiment, the fuse material layer includes a polysilicon layer.

[0018] On the other hand, the present invention provides a semiconductor device, including:

[0019] A substrate;

[0020] A fuse structure disposed on the substrate, the fuse structure includes a fuse portion, lead-out regions located at both ends of the fuse portion, and auxiliary structures located on both sides of the fuse portion, and there is a void between the auxiliary structure and the fuse portion.

[0021] In one embodiment, the void is surrounded by a dielectric material layer between the auxiliary structure and the fuse portion.

[0022] In one embodiment, the distance between the auxiliary structure and the fuse portion is less than the thickness of the fuse portion.

[0023] According to the semiconductor device and its manufacturing method provided by the present invention, by forming auxiliary structures on both sides of the fuse portion of the fuse structure, a void is formed between the fuse portion and the auxiliary structure, and the void can be used as a buffer space to improve the uniformity of fuse melting and weaken the damage and influence on surrounding devices when the fuse bursts, thereby improving the safety of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To better describe and illustrate the embodiments and / or examples of those applications disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the presently described embodiments and / or examples, and the presently understood best mode of these applications.

[0025] Figure 1 It is a flowchart of a method for fabricating a semiconductor device provided in an embodiment;

[0026] Figure 2A It is a schematic cross-sectional structure diagram of the obtained structure after forming a fuse material layer on a substrate in step S102 of a method for fabricating a semiconductor device provided in an embodiment;

[0027] Figure 2B It is a schematic cross-sectional structure diagram of the obtained structure after forming a fuse structure in step S102 of a method for fabricating a semiconductor device provided in an embodiment;

[0028] Figure 2C It is a schematic cross-sectional structure diagram of the obtained structure after forming a dielectric material layer in step S103 of a method for fabricating a semiconductor device provided in an embodiment;

[0029] Figure 3 It is a schematic cross-sectional diagram of a fuse structure in a semiconductor device provided in an embodiment;

[0030] Figure 4 It is a schematic cross-sectional diagram of another fuse structure in a semiconductor device provided in an embodiment;

[0031] Figure 5 It is a schematic cross-sectional diagram of yet another fuse structure in a semiconductor device provided in an embodiment.

[0032] DESCRIPTION OF REFERENCE NUMERALS:

[0033] 200, substrate; 210, fuse material layer; 211, fusing part; 212, lead-out area; 213, auxiliary structure; 214, trench; 215, metal silicide; 216, contact plug; 220, dielectric material layer; 230, void. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing particular embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of this application.

[0037] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented as "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0039] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. Thus, variations from the shapes shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present application.

[0040] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0041] The polysilicon fuse is formed by connecting a polysilicon layer and a metal silicide layer in parallel, and its programming mechanisms include electromigration and thermal fusing. The electromigration mechanism is that the metal atoms of the metal silicide migrate along the crystal grains from the cathode to the anode under the action of a large number of electrons, and atomic accumulation is likely to form a "bulge" at the anode, which may affect the surrounding devices. The thermal fusing mechanism is to heat the fuse and cause an irreversible phase change to increase the resistance value. When a large current is injected in a short time, the polysilicon fuse is prone to local overheating, resulting in the fuse bursting, which may cause irreversible damage or contamination to the surrounding devices.

[0042] In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, as Figure 1 shown, comprising the following steps:

[0043] Step S101: Providing a substrate;

[0044] Step S102: Forming a fuse material layer on the substrate, etching the fuse material layer to form a fusing portion of the fuse structure, lead-out regions located at both ends of the fusing portion, and auxiliary structures located on both sides of the fusing portion, and a trench is formed between the auxiliary structure and the fusing portion;

[0045] Step S103: Form a dielectric material layer to fill the trench, so as to form voids in the trench.

[0046] First, perform step S101. Referring to Figure 2A as shown, provide a substrate 200.

[0047] In one embodiment, the substrate 200 can provide an operating platform for subsequent processes. It can be any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components, which can be a bare die or a wafer after epitaxial growth process. Specifically, the substrate 200 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.

[0048] Then, perform step S102. Referring to Figure 2A to Figure 2B as shown, form a fuse material layer 210 on the substrate 200, etch the fuse material layer 210 to form a fusing part 211 of the fuse structure, lead-out regions 212 located at both ends of the fusing part 211, and auxiliary structures 213 located on both sides of the fusing part 211. A trench 214 is formed between the auxiliary structure 213 and the fusing part 211.

[0049] In one embodiment, before forming the fuse material layer 210 on the substrate 200, it further includes the step of forming an isolation layer (not shown) on the surface of the substrate 200 for isolating the substrate 200 from the fuse material layer 210. The isolation layer can be a shallow trench isolation structure (STI) or a local oxidation of silicon (LOCOS) isolation region, or a dielectric material such as silicon oxide. The present application does not limit this.

[0050] In one embodiment, referring to Figure 2A as shown, form a fuse material layer 210 on the substrate 200. The fuse material layer 210 includes but is not limited to a polysilicon layer. Processes well-known to those skilled in the art, such as chemical vapor deposition (CVD), can be used to form the fuse material layer 210, which will not be elaborated here.

[0051] In one embodiment, referring to Figure 2BAs shown, the fuse material layer 210 is etched to form a fusing portion 211 of the fuse structure, lead-out regions 212 located at both ends of the fusing portion 211, and auxiliary structures 213 located on both sides of the fusing portion 211. A trench 214 is formed between the auxiliary structure 213 and the fusing portion 211. Specifically, a photolithography process is first performed to form a patterned mask layer on the fuse material layer 210, and then dry etching is performed using the patterned mask layer as a mask to simultaneously form the fusing portion 211, the lead-out regions 212 located at both ends of the fusing portion 211, and the auxiliary structures 213 located on both sides of the fusing portion 211. The dry etching process includes, but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. A single etching method can be used, or more than one etching method can also be used.

[0052] In one embodiment, referring to Figure 2B As shown, a trench 214 is formed between the auxiliary structure 213 and the fusing portion 211 after the etching process is performed. The trench 214 penetrates through the fuse material layer 210 to disconnect the connection between the auxiliary structure 213 and the fusing portion 211. In addition, the distance between the auxiliary structure 213 and the fusing portion 211 is represented by Δx. The width of the trench 214 is equal to the distance Δx between the auxiliary structure 213 and the fusing portion 211. The thickness of the fusing portion 211 is represented by H. The thickness of the auxiliary structure 213 is equal to the thickness H of the fusing portion, and the depth of the trench 214 is also equal to the thickness of the fusing portion 211. The formed trench 214 is a high aspect ratio trench. Therefore, the depth of the trench 214 is at least greater than the width of the trench, that is, H>Δx.

[0053] In one embodiment, referring to Figure 3 、 Figure 4 and Figure 5 As shown, the length of the fusing portion 211 is greater than the width of the fusing portion 211. Taking the length direction of the fusing portion 211 as the first direction and the width direction of the fusing portion 211 as the second direction, the lead-out regions 212 include a first lead-out region and a second lead-out region respectively located at both ends of the fusing portion 211 in the first direction. The lead-out regions 212 are both connected to the fusing portion 211 to form a fuse structure. The fusing portion 211 is the middle part of the fuse structure. The lead-out regions 212 are used to lead out the fuse structure. Since the resistance value is larger at positions with smaller distances in the fuse structure, the width of the fusing portion 211 is the smallest distance in the fuse structure. The widths of the lead-out regions 212 in the second direction are both greater than the width of the fusing portion 211. Further, in order to achieve a uniform transition of the resistance value between the lead-out regions 212 and the fusing portion 211 and avoid optical pattern abnormalities, the widths of the first lead-out region and the second lead-out region in the second direction gradually decrease from both sides to the middle and smoothly transition to the width of the fusing portion 211.

[0054] In one embodiment, referring to Figure 3 、 Figure 4and Figure 5 As shown, the auxiliary structure 213 includes a first auxiliary structure and a second auxiliary structure respectively located on both sides of the fusing part 211 in the second direction. The auxiliary structures 213 are separated from the fusing part 211, that is, neither the first auxiliary structure nor the second auxiliary structure is connected to the fusing part 211. In addition, the auxiliary structure 213 is also separated from the lead-out area 212.

[0055] In one embodiment, the distance between the auxiliary structure 213 and the fusing part 211 is greater than or equal to the distance between the auxiliary structure 213 and the lead-out area 212. The auxiliary structure 213 is an integral structure or the auxiliary structure 213 is composed of a plurality of mutually separated sub-auxiliary structures. Refer to Figure 3 As shown, the distance between the auxiliary structure 213 and the fusing part 211 is equal to the distance between the auxiliary structure 213 and the lead-out area 212, and the distance between the auxiliary structure 213 and the fusing part 211 is equal everywhere, and the distance between the auxiliary structure 213 and the lead-out area 212 is equal everywhere. Both the first auxiliary structure and the second auxiliary structure are integral structures, and the cross-sectional shapes of the first auxiliary structure and the second auxiliary structure are trapezoidal. Refer to Figure 4 As shown, the auxiliary structure 213 is only provided on both sides of the fusing part 211, and the distance between the auxiliary structure 213 and the fusing part 211 is greater than the distance between the auxiliary structure 213 and the lead-out area 212. The distance between the auxiliary structure 213 and the fusing part 211 is equal everywhere. Both the first auxiliary structure and the second auxiliary structure are integral structures, and the cross-sectional shapes of the first auxiliary structure and the second auxiliary structure are rectangular. Refer to Figure 5 As shown, the auxiliary structure 213 is only provided on both sides of the fusing part 211. Both the first auxiliary structure and the second auxiliary structure are composed of a plurality of mutually separated sub-auxiliary structures, and the distance between each sub-auxiliary structure and the fusing part 211 is equal. In addition, the plurality of sub-auxiliary structures can be arranged at equal intervals, and the interval between adjacent sub-auxiliary structures can be equal to the distance between the sub-auxiliary structure and the fusing part 211. The cross-sectional shapes of the first auxiliary structure and the second auxiliary structure are a plurality of rectangles or squares arranged at intervals. It should be noted that Figure 3 、 Figure 4 and Figure 5 The auxiliary structure 213 shown is only exemplary, and the auxiliary structure 213 can also be subject to several deformations and improvements, and this application does not limit this.

[0056] Then step S103 is executed. Refer to Figure 2C As shown, a dielectric material layer 220 is formed to fill the trench 214, and a void 230 is formed in the trench 214.

[0057] In one embodiment, a gas-phase deposition process is performed to form the dielectric material layer 220, and the aspect ratio of the trench exceeds the filling limit of the gas-phase deposition process. Specifically, when forming the dielectric material layer 220 by using a High Density Plasma Chemical Vapor Deposition (HDP-CVD) process, it is necessary to control the aspect ratio of the trench 214 to be greater than 4, that is, Δx < H. At this time, the aspect ratio of the trench 214 exceeds the filling limit of the High Density Plasma Chemical Vapor Deposition (HDP-CVD) process, and the dielectric material layer 220 cannot be completely filled in the trench 214, but voids 230 will be formed in the trench 214. When forming the dielectric material layer 220 by using a High Aspect Ratio Process Chemical Vapor Deposition (HARP-CVD) process, it is necessary to control the aspect ratio of the trench 214 to be greater than 8, that is, Δx < H. At this time, the aspect ratio of the trench 214 exceeds the filling limit of the High Aspect Ratio Process Chemical Vapor Deposition (HARP-CVD) process, and the dielectric material layer 220 cannot be completely filled in the trench 214, but voids 230 will be formed in the trench 214. When forming the dielectric material layer 220 by using a Flowable Chemical Vapor Deposition (FCVD) process, it is necessary to control the aspect ratio of the trench 214 to be greater than 12, that is, Δx < H. At this time, the aspect ratio of the trench 214 exceeds the filling limit of the Flowable Chemical Vapor Deposition (FCVD) process, and the dielectric material layer 220 cannot be completely filled in the trench 214, but voids 230 will be formed in the trench 214. In other words, when the aspect ratio of the trench 214 is greater than 12, that is, Δx < H, any one of the High Density Plasma Chemical Vapor Deposition (HDP-CVD) process, the High Aspect Ratio Process Chemical Vapor Deposition (HARP-CVD) process, or the Flowable Chemical Vapor Deposition (FCVD) process can be used to form the dielectric material layer 220. When the aspect ratio of the trench 214 is greater than 8 but less than 12, that is, H < Δx < H, one of the High Density Plasma Chemical Vapor Deposition (HDP-CVD) process and the High Aspect Ratio Process Chemical Vapor Deposition (HARP-CVD) process can be used to form the dielectric material layer 220. When the aspect ratio of the trench 214 is greater than 4 but less than 8, that is, Δ H < Δx < H, the High Density Plasma Chemical Vapor Deposition (HDP-CVD) process can be used to form the dielectric material layer 220.

[0058] By setting the aspect ratio of the groove to exceed the filling limit of the chemical vapor deposition process for forming the dielectric material layer 220, a void can be formed in the groove between the fuse portion 211 and the auxiliary structure 213. This void can serve as a buffer space for the fuse structure triggering mechanism, avoiding damage to and influence on surrounding devices when the fuse bulges or bursts.

[0059] In one embodiment, it further includes the step of forming a metal silicide 215 on the top of the fuse portion 211 and the lead-out region 212. Specifically, after forming a metal layer on the upper surfaces of the fuse portion 211 and the lead-out region 212, an annealing process is performed to form a metal silicide on the top of the fuse portion 211 and the lead-out region 212. The step of forming the metal silicide 215 on the top of the fuse portion 211 can be carried out before step S103 or after step S103, and there is no limitation here.

[0060] In one embodiment, referring to Figure 3 to Figure 5 As shown, it further includes the step of forming a contact plug 216 on the lead-out region 212. Specifically, first, a photolithography process is performed to form a through hole in the dielectric material layer 220, exposing the metal silicide on the top of the lead-out region 212, and then a metal material is filled in the through hole to form the contact plug 216, which is used to lead out the fuse structure.

[0061] Thus far, the introduction of the related steps of the manufacturing method of the semiconductor device according to the embodiment of the present invention has been completed. It can be understood that the manufacturing method of the semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included within the scope of this manufacturing method.

[0062] The present invention also provides a semiconductor device, referring to Figure 2C 、 Figure 3 、 Figure 4 and Figure 5 As shown, it includes:

[0063] A substrate 200;

[0064] A fuse structure disposed on the substrate 200, the fuse structure includes a fuse portion 211, lead-out regions 212 located at both ends of the fuse portion 211, and auxiliary structures 213 located on both sides of the fuse portion 211. There is a void 230 between the auxiliary structure 213 and the fuse portion 211.

[0065] In one embodiment, the substrate 200 can provide an operating platform for subsequent processes. It can be any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components, which can be a die or a wafer processed by an epitaxial growth process. Specifically, the substrate 200 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanide-on-insulator (S-SiGeOI), silicon germanide-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. In one embodiment, the fuse structure disposed on the substrate 200 includes, but is not limited to, a polysilicon fuse.

[0066] In one embodiment, referring to Figure 3 、 Figure 4 and Figure 5 as shown, the distance between the auxiliary structure 213 and the fusing portion 211 is represented by Δx, the thickness of the fusing portion 211 is represented by H, the thickness of the auxiliary structure 213 is equal to the thickness H of the fusing portion, and the distance between the auxiliary structure 213 and the fusing portion 211 is less than the thickness of the fusing portion 211, that is, Δx < H. Specifically, Δx < H, Δx < H or Δx < H.

[0067] In one embodiment, referring to Figure 3 、 Figure 4 and Figure 5 as shown, the length of the fusing portion 211 is greater than the width of the fusing portion 211. Taking the length direction of the fusing portion 211 as the first direction and the width direction of the fusing portion 211 as the second direction, the lead-out region 212 includes a first lead-out region and a second lead-out region respectively located at both ends of the fusing portion 211 in the first direction. The lead-out region 212 is connected to the fusing portion 211 to form a fuse structure. The fusing portion 211 is the middle part of the fuse structure, and the lead-out region 212 is used to lead out the fuse structure. Since the resistance value is larger at the position with a smaller distance in the fuse structure, the width of the fusing portion 211 is the minimum distance in the fuse structure, and the widths of the lead-out region 212 in the second direction are both greater than the width of the fusing portion 211. Further, in order to achieve a uniform transition of the resistance value between the lead-out region 212 and the fusing portion 211 and avoid abnormal optical patterns, the widths of the first lead-out region and the second lead-out region in the second direction decrease from both sides to the middle in sequence and smoothly transition to the width of the fusing portion 211.

[0068] In one embodiment, referring to Figure 3 、 Figure 4 and Figure 5As shown, the auxiliary structure 213 includes a first auxiliary structure and a second auxiliary structure respectively located on both sides of the fusing part 211 in the second direction. The auxiliary structure 213 is separated from the fusing part 211, that is, neither the first auxiliary structure nor the second auxiliary structure is connected to the fusing part 211. In addition, the auxiliary structure 213 is also separated from the lead-out area 212.

[0069] In one embodiment, the distance between the auxiliary structure 213 and the fusing part 211 is greater than or equal to the distance between the auxiliary structure 213 and the lead-out area 212. The auxiliary structure 213 is an integral structure or the auxiliary structure 213 is composed of a plurality of mutually separated sub-auxiliary structures. Refer to Figure 3 As shown, the distance between the auxiliary structure 213 and the fusing part 211 is equal to the distance between the auxiliary structure 213 and the lead-out area 212, and the distance between the auxiliary structure 213 and the fusing part 211 is equal everywhere, and the distance between the auxiliary structure 213 and the lead-out area 212 is equal everywhere. Both the first auxiliary structure and the second auxiliary structure are integral structures, and the cross-sectional shapes of the first auxiliary structure and the second auxiliary structure are trapezoidal. Refer to Figure 4 As shown, the auxiliary structure 213 is only provided on both sides of the fusing part 211, and the distance between the auxiliary structure 213 and the fusing part 211 is greater than the distance between the auxiliary structure 213 and the lead-out area 212. The distance between the auxiliary structure 213 and the fusing part 211 is equal everywhere. Both the first auxiliary structure and the second auxiliary structure are integral structures, and the cross-sectional shapes of the first auxiliary structure and the second auxiliary structure are rectangular. Refer to Figure 5 As shown, the auxiliary structure 213 is only provided on both sides of the fusing part 211. Both the first auxiliary structure and the second auxiliary structure are composed of a plurality of mutually separated sub-auxiliary structures, and the distance between each sub-auxiliary structure and the fusing part 211 is equal. In addition, the plurality of sub-auxiliary structures can be arranged at equal intervals, and the interval between adjacent sub-auxiliary structures can be equal to the distance between the sub-auxiliary structure and the fusing part 211. The cross-sectional shapes of the first auxiliary structure and the second auxiliary structure are a plurality of rectangles or squares arranged at intervals. It should be noted that Figure 3 、 Figure 4 and Figure 5 The auxiliary structure 213 shown is only exemplary, and the auxiliary structure 213 can also be subject to several deformations and improvements, and this application does not limit this.

[0070] In one embodiment, there is a gap 230 between the auxiliary structure 213 and the fusing part 211. Further, the gap 230 is surrounded by a dielectric material layer 220 located between the auxiliary structure 213 and the fusing part 211. By forming a gap between the fusing part 211 and the auxiliary structure 213, this gap can serve as a buffer space for the fuse structure triggering mechanism to avoid damage and influence on surrounding devices when the fuse bulges or bursts.

[0071] The specific structure of the semiconductor device can be referred to the description in the corresponding part above. For the sake of brevity, it will not be elaborated here.

[0072] According to the semiconductor device and its manufacturing method provided by the present invention, by forming auxiliary structures on both sides of the fusing part of the fuse structure, a gap is formed between the fusing part and the auxiliary structures. The gap serves as a buffer space, which can improve the uniformity of fuse fusing and weaken the damage and influence on surrounding devices when the fuse bursts, thereby enhancing the safety of the semiconductor device.

[0073] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present application.

[0074] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0075] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0076] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes the following steps: Providing a substrate; Forming a fuse material layer on the substrate, and etching the fuse material layer to form a fusing portion of a fuse structure, lead-out regions located at two ends of the fusing portion, and auxiliary structures located on two sides of the fusing portion, wherein a trench is formed between the auxiliary structures and the fusing portion; Forming a dielectric material layer to fill the trench to form a void in the trench.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The width of the trench is equal to a distance Δx between the auxiliary structure and the fusing portion, the depth of the trench is equal to the thickness H of the fusing portion, and the width of the trench is less than the depth of the trench.

3. The manufacturing method of the semiconductor device according to claim 2, wherein, Performing a vapor deposition process to form the dielectric material layer, and the vapor deposition process includes at least one of a high density plasma chemical vapor deposition process, a high aspect ratio chemical vapor deposition process, and a flow chemical vapor deposition process.

4. The method for manufacturing a semiconductor device according to claim 3, wherein, The aspect ratio of the trench exceeds a filling limit of the vapor deposition process to form a void in the trench: When using a high-density plasma chemical vapor deposition process, Δx < H; When using a high aspect ratio chemical vapor deposition process, Δx < H; When a flowing chemical vapor deposition process is employed, Δx < H.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The lead-out regions include a first lead-out region and a second lead-out region respectively located at two ends of the fusing portion in a first direction, and the lead-out regions are connected to the fusing portion; the auxiliary structures include a first auxiliary structure and a second auxiliary structure respectively located on two sides of the fusing portion in a second direction, the auxiliary structures are separated from the fusing portion, and the auxiliary structures are separated from the lead-out regions.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The auxiliary structure includes an integral structure, or the auxiliary structure is composed of a plurality of sub-auxiliary structures separated from each other.

7. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The fuse material layer includes a polysilicon layer.

8. A semiconductor device, characterized in that, Comprising: A substrate; A fuse structure disposed on the substrate, the fuse structure including a fusing portion, lead-out regions located at two ends of the fusing portion, and auxiliary structures located on two sides of the fusing portion, wherein there is a void between the auxiliary structures and the fusing portion.

9. The semiconductor device according to claim 8, wherein, The void is surrounded by a dielectric material layer located between the auxiliary structure and the fusing portion.

10. The semiconductor device according to claim 8, wherein The distance between the auxiliary structure and the fusing portion is less than the thickness of the fusing portion.

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