Electrostatic protection structure and electronic equipment thereof

Abstract

The invention relates to an electrostatic protection structure and electronic equipment thereof, which are applied to an SCR (Selective Catalytic Reduction) device and comprise a substrate and a grid electrode, the substrate internally comprises a first well region, a second well region, a third well region and a fourth well region which extend into the substrate from the first surface and are sequentially arranged along a first direction parallel to the first surface; the first well region and the third well region have the same conductive type and are opposite to the second well region and the fourth well region; the first well region, the second well region, the third well region and the fourth well region internally comprise a plurality of ion implantation regions which extend along a second direction towards the substrate through the first surface; wherein the partial ion implantation region in the second well region is used for simultaneously short-circuiting the ion implantation region in the third well region and forming a GDMOS for increasing a current discharge path with the first well region, the grid electrode and the partial ion implantation region in the first well region, and at least the trigger voltage of the SCR device can be reduced, and the maintaining voltage can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to an electrostatic protection structure and an electronic device thereof. Background Art

[0002] ESD (Electrostatic Discharge) refers to the phenomenon of charge transfer and energy release caused by the mutual approach or direct contact of objects with different electrostatic potentials, which often occurs during the production, assembly, testing, storage, handling, etc. of integrated circuits. When the electrostatic charges accumulated in the human body, instruments, equipment or components are relatively large, transient currents of up to several tens of amperes and voltage surges of kilovolts can be generated, causing damage to electronic components or systems.

[0003] Common ESD devices include diodes and bipolar junction transistors (BJTs) of hysteresis devices, gate grounded N-metal oxide semiconductors (GGNMOS), gate drain P-metal oxide semiconductors (GDPMOS), silicon controlled rectifiers (SCRs), and so on. Compared with the above devices, under the same area condition, the SCR device has a bipolar conductivity modulation mechanism and the best robustness.

[0004] However, due to its high trigger voltage (V t ), and low holding voltage (V h ), the I-V curve of the SCR device is prone to intersect with the working area of the core device, and the latch-up effect occurs due to mutual influence. Summary of the Invention

[0005] Based on this, in view of the technical problems in the prior art, it is necessary to provide an electrostatic protection structure and an electronic device thereof, which can at least reduce the trigger voltage of the traditional SCR device while increasing its holding voltage.

[0006] In a first aspect, the present application provides an electrostatic protection structure applied to a silicon controlled rectifier (SCR) device for unidirectional thyristor electrostatic protection, including: a substrate and a gate;

[0007] The substrate includes a first well region, a second well region, a third well region, and a fourth well region that extend into the substrate via a first surface and are arranged in sequence along a first direction parallel to the first surface; the first well region and the third well region have the same conductivity type, which is opposite to the conductivity types of the second well region and the fourth well region;

[0008] The bottom surface of the gate is located within the top surface of the first well region;

[0009] The first well region, the second well region, the third well region and the fourth well region include a plurality of ion implantation regions extending along a second direction toward the substrate through the first surface;

[0010] Among them, the part of the ion implantation area in the second well region is used to simultaneously short-circuit the ion implantation area in the third well region, and to form a GDMOS with the first well region, the gate, and the part of the ion implantation area in the first well region to increase the current discharge path.

[0011] In the electrostatic protection structure in the above embodiment, the first well region, the second well region, the third well region and the fourth well region and the internal ion injection region constitute a four-well SCR structure. On this basis, part of the ion injection region in the second well region and the first well region, the gate, and part of the ion injection region in the first well region constitute a GDMOS. The GDMOS is short-circuited with the ion injection region in the third well region. When the parasitic transistor in the four-well SCR structure triggers the SCR path to be opened, the GDMOS is introduced to add an ESD current discharge path to draw away the unbalanced carriers injected into part of the SCR path due to the positive feedback effect, thereby suppressing the positive feedback effect and increasing the holding voltage of the device. In addition, its triggering is GDMOS triggering, which can reduce the triggering voltage of the device.

[0012] In some embodiments, the first well region includes a first ion implantation region and a second ion implantation region sequentially arranged along a first direction;

[0013] The second well region includes a third ion implantation region and a fourth ion implantation region sequentially arranged along the first direction; the third ion implantation region extends away from the first direction and is partially embedded in the first well region;

[0014] The third well region includes a fifth ion implantation region and a sixth ion implantation region sequentially arranged along the first direction;

[0015] The fourth well region includes a seventh ion implantation region and an eighth ion implantation region which are sequentially arranged along the first direction.

[0016] In some embodiments, the first well region, the third well region, the first ion implantation region, the fourth ion implantation region, the fifth ion implantation region, and the seventh ion implantation region have the same conductivity type;

[0017] The second well region, the fourth well region, the second ion implantation region, the third ion implantation region, the sixth ion implantation region and the eighth ion implantation region have the same conductivity type.

[0018] In some embodiments, an orthographic projection of the gate on a top surface of the first well region is located within the first well region between the second ion implantation region and the third ion implantation region.

[0019] In some embodiments, the substrate includes: a plurality of field oxide regions extending along a second direction via a first surface and arranged at intervals along a first direction.

[0020] In some embodiments, the plurality of field oxide regions include:

[0021] A first field oxide region located on a side of the first ion implantation region away from the second ion implantation region;

[0022] A second field oxide region located between the first ion implantation region and the second ion implantation region;

[0023] A third field oxide region located between the third ion implantation region and the fourth ion implantation region;

[0024] A fourth field oxide region located between the fourth ion implantation region and the fifth ion implantation region;

[0025] A fifth field oxide region located between the fifth ion implantation region and the sixth ion implantation region;

[0026] A sixth field oxide region located between the sixth ion implantation region and the seventh ion implantation region;

[0027] A seventh field oxide region located between the seventh ion implantation region and the eighth ion implantation region;

[0028] An eighth field oxide region located on a side of the eighth ion implantation region away from the seventh ion implantation region.

[0029] In some embodiments, the first ion implantation region, the second ion implantation region, the seventh ion implantation region, and the gate are used to connect to the anode;

[0030] The third ion implantation region and the sixth ion implantation region are short-circuited;

[0031] The fourth ion implantation region, the fifth ion implantation region, and the eighth ion implantation region are used to connect to the cathode.

[0032] In some embodiments, the dimension of the gate along the first direction is related to the trigger voltage of the electrostatic protection device.

[0033] In some embodiments, the dimension of the ion implantation region along the second direction is greater than the dimension of the field oxide region along the second direction;

[0034] The doping concentration of the ion implantation region is greater than the doping concentration in the first well region, the second well region, the third well region, and the fourth well region.

[0035] In a second aspect, the present application further provides an electronic device, including the electrostatic protection structure described in any one of the above embodiments.

[0036] In the electronic device of the above embodiment, compared with the electronic device using SCR devices, by adding a parasitic transistor to shunt and weaken the positive feedback, the holding voltage is significantly increased, and the risk of latch-up effect is reduced. At the same time, the discharge efficiency of the ESD current is improved under the same area, effectively reducing local heat accumulation, further reducing the damage probability of the core devices in the electronic device, achieving a balance among the protection efficiency, robustness, and design compatibility, and providing a more robust ESD solution for high-density electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 It is a schematic diagram of the ESD design window;

[0039] Figure 2 It is a traditional SCR electrostatic protection structure;

[0040] Figure 3 It is an equivalent circuit diagram of the traditional SCR electrostatic protection structure;

[0041] Figure 4 It is one of the cross-sectional schematic diagrams of the electrostatic protection structure provided in an embodiment of the present application;

[0042] Figure 5 It is the second cross-sectional schematic diagram of the electrostatic protection structure provided in an embodiment of the present application;

[0043] Figure 6 For Figure 5 the equivalent circuit diagram of the shown electrostatic protection structure;

[0044] Figure 7 For Figure 5 the simulation diagram of the total current density distribution of the shown electrostatic protection structure.

[0045] Description of the reference numerals:

[0046] 10. Substrate; 201. First well region; 202. Second well region; 203. Third well region; 204. Fourth well region; 30. Ion implantation region; 301. First ion implantation region; 302. Second ion implantation region; 303. Third ion implantation region; 304. Fourth ion implantation region; 305. Fifth ion implantation region; 306. Sixth ion implantation region; 307. Seventh ion implantation region; 308. Eighth ion implantation region; 40. Field oxide region; 401. First field oxide region; 402. Second field oxide region; 403. Third field oxide region; 404. Fourth field oxide region; 405. Fifth field oxide region; 406. Sixth field oxide region; 407. Seventh field oxide region; 50. Gate. Detailed implementation manners

[0047] To facilitate the understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant accompanying drawings. The preferred embodiments of this application are shown in the accompanying drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] It should be understood that when an element or layer is referred to as "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0050] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0051] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be ascertained, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not precluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0052] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, and such variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shape of regions of the device and do not limit the scope of the invention.

[0053] Please refer to Figures 1 - 3 , as Figure 1 shown in the schematic diagram of the ESD design window in h , after the ESD protection device is turned on, the lowest voltage value (holding voltage V DD ) should be higher than the normal operating voltage V of the core device

[0054] Figure 2 is a conventional SCR electrostatic protection structure. The N-type ion implantation region (N+) and P-type ion implantation region (P+) in the N-well are connected to the anode, and the N-type ion implantation region (N+) and P-type ion implantation region (P+) in the P-well are connected to the cathode. Among them, resistor R NW , resistor R NPrespectively represent the resistances of the N-well and P-well. As the anode pulse increases, the PN junction between the P-well and the N-well undergoes avalanche breakdown first. At this time, the voltage drops across the resistors R NW and R NP increase, turning on the PNPN path (formed by the parasitic transistor PNP and the parasitic transistor NPN) within the SCR structure. Figure 3 is the equivalent circuit of the traditional SCR electrostatic protection structure. As can be seen from Figure 3 , the bases and collectors of the parasitic transistor NPN and the parasitic transistor PNP are short-circuited. Therefore, as long as one parasitic BJT is turned on, the other parasitic BJT will also be immediately turned on. In this case, the cross-coupling of NPN and PNP will generate positive feedback, leading to the occurrence of the conductance modulation effect inside the device, which causes the device to move towards the negative resistance region to the holding point V h .

[0055] As the ESD design window narrows, how to solve the problem of the too low holding voltage V h of the SCR device has become one of the problems that need to be urgently solved by researchers in this field.

[0056] In the embodiments of the present application, the substrate may include a first surface on the front side and a back surface opposite to the front side, that is, a second surface. Ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction towards the substrate includes a second direction perpendicular to the first surface of the substrate. Among them, the first direction and the second direction are perpendicular to each other. In the embodiments of the present application, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction.

[0057] Based on this, please refer to Figure 4 , the present application provides an electrostatic protection structure applied to an SCR device, including: a substrate 10, a gate 50;

[0058] The substrate 10 includes a first well region 201, a second well region 202, a third well region 203, and a fourth well region 204 that extend into the substrate 10 via the first surface and are arranged in sequence along the OY direction parallel to the first surface; the first well region 201 and the third well region 203 have the same conductivity type, which is opposite to the conductivity types of the second well region 202 and the fourth well region 204;

[0059] The bottom surface of the gate 50 is located within the top surface of the first well region 201;

[0060] The first well region 201, the second well region 202, the third well region 203, and the fourth well region 204 include a plurality of ion implantation regions 30 that extend along the OX direction towards the substrate 10 via the first surface;

[0061] Among them, a partial ion implantation region 30 in the second well region 202 is used to short-circuit the ion implantation region 30 in the third well region 203, and together with the first well region 201, the gate 50, and the partial ion implantation region 30 in the first well region 201, a GDMOS that increases the current discharge path is formed.

[0062] Further, in some embodiments, the substrate 10 includes: a plurality of field oxide regions 40 extending along the OX direction via the first surface and arranged at intervals along the OY direction.

[0063] Exemplarily, a layer of oxide layer and a photoresist layer can be grown on the first surface of the substrate 10 first, and then photolithography, implantation, and high-temperature annealing of the first well region 201, the second well region 202, the third well region 203, and the fourth well region 204 are performed; after removing the remaining photoresist layer and oxide layer, a patterned barrier layer is formed, and a field oxide region 40 is formed by using photolithography and furnace tube thermal oxidation processes; after removing the barrier layer, the preparation steps of the well region 20 (the first well region 201, the second well region 202, the third well region 203, and the fourth well region 204) are repeated to form the ion implantation region 30.

[0064] Among them, the material of the substrate 10 includes but is not limited to one or more other semiconductor materials, such as a silicon (Si) substrate, or, for example, the substrate can also include substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The semiconductor material can be doped or undoped. Other substrates that can be used include multi-layer substrates, gradient substrates, or mixed-orientation substrates.

[0065] Among them, the first well region 201 and the third well region 203 have the same conduction type, which is opposite to the conduction types of the second well region 202 and the fourth well region 204. For example, when the first well region 201 and the third well region 203 are N-type, the second well region 202 and the fourth well region 204 are P-type, forming an NPNP path in the OY direction; correspondingly, when the first well region 201 and the third well region 203 are P-type, the second well region 202 and the fourth well region 204 are N-type, forming a PNPN in the OY direction.

[0066] Further, please continue to refer to Figure 4 , in some embodiments, the first well region 201 includes a first ion implantation region 301 and a second ion implantation region 302 arranged in sequence along the OY direction;

[0067] The second well region 202 includes a third ion implantation region 303 and a fourth ion implantation region 304 arranged in sequence along the OY direction; the third ion implantation region 303 extends away from the OY direction and partially embeds into the first well region 201;

[0068] The third well region 203 includes a fifth ion implantation region 305 and a sixth ion implantation region 306 arranged in sequence along the OY direction;

[0069] The fourth well region 204 includes a seventh ion implantation region 307 and an eighth ion implantation region 308 arranged in sequence along the OY direction.

[0070] Among them, the first well region 201, the third well region 203, the first ion implantation region 301, the fourth ion implantation region 304, the fifth ion implantation region 305, and the seventh ion implantation region 307 have the same conductivity type;

[0071] The second well region 202, the fourth well region 204, the second ion implantation region 302, the third ion implantation region 303, the sixth ion implantation region 306, and the eighth ion implantation region 308 have the same conductivity type;

[0072] The doping concentration of the ion implantation region 30 is greater than the doping concentration of the well region 20 in the substrate 10.

[0073] In the embodiment of the present application, the substrate 10 is a P-type silicon substrate, the first well region 201 and the third well region 203 are N-type, and the second well region 202 and the fourth well region 204 are P-type. The specific structure is as Figure 5 shown. The above structure can be formed by implanting P-type ions or N-type ions. The types of P-type impurity ions are not specifically limited in the embodiments of the present disclosure. As an example, the P-type impurity ions may include, but are not limited to, any one or several of boron (B) ions, gallium (Mg) ions, indium (In) ions, etc. Similarly, the types of N-type impurity ions are not specifically limited in the embodiments of the present disclosure. As an example, the N-type impurity ions may include, but are not limited to, any one or several of phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions.

[0074] Among them, the doping concentrations of the first well region 201, the second well region 202, the third well region 203, and the fourth well region 204 are 5e 16 cm -3 -9e 16 cm -3 , for example, 5e 16 cm -3 , 6e 16 cm -3 , 7e 16 cm -3 , 8e 16 cm -3 or 9e 16 cm -3 ; the doping concentration of the ion implantation region with the conductivity type is 5e19 cm -3 -9e 19 cm -3 For example, 5e 19 cm -3 , 6e 19 cm -3 , 7e 19 cm -3 , 8e 19 cm -3 or 9e 19 cm -3 , the doping concentration of the ion implantation region with N-type conductivity type needs to be appropriately greater than the doping concentration of the ion implantation region with P-type conductivity type.

[0075] Furthermore, in some embodiments, a plurality of field oxide regions 40, denoted as FOX, include:

[0076] The first field oxide region 401 is located on the side of the first ion implantation region 301 away from the second ion implantation region 302;

[0077] The second field oxide region 402 is located between the first ion implantation region 301 and the second ion implantation region 302;

[0078] The third field oxide region 403 is located between the third ion implantation region 303 and the fourth ion implantation region 304;

[0079] The fourth field oxide region 404 is located between the fourth ion implantation region 304 and the fifth ion implantation region 305;

[0080] The fifth field oxide region 405 is located between the fifth ion implantation region 305 and the sixth ion implantation region 306;

[0081] The sixth field oxide region 406 is located between the sixth ion implantation region 306 and the seventh ion implantation region 307;

[0082] The seventh field oxide region 407 is located between the seventh ion implantation region 307 and the eighth ion implantation region 308;

[0083] The eighth field oxide region 408 is located on the side of the eighth ion implantation region 308 away from the seventh ion implantation region 307.

[0084] Among them, the dimension (depth) of the ion implantation region 30 along the OX direction is greater than the dimension (depth) of the field oxide region 40 along the OX direction.

[0085] Exemplarily, for the specific electrostatic protection structure above, reference can be made to Figure 5 . For the convenience of understanding this application, Figure 5An example of the electrostatic protection structure provided by this application is given. There can be other suitable examples of the semiconductor structure prepared by this application, which are not limited herein.

[0086] Please continue to refer to Figure 5 , in some embodiments, the first ion implantation region 301, the second ion implantation region 302, the seventh ion implantation region 307 and the gate 50 are used to connect to the anode Anode;

[0087] The third ion implantation region 303 and the sixth ion implantation region 306 are short-circuited;

[0088] The fourth ion implantation region 304, the fifth ion implantation region 305 and the eighth ion implantation region 308 are used to connect to the cathode Cathode.

[0089] Among them, R NW represents the resistance of the first well region 201; R PW represents the resistance of the second well region 202.

[0090] In the above embodiments, the second ion implantation region 302 / the first well region 201 / the second well region 202 form a parasitic transistor PNP, the first well region 201 / the second well region 202 / the fourth ion implantation region 304 form a first parasitic transistor NPN, and the first well region 201 / the second well region 202 / the fifth ion implantation region 305 form a second parasitic transistor NPN. When the PNP and NPN are turned on, a forward SCR path is formed, and its breakdown plane is between the first N well 201 and the second P+ implantation 303.

[0091] Since the gate 50 has the same potential as the second ion implantation region 302, the first well region 201 is equivalent to the substrate of the MOS, the second ion implantation region 302 is equivalent to the drain region (D) of the MOS, and the third ion implantation region 303 is equivalent to the source (S) of the MOS, forming a GDPMOS. The third ion implantation region 303 across the first well region 201 and the second well region 202 is short-circuited with the sixth ion implantation region 306 in the third well region 203.

[0092] In the above embodiments, when an ESD pulse reaches the cathode Cathode of the device, the eighth ion implantation region 308 / the seventh ion implantation region 307 form a forward PN junction, reducing the reverse conduction resistance of this structure.

[0093] When the pulse reaches the anode Anode, the PN junction between the third ion implantation region 303 and the first well region 201 conducts, accelerating the charge accumulation rate in the first well region 201, making the resistance R NWThe voltage drop rises more quickly, causing the parasitic transistor PNP to conduct. Compared with the trigger voltage required for the avalanche effect to occur at the PN junction between the first well region 201 and the second well region 202, the trigger voltage required for the GDPMOS structure is lower.

[0094] Figure 6 is Figure 5 The equivalent circuit diagram of the electrostatic protection structure shown. The bases and collectors of the parasitic transistor PNP and the first parasitic transistor NPN are short-circuited. When the parasitic transistor PNP conducts, the first parasitic transistor NPN turns on accordingly. In the electrostatic protection structure provided in the above embodiment, on the one hand, the introduced second parasitic NPN transistor draws away a part of the current on the main SCR path, that is, from the fifth ion implantation region 305 to the cathode Cathode, alleviating the conductance modulation effect in the well region 20. On the other hand, the continuously accumulated charge in the first well region 201 causes the PN junction between the first well region 201 and the third ion implantation region 303 to break down. The current flows to the sixth ion implantation region 306 short-circuited to the third ion implantation region 303 and flows out through the fifth ion implantation region 305 from the cathode Cathode. Through the synergistic effect of the above two aspects, the positive feedback effect in the SCR structure is effectively suppressed, and the holding voltage is thus increased.

[0095] In addition, the third ion implantation region 303 controls the connection across the first well region 201 and the second well region 202. By increasing its size (width) along the first direction, the base widths of the first parasitic transistor NPN and the second parasitic transistor NPN can be adjusted, thereby reducing their current amplification factors and weakening the positive feedback effect to achieve the purpose of increasing the holding voltage.

[0096] Figure 7 is Figure 5 The simulation diagram of the total current density distribution of the electrostatic protection structure shown. As Figure 7 shown, the white highlighted areas represent high current density. When the ESD pulse reaches the anode of the device and the cathode Cathode of the device is connected to a low potential, the trigger current will enter from the anode and pass through the second ion implantation region 302, the first well region 201 and the third ion implantation region 303, and the sixth ion implantation region 306, the fourth ion implantation region 304, and the fifth ion implantation region 305 in sequence, and finally flow out from the cathode Cathode, which is the same as the current discharge path analyzed before.

[0097] Please continue to refer to Figure 5 , in some embodiments, the orthographic projection of the gate 50 on the top surface of the first well region 201 is located within the first well region 201 between the second ion implantation region 302 and the third ion implantation region 303.

[0098] In some embodiments, the dimension D of the gate 50 along the OY direction is related to the trigger voltage V of the electrostatic protection devicet 。

[0099] Among them, D is used to represent the dimension of the gate 50 in the OY direction, that is, the width.

[0100] In the electrostatic protection structure in the above embodiment, its triggering method is GDPMOS triggering. According to the requirements of the ESD design window in different application scenarios, by controlling the width D of the gate 50 in the first well region 201, the triggering voltage of the GDPMOS can be adjusted.

[0101] In some embodiments, the present application provides an electronic device including the electrostatic protection structure described in any of the above embodiments. Since the electronic device of the above embodiment and the electrostatic protection structure provided by the present invention are based on the same inventive concept, therefore, the electronic device adopting the above electrostatic protection structure has all the advantages provided by the present invention, and will not be elaborated herein one by one.

[0102] The electrostatic protection structure and its electronic device provided by the present application have the following unexpected technical effects:

[0103] Compared with the traditional SCR, due to the low holding voltage, it is easy to trigger the latch-up effect, resulting in continuous conduction of the device and damage to the circuit. The present application actively extracts some non-equilibrium carriers by adding a parasitic NPN transistor in parallel with the main SCR path inside to suppress the conductance modulation effect, thereby weakening the positive feedback intensity and significantly increasing the holding voltage of the device. At the same time, introducing GDMOS (composed of the first well region, the second ion implantation region, the third ion implantation region and the gate) can replace the traditional avalanche breakdown triggering method when the positive feedback effect of the main SCR path is started, so as to achieve the purpose of reducing the triggering voltage.

[0104] This structure provides a more robust ESD protection scheme for high-density integrated circuits through multi-path discharge design, taking into account both robustness and anti-latch-up ability.

[0105] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0106] The above embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An electrostatic protection structure, characterized in that, Applied to unidirectional thyristor electrostatic protection devices, including: substrate, gate; The substrate includes a first well region, a second well region, a third well region and a fourth well region extending into the substrate through the first surface and arranged in sequence along a first direction parallel to the first surface; the first well region and the third well region have the same conductivity type, which is opposite to the conductivity type of the second well region and the fourth well region; The bottom surface of the gate is located within the top surface of the first well region; The first well region, the second well region, the third well region and the fourth well region include a plurality of ion implantation regions extending along a second direction toward the substrate through the first surface; Part of the ion implanted area in the second well region is used to simultaneously short-circuit the ion implanted area in the third well region, and to form a GDMOS that increases a current discharge path together with the first well region, the gate, and part of the ion implanted area in the first well region.

2. The electrostatic protection structure according to claim 1, wherein, The first well region includes a first ion implantation region and a second ion implantation region sequentially arranged along the first direction; The second well region includes a third ion implantation region and a fourth ion implantation region sequentially arranged along the first direction; the third ion implantation region extends away from the first direction and is partially embedded in the first well region; The third well region includes a fifth ion implantation region and a sixth ion implantation region sequentially arranged along the first direction; The fourth well region includes a seventh ion implantation region and an eighth ion implantation region sequentially arranged along the first direction.

3. The electrostatic protection structure according to claim 2, wherein The first well region, the third well region, the first ion implantation region, the fourth ion implantation region, the fifth ion implantation region and the seventh ion implantation region have the same conductivity type; The second well region, the fourth well region, the second ion implantation region, the third ion implantation region, the sixth ion implantation region and the eighth ion implantation region have the same conductivity type.

4. The electrostatic protection structure according to claim 3, characterized in that, The first ion implantation region, the second ion implantation region, the seventh ion implantation region and the gate are used to connect to the anode; The third ion implantation region and the sixth ion implantation region are short-circuited; The fourth ion implantation region, the fifth ion implantation region and the eighth ion implantation region are used to connect to a cathode.

5. The electrostatic protection structure according to claim 2, wherein, The orthographic projection of the gate on the top surface of the first well region is located within the first well region between the second ion implantation region and the third ion implantation region.

6. The electrostatic protection structure according to claim 2, wherein, The substrate includes: a plurality of field oxygen regions extending along the second direction via the first surface and arranged at intervals along the first direction.

7. The electrostatic protection structure according to claim 6, wherein The plurality of field oxygen regions include: A first field oxygen region, located at a side of the first ion implantation region away from the second ion implantation region; a second field oxygen region, located between the first ion implantation region and the second ion implantation region; A third field oxygen region, located between the third ion implantation region and the fourth ion implantation region; a fourth field oxygen region, located between the fourth ion implantation region and the fifth ion implantation region; a fifth field oxygen region, located between the fifth ion implantation region and the sixth ion implantation region; a sixth field oxygen region, located between the sixth ion implantation region and the seventh ion implantation region; a seventh field oxygen region, located between the seventh ion implantation region and the eighth ion implantation region; The eighth field-oxide region is located on the side of the eighth ion-implantation region away from the seventh ion-implantation region.

8. The electrostatic protection structure according to any one of claims 1-6, characterized in that The dimension of the gate along the first direction is related to the trigger voltage of the electrostatic protection structure.

9. The electrostatic protection structure according to any one of claims 1-6, characterized in that, The dimension of the ion-implantation region along the second direction is greater than the dimension of the field-oxide region along the second direction; The doping concentration of the ion-implantation region is greater than the doping concentrations in the first well region, the second well region, the third well region, and the fourth well region.

10. An electronic device, characterized in that, Comprising: The electrostatic protection structure according to any one of claims 1-9.

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