Display assembly and manufacturing method thereof

Abstract

The invention discloses a display assembly and a manufacturing method thereof, the display assembly comprises a driving backboard, an epitaxial structure, a passivation layer and a conductive interconnection layer, the epitaxial structure is arranged on the driving backboard, and the epitaxial structure comprises a plurality of epitaxial units; the passivation layer is arranged on the side, away from the driving backboard, of the epitaxial structure; the passivation layer is provided with a through hole, and the through hole directly faces the side, away from the driving backboard, of the epitaxial unit. The conductive interconnection layer is arranged on the passivation layer, and the conductive interconnection layer is electrically connected with the epitaxial unit through the through hole; in the direction of the epitaxial structure away from the driving back plate, the epitaxial units are arranged to have gradually reduced section widths. The section width of the epitaxial unit is gradually reduced, so that the depth-to-width ratio between the epitaxial unit and the driving backboard is reduced, and the step coverage rate of the side surface of the epitaxial unit is increased, thereby reducing the risk of disconnection of a connecting line when a passivation layer and a conductive layer are deposited, reducing the failure rate of a product, and improving the yield of the product.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a display component and a manufacturing method thereof. Background Art

[0002] Wafer bonding is an emerging semiconductor processing technology that has developed rapidly in recent years. It has important applications in the field of chip processing and has received increasing attention. Wafer bonding technology has made important contributions to our information-based life. Wafer bonding technology refers to tightly bonding two polished wafers of the same or different materials through chemical and physical actions. After the wafers are bonded, the atoms at the interface react under the action of external forces to form covalent bonds and integrate into one body, and the bonding interface reaches a specific bonding strength. The surface light source made by wafer bonding technology has the advantages of small size, low power consumption, long service life, environmental protection, etc., and is increasingly widely used in various places.

[0003] However, in the manufacturing process of the existing surface light source, the display component is made on the wafer, and faults such as disconnection of the wiring are likely to occur during the processing. Specifically, because the aspect ratio between the epitaxial layer and the conductive layer of the chip is high and the step coverage is poor, the thickness of the conductive layer covering the side of the epitaxial layer often becomes thinner or even disconnected. That is to say, defects such as disconnection of the wiring are likely to occur at the connection between the epitaxial layer and the conductive layer during the processing, resulting in an increase in the failure rate of the product and affecting the product yield.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the Invention

[0005] In view of the above deficiencies of the prior art, the purpose of the present invention is to provide a display component and a manufacturing method thereof, aiming to solve the problem that the wiring is easily disconnected during the manufacturing process of the display component of the existing surface light source, resulting in product failure.

[0006] The technical solution of the present invention is as follows:

[0007] A display component, comprising a driving backplane, an epitaxial structure, a passivation layer, and a conductive interconnect layer. The epitaxial structure is disposed on the driving backplane, and the epitaxial structure includes a plurality of epitaxial units; the passivation layer is disposed on a side of the epitaxial structure away from the driving backplane; through holes are formed in the passivation layer, and the through holes are opposite to a side of the epitaxial unit away from the driving backplane; the conductive interconnect layer is disposed on the passivation layer, and the conductive interconnect layer is electrically connected to the epitaxial unit through the through holes; along the direction of the epitaxial structure away from the driving backplane, the epitaxial unit is configured to have a gradually decreasing cross-sectional width.

[0008] Optionally, the display component further includes a bonding layer, and the bonding layer is disposed between the epitaxial unit and the driving backplane.

[0009] Optionally, along the direction of the epitaxial structure away from the driving backplane, the cross-sectional width of the bonding layer is greater than the cross-sectional width of the epitaxial unit.

[0010] Optionally, the display component further includes a current spreading layer disposed between the bonding layer and the epitaxial unit.

[0011] Optionally, along the direction of the epitaxial structure away from the driving backplane, the cross-sectional widths of the bonding layer, the current spreading layer, and the epitaxial unit gradually decrease.

[0012] Optionally, the bonding layer includes a bonding layer of a metal material or a bonding layer of an alloy material.

[0013] Optionally, the epitaxial unit includes a first semiconductor layer, an active layer, and a second semiconductor layer; the first semiconductor layer is on the side close to the driving backplane; along the direction of the epitaxial structure away from the driving backplane, the cross-sectional widths of the first semiconductor layer, the active layer, and the second semiconductor layer gradually decrease; or,

[0014] Along the direction of the epitaxial structure away from the driving backplane, the cross-sectional width of the first semiconductor layer is the same as the cross-sectional width of the active layer, and the cross-sectional width of the first semiconductor layer is greater than the cross-sectional width of the second semiconductor layer.

[0015] The present application also discloses a method for manufacturing a display component for manufacturing any one of the above display components, which includes:

[0016] Providing a driving backplane and an epitaxial structure;

[0017] Bonding the epitaxial layer of the epitaxial structure to the driving backplane to form an intermediate structure;

[0018] Etching the intermediate structure multiple times to form a plurality of epitaxial units on the driving backplane; wherein, the cross-sectional width of the intermediate structure gradually decreases along the direction away from the driving backplane;

[0019] Fabricating a passivation layer and a conductive interconnect layer on the driving backplane to fabricate a display component.

[0020] Optionally, the step of etching the intermediate structure multiple times to form a plurality of epitaxial units on the driving backplane specifically includes:

[0021] Coating and patterning a photoresist on the epitaxial layer of the intermediate structure to form a patterned first photoresist layer;

[0022] Using the patterned first photoresist layer as a mask, etch the epitaxial layer to form a once-patterned epitaxial layer, and remove the patterned first photoresist layer;

[0023] Apply photoresist on the once-patterned epitaxial layer and pattern it to expose the edges on both sides of the once-patterned epitaxial layer, forming a patterned second photoresist layer;

[0024] Using the patterned second photoresist layer as a mask, etch the once-patterned epitaxial layer to form a twice-patterned epitaxial layer; wherein, the cross-sectional width of the twice-patterned epitaxial layer gradually decreases in the direction away from the driving backplane;

[0025] Remove the patterned second photoresist layer;

[0026] Deposit a hard mask on the twice-patterned epitaxial layer and pattern it to form a patterned hard mask layer;

[0027] Using the patterned hard mask layer as a mask, etch the twice-patterned epitaxial layer to form a plurality of epitaxial units;

[0028] Remove the patterned hard mask layer.

[0029] Optionally, the step of fabricating a passivation layer and a conductive interconnect layer on the driving backplane to fabricate a display component specifically includes:

[0030] Fabricate a passivation layer on the driving backplane to cover the epitaxial units;

[0031] Etch the passivation layer to open a through hole on the side of the epitaxial unit away from the driving backplane, forming a patterned passivation layer;

[0032] Fabricate a conductive interconnect layer on the patterned passivation layer so that the conductive interconnect layer is electrically connected to the epitaxial unit through the through hole, thereby fabricating a display component.

[0033] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0034] The display component disclosed in the present invention is used for a surface light source and is processed by wafer bonding. The epitaxial structure is arranged on a driving backplane, and the cross-sectional width of the epitaxial unit gradually decreases in a direction away from the driving backplane, forming a plurality of steps, thereby improving the step coverage. Originally, the height difference between the top surface of the epitaxial unit and the surface of the driving backplane is large. After forming a plurality of steps, the gradient of the side surface of the epitaxial unit is slowed down, and the aspect ratio is reduced, thereby avoiding the passivation layer or the conductive interconnect layer from being disconnected at the side position of the epitaxial unit, improving the production yield of the product, and increasing the processing reliability. In addition, by forming a multi-layer stepped structure, the surface area of the epitaxial unit is also increased, thereby improving the external quantum efficiency of the display component and improving the performance of the semiconductor product. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a schematic diagram of the structure of the display component in the present invention;

[0037] Figure 2 A schematic diagram of the structure of an epitaxial structure in one embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the structure of an epitaxial structure in another embodiment of the present invention;

[0039] Figure 4 A schematic diagram of the structure of an epitaxial structure in another embodiment of the present invention;

[0040] Figure 5 A flowchart of a method for manufacturing a display component in the present invention;

[0041] Figure 6 It is a schematic diagram of the process of the method for manufacturing the display component in the present invention.

[0042] Among them, 10, driving backplane; 20, epitaxial unit; 211, first semiconductor layer; 212, active layer; 213, second semiconductor layer; 30, passivation layer; 31, through hole; 40, conductive interconnection layer; 50, bonding layer; 60, current spreading layer. DETAILED DESCRIPTION

[0043] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0044] Referring to Figure 1 , as an implementation manner of this embodiment, a display component is disclosed, which includes a driving backplane 10, an epitaxial structure, a passivation layer 30, and a conductive interconnection layer 40. The epitaxial structure is disposed on the driving backplane 10, and the epitaxial structure includes a plurality of epitaxial units 20; the passivation layer 30 is disposed on a side of the epitaxial structure away from the driving backplane 10; a through hole 31 is formed in the passivation layer 30, and the through hole 31 is opposite to a side of the epitaxial unit 20 away from the driving backplane 10; the conductive interconnection layer 40 is disposed on the passivation layer 30, and the conductive interconnection layer 40 is electrically connected to the epitaxial unit 20 through the through hole 31; along a direction in which the epitaxial structure is away from the driving backplane 10, the epitaxial unit 20 is configured to have a gradually decreasing cross-sectional width.

[0045] The display component disclosed in this embodiment is used for a surface light source and is processed by a wafer bonding method. The driving backplane 10 disclosed in this embodiment includes, but is not limited to, a complementary metal oxide semiconductor (CMOS) backplane, which has the advantages of low power consumption and high integration. It can be vertically integrated to improve the efficiency of a micro-electromechanical system (MEMS) to meet the requirements for function addition, miniaturization, and a higher number of dies per wafer in the semiconductor processing process. A plurality of light-emitting components, such as organic light-emitting diodes, Mini LEDs, Micro LEDs, etc., can be integrated on the driving backplane 10 to form a surface light source with good light-emitting effects. When in use, an electrical signal is input through the conductive interconnection layer 40 to make the epitaxial unit 20 emit light.

[0046] Specifically, the epitaxial structure is disposed on the driving backplane 10. The cross-sectional width of the epitaxial unit 20 gradually decreases in the direction away from the driving backplane 10, forming a plurality of steps, thereby improving the step coverage rate. Originally, the height difference between the top surface of the epitaxial unit 20 and the surface of the driving backplane 10 was large. After forming a plurality of steps, the gradient of the side surface of the epitaxial unit 20 is slowed down, and the aspect ratio is reduced, thereby preventing the passivation layer 30 or the conductive interconnect layer 40 from being disconnected at the side position of the epitaxial unit 20, improving the production yield of the product, and increasing the processing reliability. In addition, by forming a multi-layer stepped structure, the surface area of the epitaxial unit 20 is also increased, thereby improving the external quantum efficiency of the display component and enhancing the performance of the semiconductor product.

[0047] As Figure 1 shown, as an implementation manner of this embodiment, it is disclosed that the display component further includes a bonding layer 50, and the bonding layer 50 is disposed between the epitaxial unit 20 and the driving backplane 10. By providing the bonding layer 50 to connect the epitaxial unit 20 and the driving backplane 10, the risk of accidental peeling is reduced. During the processing, the epitaxial structure can be first bonded to the driving backplane 10 to maintain a stable connection, and then etching processing is performed to form the epitaxial unit 20 stably connected to the driving backplane 10, improving the stability of the processing.

[0048] Specifically, as another implementation manner of this embodiment, it is disclosed that along the direction in which the epitaxial structure is away from the driving backplane 10, the cross-sectional width of the bonding layer 50 is greater than the cross-sectional width of the epitaxial unit 20. In this embodiment, the bonding layer 50 is disposed between the epitaxial unit 20 and the driving backplane 10, which is equivalent to the bonding layer 50 being located "below" the epitaxial unit 20. Therefore, the cross-sectional width of the bonding layer 50 is larger, forming a stepped structure with the epitaxial unit 20, which can further slow down the gradient and avoid the problem that the passivation layer 30 or the conductive interconnect layer 40 is disconnected due to an excessive aspect ratio.

[0049] Specifically, as another implementation manner of this embodiment, it is disclosed that the bonding layer 50 includes a metal material bonding layer or an alloy material bonding layer. In this embodiment, the driving backplane 10 and the epitaxial structure are connected through the bonding layer 50. During the processing, bonding materials can be respectively disposed on the driving backplane 10 and the epitaxial structure, which can be the same metal bonding material, and a metal material bonding layer is formed by bonding, or an alloy material is used to form an alloy material bonding layer, both of which can achieve the effect of stable connection.

[0050] Again, as Figure 1As shown, as another implementation of this embodiment, it is disclosed that the display component further includes a current spreading layer 60, and the current spreading layer 60 is disposed between the bonding layer 50 and the epitaxial unit 20. The current spreading layer 60 can be made of indium tin oxide material. The setting of the current spreading layer 60 in the display component disclosed in this embodiment can achieve a uniform current density distribution, improve the uniformity of the light emission of the display component, and improve the light emission efficiency.

[0051] Specifically, as another implementation of this embodiment, it is disclosed that along the direction in which the epitaxial structure is away from the driving backplane 10, the cross-sectional widths of the bonding layer 50, the current spreading layer 60, and the epitaxial unit 20 gradually decrease. In this embodiment, the bonding layer 50, the current spreading layer 60, and the epitaxial unit 20 are sequentially stacked on the driving backplane 10. Therefore, the cross-sectional widths of the three gradually decrease and extend upward in a shape similar to a pyramid, so that the side surface of the epitaxial unit 20 has a certain slope, which is convenient for the deposition of the passivation layer 30 and the conductive interconnection layer 40.

[0052] Specifically, the cross-sectional width of the bonding layer 50 is greater than the cross-sectional width of the current spreading layer 60, and a step is formed at the junction of the two; similarly, a step is also formed at the junction of the current spreading layer 60 and the epitaxial unit 20; thus, multiple steps are formed from top to bottom, reducing the risk that the passivation layer 30 and the conductive interconnection layer 40 deposited on the side wall of the epitaxial unit 20 are disconnected, which is beneficial to improving the production and processing yield of the product.

[0053] As Figure 2 shown, as another implementation of this embodiment, it is disclosed that the epitaxial unit 20 includes a first semiconductor layer 211, an active layer 212, and a second semiconductor layer 213; the first semiconductor layer 211 is on the side close to the driving backplane 10; along the direction in which the epitaxial structure is away from the driving backplane 10, the cross-sectional widths of the first semiconductor layer 211, the active layer 212, and the second semiconductor layer 213 gradually decrease; or, as Figure 3 shown, along the direction in which the epitaxial structure is away from the driving backplane 10, the cross-sectional width of the first semiconductor layer 211 is the same as the cross-sectional width of the active layer 212, and the cross-sectional width of the first semiconductor layer 211 is greater than the cross-sectional width of the second semiconductor layer 213.

[0054] In this embodiment, the first semiconductor layer 211, the active layer 212, and the second semiconductor layer 213 disclosed form a light-emitting structure for emitting light. The first semiconductor layer 211 can be set as a P-type semiconductor layer, and the second semiconductor layer 213 can be set as an N-type semiconductor layer, such as a p-type gallium nitride layer and an n-type gallium nitride layer respectively. The active layer 212 is a multi-quantum well layer (MQW). Electrons and holes recombine in the quantum well region to generate photons, realizing light emission. By setting the cross-sectional widths of the first semiconductor layer 211, the active layer 212, and the second semiconductor layer 213 to gradually decrease, the sidewalls of the epitaxial unit 20 itself extend downward in a stepped manner, thereby slowing down the slope and reducing the drop, which is beneficial to depositing the passivation layer 30 and the conductive interconnection layer 40, avoiding disconnection, and improving the production yield of the product. In addition, it can also increase the surface area of the epitaxial unit 20 and improve the display performance.

[0055] As Figure 4 shown, in another embodiment of this embodiment, it can also be set that along the direction in which the epitaxial structure is away from the driving backplane 10, the cross-sectional width of the first semiconductor layer 211 is greater than the cross-sectional width of the active layer 212, and the cross-sectional width of the active layer 212 is the same as the cross-sectional width of the second semiconductor layer 213. In the embodiments of the present application, in order to increase the deposition success rate of the passivation layer 30 and the conductive interconnection layer 40, multiple combinations can be set:

[0056] Bonding layer 50, current spreading layer 60, and the cross-sectional widths of the epitaxial unit 20 decrease in sequence along the direction in which the epitaxial structure is away from the driving backplane 10; and within each of the bonding layer 50, the current spreading layer 60, and the epitaxial unit 20, a multi-layer stepped structure with gradually decreasing cross-sectional widths can also be set, so that several steps are formed on the sides of the bonding layer 50, the current spreading layer 60, and the epitaxial unit 20 formed on the driving backplane 10, reducing the risk of disconnection when depositing the passivation material and the conductive interconnection layer 40 material.

[0057] As Figure 5 and Figure 6 shown, as another embodiment of the present application, a manufacturing method of a display component is disclosed, which is used to manufacture any one of the display components described above, and includes:

[0058] S100, as Figure 6 shown in figure (a) therein, provide a driving backplane and an epitaxial structure;

[0059] S200, as Figure 6 shown in figure (b) therein, bond the epitaxial layer of the epitaxial structure to the driving backplane to form an intermediate structure;

[0060] S300, as Figure 6As shown in Figure (c), the intermediate structure is etched multiple times to form a plurality of epitaxial units on the driving backplane; wherein, the cross-sectional width of the intermediate structure gradually decreases in a direction away from the driving backplane;

[0061] S400. As Figure 6 As shown in Figure (d), a passivation layer and a conductive interconnection layer are fabricated on the driving backplane to fabricate a display component.

[0062] The manufacturing method of the display component disclosed in this embodiment is used to process a surface light source. The initial semiconductor structure is fabricated by means of wafer bonding. Wafer bonding is a wafer-level packaging technology that allows more than two wafers to be vertically stacked and provides electrical connection and hermetical sealing between wafers. Now various wafer bonding technologies are being developed and applied to bond two homogeneous or heterogeneous wafers.

[0063] Specifically, compared with the conventional process of etching the epitaxial structure only once to form a plurality of independent epitaxial units, in this embodiment, by etching the epitaxial structure multiple times, multiple stepped surfaces are formed on the sidewalls of the epitaxial units, thereby improving the step coverage rate, slowing down the gradient between the top surface of the epitaxial unit and the surface of the driving backplane, reducing the aspect ratio, and thus avoiding the disconnection of the passivation layer or the conductive interconnection layer at the sidewall positions on both sides of the epitaxial unit when depositing the passivation layer and the conductive interconnection layer subsequently, improving the production yield and processing reliability of the product.

[0064] Specifically, by etching the intermediate structure multiple times in this embodiment, the surface area of the epitaxial unit is also increased, thereby improving the external quantum efficiency of the display component and enhancing the performance of the semiconductor product.

[0065] Specifically, a bonding material can be deposited on the driving backplane disclosed in this embodiment to form a first bonding layer; a bonding material can also be deposited on the epitaxial structure to form a second bonding layer. Then, during processing, by aligning and bonding the first bonding layer and the second bonding layer, a complete bonding layer is formed to connect the epitaxial layer and the driving backplane; then, by peeling off the substrate layer, the epitaxial layer is exposed to facilitate further processing on the side of the epitaxial layer away from the driving backplane. This processing method stably connects and conducts the driving backplane and the epitaxial structure, realizes vertical interconnection, has a shorter interconnection distance, a higher interconnection density and a lower cost, and has high connection reliability, which is beneficial to extending the service life of the product.

[0066] Specifically, in another implementation manner of this embodiment, the evaporation coating process can be used to form both the first bonding layer and the second bonding layer. Moreover, when bonding between the first bonding layer and the second bonding layer disclosed in this embodiment is performed, the evaporation coating process can also be used for bonding, thereby improving the uniformity of bonding, making the connection between the bonding layer, the driving backplane, and the epitaxial structure tighter, and further improving the reliability of the connection after bonding.

[0067] Specifically, as another implementation manner of this embodiment, it is disclosed that the first bonding layer and the second bonding layer can be deposited from the same metal material. Bonding with the same material makes the bonding layer formed by bonding have better uniformity, which is beneficial to improving the stability of the connection, while maintaining good electrical performance to conduct the epitaxial structure and the driving backplane. Specifically, the first bonding layer and the second bonding layer can be an aluminum metal layer, a silver metal layer, a copper metal layer, etc., and are bonded by hot pressing.

[0068] Specifically, the substrate layer disclosed in this embodiment includes but is not limited to any one of a sapphire substrate layer, a single crystal silicon substrate layer, a silicon carbide substrate layer, and a gallium arsenide substrate layer.

[0069] Specifically, as an implementation manner of this embodiment, it is disclosed that the step S300 specifically includes:

[0070] S301. Apply glue on the epitaxial layer of the intermediate structure and pattern it to form a patterned first photoresist layer;

[0071] S302. Use the patterned first photoresist layer as a mask to etch the epitaxial layer to form a once-patterned epitaxial layer, and remove the patterned first photoresist layer;

[0072] S303. Apply glue on the once-patterned epitaxial layer and pattern it to expose the edges on both sides of the once-patterned epitaxial layer to form a patterned second photoresist layer;

[0073] S304. Use the patterned second photoresist layer as a mask to etch the once-patterned epitaxial layer to form a twice-patterned epitaxial layer; wherein, the cross-sectional width of the twice-patterned epitaxial layer gradually decreases in the direction away from the driving backplane;

[0074] S305. Remove the patterned second photoresist layer;

[0075] S306. Deposit a hard mask on the twice-patterned epitaxial layer and pattern it to form a patterned hard mask layer;

[0076] S307. Use the patterned hard mask layer as a mask to etch the twice-patterned epitaxial layer to form a number of epitaxial units;

[0077] S308 , removing the patterned hard mask layer.

[0078] After the substrate layer is peeled off from the intermediate structure disclosed in this embodiment, the side of the epitaxial layer away from the driving backplane is exposed, and the side of the epitaxial layer away from the driving backplane is coated with glue and patterned, and the epitaxial layer is processed by photolithography, which is simple and direct, and easy to operate. However, in actual operation, after the epitaxial structure is etched once, the height difference between it and the driving backplane is large, which is easy to affect the deposition effect of the subsequent passivation layer and the conductive interconnection layer. Therefore, the second coating of glue and patterning are continued on the epitaxial layer that has been patterned once, so as to perform the second etching.

[0079] Specifically, in this embodiment, the edge position of the once patterned epitaxial layer is removed by secondary etching, so that the side of the once patterned epitaxial layer forms a stepped structure to reduce the gradient. It can be seen that in this embodiment, only two etchings are performed to form a two-level step structure, which can increase the deposition success rate of the passivation layer and the conductive interconnect layer and reduce the risk of disconnection. It should be noted that the manufacturing method disclosed in the present application is not limited to this. According to the needs of use, the number of etchings can be adjusted, and the side of the epitaxial structure can be etched three, four or more times to form multiple steps, which can further reduce the aspect ratio and improve the success rate of the subsequent deposition of the passivation layer or the conductive interconnect layer.

[0080] In addition, the epitaxial structure disclosed in this embodiment can set a current expansion layer and a bonding layer between the epitaxial unit and the driving backplane. In order from top to bottom, the epitaxial unit, the current expansion layer and the bonding layer can be etched in sequence to form a multi-level ladder structure with increasing cross-sectional widths. The number of step surfaces on the side of the epitaxial unit is further increased to reduce the slope. Of course, if the process permits, multiple step surfaces can also be etched inside the current expansion layer and the bonding layer in a direction away from the driving backplane to further increase the success rate of the deposition of the passivation layer and the conductive interconnect layer.

[0081] Specifically, the hard mask disclosed in the present embodiment is an inorganic thin film material generated by chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD). Its main components usually include titanium nitride (TiN), silicon nitride (SiN), silicon dioxide (SiO2), etc. The hard mask is mainly used in multiple photolithography processes. First, multiple photoresist images are transferred to the hard mask, and then the final pattern etching is transferred to the substrate by the hard mask. In the present embodiment, the hard mask is patterned and arranged on the driving backplane, and then etching is performed using this as a mask. The loss of the hard mask is small, and the etching depth is deep, so that the current expansion layer and the bonding layer can be completely etched, and the effect of the driving backplane is exposed. A plurality of independent light-emitting structure intermediates are formed on the driving backplane, so that subsequent encapsulation is facilitated, and a large number of display components are made by one-time integration to complete the production of the surface light source.

[0082] Specifically, in another implementation manner of this embodiment, it is disclosed that the etching depth value on the epitaxial layer of the first patterning is half of the height value of the epitaxial layer of the first patterning. The second etching on the epitaxial layer of the first patterning disclosed in this embodiment is to form a second-level step. In order to achieve the purpose of slowing down the gradient and reducing the aspect ratio, it is more appropriate that the etching height is in the range of one-fourth to three-fourths of the height of the epitaxial layer; preferably, during the second etching process, the etching height is half of the height value of the epitaxial layer, so that the heights of the upper and lower layers in the step structure are the same, improving the uniformity during the deposition of the passivation layer or the conductive interconnect layer, and avoiding the disconnection problem of the passivation layer material or the conductive interconnect layer material on the side walls of the upper or lower steps.

[0083] Specifically, as another implementation manner of this embodiment, it is disclosed that the step S400 specifically includes:

[0084] S401. Fabricate a passivation layer on the driving backplane to cover the epitaxial unit;

[0085] S402. Etch the passivation layer to open a through hole on the side of the epitaxial unit facing away from the driving backplane to form a patterned passivation layer;

[0086] S403. Fabricate a conductive interconnect layer on the patterned passivation layer so that the conductive interconnect layer is electrically connected to the epitaxial unit through the through hole to fabricate a display component.

[0087] The passivation layer disclosed in this embodiment can be deposited on the epitaxial unit by physical passivation deposition and cover the exposed driving backplane to protect the epitaxial unit and the driving backplane. In order to facilitate subsequent conduction, the passivation layer at the top surface position of the epitaxial unit is etched to form a through hole to achieve the effect of patterning the passivation layer, and then the conductive interconnect layer is deposited by evaporation coating process to uniformly deposit the conductive interconnect layer material on the surface of the passivation layer, improving the uniformity of the conductive interconnect layer.

[0088] In summary, the present application discloses a display component, which includes a driving backplane, an epitaxial structure, a passivation layer and a conductive interconnection layer, wherein the epitaxial structure is arranged on the driving backplane, and the epitaxial structure includes a plurality of epitaxial units; the passivation layer is arranged on the side of the epitaxial structure away from the driving backplane; a through hole is opened on the passivation layer, and the through hole is directly opposite to the side of the epitaxial unit away from the driving backplane; the conductive interconnection layer is arranged on the passivation layer, and the conductive interconnection layer is electrically connected to the epitaxial unit through the through hole; along the direction in which the epitaxial structure is away from the driving backplane, the epitaxial unit is arranged to have a gradually decreasing cross-sectional width. The display component disclosed in this embodiment is used for a surface light source and is processed by wafer bonding. The epitaxial structure is arranged on the driving backplane, and the cross-sectional width of the epitaxial unit gradually decreases in the direction away from the driving backplane, forming multiple steps, thereby improving the step coverage. The original height difference between the top surface of the epitaxial unit and the surface of the driving backplane is large. After forming multiple steps, the gradient of the side of the epitaxial unit is reduced, and the aspect ratio is reduced, thereby avoiding the passivation layer or the conductive interconnect layer from being disconnected at the side of the epitaxial unit, improving the production yield of the product and increasing processing reliability. In addition, by forming a multi-layer stepped structure, the surface area of the epitaxial unit is also increased, thereby improving the external quantum efficiency of the display component and improving the performance of the semiconductor product.

[0089] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0090] It should be noted that the present invention takes the display component and its manufacturing method as an example to introduce the specific structure and working principle of the present invention, but the application of the present invention is not limited to the display component or its manufacturing method, and can also be applied to the production and use of other similar workpieces.

[0091] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

[0092] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display component, characterized in that, Comprising: A driving backplane; An epitaxial structure disposed on the driving backplane, and the epitaxial structure includes a plurality of epitaxial units; A passivation layer disposed on a side of the epitaxial structure away from the driving backplane; through holes are formed in the passivation layer, and the through holes face a side of the epitaxial unit away from the driving backplane; A conductive interconnect layer disposed on the passivation layer, and the conductive interconnect layer is electrically connected to the epitaxial unit through the through hole; Wherein, along a direction in which the epitaxial structure is away from the driving backplane, the epitaxial unit is configured to have a gradually decreasing cross-sectional width.

2. The display component according to claim 1, wherein The display component further includes a bonding layer disposed between the epitaxial unit and the driving backplane.

3. The display component according to claim 2, characterized in that Along a direction in which the epitaxial structure is away from the driving backplane, a cross-sectional width of the bonding layer is greater than a cross-sectional width of the epitaxial unit.

4. The display component according to claim 2, wherein The display component further includes a current spreading layer disposed between the bonding layer and the epitaxial unit.

5. The display component according to claim 4, wherein Along a direction in which the epitaxial structure is away from the driving backplane, cross-sectional widths of the bonding layer, the current spreading layer, and the epitaxial unit gradually decrease.

6. The display component according to claim 2, wherein The bonding layer includes a bonding layer of a metal material or a bonding layer of an alloy material.

7. The display component according to claim 1, characterized in that, The epitaxial unit includes a first semiconductor layer, an active layer, and a second semiconductor layer; the first semiconductor layer is close to a side of the driving backplane; Along a direction in which the epitaxial structure is away from the driving backplane, cross-sectional widths of the first semiconductor layer, the active layer, and the second semiconductor layer gradually decrease; or, Along a direction in which the epitaxial structure is away from the driving backplane, a cross-sectional width of the first semiconductor layer is the same as a cross-sectional width of the active layer, and the cross-sectional width of the first semiconductor layer is greater than a cross-sectional width of the second semiconductor layer.

8. A manufacturing method of a display component, which is used to manufacture the display component according to any one of claims 1 to 7, characterized in that, Comprising: Providing a driving backplane and an epitaxial structure; Bonding the epitaxial structure to the driving backplane to form an intermediate structure; Etching the intermediate structure multiple times to form a plurality of epitaxial units on the driving backplane; wherein, a cross-sectional width of the intermediate structure gradually decreases along a direction away from the driving backplane; Fabricating a passivation layer and a conductive interconnect layer on the driving backplane to fabricate a display component.

9. The manufacturing method of the display component according to claim 8, characterized in that The step of etching the intermediate structure multiple times to form a plurality of epitaxial units on the driving backplane specifically includes: Coating and patterning a photoresist on an epitaxial layer of the intermediate structure to form a patterned first photoresist layer; Etching the epitaxial layer using the patterned first photoresist layer as a mask to form a once-patterned epitaxial layer, and removing the patterned first photoresist layer; Coating and patterning a photoresist on the once-patterned epitaxial layer to expose edges on both sides of the once-patterned epitaxial layer to form a patterned second photoresist layer; Etching the once-patterned epitaxial layer using the patterned second photoresist layer as a mask to form a twice-patterned epitaxial layer; wherein, a cross-sectional width of the twice-patterned epitaxial layer gradually decreases along a direction away from the driving backplane; Removing the patterned second photoresist layer; Depositing and patterning a hard mask on the twice-patterned epitaxial layer to form a patterned hard mask layer; Using the patterned hard mask layer as a mask, etching the secondarily patterned epitaxial layer to form a plurality of epitaxial units; Removing the patterned hard mask layer.

10. The manufacturing method of the display component according to claim 8, wherein, The step of fabricating a passivation layer and a conductive interconnection layer on the driving backplane to fabricate a display component specifically includes: Fabricating a passivation layer on the driving backplane to cover the epitaxial units; Etching the passivation layer to form through holes on a side of the epitaxial units facing away from the driving backplane, forming a patterned passivation layer; Fabricating a conductive interconnection layer on the patterned passivation layer so that the conductive interconnection layer is electrically connected to the epitaxial units through the through holes, fabricating a display component.

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