Semiconductor device

Abstract

The invention relates to a semiconductor device. A novel semiconductor device is provided. The semiconductor device includes a first transistor having a gate and a back gate, and a light emitting element. The semiconductor device is configured to perform a first operation of supplying a first potential to a back gate of the first transistor. A second operation in which a gate potential and a source potential of the first transistor are fixed and a drain and a back gate of the first transistor are turned on to set a potential of the back gate to a second potential corresponding to a potential difference between the source and the gate of the first transistor; a third operation in which a video signal is supplied to the gate of the first transistor; and a fourth operation of supplying a current corresponding to the image signal to the light-emitting element. The frequency at which the second operation is performed is lower than the frequency at which the third and fourth operations are performed.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As an example of the technical field of one aspect of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof can be cited. Background Art

[0003] In recent years, research and development of a self-emitting display device using a light-emitting element such as a light-emitting diode (LED) for pixels has been increasingly active. In particular, an active matrix display device using an organic EL (ElectroLuminescence) element as a light-emitting element has attracted attention. Generally, a self-emitting active matrix display device includes a pixel circuit having a light-emitting element. In addition, the pixel circuit has a transistor (driving transistor) that controls the amount of current supplied to the light-emitting element according to an image signal.

[0004] The emission luminance of the light-emitting element depends on the magnitude of the drain current of the driving transistor. Therefore, when the electrical characteristics (threshold voltage, etc.) of the driving transistors are uneven among a plurality of pixels constituting the screen of the display device, even if the same image signal is supplied to the plurality of pixels, a difference in the emission luminance of each pixel occurs. The unevenness of the electrical characteristics of the driving transistors among the plurality of pixels is one of the causes of the deterioration of the display quality of the display device.

[0005] In order to reduce the unevenness of the electrical characteristics of the driving transistors among a plurality of pixels, pixel circuits having various structures have been proposed. Patent Document 1 discloses a structure in which a transistor having a gate and a back gate is used as a driving transistor to reduce the unevenness of the electrical characteristics of the driving transistor.

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-132816 Summary of the Invention

[0007] Patent Document 1 shows the following structure: In a structure where the source of a driving transistor is connected to an organic EL element, by fixing the potential of the back gate of the driving transistor and changing the potential of the source, the threshold voltage of the driving transistor is obtained. The organic EL element has a structure in which a light-emitting layer is sandwiched between an anode and a cathode, and thus has a capacitance. Therefore, in the structure shown in Patent Document 1, in order to obtain the threshold voltage of the driving transistor, it is necessary to charge the capacitance of the organic EL element. Therefore, there is a problem that the period for obtaining the threshold voltage tends to be long.

[0008] One of the objects of one embodiment of the present invention is to provide a semiconductor device in which the influence of non-uniform characteristics is reduced. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with low power consumption. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with high reliability. In addition, one of the objects of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the objects of one embodiment of the present invention is to provide a display device with high display quality. In addition, one of the objects of one embodiment of the present invention is to provide a display device with low power consumption. In addition, one of the objects of one embodiment of the present invention is to provide a novel display device.

[0009] Note that the description of the above objects does not preclude the existence of other objects. Those of ordinary skill in the art can naturally learn and extract other objects from the descriptions in the specification, drawings, claims, etc. One embodiment of the present invention does not need to achieve all of the above objects (the above objects and other objects).

[0010] (1) One embodiment of the present invention is a semiconductor device including a first transistor having a gate and a back gate and a light-emitting element. The semiconductor device is configured to perform a first operation of supplying a first potential to the back gate of the first transistor, a second operation of fixing the gate potential and the source potential of the first transistor and bringing the drain and the back gate of the first transistor into a conductive state to set the potential of the back gate to a second potential, a third operation of supplying an image signal to the gate of the first transistor, and a fourth operation of supplying a current corresponding to the image signal to the light-emitting element. The second potential corresponds to the difference between the source potential and the gate potential of the first transistor, the frequency of performing the second operation is lower than the frequency of performing the third operation, and the frequency of performing the second operation is lower than the frequency of performing the fourth operation.

[0011] In (1), for example, the second potential is lower than the first potential.

[0012] (2) Another aspect of the present invention is a semiconductor device including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; a first capacitor element and a second capacitor element; and a light-emitting element. The first transistor includes a gate, a back gate, a first terminal, and a second terminal. The second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the first capacitor element, the second capacitor element, and the light-emitting element all include a first terminal and a second terminal. The first terminal of the first transistor is electrically connected to the second terminal of the second transistor and the first terminal of the third transistor. The second terminal of the third transistor is electrically connected to the back gate of the first transistor, the first terminal of the seventh transistor, and the first terminal of the second capacitor element. The second terminal of the second capacitor element is electrically connected to the first terminal of the fourth transistor, the second terminal of the first transistor, the first terminal of the light-emitting element, and the second terminal of the first capacitor element. The gate of the first transistor is electrically connected to the first terminal of the first capacitor element, the second terminal of the fifth transistor, and the first terminal of the sixth transistor. The W / L of the third transistor is smaller than the W / L of the fifth transistor. The W / L of the third transistor is smaller than the W / L of the sixth transistor. The W / L of the seventh transistor is smaller than the W / L of the fifth transistor. The W / L of the seventh transistor is smaller than the W / L of the sixth transistor.

[0013] In (2), the first capacitor element is configured to maintain the potential difference between the second terminal and the gate of the first transistor, and the second capacitor element is configured to maintain the potential difference between the second terminal and the back gate of the first transistor.

[0014] In (2), the first terminal of the second transistor is electrically connected to the first wiring, the first terminal of the fifth transistor is electrically connected to the second wiring, the second terminal of the sixth transistor is electrically connected to the third wiring, the second terminal of the seventh transistor is electrically connected to the fourth wiring, the second terminal of the fourth transistor is electrically connected to the fifth wiring, the second terminal of the light-emitting element is electrically connected to the sixth wiring. The first wiring is configured to supply a first potential, the second wiring is configured to supply an image signal, the third wiring is configured to supply a second potential, the fourth wiring is configured to supply a third potential, the fifth wiring is configured to supply a fourth potential, and the sixth wiring is configured to supply a fifth potential.

[0015] In (1) and (2), the first transistor may be an n-type transistor. The first transistor may include an oxide semiconductor in the semiconductor layer forming the channel. The light-emitting element may be an organic EL element.

[0016] According to one aspect of the present invention, a semiconductor device can be provided in which the influence of non-uniform characteristics is reduced. In addition, a semiconductor device with low power consumption can be provided. In addition, a semiconductor device with high reliability can be provided. In addition, a novel semiconductor device can be provided. In addition, a display device with high display quality can be provided. In addition, a display device with low power consumption can be provided. In addition, a novel display device can be provided.

[0017] Note that the description of the above effects does not preclude the existence of other effects. Those of ordinary skill in the art can naturally learn and extract other effects from the descriptions in the specification, drawings, claims, etc. One aspect of the present invention does not necessarily have all of the above effects (the above effects and other effects). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A and Figure 1B is a diagram showing an example of the circuit structure of a semiconductor device;

[0019] Figure 2 is a diagram showing an example of the circuit structure of a semiconductor device;

[0020] Figure 3 is a timing diagram illustrating an example of the operation of a semiconductor device;

[0021] Figure 4A and Figure 4B is a diagram illustrating an example of the operation of a semiconductor device;

[0022] Figure 5A and Figure 5B is a diagram illustrating an example of the operation of a semiconductor device;

[0023] Figure 6A is a timing diagram illustrating an example of the operation of a semiconductor device, Figure 6B is a diagram illustrating an example of the operation of a semiconductor device;

[0024] Figure 7A is a timing diagram illustrating an example of the operation of a semiconductor device, Figure 7B is a diagram illustrating an example of the operation of a semiconductor device;

[0025] Figure 8A is a timing diagram illustrating an example of the operation of a semiconductor device, Figure 8B is a diagram illustrating an example of the operation of a semiconductor device;

[0026] Figure 9A is a timing diagram illustrating an example of the operation of a semiconductor device, Figure 9B is a diagram illustrating an example of the operation of a semiconductor device;

[0027] Figure 10is a timing chart illustrating an operation example of a semiconductor device;

[0028] Figure 11A and Figure 11B is a diagram illustrating an operation example of a semiconductor device;

[0029] Figure 12A and Figure 12B is a diagram illustrating an operation example of a semiconductor device;

[0030] Figure 13 is a diagram showing an example of the circuit structure of a semiconductor device;

[0031] Figure 14A is a diagram showing an example of the circuit structure of a semiconductor device, Figure 14B is a diagram illustrating an operation example of a semiconductor device;

[0032] Figure 15A and Figure 15B is a diagram showing an example of the circuit structure of a semiconductor device;

[0033] Figure 16A is a diagram showing an example of the circuit structure of a semiconductor device; Figure 16B is a diagram illustrating an operation example of a semiconductor device;

[0034] Figure 17A and Figure 17B is a diagram illustrating an operation example of a semiconductor device;

[0035] Figure 18A and Figure 18B is a diagram showing an example of the circuit structure of a semiconductor device;

[0036] Figure 19 is a diagram showing an example of the circuit structure of a semiconductor device;

[0037] Figure 20A and Figure 20B is a diagram showing an example of the circuit structure of a semiconductor device;

[0038] Figure 21 is a diagram showing an example of the circuit structure of a semiconductor device;

[0039] Figure 22 is a diagram showing an example of the circuit structure of a semiconductor device;

[0040] Figure 23A is a diagram showing an example of the circuit structure of a semiconductor device; Figure 23B and Figure 23C is a diagram showing the circuit symbol of a transistor;

[0041] Figure 24 is a diagram showing an example of the circuit structure of a semiconductor device;

[0042] Figure 25A and Figure 25B is a diagram showing the circuit symbol of a transistor;

[0043] Figure 26 is a timing diagram explaining an operating example of a semiconductor device;

[0044] Figure 27 is a diagram showing an example of the circuit structure of a semiconductor device;

[0045] Figures 28A1 to 28A7 and Figures 28B1 to 28B6 is a diagram explaining an electrical connection;

[0046] Figures 29A to 29C is a diagram explaining the structure of a transistor;

[0047] Figures 30A to 30C is a diagram explaining the structure of a transistor;

[0048] Figure 31A and Figure 31B is a diagram explaining the structure of a transistor;

[0049] Figure 32A and Figure 32B is a diagram explaining the structure of a transistor;

[0050] Figures 33A to 33C is a diagram explaining the structure of a transistor;

[0051] Figures 34A to 34C is a diagram explaining the structure of a transistor;

[0052] Figures 35A to 35E is a diagram explaining an example of the structure of a transistor;

[0053] Figure 36A and Figure 36B is a diagram explaining an example of the structure of a transistor;

[0054] Figures 37A to 37E is a diagram explaining an example of the structure of a transistor;

[0055] Figure 38 is a diagram explaining an example of the structure of a transistor;

[0056] Figures 39A to 39E is a diagram explaining an example of the structure of a transistor;

[0057] Figures 40A to 40D is a cross-sectional view explaining a method of depositing a metal oxide;

[0058] Figures 41A to 41D is a cross-sectional view explaining a method of depositing a metal oxide;

[0059] Figure 42 It is a diagram showing an example of the planar structure of a semiconductor device;

[0060] Figure 43A and Figure 43B It is a diagram showing an example of the planar structure of a semiconductor device;

[0061] Figure 44 It is a diagram showing an example of the cross-sectional structure of a semiconductor device;

[0062] Figure 45 It is a diagram showing an example of the cross-sectional structure of a semiconductor device;

[0063] Figure 46A It is a perspective view showing an example of the structure of a display device, Figures 46B to 46F It is a plan view showing an example of pixel arrangement;

[0064] Figures 47A to 47D It is a diagram showing an example of the structure of a light-emitting element;

[0065] Figures 48A to 48D It is a diagram showing an example of the structure of a light-emitting element;

[0066] Figures 49A to 49D It is a diagram showing an example of the structure of a light-emitting element;

[0067] Figures 50A to 50C It is a diagram showing an example of the structure of a light-emitting element;

[0068] Figure 51 It is a block diagram showing an example of the structure of a display device;

[0069] Figure 52A and Figure 52B It is a block diagram showing an example of the structure of a display device;

[0070] Figure 53A and Figure 53B It is a block diagram showing an example of the structure of a display device;

[0071] Figures 54A to 54C and Figure 54E It is a circuit diagram showing an example of the structure of a semiconductor device, Figure 54D It is a timing diagram showing an example of the operation of a semiconductor device;

[0072] Figure 55 It is a cross-sectional view showing an example of the structure of a display device;

[0073] Figure 56A and Figure 56B It is a cross-sectional view showing an example of the structure of a display device;

[0074] Figure 57A and Figure 57Bis a cross-sectional view showing a structural example of a display device;

[0075] Figure 58A and Figure 58B is a diagram showing a structural example of a display device;

[0076] Figures 59A to 59D is a diagram showing an example of an electronic device;

[0077] Figures 60A to 60F is a diagram showing an example of an electronic device;

[0078] Figures 61A to 61G is a diagram showing an example of an electronic device. Detailed Embodiments

[0079] Hereinafter, embodiments will be described with reference to the drawings. Note that the embodiments can be implemented in a plurality of different ways, and it is easily understood by those skilled in the art that the ways and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the contents described in the following embodiments.

[0080] In this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics and refers to a circuit including semiconductor elements (such as transistors, diodes, photodiodes, etc.) and a device having such a circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips having integrated circuits, and electronic components in which chips are housed in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices and sometimes include semiconductor devices.

[0081] In the drawings according to this specification and the like, for ease of understanding, the display size, layer thickness, or area may sometimes be exaggerated. Therefore, the present invention is not necessarily limited to the sizes, aspect ratios, etc. in the drawings. In addition, in the drawings, ideal examples are schematically shown and are not limited to the shapes, values, etc. shown in the drawings.

[0082] Note that in the structure of the invention in the embodiments, the same reference numerals may sometimes be used in different drawings to indicate the same part or parts having the same function, and repeated descriptions may sometimes be omitted. In addition, when showing parts having the same function, the same hatching may sometimes be used without particularly attaching reference numerals. In addition, for ease of understanding, in perspective views, plan views, etc., the description of some constituent elements may sometimes be omitted.

[0083] In this specification and the like, ordinal numbers such as "first", "second", etc. are added to avoid confusion of components. Therefore, the ordinal numbers do not limit the number of components. In addition, the ordinal numbers do not limit the order of components. For example, a component attached with "first" in one embodiment of this specification and the like may be a component attached with "second" in other embodiments or claims and the like. In addition, for example, a component attached with "first" in one embodiment of this specification and the like may be omitted in other embodiments or claims and the like. In addition, to avoid confusion of components, even if there is no ordinal number attached to a phrase in this specification, an ordinal number may sometimes be attached to it in the claims. In addition, even if there is an ordinal number attached to a phrase in this specification, an ordinal number different from the above may sometimes be attached to it in the claims. In addition, even if there is an ordinal number attached to a phrase in this specification, the ordinal number may sometimes be omitted in the claims.

[0084] In this specification and the like, for convenience, phrases indicating configuration such as "upper", "lower", "above", "below", etc. are sometimes used to describe the positional relationship of components with reference to the accompanying drawings. In addition, the positional relationship of components is appropriately changed according to the direction describing each structure. Therefore, it is not limited to the phrases described in the specification and the like, and the phrases can be appropriately changed according to the situation. For example, for the expression "the insulator located on the top surface of the conductor", by rotating the direction of the shown accompanying drawing by 180 degrees, it can be changed to "the insulator located on the bottom surface of the conductor".

[0085] In addition, the phrases "upper" and "lower" do not limit the positional relationship of components to be directly above or directly below and in direct contact. For example, for the expression "electrode B on insulating layer A", it is not necessarily required that electrode B is formed directly in contact on insulating layer A, and it may also include cases where other components are included between insulating layer A and electrode B.

[0086] In this specification and the like, phrases such as "overlap" do not limit the state such as the lamination order of components. For example, when expressed as "electrode B overlapping insulating layer A", it is not limited to the state where electrode B is formed on insulating layer A, and it may also include the state where electrode B is formed under insulating layer A or the state where electrode B is formed on the right side (or left side) of insulating layer A.

[0087] In addition, in this specification and the like, depending on the circumstances, the terms such as "film" and "layer" can be interchanged with each other. For example, sometimes the "conductive layer" can be interchanged with the "conductive film". For example, sometimes the "insulating film" can be interchanged with the "insulating layer". Or, depending on the situation or circumstances, the terms such as "film" and "layer" can be replaced with other terms without using them. For example, sometimes the "conductive layer" or the "conductive film" can be interchanged with the "conductor". Or, sometimes the "conductor" can be interchanged with the "conductive layer" or the "conductive film". For example, sometimes the "insulating layer" or the "insulating film" can be interchanged with the "insulator". Or, sometimes the "insulator" can be interchanged with the "insulating layer" or the "insulating film".

[0088] In this specification and the like, the terms such as "electrode", "wiring", and "terminal" do not functionally limit their constituent elements. For example, sometimes the "electrode" is used as part of the "wiring", and vice versa. Furthermore, the "electrode" or "wiring" includes cases where multiple "electrodes" or multiple "wirings" are formed integrally, etc. In addition, for example, sometimes the "terminal" is used as part of the "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes", multiple "wirings", multiple "terminals", etc. are formed integrally, etc. Thus, for example, the "electrode" can be part of the "wiring" or "terminal", and, for example, the "terminal" can be part of the "wiring" or "electrode". In addition, sometimes the terms such as "electrode", "wiring", and "terminal" are interchanged with the terms such as "region", "conductive layer", etc.

[0089] In this specification and the like, depending on the situation or circumstances, sometimes the terms such as "wiring", "signal line", and "power supply line" can be interchanged with each other. For example, sometimes the "wiring" can be interchanged with the "signal line". In addition, for example, sometimes the "wiring" can be interchanged with the "power supply line", etc. Vice versa, sometimes the "signal line" and "power supply line" can be interchanged with the "wiring". Sometimes the "power supply line", etc. can be interchanged with the "signal line", etc. Vice versa, sometimes the "signal line", etc. can be interchanged with the "power supply line", etc. In addition, depending on the situation or circumstances, the "potential" applied to the wiring can be interchanged with the "signal", etc. Vice versa, sometimes the "signal", etc. can be interchanged with the "potential".

[0090] In this specification, the "source" refers to the source region, source electrode, or source wiring. The source region refers to one of the two regions adjacent to the channel formation region in the semiconductor layer. The source electrode refers to a conductive layer having a part connected to the source region.

[0091] In this specification, the "drain" refers to the drain region, drain electrode, or drain wiring. The drain region refers to the other of the two regions adjacent to the channel formation region in the semiconductor layer. The drain electrode refers to a conductive layer having a part connected to the drain region.

[0092] In this specification, "gate" refers to a gate electrode or a gate wiring. The gate electrode refers to an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling a resistance value between a source and a drain of the transistor according to a supplied voltage.

[0093] In this specification, sometimes one of a source and a drain of a transistor is referred to as "the first terminal of the transistor", and the other of the source and the drain of the transistor is referred to as "the second terminal of the transistor".

[0094] In this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less. In addition, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. In addition, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes a state in which the angle is 85° or more and 95° or less. In addition, "substantially perpendicular" or "roughly perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0095] In addition, in many cases, voltage means a potential difference between a certain potential and a reference potential (for example, a ground potential or a source potential). Thus, in many cases, voltage and potential can be interchanged. In this specification and the like, without special description, voltage and potential can be interchanged.

[0096] In addition, in this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential whose potential is higher than a low power supply potential VSS. In addition, a low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential whose potential is lower than a high power supply potential VDD. In addition, a ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a potential lower than GND, and when VSS is GND, VDD is a potential higher than GND.

[0097] In this specification, an "on state" of a transistor refers to a state in which a source and a drain of the transistor are in a conducting state (a state capable of conducting). In addition, an "off state" of a transistor refers to a state in which a source and a drain of the transistor are in a non-conducting state (a state that can be regarded as electrically interrupted).

[0098] In addition, in this specification and the like, the "on-state current" refers to the current flowing between the source and the drain when the transistor is in the on state. In addition, the "off-state current" refers to the current flowing between the source and the drain when the transistor is in the off state.

[0099] In this specification and the like, the potential H is the potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor"), and is the potential that turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). In addition, the potential L is the potential that turns off the n-type transistor, and is the potential that turns on the p-type transistor. Therefore, the potential H is a higher potential than the potential L. The potential H is sometimes equal to VDD. The potential L is sometimes equal to VSS. In addition, unless otherwise stated, the transistors shown in this specification are enhancement-mode (normally-off) n-type transistors.

[0100] In addition, in the drawings and the like, in order to clearly show the potential of wirings, electrodes, etc., an "H" indicating the potential H or an "L" indicating the potential L may be attached at a position adjacent to the wirings, electrodes, etc. In addition, an "H" or an "L" is attached in a framed form to the wirings, electrodes, etc. where the potential changes. In addition, when the transistor is in the off state, an "×" may be attached overlapping the transistor. In addition, an arrow indicating the direction of current flow may be attached.

[0101] In this specification and the like, unless otherwise stated, cases of "identical", "the same", "equal", "uniform" (including synonyms of these words) for count values and measurement values include an error of ±10%.

[0102] In addition, in the drawings of this specification and the like, arrows indicating the X direction, the Y direction, and the Z direction may be attached. In this specification and the like, the "X direction" refers to the direction along the X axis, and unless otherwise stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and the "Z direction". In addition, the X direction, the Y direction, and the Z direction are directions that cross each other. For example, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification and the like, one of the X direction, the Y direction, and the Z direction may be referred to as the "first direction". In addition, another one of the above directions may be referred to as the "second direction". In addition, the remaining one of the above directions may be referred to as the "third direction".

[0103] Generally, "electrostatic capacitance" has a structure in which two electrodes face each other across an insulator (dielectric). This specification, etc. includes the case where a "capacitor element" is the above "electrostatic capacitance". That is, in this specification, etc., a "capacitor element" includes a structure in which two electrodes face each other across an insulator, a structure in which two wirings face each other across an insulator, or a structure in which two wirings are arranged across an insulator. In addition, in this specification, sometimes one electrode of a capacitor element is referred to as "the first terminal of the capacitor element", and the other electrode is referred to as "the second terminal of the capacitor element".

[0104] In addition, in this specification, etc., a "switch" includes a plurality of terminals and has a function of switching (selecting) the conduction state and non-conduction state between the terminals. For example, when a switch includes two terminals and the two terminals are in a conduction state, it can be said that the switch is in the "conduction state". In addition, when the two terminals are in a non-conduction state, it can be said that the switch is in the "off state". Note that being switched to one of the conduction state and non-conduction state or maintaining one of the conduction state and non-conduction state is sometimes referred to as "controlling the conduction state". In addition, in this specification, for example, when a switch includes two terminals, sometimes one terminal is referred to as "the first terminal of the switch", and the other terminal is referred to as "the second terminal of the switch".

[0105] That is, a switch refers to an element having a function of controlling the conduction state. Or, a switch refers to an element having a function of selecting and switching a current path. As an example of a switch, an electrical switch or a mechanical switch, etc. can be used. That is, as long as a switch can control current, it is not limited to a specific element.

[0106] As a switch, an electrical switch or a mechanical switch, etc. can be used. As an example of an electrical switch, there are transistors (such as bipolar transistors, MOS transistors, etc.), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM; Metal Insulator Metal) diodes, metal-insulator-semiconductor (MIS; Metal Insulator Semiconductor) diodes, transistor-connected diodes, etc.) or logic circuits combining such elements, etc. In addition, when a transistor is used as a switch, the "conduction state" of the transistor refers to a state in which the source and drain of the transistor are regarded as short-circuited. In addition, the "non-conduction state" of the transistor refers to a state in which the source and drain of the transistor are electrically disconnected. When a transistor is used only as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.

[0107] As an example of a mechanical switch, a switch using MEMS (Micro Electro Mechanical Systems) technology can be cited. This switch has electrodes that can move mechanically, and the on-state or off-state is selected by moving these electrodes.

[0108] In this specification, when the same symbol is used for multiple components, especially when it is necessary to distinguish them, sometimes a distinguishing symbol such as "A", "b", "_1", "[n]", "[m, n]", etc. is attached to the symbol for display.

[0109] "Connection" in this specification includes, for example, "electrical connection". Note that when the connection relationship of circuit elements is defined as an object and expressed as "electrical connection", "electrical connection" includes, for example, "direct connection" and "indirect connection". "A is directly connected to B" means, for example, that no circuit element (such as a transistor or a switch. Note that wiring is not a circuit element) is interposed between A and B. On the other hand, "A is indirectly connected to B" means, for example, that A and B are connected through one or more circuit elements.

[0110] Here, when it is defined as "A is indirectly connected to B", it refers to the connection relationship in the following cases, for example. That is, when it is assumed that the circuit is operating, in the case where there is a timing of transfer of an electrical signal or interaction of potentials between A and B during the operation of the circuit, such a circuit can be defined as an object as "A is indirectly connected to B". In addition, even if there is no timing of transfer of an electrical signal or interaction of potentials between A and B, in the case where there is a timing of transfer of an electrical signal or interaction of potentials between A and B during the operation of the circuit, it can also be defined as "A is indirectly connected to B". Note that the expression "A is indirectly connected to B" defines the connection relationship of circuit elements as an object. Therefore, for example, even when the circuit is not operating because the power supply voltage is not supplied, the circuit can be defined as an object as "A is indirectly connected to B" (however, for example, it is limited to the case where there is a transfer of an electrical signal or interaction of potentials between A and B during the operation of the circuit when the circuit is operating because the power supply voltage is supplied).

[0111] The following shows specific examples of the case of "indirect connection". First, as an example of "A is indirectly connected to B", there is Figure 28A1 and Figure 28A2A and B are connected through the sources and drains of more than one transistor as shown, etc. As another example of the case of "A and B are indirectly connected", there is the case where A and B are connected through more than one switch, etc. In the case of "A and B are indirectly connected", there is a timing when at least once between A and B, one transistor becomes in an on state, a conducting state, or a state where current can flow, assuming the circuit is operating. In addition, in the case of "A and B are indirectly connected", there is a case including a timing when one transistor between A and B becomes in an off state or a non-conducting state. In the case of "A and B are indirectly connected", if a plurality of transistors are connected between A and B, there is a timing when each of the plurality of transistors between A and B becomes in an on state, a conducting state, or a state where current can flow, assuming the circuit is operating. That is, in the case of "A and B are indirectly connected", it is not necessary for all the plurality of transistors to become in an on state, a conducting state, or a state where current can flow at the same time. Therefore, in the case of "A and B are indirectly connected", there is a case including a timing when the plurality of transistors between A and B become in an off state or a non-conducting state at the same time or at different timings. As another example, as Figure 28A3 shown, in the case where A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that as described below, in the case where a fixed potential V is supplied to C from a power supply or GND, etc., although it can be said that "A and C are indirectly connected" or "B and C are indirectly connected", it cannot be said that "A and B are indirectly connected".

[0112] The above shows examples of cases where it can be said or cannot be said that there is an "indirect connection", but the following shows other examples of cases where it cannot be said that there is an "indirect connection". Even when there is a transfer of an electrical signal or an interaction of potentials between A and B during the operation of the circuit, there are sometimes exceptions where it cannot be said that "A and B are indirectly connected". As an example of such an exceptional case, there is the case where A and B are connected through an insulator. That is, in the case where A and B are connected through an insulator, it cannot be said that "A and B are indirectly connected". As a specific example of the case where A and B are connected through an insulator, there is the case of connecting a capacitor element between A and B as shown in Figure 28A4 . As another example of the case where A and B are connected through an insulator, there is the case of sandwiching a gate insulating film of a transistor between A and B as shown in Figure 28A5 . In this case, it cannot be said that "A (gate of the transistor) and B (source or drain of the transistor) are indirectly connected".

[0113] As other examples where it cannot be said that "A is indirectly connected to B", cases can be cited where there is no timing of transfer of electrical signals or interaction of potentials between A and B. For example, there are the following cases: As Figure 28A6 and Figure 28A7 shown, on the path from A to B, multiple transistors are connected through their sources and drains, and a fixed potential V is supplied to the nodes between the transistors from a power supply or GND, etc. In this case, although it cannot be said that "A is indirectly connected to B", it can be said that "A is indirectly connected to V" or "B is indirectly connected to V". In Figure 28A3 , in the case where A and C are connected through the source and drain of transistor TrP, B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from a power supply or GND, etc., since it has the same connection relationship as Figure 28A6 and Figure 28A7 , it cannot be said that "A is indirectly connected to B", but it can be said that "A is indirectly connected to C" or "B is indirectly connected to C".

[0114] Although the above shows examples of "indirect connection", the definition of "indirect connection" is included in the definition of "electrical connection", for example. Therefore, in the case where "A is indirectly connected to B", it can be said that "A is electrically connected to B".

[0115] The following shows specific examples of the case of "direct connection". As an example of the case where "A is directly connected to B", as Figure 28B1 , Figure 28B2 and Figure 28B3 shown, there is a case where A and B are not connected through a circuit element. In addition, as Figure 28B4 and Figure 28B5 shown, in the case where A and B are not connected to a power supply or GND, etc. that supplies a fixed potential V through a circuit element, it can be said that "A is directly connected to B", "A is directly connected to V", or "B is directly connected to V". In addition, as Figure 28B6 shown, even in the case where A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A is directly connected to B". In addition, since A and V or B and V are connected through the source and drain of a transistor, it cannot be said to be directly connected, but it can be said that "A is indirectly connected to V" or "B is indirectly connected to V".

[0116] Although the above shows examples of "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", for example. Therefore, in the case where "A is directly connected to B", it can be said that "A is electrically connected to B".

[0117] In addition, one aspect of the present invention includes a structure in which at least one of the gate, source, and drain of one or more transistors is not connected to any component or is connected to an arbitrary node. In addition, one aspect of the present invention includes a structure in which no signal or voltage is input to one or more wirings or an arbitrary signal or voltage is input.

[0118] Embodiment 1

[0119] A semiconductor device 10A according to one aspect of the present invention will be described with reference to the accompanying drawings. The semiconductor device 10A can be used, for example, for pixels of a display device.

[0120] <Example of structure>

[0121] Figure 1A An example of the circuit structure of the semiconductor device 10A is shown. The semiconductor device 10A includes switches SW1 to SW6, a transistor TrD, a capacitor element Cs1, a capacitor element Cs2, and a light-emitting element 61. The switches SW1 to SW6 each include a first terminal and a second terminal.

[0122] The first terminal of the switch SW1 is connected to the wiring Pw1, and the second terminal is connected to the first terminal of the switch SW2 and one of the source and drain of the transistor TrD. The second terminal of the switch SW2 is connected to the first terminal of the switch SW6, the back gate of the transistor TrD, and the first terminal of the capacitor element Cs2. The second terminal of the switch SW6 is connected to the wiring Vref1. The second terminal of the capacitor element Cs2 is connected to the first terminal of the switch SW3, the other of the source and drain of the transistor TrD, the second terminal of the capacitor element Cs1, and the first terminal of the light-emitting element 61. The second terminal of the switch SW3 is connected to the wiring Vref2. The second terminal of the light-emitting element 61 is connected to the wiring Pw2. In addition, in Figure 1A the first terminal of the light-emitting element 61 is used as an anode, and the second terminal of the light-emitting element 61 is used as a cathode.

[0123] The first terminal of the switch SW4 is connected to the wiring DL, and the second terminal of the switch SW4 is connected to the gate of the transistor TrD, the first terminal of the capacitor element Cs1, and the first terminal of the switch SW5. The second terminal of the switch SW5 is connected to the wiring Vref3.

[0124] In Figure 1A the region where the second terminal of the switch SW1, the first terminal of the switch SW2, and one of the source and drain of the transistor TrD are connected and they always have the same potential is referred to as the node Na.

[0125] Furthermore, a region where the other of the source and the drain of the transistor TrD, the second terminal of the capacitor Cs1 , the second terminal of the capacitor Cs2 , and the first terminal of the light emitting element 61 are connected and always have the same potential is referred to as a node Nb.

[0126] In addition, a region where the second terminal of the switch SW4 , the first terminal of the switch SW5 , the first terminal of the capacitor Cs1 , and the gate of the transistor TrD are connected and always have the same potential is referred to as a node Nc.

[0127] In addition, a region where the second terminal of the switch SW2 , the first terminal of the switch SW6 , the first terminal of the capacitor Cs2 , and the back gate of the transistor TrD are connected and always have the same potential is referred to as a node Nd.

[0128] The transistor TrD is a transistor including a back gate. Generally speaking, the gate and the back gate of the transistor including a back gate are configured in a manner of sandwiching a channel forming region of the semiconductor layer. In addition, both the gate and the back gate are formed using a conductive layer or a semiconductor layer with low resistivity. The back gate can have the same function as the gate.

[0129] Therefore, if Figure 1B As in the semiconductor device 10A shown in FIG. 1 , the gate and the back gate of the transistor TrD may be interchanged. In addition, when the gate is used to control the on and off states of the transistor, the potential of the back gate may be the same as the potential of the gate.

[0130] For example, when turning on a transistor, the on-state current can be further increased by supplying the potential to both the gate and the back gate, compared to the case where the potential to turn on the transistor is supplied to only one of the gate and the back gate. In addition, the threshold voltage of the transistor can be adjusted by independently controlling the potential of the back gate without interlocking with the gate.

[0131] In addition, since the gate and the back gate are formed by a conductive layer or the like in a transistor including a back gate, the electric field generated outside the transistor is not easy to act on the channel formation region (also referred to as "electric field shielding effect") by using the gate and the back gate to clamp the channel formation region of the semiconductor layer. Therefore, by providing a back gate in the transistor, the transistor can be operated stably. In addition, by providing a back gate in the transistor, the unevenness of characteristics between multiple transistors is reduced. By providing a back gate in the transistor, the reliability of the transistor can be improved. Therefore, the reliability of the semiconductor device including the transistor can be improved. Note that although the electric field shielding effect can be obtained when one or both of the gate and the back gate are in an electrically floating state (also referred to as a "floating state"), this effect can be improved by supplying a potential to the gate and the back gate.

[0132] In addition, when light is irradiated onto the channel formation region of a transistor, sometimes the electrical characteristics of the transistor change. Further, when light is irradiated onto the channel formation region while a voltage is applied to the transistor, sometimes the electrical characteristics of the transistor deteriorate. That is, sometimes the reliability of the transistor decreases. By using a conductive material having light-shielding properties for both the gate and the back gate, deterioration of the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0133] Although Figure 1A and Figure 1B show the circuit configuration when the transistor TrD is an n-type transistor, a p-type transistor can also be used as the transistor TrD. Compared with an n-type transistor, a p-type transistor can more easily implement a normally-off transistor, and the circuit design is relatively easy. On the other hand, the field-effect mobility of an n-type transistor is higher than that of a p-type transistor, so the operating speed of the semiconductor device 10A can be increased.

[0134] The wirings Pw1 and Pw2 are used as power supply lines. As Figure 2 shown, when a p-type transistor is used as the transistor TrD, the first terminal of the light-emitting element 61 is connected to the wiring Pw2, and the second terminal of the light-emitting element 61 is connected to the node Nb. Further, when an n-type transistor is used as the transistor TrD, the wiring Pw1 is supplied with the potential H or VDD, and the wiring Pw2 is supplied with the potential L or VSS. In addition, when a p-type transistor is used as the transistor TrD, the wiring Pw2 is supplied with the potential H or VDD, and the wiring Pw1 is supplied with the potential L or VSS.

[0135] <Working Example>

[0136] Next, a working example of the semiconductor device 10A shown in Figure 1A is described with reference to the drawings. Figure 3 is a timing chart for explaining Figure 1A the working example of the semiconductor device 10A shown in

[0137] Figure 4A , Figure 4B , Figure 5A and Figure 5B are circuit diagrams for explaining Figure 1A the working example of the semiconductor device 10A shown in

[0138] In addition, the wiring Vref1 is supplied with the potential V1, the wiring Vref2 is supplied with the potential V2, and the wiring Vref3 is supplied with the potential V3. The potential V1 is a potential that turns on the transistor TrD. Therefore, the potential V1 can also be the potential H or VDD. The potential V2 is a potential used to make the potential of the node Nb lower than the potential L. More specifically, the potential V2 is a potential lower than the value obtained by adding the threshold voltage of the light-emitting element 61 to the potential L. The potential V3 is preferably a reference potential (e.g., 0V).

[0139] The wiring Pw1 is supplied with the potential H, and the wiring Pw2 is supplied with the potential L. Note that the potential difference between the potential H and the potential L is sufficiently larger than the threshold voltage of the light-emitting element 61. The wiring DL is supplied with the video signal Vda. The video signal Vda is a potential between the potential V3 and the potential H. The magnitude of the drain current of the transistor TrD is determined according to the potential of the video signal Vda. That is, the amount of current flowing through the light-emitting element 61 depends on the potential of the video signal Vda.

[0140] As an initial state, the switch SW1 is in the ON state, and the switches SW2 to SW6 are in the OFF state. In addition, the potential of the node Na is the potential H, the potential of the node Nb is the potential VE, the potential of the node Nc is the video signal Vda + the potential VE, and the potential of the node Nd is the potential Vt. The potential VE is the potential when current flows through the light-emitting element 61. The potential Vt corresponds to the threshold voltage of the transistor TrD.

[0141] [Period T11]

[0142] The period T11 is a period used to reset (also referred to as "initialize") the potentials of the node Nb, the node Nc, and the node Nd of the semiconductor device 10A before setting the threshold voltage of the transistor TrD.

[0143] During the period T11, the switch SW1 is turned OFF, and the switches SW3, SW5, and SW6 are turned ON (refer to Figure 3 and Figure 4A ). During the period T11, the potential of the node Nb becomes the potential V2, the potential of the node Nc becomes the potential V3, and the potential of the node Nd becomes the potential V1. Thus, when the switch is in the conducting state, conduction exists between the two terminals, and when the switch is in the OFF state, non-conduction exists between the two terminals.

[0144] [Period T12]

[0145] Period T12 is a period for controlling the potential of node Nd. Specifically, this period is used to control the potential of node Nd according to the threshold voltage of transistor TrD and set the threshold voltage of transistor TrD in periods T13 and T14 to potential V3 - potential V2. For example, when potential V3 and potential V2 are the same potential, the threshold voltage of transistor TrD in periods T13 and T14 can be set to 0V.

[0146] During period T12, switch SW2 is turned off and switch SW6 is turned off (refer to Figure 3 and Figure 4B ). Since switch SW5 remains on, the potential of node Nc remains at potential V3. Also, since switch SW3 remains on, the potential of node Nb remains at potential V2.

[0147] During period T12, when switch SW2 becomes on and switch SW6 becomes off, current flows from node Nd through switch SW2, transistor TrD, and switch SW3 to wiring Vref2. As a result, the potential of node Nd drops from potential V1. The potential of node Nd drops until transistor TrD becomes off. When transistor TrD becomes off, node Nd becomes a floating state and the potential drop of node Nd stops. Also, node Na located between node Nd and transistor TrD becomes a floating state. The potentials of node Na and node Nd at this time are potential Vt. In this way, the potential of node Nd is set to potential V3 - potential V2. By obtaining potential Vt, the threshold voltage of transistor TrD is set to potential V3 - potential V2. That is to say, by obtaining potential Vt, the influence of the threshold voltage non-uniformity of transistor TrD can be mitigated.

[0148] In addition, in semiconductor device 10A according to one embodiment of the present invention, the potential of node Nc connected to the gate of transistor TrD and the potential of node Nb connected to the source of transistor TrD are fixed, and node Na connected to the drain of transistor TrD and node Nd connected to the back gate of transistor TrD are made conductive and charged and discharged, thereby setting the threshold voltage of transistor TrD to potential V3 - potential V2. Since the parasitic capacitances of node Na and node Nd are smaller than the parasitic capacitance of node Nb, the period for obtaining the threshold voltage can be shortened compared with the circuit for charging and discharging node Nb. Therefore, the time required for period T12 can be shortened.

[0149] [Period T13]

[0150] Period T13 is a period for setting the video signal Vda in node Nc.

[0151] During period T13, switch SW2 and switch SW5 are turned off and switch SW4 is turned on (see Figure 3 and Figure 5A ). By turning on switch SW4, the video signal Vda is set at node Nc. In addition, when switch SW2 is turned off, node Nd becomes a floating state and the potential (potential Vt) of node Nd is held. Further, since switch SW3 remains on, the potential of node Nb remains at potential V2. Therefore, the potential difference between the gate and the source of transistor TrD used as a driving transistor is Vda - V2. The potential difference between the back gate and the source of the driving transistor is Vt - V2.

[0152] Here, the capacitance value of capacitor element Cs2 is preferably greater than the capacitance value when the gate capacitance and the back gate capacitance of transistor TrD are connected in series. When the former capacitance is substantially the same as or less than the latter capacitance, the potential of node Nd may change according to the potential change of node Nc. The capacitance value of capacitor element Cs2 is preferably 5 times or more, more preferably 10 times or more, the capacitance value when the gate capacitance and the back gate capacitance of transistor TrD are connected in series.

[0153] [Period T14]

[0154] Period T14 is a period in which a current corresponding to the video signal Vda is supplied to the light-emitting element 61 to cause the light-emitting element 61 to emit light.

[0155] During period T14, switch SW1 is turned on and switch SW3 and switch SW4 are turned off (see Figure 3 and Figure 5B ). When switch SW1 is turned on, the potential of node Na becomes potential H. In addition, when switch SW3 is turned off, node Nb becomes a floating state. Further, when switch SW4 is turned off, node Nc becomes a floating state and the video signal Vda set at node Nc is held.

[0156] Here, capacitor element Cs1 holds the potential difference between node Nc and node Nb, and capacitor element Cs2 holds the potential difference between node Nd and node Nb. Further, by obtaining potential Vt during period T12, the threshold voltage of transistor TrD is set to potential V3 - potential V2. When the potential of node Nb is potential V2 and the potential of node Nc is the video signal Vda, the drain current (Id) of transistor TrD is represented by equation (1).

[0157] [Equation 1]

[0158]

[0159] In Equation (1), Id represents the drain current of transistor TrD, W represents the channel width of transistor TrD, L represents the channel length of transistor TrD, μ represents the mobility of transistor TrD, and C OX represents the gate capacitance of transistor TrD. In addition, Equation (1) can be converted into Equation (2).

[0160] [Equation 2]

[0161]

[0162] According to Equation (2), the drain current of transistor TrD becomes a value proportional to the square of the potential difference between the video signal Vda and the potential V3. Here, Equation (2) does not include the threshold voltage of transistor TrD. This means that the semiconductor device 10A according to one aspect of the present invention can significantly mitigate the influence of the non-uniformity of the threshold voltage of transistor TrD.

[0163] In addition, when the drain current of transistor TrD starts to flow, the potential of node Nb rises to become potential VE. For example, when the potential V2 is 0V, the potential of node Nb rises to potential VE. That is, the source potential of transistor TrD rises. Note that since node Nb is coupled to node Nc through the capacitive element Cs1, the potential of node Nc also rises by potential VE. Therefore, the potential difference between node Nc and node Nb is maintained. Similarly, since node Nb is coupled to node Nd through the capacitive element Cs2, the potential of node Nd also rises by potential VE. Therefore, the potential difference between node Nd and node Nb is maintained.

[0164] At this time, the capacitance of the capacitive element Cs1 is preferably larger than the gate capacitance of transistor TrD. When the capacitance of the capacitive element Cs1 is approximately the same as or smaller than the gate capacitance, sometimes the potential change of node Nb is not correctly transmitted to node Nc. The capacitance of the capacitive element Cs1 is preferably 5 times or more, more preferably 10 times or more, of the gate capacitance of transistor TrD. Similarly, the capacitance of the capacitive element Cs2 is preferably larger than the back-gate capacitance of transistor TrD. When the capacitance of the capacitive element Cs2 is approximately the same as or smaller than the back-gate capacitance, sometimes the potential change of node Nb is not correctly transmitted to node Nd. The capacitance of the capacitive element Cs2 is preferably 5 times or more, more preferably 10 times or more, of the back-gate capacitance of transistor TrD.

[0165] By using the semiconductor device 10A according to one embodiment of the present invention as a pixel, a display device with high display quality can be realized. In addition, by obtaining the threshold voltage for each frame or for each certain period, a decrease in display quality can be suppressed, and high display quality can be maintained for a long time. Therefore, by using the semiconductor device 10A according to one embodiment of the present invention as a pixel, a display device with high reliability can be realized.

[0166] The semiconductor device 10A according to one embodiment of the present invention obtains the threshold voltage of the transistor TrD by charging and discharging the node Nd without charging and discharging the node Nb. Since the parasitic capacitance of the node Nd is smaller than the parasitic capacitance of the node Nb, the period for obtaining the threshold voltage can be shortened compared with the circuit that charges and discharges the node Nb. By shortening the period for obtaining the threshold voltage, the power consumption of the semiconductor device 10A is reduced.

[0167] In addition, in the semiconductor device 10A according to one embodiment of the present invention, the wirings that are in conduction with the node Nc are different during the period T12 and the period T13. Therefore, the threshold voltage can be obtained when the video signal Vda is written in other rows. That is, the period T13 of a certain row and the period T12 of other rows can be performed simultaneously. Therefore, the time required for the period T12 can be shortened. Therefore, by using the semiconductor device 10A according to one embodiment of the present invention as a pixel, an increase in frame frequency and an increase in resolution can be realized, and thus the display quality of the display device can be improved.

[0168] In addition, during the periods T11 to T13, by setting the potential V2 to a potential lower than the potential L, a reverse bias can be applied to the light-emitting element 61. By applying a reverse bias to the light-emitting element 61, deterioration of the light-emitting element 61 can be suppressed.

[0169] In addition, during the period T14, the transistor TrD operates in the saturation region. Therefore, even if the potential of the wiring Pw1 changes, the drain current of the transistor TrD is not easily changed. Therefore, the influence of the voltage drop of the wiring Pw1 can be mitigated.

[0170] Figure 6A It is a timing chart showing a modified example of the operation during the period T11. Figure 6B It shows Figure 6A It is a circuit diagram showing the operation during the period T11 shown. During the period T11, the switch SW2 can be made in the ON state. By making the switch SW2 in the ON state, the potential of the node Na can also be the same potential V1 as the node Nd.

[0171] Figure 7A It is a timing chart showing a modified example of the operation during the period T13. Figure 7B It shows Figure 7AThe circuit diagram of the operation during period T13 is shown. During period T13, switch SW3 can be made in the closed state. In this case, during period T13, transistor TrD becomes in the on state, and current flows from wiring Pw1 through switch SW1 and transistor TrD to node Nb. Therefore, the potential of node Nd is slightly higher than potential V2. The rising amplitude of the potential of this node Nd is a value corresponding to the mobility of transistor TrD. The higher the mobility of transistor TrD, the larger the rising amplitude of the potential of node Nd. The larger the rising amplitude of the potential of node Nd, the smaller the potential difference between the gate and source of transistor TrD. The smaller the potential difference between the gate and source of transistor TrD, the smaller the drain current of transistor TrD. Thus, the influence of the non-uniformity of the mobility of transistor TrD can be reduced.

[0172] Figure 8A It is a timing chart showing a modified example of the operation during period T11. Figure 8B It shows Figure 8A The circuit diagram of the operation during period T11 shown. During period T11, switch SW5 can be made in the closed state.

[0173] Figure 9A It is a timing chart showing a modified example of the operation during period T12. Figure 9B It shows Figure 9A The circuit diagram of the operation during period T12 shown. During period T12, switch SW5 can be made in the closed state.

[0174] Figure 10 It shows Figure 3 The timing chart of a modified example of the operation of semiconductor device 10A shown. Figure 11A , Figure 11B , Figure 12A and Figure 12B are used to illustrate Figure 4A , Figure 4B , Figure 5A and Figure 5B The circuit diagram of a modified example of the operation of semiconductor device 10A shown.

[0175] Figure 1A The semiconductor device 10A shown can keep switch SW4 in the on state and switch SW5 in the off state during period T11 and period T12 (see Figure 10 , Figure 11A and Figure 11B ). In this case, the threshold voltage of transistor TrD during period T13 and period T14 is set to affect signal Vda - potential V2. Then, during period T13, switch SW4 is made in the off state and switch SW5 is made in the on state. Thereby, node Nc is supplied with potential V3 (see Figure 10 and Figure 12A)。During period T14, when current flows through the light-emitting element 61, the potential at node Nb becomes potential VE, the potential at node Nc becomes potential V3 + potential VE, and the potential at node Nd becomes potential Vt + potential VE (refer to Figure 10 and Figure 12B ). By Figure 10 , Figure 11A , Figure 11B , Figure 12A and Figure 12B shown in the working examples, the influence of the threshold voltage non-uniformity of transistor TrD can also be reduced.

[0176] The structure shown in this embodiment can be implemented by appropriately combining with the structures shown in other embodiments.

[0177] Embodiment 2

[0178] In this embodiment, a modification example of the semiconductor device 10A according to one aspect of the present invention will be described. To avoid repetitive description, in this embodiment, mainly the differences from the semiconductor device 10A will be described.

[0179] Figure 13 Shows Figure 1A The circuit diagram of the semiconductor device 10B which is a modification example of the semiconductor device 10A shown. The difference between the semiconductor device 10B and Figure 1A the semiconductor device 10A shown is that in the semiconductor device 10B, the second terminal of the switch SW6 is connected to the wiring Pw1. By connecting the second terminal of the switch SW6 to the wiring Pw1, the wiring Vref1 can be omitted. By not providing the wiring Vref1, the occupied area of the semiconductor device 10B is reduced, and thus the integration degree can be improved. For example, one or both of the resolution and clarity of the display device using the semiconductor device 10B for the display part can be improved. In the semiconductor device 10B, the potential at node Nd becomes potential H during the initialization in period T11.

[0180] Figure 14A Shows Figure 1A The circuit diagram of the semiconductor device 10C which is a modification example of the semiconductor device 10A shown. The difference between the semiconductor device 10C and Figure 1A the semiconductor device 10A shown is that in the semiconductor device 10C, the switch SW6 and the wiring Vref1 are not provided. By not providing the switch SW6 and the wiring Vref1, the integration degree of the semiconductor device 10C can be improved. For example, one or both of the resolution and clarity of the display device using the semiconductor device 10C for the display part can be improved. In addition, the semiconductor device 10C is also a modification example of the semiconductor device 10B. By not providing the switch SW6, the occupied area can be further reduced compared with the semiconductor device 10B.

[0181] Figure 14B It is a circuit diagram showing an operation example of the semiconductor device 10C during the period T11. By turning on the switch SW1 and the switch SW2 during the period T11, the potential H can be supplied to the node Nd.

[0182] Figure 15A Shows Figure 1A A circuit diagram of the semiconductor device 10D which is a modified example of the semiconductor device 10A shown. The semiconductor device 10D is different from Figure 1A the semiconductor device 10A shown in that the second terminal of the switch SW5 is connected to the node Nb in the semiconductor device 10D.

[0183] By connecting the second terminal of the switch SW5 to the node Nb, the wiring Vref3 can be omitted. By not providing the wiring Vref3, the occupied area of the semiconductor device 10D is reduced, and thus the integration degree can be improved. For example, one or both of the resolution and clarity of the display device using the semiconductor device 10D for the display unit can be improved.

[0184] Figure 15B Shows Figure 1A A circuit diagram of the semiconductor device 10E which is a modified example of the semiconductor device 10A shown. The semiconductor device 10E is different from Figure 1A the semiconductor device 10A shown in that the second terminal of the switch SW5 is connected to the wiring Vref2 in the semiconductor device 10E. In addition, the semiconductor device 10E is also a modified example of the semiconductor device 10D.

[0185] By connecting the second terminal of the switch SW5 to the wiring Vref2, the wiring Vref3 can be omitted. By not providing the wiring Vref3, the occupied area of the semiconductor device 10E is reduced, and thus the integration degree can be improved. For example, one or both of the resolution and clarity of the display device using the semiconductor device 10E for the display unit can be improved.

[0186] Figure 16A Shows Figure 1A A circuit diagram of the semiconductor device 10F which is a modified example of the semiconductor device 10A shown. The semiconductor device 10F is different from Figure 1AThe difference of the semiconductor device 10A shown is that the switch SW5 and the wiring Vref3 are not provided in the semiconductor device 10F. By not providing the switch SW5 and the wiring Vref3, the integration degree of the semiconductor device 10F can be improved. For example, one or both of the resolution and clarity of a display device using the semiconductor device 10F for a display section can be improved. In addition, the semiconductor device 10F is also a modified example of the semiconductor device 10D. By not providing the switch SW5, the occupied area can be further reduced compared with the semiconductor device 10D.

[0187] Figure 16B It is a circuit diagram showing an operation example during the period T11 of the semiconductor device 10F. Figure 17A It is a circuit diagram showing an operation example during the period T12 of the semiconductor device 10F. Figure 17B It is a circuit diagram showing an operation example during the period T13 of the semiconductor device 10F. As Figure 16B and Figure 17A shown, during the period T11 and the period T12, the switch SW4 is turned on, and the potential V3 is supplied to the wiring DL. In addition, as Figure 17B shown, during the period T13, the switch SW4 is turned on, and the video signal Vda is supplied from the wiring DL to the node Nc.

[0188] Figure 18A Shows Figure 1A a circuit diagram of the semiconductor device 10G which is a modified example of the semiconductor device 10A shown. The semiconductor device 10G is different from the semiconductor device 10A shown in that the second terminal of the switch SW6 is connected to the wiring Pw1, and the second terminal of the switch SW5 is connected to the node Nb. In addition, it can also be said that the semiconductor device 10G has a structure combining the semiconductor device 10B and the semiconductor device 10D. Figure 1A shown in that in the semiconductor device 10G, the second terminal of the switch SW6 is connected to the wiring Pw1, and the second terminal of the switch SW5 is connected to the node Nb. In addition, it can also be said that the semiconductor device 10G has a structure combining the semiconductor device 10B and the semiconductor device 10D.

[0189] In the circuit structure of the semiconductor device 10G, the wiring Vref1 and the wiring Vref3 can be omitted. By not providing the wiring Vref1 and the wiring Vref3, the integration degree of the semiconductor device 10G can be improved. For example, one or both of the resolution and clarity of a display device using the semiconductor device 10G for a display section can be improved.

[0190] Figure 18B Shows Figure 1A a circuit diagram of the semiconductor device 10H which is a modified example of the semiconductor device 10A shown. The semiconductor device 10H is different from Figure 1AThe difference of the semiconductor device 10A shown is that in the semiconductor device 10H, the second terminal of the switch SW6 is connected to the wiring Pw1, and the second terminal of the switch SW5 is connected to the wiring Vref2. In addition, it can also be said that the semiconductor device 10H has a structure combining the semiconductor device 10B and the semiconductor device 10E.

[0191] In the circuit structure of the semiconductor device 10H, the wirings Vref1 and Vref3 can be omitted. By not providing the wirings Vref1 and Vref3, the integration degree of the semiconductor device 10H can be improved. For example, one or both of the resolution and clarity of a display device using the semiconductor device 10H for a display section can be improved.

[0192] Figure 19 shown Figure 1A The circuit diagram of the semiconductor device 10I, which is a modified example of the semiconductor device 10A shown. The semiconductor device 10I is Figure 1A different from the semiconductor device 10A shown in that in the semiconductor device 10I, the second terminal of the switch SW6 is connected to the wiring Pw1, and the switch SW5 is omitted. In addition, it can also be said that the semiconductor device 10I has a structure combining the semiconductor device 10B and the semiconductor device 10D. Additionally, it can also be said that the semiconductor device 10I has a structure obtained by removing the switch SW5 from the semiconductor device 10G.

[0193] In the circuit structure of the semiconductor device 10I, the wirings Vref1 and Vref3 can be omitted. By not providing the wirings Vref1 and Vref3, the integration degree of the semiconductor device 10I can be improved. For example, one or both of the resolution and clarity of a display device using the semiconductor device 10I for a display section can be improved.

[0194] Figure 20A shown Figure 1A The circuit diagram of the semiconductor device 10J, which is a modified example of the semiconductor device 10A shown. In addition, the semiconductor device 10J is also a modified example of the semiconductor device 10G. The semiconductor device 10J is different from the semiconductor device 10G in that the semiconductor device 10J does not include the switch SW6. By not providing the switch SW6, the occupied area can be further reduced compared with the semiconductor device 10G. Therefore, the integration degree of the semiconductor device 10J can be further improved compared with the semiconductor device 10G. For example, one or both of the resolution and clarity of a display device using the semiconductor device 10J for a display section can be improved.

[0195] Figure 20B shown Figure 1ACircuit diagram of the semiconductor device 10K which is a modified example of the semiconductor device 10A shown. In addition, the semiconductor device 10K is also a modified example of the semiconductor device 10H. The difference between the semiconductor device 10K and the semiconductor device 10H is that the semiconductor device 10K does not include the switch SW6. By not providing the switch SW6, the occupied area can be further reduced compared with the semiconductor device 10H. Therefore, the integration degree of the semiconductor device 10K can be further improved compared with the semiconductor device 10H. For example, one or both of the resolution and clarity of the display device using the semiconductor device 10K for the display section can be improved.

[0196] Figure 21 Shows Figure 1A Circuit diagram of the semiconductor device 10L which is a modified example of the semiconductor device 10A shown. In addition, the semiconductor device 10L is also a modified example of the semiconductor device 10J. The difference between the semiconductor device 10L and the semiconductor device 10J is that the semiconductor device 10L does not include the switch SW5. By not providing the switch SW5, the occupied area can be further reduced compared with the semiconductor device 10J. Therefore, the integration degree of the semiconductor device 10L can be further improved compared with the semiconductor device 10J. For example, one or both of the resolution and clarity of the display device using the semiconductor device 10L for the display section can be improved.

[0197] Figure 22 Shows Figure 1A Circuit diagram of the semiconductor device 10M which is a modified example of the semiconductor device 10A shown. The difference between the semiconductor device 10M and the semiconductor device 10A is that in the semiconductor device 10M, the light-emitting element 61 is connected in parallel with the capacitor element Cs3. Specifically, the first terminal of the capacitor element Cs3 is connected to the first terminal of the light-emitting element 61, and the second terminal of the capacitor element Cs3 is connected to the second terminal of the light-emitting element 61.

[0198] When the semiconductor device 10A is used for a pixel, the capacitance of the light-emitting element 61 sometimes varies depending on the emission color of the light-emitting element 61. By connecting the light-emitting element 61 in parallel with the capacitor element Cs3 as in the semiconductor device 10M, the luminance non-uniformity between pixels is reduced, and the display quality of the display device using the semiconductor device 10M for the display section can be improved.

[0199] As the switches SW1 to SW6, for example, transistors can be used. Figure 1AThe semiconductor device 10A shown can be composed of transistors Tr1 to Tr6, transistor TrD, capacitor element Cs1, capacitor element Cs2, and light-emitting element 61. For example, one of the source and drain of transistor Tr1 is used as the first terminal of switch SW1, and the other of the source and drain of transistor Tr1 is used as the second terminal of switch SW1.

[0200] Figure 23A Illustrated as Figure 1A An example of the circuit structure when switches SW1 to SW6 of the semiconductor device 10A shown use transistors Tr1 to Tr6.

[0201] Note that in the description using Figure 23A etc., the semiconductor device 10A is illustrated, but the description of the semiconductor device 10A can be applied to all semiconductor devices 10 (semiconductor devices 10A to 10M).

[0202] In Figure 23A , the gate of transistor Tr1 is connected to wiring GL1, and one of the source and drain of transistor Tr1 is connected to wiring Pw1. The other of the source and drain of transistor Tr1 is connected to one of the source and drain of transistor TrD and one of the source and drain of transistor Tr2. The gate of transistor Tr2 is connected to wiring GL2. The other of the source and drain of transistor Tr2 is connected to the back gate of transistor TrD, one of the source and drain of transistor Tr6, and the first terminal of capacitor element Cs2. The other of the source and drain of transistor Tr6 is connected to wiring Vref1, and the gate of transistor Tr6 is connected to wiring GL3.

[0203] The second terminal of capacitor element Cs2 is connected to one of the source and drain of transistor Tr3, the other of the source and drain of transistor TrD, the first terminal of light-emitting element 61, and the second terminal of capacitor element Cs1. The other of the source and drain of transistor Tr3 is connected to wiring Vref2, and the gate of transistor Tr3 is connected to wiring GL6. The second terminal of light-emitting element 61 is connected to wiring Pw2. The gate of transistor Tr4 is connected to wiring GL4, and one of the source and drain of transistor Tr4 is connected to wiring DL. The other of the source and drain of transistor Tr4 is connected to one of the source and drain of transistor Tr5, the first terminal of capacitor element Cs1, and the gate of transistor TrD.

[0204] Transistor TrD is a transistor including a back gate. In addition, transistors including a back gate can also be used as transistors Tr1 to Tr6. Since transistor TrD includes a back gate, a back gate can be provided in transistors Tr1 to Tr6 without adding processes.Figure 23B An example of a circuit symbol showing a transistor including a back gate is shown. As Figure 23C shown, by connecting the gate and the back gate, the gate and the back gate can always be kept at the same potential.

[0205] Although Figure 23A an example in which transistors Tr1 to Tr6 are formed of n-type transistors is shown, as Figure 24 shown, p-type transistors can also be used as transistors Tr1 to Tr6. In addition, n-type transistors can be used as a part of transistors Tr1 to Tr6 and p-type transistors can be used as other parts.

[0206] The field-effect mobility of an n-type transistor is higher than that of a p-type transistor, so the operating speed of the semiconductor device 10A can be increased. On the other hand, compared with an n-type transistor, a p-type transistor is more likely to realize a normally-off transistor, and the circuit design is relatively easy.

[0207] In addition, the semiconductor device 10A according to one embodiment of the present invention can use transistors having various structures. For example, transistors having various structures such as a planar type, a FIN (fin) type, a top gate type, and a bottom gate type can be used. In addition, as the transistor according to one embodiment of the present invention, a MOS type transistor, a junction type transistor, a bipolar transistor, etc. can be used.

[0208] When an n-type transistor is used as the transistor constituting the semiconductor device 10A, it is preferable to use an OS transistor (a transistor in which an oxide semiconductor is contained in a semiconductor layer forming a channel) as the transistor. Since the bandgap of the oxide semiconductor is 2 eV or more, the off-state current is significantly small. Specifically, the off-state current value of an OS transistor per channel width of 1 μm at room temperature can be 1 pA (1×10 -12 A), 1 aA (1×10 -18 A) or less, 1 zA (1×10 -21 A) or less, or 1 yA (1×10 -24 A) or less.

[0209] When an OS transistor is used as the transistor constituting the semiconductor device 10A, the charge written to each node can be maintained for a long time. For example, in a display device including the semiconductor device 10A, when a static image that does not need to be rewritten for each frame is displayed, the image can be continuously displayed even if the operation of the peripheral drive circuit is stopped. The above-described drive method of stopping the operation of the peripheral drive circuit when displaying a static image is also called "idle-stop drive". By performing idle-stop drive, the power consumption of the display device can be reduced.

[0210] In particular, when OS transistors are used as transistors Tr2 and Tr6, the charge written to node Nd can be retained for a long time. In addition, when OS transistors are used as transistors Tr4 and Tr5, the charge written to node Nc can be retained for a long time.

[0211] In addition, even in a high-temperature environment, the off-state current of the OS transistor hardly increases. Specifically, even in an environmental temperature above room temperature and below 200 °C, the off-state current hardly increases. In addition, even in a high-temperature environment, the on-state current is not easily reduced. The semiconductor device including the OS transistor operates stably and has high reliability even in a high-temperature environment.

[0212] In addition, an OS transistor can be used as transistor TrD. In addition, a Si transistor (a transistor in which a semiconductor layer forming a channel contains silicon) can be used as transistor TrD. Since the mobility of the Si transistor is higher than that of the OS transistor, a larger drain current than that of the OS transistor can flow. In addition, Si transistors can also be used as transistors Tr1 to Tr6. By using Si transistors, the operating speed of semiconductor device 10A can be increased.

[0213] As the transistors constituting semiconductor device 10A, single-gate transistors including one gate between the source and the drain can be used. In addition to this, double-gate transistors can also be used. Figure 25A The circuit symbol of double-gate transistor 180A is shown.

[0214] Transistor 180A has a structure in which transistors M1 and M2 are connected in series. In Figure 25A it shows the following state: One of the source and the drain of transistor M1 is connected to terminal S, the other of the source and the drain of transistor M1 is connected to one of the source and the drain of transistor M2, and the other of the source and the drain of transistor M2 is connected to terminal D. In addition, in Figure 25A it shows the state in which the gates of transistors M1 and M2 are connected and connected to terminal G.

[0215] Figure 25A The transistor 180A shown has a function of switching the conduction and non-conduction between terminal S and terminal D by changing the potential of terminal G. Therefore, transistor 180A as a double-gate transistor includes transistors M1 and M2 connected in series and is used as one transistor. That is to say, in Figure 25AIn this case, one of the source and drain of the transistor 180A is connected to the terminal S, the other of the source and drain is connected to the terminal D, and the gate is connected to the terminal G. In addition, since the double-gate transistor includes transistors M1 and M2 connected in series, the breakdown voltage between the terminal S and the terminal D is high. Therefore, the reliability is high.

[0216] In addition, the transistors constituting the semiconductor device 10A may also be triple-gate transistors. Figure 25B An example of the circuit symbol of the triple-gate transistor 180B is shown.

[0217] The transistor 180B has a structure in which transistors M1, M2, and M3 are connected in series. In Figure 25B it shows the following state: one of the source and drain of the transistor M1 is connected to the terminal S, the other of the source and drain of the transistor M1 is connected to one of the source and drain of the transistor M2, the other of the source and drain of the transistor M2 is connected to one of the source and drain of the transistor M3, and the other of the source and drain of the transistor M3 is connected to the terminal D. In addition, in Figure 25B it shows the state in which the gates of the transistors M1, M2, and M3 are connected to each other and connected to the terminal G.

[0218] Figure 25B The transistor 180B shown has a function of switching between conduction and non-conduction between the terminal S and the terminal D by changing the potential of the terminal G. Therefore, the transistor 180B as a triple-gate transistor includes transistors M1, M2, and M3 connected in series and is used as one transistor. That is to say, in Figure 25B one of the source and drain of the transistor 180B is connected to the terminal S, the other of the source and drain is connected to the terminal D, and the gate is connected to the terminal G. In addition, compared with the double-gate transistor, the breakdown voltage between the terminal S and the terminal D of the triple-gate transistor is high. Therefore, the reliability is higher.

[0219] The transistors constituting the semiconductor device 10A may also have a structure in which four or more transistors are connected in series.

[0220] Note that in Figure 25A and Figure 25B the transistors M1 to M3 are n-type transistors, but even if the transistors M1 to M3 use p-type transistors, the same effects as those described using Figure 25A and Figure 25B can be obtained.

[0221] Sometimes, transistors such as the transistor 180A and the transistor 180B that include multiple gates and are formed by connecting the multiple gates are called "multi-gate transistors" or "multi-gate transistors".

[0222] In addition, the multi-gate transistor is equivalent to a transistor with a long channel length. Therefore, compared with a single-gate transistor, the multi-gate transistor has good electrical characteristics (also referred to as "saturation characteristics") in the saturation region. Therefore, in order to improve the saturation characteristics of the transistor, a multi-gate transistor can be used.

[0223] Specifically, by using a multi-gate transistor as the transistor TrD, the saturation characteristics of the transistor TrD can be improved. By improving the saturation characteristics of the transistor TrD, the reproducibility of the emission luminance of the light-emitting element 61 with respect to the image signal written into the semiconductor device 10A is improved. As a result, the display quality of the display device using the semiconductor device 10A can be improved.

[0224] In addition, since the transistors Tr2 and Tr6 have the function of holding the charge of the node Nd, the off-state current is preferably small. Regarding this off-state current, the off-state current of the multi-gate transistor can be reduced compared with that of the single-gate transistor. Therefore, a multi-gate transistor is preferably used as the transistors Tr2 and Tr6. In addition, since the transistors Tr4 and Tr5 have the function of holding the charge of the node Nc, the off-state current is preferably small. Therefore, a multi-gate transistor is preferably used as the transistors Tr4 and Tr5. In addition, a multi-gate transistor can also be used as the transistors Tr1 and Tr3.

[0225] Here, in the periods T11 and T12, the threshold voltage of the transistor TrD is set to the potential V3 - the potential V2. Once the setting of the threshold voltage of the transistor TrD is performed, it does not need to be repeated. Therefore, the operations in the periods T11 and T12 are only performed once after the power supply is turned on, and the operations in the subsequent periods T11 and T12 can be omitted. In addition, even if the operations in the periods T11 and T12 are repeated, the frequency of repeating the operations in the periods T11 and T12 can be made lower than the frequency of repeating the operations in the periods T13 and T14. Figure 26 An example of a timing chart is shown when the operations in the periods T11, T12, T13, and T14 are performed and then the periods T11 and T12 are omitted and the operations in the periods T13 and T14 are repeated. In this way, if the implementation frequency of the periods T11 and T12 can be reduced, the power consumption generated by the operations in the periods T11 and T12 can be reduced. In addition, since the period T13 can be extended, the number of pixels can be increased, and the display unit and the like can be enlarged.

[0226] The time for which the charge is held at node Nd is sometimes longer than the time for which the charge is held at node Nc. Therefore, the off-state currents of transistors Tr2 and Tr6, which have the function of holding the charge at node Nd, are preferably smaller than the off-state currents of transistors Tr4 and Tr5, which have the function of holding the charge at node Nc. For example, the W / L of transistor Tr2 is preferably smaller than the W / L of transistor Tr4. For example, the W / L of transistor Tr2 is preferably smaller than the W / L of transistor Tr5. For example, the W / L of transistor Tr6 is preferably smaller than the W / L of transistor Tr4. In Figure 27 , transistor Tr2 is a multi-gate transistor, and the channel length of transistor Tr2 is longer than the channel length of transistor Tr4 and longer than the channel length of transistor Tr5. Transistor Tr6 is a multi-gate transistor, and its channel length is longer than that of transistor Tr4 and longer than that of transistor Tr5.

[0227] Furthermore, by shortening the channel lengths L of transistors Tr1 to Tr6 used as switches, the operating speed (the switching speed between the on-state and the off-state, the signal transmission speed, etc.) can be increased. Therefore, by making the channel lengths L of transistors Tr1 to Tr6 shorter than the channel length L of transistor TrD, the operating speed of semiconductor device 10A and the reproducibility of the emission luminance of light-emitting element 61 with respect to video signal Vda can be improved.

[0228] As the light-emitting element 61, various display elements such as an EL element (an EL element including an organic and an inorganic material, an organic EL element, an inorganic EL element), an LED (a white LED, a red LED, a green LED, a blue LED, etc.), a Micro LED, a QLED (Quantum-dot Light Emitting Diode), or an electron-emitting element can be used.

[0229] The structure shown in this embodiment can be implemented in appropriate combination with the structures shown in other embodiments.

[0230] Embodiment 3

[0231] In this embodiment, a transistor that can be used in a semiconductor device according to one aspect of the present invention will be described.

[0232] <Example of the structure of a transistor 1>

[0233] Figure 29A is a plan view of a transistor 200A that can be used in a semiconductor device according to one aspect of the present invention. Transistor 200A is an example of a planar transistor. Furthermore, in this specification, a planar transistor refers to a structure in which the source electrode and the drain electrode are located at the same height or approximately the same height and the current flowing through the semiconductor has a lateral component.

[0234] Figure 29B is a cross-sectional view along the dash-dotted line A1 - A2 in Figure 29A . Figure 29C is a cross-sectional view along the dash-dotted line A3 - A4 in Figure 29A . Note that, in the plan view of Figure 29A , some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in other plan views.

[0235] The transistor 200A includes an insulating layer 202 on a substrate 201, and includes a semiconductor layer 203 on the insulating layer 202. Further, an insulating layer 204 is included on the insulating layer 202 and the semiconductor layer 203. Further, a conductive layer 205 is included on the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have regions overlapping with each other with the insulating layer 204 therebetween.

[0236] The semiconductor layer 203 includes a region 203a, a channel formation region 203b, and a region 203c. The region 203a is used as one of a source region and a drain region. The region 203c is used as the other of the source region and the drain region. In the semiconductor layer 203, the region overlapping with the conductive layer 205 is used as the channel formation region 203b. Thus, the conductive layer 205 is used as the gate electrode of the transistor 200A. Further, the insulating layer 204 is used as the gate insulating layer of the transistor 200A.

[0237] Further, the length of the channel formation region 203b in the X direction is the channel length L of the transistor 200A (refer to Figure 29B ). Further, the length of the channel formation region 203b in the Y direction is the channel width W of the transistor 200A (refer to Figure 29C ).

[0238] Further, an insulating layer 206 is included on the insulating layer 204 and the conductive layer 205. Further, openings 207a are provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203a of the semiconductor layer 203. Further, openings 207b are provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203c of the semiconductor layer 203.

[0239] Further, a conductive layer 208a is provided on the insulating layer 206 and the opening 207a, and a conductive layer 208b is provided on the insulating layer 206 and the opening 207b. The conductive layer 208a is connected to the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. Further, the conductive layer 208b is connected to the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Further, the conductive layer 208a is used as one of the source electrode and the drain electrode of the transistor 200A, and the conductive layer 208b is used as the other of the source electrode and the drain electrode of the transistor 200A.

[0240] In addition, an insulating layer 209 is provided on the insulating layer 206 and the conductive layer 208 (the conductive layer 208a and the conductive layer 208b).

[0241] <Example structure of a transistor 2>

[0242] Figure 30A It is a plan view of a transistor 200B of a semiconductor device that can be used according to one aspect of the present invention. The transistor 200B is a modified example of the transistor 200A. Therefore, in order to avoid redundant description, mainly the differences between the transistor 200B and the transistor 200A will be described.

[0243] Figure 30B It is along Figure 30A the cross-sectional view along the dash-dotted line A1 - A2 in Figure 30C It is along Figure 30A the cross-sectional view along the dash-dotted line A3 - A4 in

[0244] The difference between the transistor 200B and the transistor 200A is that in the transistor 200B, a conductive layer 219 is included between the substrate 201 and the insulating layer 202. The conductive layer 219 is used as the back gate electrode of the transistor 200B. Therefore, the conductive layer 219 overlaps with the channel formation region 203b. In addition, the conductive layer 219 preferably extends beyond the end of the channel formation region 203b. That is, preferably, the channel formation region 203b is covered by the conductive layer 219. By covering the channel formation region 203b with the conductive layer 219, the electric field shielding effect described in the above embodiment can be improved.

[0245] <Example structure of a transistor 3>

[0246] Figure 31A It is a plan view of a transistor 200C of a semiconductor device that can be used according to one aspect of the present invention. Figure 31B It is along Figure 31A the cross-sectional view along the dash-dotted line A1 - A2 in

[0247] In the transistor 200C, an insulating layer 202 is included on the substrate 201, and a conductive layer 255 is included on the insulating layer 202. In addition, an insulating layer 257 is included on the conductive layer 255, an insulating layer 258 is included on the insulating layer 257, and an insulating layer 259 is included on the insulating layer 258. In this specification, sometimes the insulating layer 257, the insulating layer 258, and the insulating layer 259 are collectively referred to as the insulating layer 256 or the spacer layer. In addition, a conductive layer 261 is included on the insulating layer 259.

[0248] In a region overlapping a part of the conductive layer 255, an opening 262 is provided that passes through the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257. In addition, a semiconductor layer 263 is provided so as to cover the inner wall of the opening 262.

[0249] The semiconductor layer 263 has a region overlapping the bottom of the opening 262 and a region overlapping the side surface of the opening 262. That is, the semiconductor layer 263 has a region in contact with the insulating layer 256 inside the opening 262. In addition, the semiconductor layer 263 has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 inside the opening 262.

[0250] In addition, an insulating layer 264 is provided on the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided on the insulating layer 264. The conductive layer 265 has a region overlapping the semiconductor layer 263. The conductive layer 265 has a region overlapping the semiconductor layer 263 with the insulating layer 264 therebetween.

[0251] In addition, both the insulating layer 264 and the conductive layer 265 have a region overlapping the opening 262. In addition, each of the insulating layer 264 and the conductive layer 265 has a region overlapping the inside of the opening 262. Inside the opening 262, the semiconductor layer 263 has a region overlapping the conductive layer 265 with the insulating layer 264 therebetween and a region overlapping the side surface of the opening 262 (the side surface of the insulating layer 256).

[0252] In addition, an insulating layer 266 is included on the insulating layer 264. The top surface of the insulating layer 266 is preferably flat. Alternatively, the top surface height (the position in the Z direction (the direction perpendicular to the substrate surface)) of the insulating layer 266 and the conductive layer 265 is preferably the same or substantially the same. For example, by performing a chemical mechanical polishing (CMP: Chemical Mechanical Polishing) process or the like, the flatness of the top surface of the insulating layer 266 can be improved. In addition, by performing the CMP process, the top surface positions of the insulating layer 266 and the conductive layer 265 can be made the same or substantially the same. By performing the CMP process, the unevenness on the surface can be reduced, and thus the coverage of the insulating layer and the conductive layer formed later can be improved.

[0253] In addition, when an oxide semiconductor is used for the semiconductor layer 263, the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 preferably use a conductive material that n-type dopes the oxide semiconductor. For example, a conductive material containing nitrogen can be used. For example, a conductive material containing titanium or tantalum and nitrogen can be used. In addition, other conductive materials can be provided so as to overlap with the nitrogen-containing conductive material.

[0254] When an oxide semiconductor is used for the semiconductor layer 263, an insulating material with reduced hydrogen content and containing oxygen is preferably used for the insulating layer 258. For example, a material containing silicon and oxygen can be used. Specifically, silicon oxide, silicon oxynitride, etc. can be used. In an oxide semiconductor, hydrogen is an impurity element. Therefore, when the semiconductor layer 263 of the oxide semiconductor is in contact with the insulating layer 258 with reduced hydrogen, the semiconductor layer 263 is not easily n-type doped. In addition, when the semiconductor layer 263 of the oxide semiconductor is in contact with the insulating layer 258 containing oxygen, the oxygen vacancies in the semiconductor layer 263 are reduced, the characteristics of the transistor become stable, and the reliability is improved.

[0255] In addition, when an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 preferably contains excess oxygen. In this specification, excess oxygen refers to oxygen that is desorbed by heating. A material from which oxygen is desorbed by heating means that the desorption amount of oxygen converted to oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or a material of 3.0×10 20 atoms / cm 3 or more. In addition, when performing the above TDS analysis, the surface temperature of the film is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0256] In addition, when a material containing excess oxygen is used for the insulating layer 258, the insulating layers 257 and 259 are preferably made of materials that do not easily allow oxygen to permeate. As materials that do not easily allow oxygen to permeate, for example, oxides containing one or both of aluminum and hafnium, nitrides of silicon, etc. can be used. By using materials that do not easily allow oxygen to permeate for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is not easily desorbed to the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, an insulating layer containing silicon and oxygen (insulating layer 258) can be included between two insulating layers containing silicon and nitrogen (insulating layers 257 and 259). As the insulating layer containing silicon and nitrogen, silicon nitride, silicon oxynitride, etc. can be used. In addition, as the insulating layer containing silicon and oxygen, silicon oxide, silicon oxynitride, etc. can be used.

[0257] In addition, in the case where an oxide semiconductor is used as the semiconductor layer 263, by using a hydrogen-containing material as the insulating layer 257 and the insulating layer 259, the regions of the semiconductor layer 263 in contact with the insulating layer 257 and the regions of the semiconductor layer 263 in contact with the insulating layer 259 are supplied with hydrogen and each region in the semiconductor layer 263 is n-type doped. Therefore, the regions of the semiconductor layer 263 in contact with the conductive layer 261 and the regions of the semiconductor layer 263 in contact with the insulating layer 259 are used as one of the source region and the drain region. In addition, the regions of the semiconductor layer 263 in contact with the conductive layer 255 and the regions of the semiconductor layer 263 in contact with the insulating layer 257 are used as the other of the source region and the drain region.

[0258] The conductive layer 261 is used as one of the source electrode and the drain electrode of the transistor 200C. The conductive layer 255 is used as the other of the source electrode and the drain electrode of the transistor 200C. That is to say, the transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is to say, the source and the drain of the transistor 200C are respectively arranged at different heights. In other words, the source and the drain of the transistor 200C are respectively arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor", a "vertical type channel transistor", a "vertical transistor", or a "VFET (Vertical Field Effect Transistor)".

[0259] In the above structure, in the transistor 200C of the VFET, when viewed from the X direction or the Y direction, the length of the side surface of the insulating layer 158 is the channel length L (channel length L1) (refer to Figure 31B ). Therefore, the channel length L of the transistor 200C is determined according to the thickness t1 of the insulating layer 258.

[0260] In addition, it is preferable to use a material that does not contain hydrogen or contains extremely little hydrogen for the insulating layer 257 and the insulating layer 259. For example, it is preferable to use silicon nitride with extremely little hydrogen or silicon oxynitride with extremely little hydrogen, etc. At this time, the regions of the semiconductor layer 263 in contact with the insulating layer 257 and the regions of the semiconductor layer 263 in contact with the insulating layer 259 are not n-type doped. Therefore, the regions of the semiconductor layer 263 in contact with the conductive layer 261 are used as one of the source region and the drain region. In addition, the regions of the semiconductor layer 263 in contact with the conductive layer 255 are used as the other of the source region and the drain region. In addition, the regions of the semiconductor layer 263 in contact with the insulating layer 258 are used as the channel formation region.

[0261] In this case, the total length of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259 when viewed from the X direction or the Y direction is the channel length L (channel length L2). Therefore, the channel length L of the transistor 200C is determined according to the total thickness t2 of the insulating layer 257, the insulating layer 258, and the insulating layer 259. Thus, the transistor 200C has a region where the channel formation region is along the side surface of the insulating layer 256.

[0262] Since the semiconductor layer 263 is disposed in the opening 262, the perimeter of the opening 262 when viewed from the Z direction is the channel width W of the transistor 200C (see Figure 31A ). As the perimeter, for example, the perimeter at the position of half of the thickness t1 of the insulating layer 258 or the position of half of the thickness t2 can be obtained. Note that, as needed, the perimeter at any position of the opening 262 can be set as the channel width W. For example, the perimeter at the lowermost part of the opening 262 can be set as the channel width W or the perimeter at the uppermost part of the opening 262 can be set as the channel width W. In addition, in Figure 31A , the outline (planar shape) of the opening 262 when viewed from the Z direction is shown as a circle, but it is not limited thereto. For example, the outline of the opening 262 when viewed from the Z direction can be an ellipse, a rectangle, etc.

[0263] In addition, in the semiconductor device according to one embodiment of the present invention, the channel length L is preferably at least less than the channel width W. The channel length L in one embodiment of the present invention is preferably 0.1 times or more and 0.99 times or less of the channel width W, and more preferably 0.5 times or more and 0.8 times or less.

[0264] In addition, in order to improve the coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed inside the opening 262, it is preferable to set the taper angle θ of the side surface of the opening 262, that is, the taper angle θ of each of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, to 45 degrees or more and less than 90 degrees, and more preferably 50 degrees or more and 75 degrees or less. The taper angle θ of each side surface of the insulating layer 257, the insulating layer 258, and the insulating layer 259 can be the same angle or different angles. The taper angle θ of the side surface of the layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed by the bottom surface and the side surface of the layer (see Figure 31B ).

[0265] Compared with a transistor (also called a planar transistor) in which a channel formation region, a source region, and a drain region are respectively provided on the XY plane, the vertical transistor can reduce the occupied area. In addition, by using the vertical channel type transistor for the semiconductor device, the occupied area of the semiconductor device can be reduced. By using the vertical channel type transistor for the semiconductor device, high integration of the semiconductor device can be achieved.

[0266] In addition, the channel length of a planar transistor is limited by the exposure limit of photolithography. The vertical-channel transistor according to one aspect of the present invention can set the channel length according to the thickness of the insulating layer 256 or the insulating layer 258. Therefore, the channel length of the transistor can be set to be very fine, that is, below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). Thereby, the on-state current of the transistor 200C increases, and thus the frequency characteristics can be improved. By adopting the vertical-channel transistor, a semiconductor device with a high operating speed can be provided.

[0267] <Example structure 4 of the transistor>

[0268] Figure 32A is a plan view of the transistor 200D that can be used in the semiconductor device according to one aspect of the present invention. Figure 32B is along Figure 32A The cross-sectional view taken along the dash-dotted line A1-A2 in. The transistor 200D is a modified example of the transistor 200C. To avoid redundant description, mainly the differences between the transistor 200D and the transistor 200C will be described.

[0269] The transistor 200D includes an insulating layer 258a and an insulating layer 258b between the insulating layer 257 and the insulating layer 259, and includes a conductive layer 267 between the insulating layer 258a and the insulating layer 258b. The insulating layer 258a and the insulating layer 258b can be formed using the same materials and methods as the insulating layer 258. In addition, the opening 262 of the transistor 200D is provided in a region overlapping a part of the conductive layer 255 so as to pass through the conductive layer 261, the insulating layer 259, the insulating layer 258b, the conductive layer 267, the insulating layer 258a, and the insulating layer 257.

[0270] In addition, in the transistor 200D, an insulating layer 268 is provided along the side surface of the opening 262. Inside the opening 262, the insulating layer 268 has a region overlapping the side surface of the conductive layer 261, a region overlapping the side surface of the insulating layer 259, a region overlapping the side surface of the insulating layer 258b, a region overlapping the side surface of the conductive layer 267, a region overlapping the side surface of the insulating layer 258a, and a region overlapping the side surface of the insulating layer 257.

[0271] In addition, the semiconductor layer 263 in the transistor 200D has regions that overlap the side surfaces of the conductive layer 261, the insulating layer 259, the insulating layer 258b, the conductive layer 267, the insulating layer 258a, and the insulating layer 257 across the insulating layer 268 inside the opening 262.

[0272] When the conductive layer 265 is used as the gate electrode, the conductive layer 267 is used as the back gate electrode. In addition, when the conductive layer 267 is used as the gate electrode, the conductive layer 265 is used as the back gate electrode. One of the insulating layer 264 and the insulating layer 268 is used as the gate insulating layer, and the other of the insulating layer 264 and the insulating layer 268 is used as the back gate insulating layer. The insulating layer 268 can be formed using the same material and method as the insulating layer 264.

[0273] <Example structure 5 of the transistor>

[0274] Figure 33A is a plan view of the transistor 200E of a semiconductor device that can be used according to one aspect of the present invention. Figure 33B is along Figure 33A the cross-sectional view of the dotted line A1 - A2 in.

[0275] Figure 33C is along Figure 33A the cross-sectional view of the dotted line A3 - A4 in. Note that Figure 33A is the cross-sectional view in the channel length direction of the transistor 200E, Figure 33C is the cross-sectional view in the channel width direction of the transistor 200E.

[0276] As Figures 33A to 33C shown, the transistor 200E includes a semiconductor layer 520a disposed on the substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed separately on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b with an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed between the semiconductor layer 520b, the conductive layers 542a and 542b, the insulating layer 580 and the conductive layer 560, and a semiconductor layer 520c disposed between the semiconductor layer 520b, the conductive layers 542a and 542b, the insulating layer 580 and the insulating layer 550. Here, as Figure 33B and Figure 33CAs shown, the top surface of the conductive layer 560 is substantially aligned with the top surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. In addition, the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c are sometimes collectively referred to as the semiconductor layer 520. In addition, the conductive layer 542a and the conductive layer 542b are sometimes collectively referred to as the conductive layer 542.

[0277] As Figures 33A to 33C As shown, the insulating layer 524 is disposed between the insulating layer 554, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580. The insulating layer 524 is in contact with the side surface of the semiconductor layer 520c, the top surface and the side surface of the conductive layer 542a, the top surface and the side surface of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 554.

[0278] Note that in the transistor 200E, three layers of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c are stacked in the channel formation region and its vicinity, but the present invention is not limited thereto. For example, a two-layer structure of the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers can be employed. In addition, the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may each have a stacked structure of two or more layers.

[0279] For example, in the case where an oxide semiconductor, which is one of metal oxides, is used as the semiconductor layer 520 and the semiconductor layer 520c has a stacked structure composed of a first metal oxide and a second metal oxide on the first metal oxide, preferably, the first metal oxide has the same composition as the semiconductor layer 520b, and the second metal oxide has the same composition as the semiconductor layer 520a.

[0280] Here, the conductive layer 560 is used as the gate electrode of the transistor, and the conductive layer 542a and the conductive layer 542b are each used as the source electrode or the drain electrode of the transistor. As described above, the conductive layer 560 is formed in such a manner as to be embedded in the opening of the insulating layer 580 and the region sandwiched between the conductive layer 542a and the conductive layer 542b. Here, the conductive layer 560, the conductive layer 542a, and the conductive layer 542b are disposed self-aligned with respect to the opening of the insulating layer 580. That is, in the transistor 200E, the gate electrode can be disposed self-aligned between the source electrode and the drain electrode. Thus, the conductive layer 560 can be formed without providing a margin for position alignment, so that the occupied area of the transistor 200E can be reduced. Thereby, the occupied area of the semiconductor device can be reduced. In addition, the integration degree of the semiconductor device can be improved.

[0281] As Figures 33A to 33CAs shown, the conductive layer 560 preferably includes a conductive layer 560a disposed inside the insulating layer 550 and a conductive layer 560b disposed in such a manner as to be embedded inside the conductive layer 560a. Further, in the transistor 200E, the conductive layer 560 has a stacked structure of two layers, but the present invention is not limited thereto. For example, the conductive layer 560 may also have a single-layer structure or a stacked structure of three or more layers.

[0282] The transistor 200E includes an insulating layer 202 disposed on a substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed in such a manner as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. Further, a semiconductor layer 520a is disposed on the insulating layer 524.

[0283] Further, an insulating layer 574 and an insulating layer 581 serving as an interlayer film are disposed on the transistor 200E. The insulating layer 574 is disposed in such a manner as to be in contact with the top surfaces of the conductive layer 560, the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580.

[0284] In the case where an oxide semiconductor is used as the semiconductor layer 520, as the insulating layers 522, 554, and 574, an insulating layer having a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.) is preferably used. For example, as the insulating layers 522, 554, and 574, an insulating layer having a lower hydrogen permeability than the insulating layers 524, 550, and 580 is preferably used. For example, silicon nitride, silicon oxynitride, etc. can be used.

[0285] Further, as the insulating layers 522 and 554, an insulating layer having a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule, etc.) is preferably used. For example, as the insulating layers 522 and 554, an insulating layer having a lower oxygen permeability than the insulating layers 524, 550, and 580 is preferably used. For example, silicon nitride, silicon oxynitride, etc. can be used.

[0286] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated by the insulating layers 522 and 574. Thereby, it is possible to suppress impurities such as hydrogen and excess oxygen contained in the upper layer of the insulating layer 574 and the lower layer of the insulating layer 522 from mixing into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0287] Figure 33BAn example of a conductive layer 545 (conductive layer 545a and conductive layer 545b) that is connected to the transistor 200E and serves as a plug is shown. In addition, an insulating layer 541 (insulating layer 541a and insulating layer 541b) that contacts the side surface of the conductive layer 545 serving as a plug is also provided. That is, the insulating layer 541 is provided so as to contact the inner wall of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in Figure 33B a first conductive layer of the conductive layer 545 is provided so as to contact the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided inside the first conductive layer of the conductive layer 545.

[0288] Here, the height of the top surface of the conductive layer 545 and the height of the top surface of the insulating layer 581 may be substantially the same. In addition, the transistor 200E shows a structure in which a first conductive layer and a second conductive layer of the conductive layer 545 are stacked, but the present invention is not limited thereto. For example, the conductive layer 545 may also have a single-layer structure or a stacked structure of three or more layers. In the case where the structure has a stacked structure, sometimes numbers are assigned in the formation order for distinction.

[0289] In addition, the thickness of the region in the semiconductor layer 520b that does not overlap with the conductive layer 542 is sometimes thinner than the thickness of the region that overlaps with the conductive layer 542. This thinner region is formed by removing a part of the top surface of the semiconductor layer 520b when forming the conductive layer 542a and the conductive layer 542b. When a conductive film that becomes the conductive layer 542 is deposited on the top surface of the semiconductor layer 520b, a low-resistance region is sometimes formed near the interface with the conductive film. In this way, by removing the low-resistance region of the semiconductor layer 520b located between the conductive layer 542a and the conductive layer 542b in a plan view, channel formation in this region can be suppressed.

[0290] Next, the detailed structure of the transistor 200E of the semiconductor device that can be used in one embodiment of the present invention will be described.

[0291] The conductive layer 505 is arranged so as to have a region that overlaps with the conductive layer 560 with the semiconductor layer 520 therebetween. In addition, by providing the conductive layer 505 in a manner embedded in the insulating layer 516, the unevenness of the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and thus the coverage of the layer formed in the subsequent process can be improved.

[0292] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in a manner in contact with the bottom surface and side walls of the opening provided in the insulating layer 516. The conductive layer 505b is provided in a manner embedded in a recess formed in the conductive layer 505a. Here, the top surface of the conductive layer 505b is lower than the top surface of the conductive layer 505a and the top surface of the insulating layer 516. The conductive layer 505c is provided in a manner in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. Here, the height of the top surface of the conductive layer 505c is consistent or substantially consistent with the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layer 505a and the conductive layer 505c.

[0293] When an oxide semiconductor is used as the semiconductor layer 520, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, or NO2), or copper atoms is preferably used as the conductive layer 505a and the conductive layer 505c. Alternatively, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0294] By using a conductive material having a function of suppressing the diffusion of hydrogen as the conductive layer 505a and the conductive layer 505c, it is possible to suppress the diffusion of impurities such as hydrogen contained in the conductive layer 505b to the semiconductor layer 520 through the insulating layer 524 and the like. In addition, by using a conductive material having a function of suppressing the diffusion of oxygen as the conductive layer 505a and the conductive layer 505c, it is possible to suppress the conductive layer 505b from being oxidized and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. can be used. Thus, the conductive layer 505a can be a single layer or a stack of the above conductive materials. For example, titanium nitride can be used as the conductive layer 505a.

[0295] The conductive layer 505 b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten is preferably used for the conductive layer 505 b. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 is used as a back gate electrode.

[0296] The conductive layer 505 is preferably larger than the channel formation region in the semiconductor layer 520. In particular, Figure 33C As shown, the conductive layer 505 preferably extends to the region outside the end intersecting the channel width direction of the semiconductor layer 520. That is, the conductive layer 505 and the conductive layer 560 preferably overlap with each other via the insulating layer outside the side surface of the semiconductor layer 520 in the channel width direction.

[0297] With the above structure, the channel formation region of the semiconductor layer 520 can be electrically surrounded by the electric fields of the conductive layer 560 serving as the gate electrode and the conductive layer 505 serving as the back gate electrode.

[0298] The conductive layer 505 can extend beyond the end of the semiconductor layer 520 and be used as a wiring. However, it is not limited thereto, and a conductive layer used as a wiring can be provided under the conductive layer 505.

[0299] As the insulating layer 514, it is preferable to use an insulating material that serves as a barrier insulating film for suppressing impurities such as water or hydrogen from entering the transistor 200E from the substrate side. Therefore, as the insulating layer 514, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (not easily allowing the above impurities to pass through). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.) (not easily allowing the above oxygen to pass through).

[0300] For example, preferably, alumina or silicon nitride is used as the insulating layer 514. Thereby, the diffusion of impurities such as water or hydrogen from the side closer to the substrate than the insulating layer 514 to the transistor 200E side can be suppressed. Alternatively, the diffusion of oxygen contained in the insulating layer 524 or the like to the side closer to the substrate than the insulating layer 514 can be suppressed.

[0301] As the insulating layers 516, 580, and 581 serving as interlayer films, it is preferable to use an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulating layers 516, 580, and 581, it is sufficient to appropriately use silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon- and nitrogen-added silicon oxide, or porous silicon oxide, etc.

[0302] When the conductive layer 560 is used as the gate electrode, the insulating layers 522 and 524 are used as the gate insulating layers.

[0303] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, it is sufficient to appropriately use silicon oxide or silicon oxynitride as the insulating layer 524. By providing an oxygen-containing insulating layer in contact with the semiconductor layer 520, the oxygen vacancies in the semiconductor layer 520 can be reduced, thereby improving the reliability of the transistor 200E.

[0304] As Figure 33CAs shown, sometimes the thickness of the region in the insulating layer 524 that does not overlap with the insulating layer 554 and does not overlap with the semiconductor layer 520b is thinner than that of other regions. In the insulating layer 524, the thickness of the region that does not overlap with the insulating layer 554 and does not overlap with the semiconductor layer 520b is preferably thick enough to diffuse the above-mentioned oxygen.

[0305] Similar to the insulating layer 514 and the like, as the insulating layer 522, it is preferable to use an insulating material that serves as a barrier insulating film for suppressing the mixing of impurities such as water or hydrogen from the substrate side into the transistor 200E. For example, a material with a lower hydrogen permeability than the insulating layer 524 is used as the insulating layer 522. By surrounding the insulating layer 524, the semiconductor layer 520, and the insulating layer 550, etc. with the insulating layer 522, the insulating layer 554, and the insulating layer 574, the entry of impurities such as water or hydrogen from the outside into the transistor 200E can be suppressed.

[0306] Furthermore, as the insulating layer 522, it is preferable to use a material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.) (not easily allowing the above-mentioned oxygen to pass through). For example, a material with a lower oxygen permeability than the insulating layer 524 is used as the insulating layer 522. By making the insulating layer 522 have the function of suppressing the diffusion of oxygen and impurities, the oxygen diffusing from the semiconductor layer 520 to the substrate side can be reduced. In addition, the reaction between the conductive layer 505 and the oxygen contained in the insulating layer 524 and the semiconductor layer 520 can be suppressed.

[0307] As the insulating layer 522, it is preferable to use an insulating layer containing one or both of oxides of aluminum and hafnium as the insulating material. As the insulating layer containing one or both of oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When using such a material to form the insulating layer 522, the insulating layer 522 is used as a layer for suppressing the release of oxygen from the semiconductor layer 520 and the entry of impurities such as hydrogen from the peripheral part of the transistor 200E into the semiconductor layer 520.

[0308] Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the insulating layer 522. Alternatively, the insulating layer 522 can be nitrided. Alternatively, a silicon oxide, silicon oxynitride, or silicon nitride layer can be laminated on the insulating layer 522 for use. For example, as the insulating layer 522, a structure in which a silicon nitride layer, a silicon oxide layer, and an aluminum oxide layer are laminated in sequence can be adopted.

[0309] As the insulating layer 522, for example, an insulating layer containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) can be used in a single layer or a stacked layer. With the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material as the insulating layer used as the gate insulating layer, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0310] In addition, both the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. At this time, it is not limited to a stacked structure composed of the same material, and thus a stacked structure composed of different materials can be adopted.

[0311] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. When the semiconductor layer 520a is provided under the semiconductor layer 520b, diffusion of impurities from a structure formed below the semiconductor layer 520a into the semiconductor layer 520b can be suppressed. When the semiconductor layer 520c is provided on the semiconductor layer 520b, diffusion of impurities from a structure formed above the semiconductor layer 520c into the semiconductor layer 520b can be suppressed.

[0312] In addition, when an oxide semiconductor is used as the semiconductor layer 520, a stacked structure of multiple oxide layers with different atomic ratios of each metal atom is preferably adopted. For example, when the semiconductor layer 520 contains at least indium (In) and element M, the atomic ratio of element M to all elements constituting the semiconductor layer 520a is higher than the atomic ratio of element M to all elements constituting the semiconductor layer 520b. In addition, the atomic ratio of element M to In in the semiconductor layer 520a is greater than the atomic ratio of element M to In in the semiconductor layer 520b. Here, the semiconductor layer 520c can use a metal oxide that can be used for the semiconductor layer 520a or the semiconductor layer 520b.

[0313] The energy of the bottom of the conduction band of the semiconductor layer 520a and the semiconductor layer 520c is preferably higher than the energy of the bottom of the conduction band of the semiconductor layer 520b. In addition, in other words, the electron affinity of the semiconductor layer 520a and the semiconductor layer 520c is preferably smaller than the electron affinity of the semiconductor layer 520b. In this case, a metal oxide that can be used for the semiconductor layer 520a can be used as the semiconductor layer 520c. Specifically, it is preferable that the atomic number ratio of the element M in the semiconductor layer 520c to all the elements constituting the semiconductor layer 520c is higher than the atomic number ratio of the element M in the semiconductor layer 520b to all the elements constituting the semiconductor layer 520b. In addition, it is preferable that the atomic number ratio of the element M to In in the semiconductor layer 520c is larger than the atomic number ratio of the element M to In in the semiconductor layer 520b.

[0314] Here, the energy level of the bottom of the conduction band changes smoothly at the junction of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the above situation can also be expressed as the energy level of the bottom of the conduction band at the junction of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changing continuously or being continuously joined. For this purpose, it is preferable to reduce the density of defect states in the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and at the interface between the semiconductor layer 520b and the semiconductor layer 520c.

[0315] Specifically, when the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c have a common element other than oxygen (with the common element other than oxygen as the main component), a mixed layer with a low density of defect states can be formed. For example, when the semiconductor layer 520b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. can be used as the semiconductor layer 520a and the semiconductor layer 520c. In addition, the semiconductor layer 520c can have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide can be used, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, as the semiconductor layer 520c, a stacked structure of In-Ga-Zn oxide and an oxide not containing In can be used.

[0316] Specifically, it is sufficient to use a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof or 1:1:0.5 [atomic ratio] or in the vicinity thereof as the semiconductor layer 520a. In addition, it is sufficient to use a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, 3:1:2 [atomic ratio] or in the vicinity thereof, 1:1:1 [atomic ratio] or in the vicinity thereof as the semiconductor layer 520b. In addition, it is sufficient to use a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, Ga:Zn = 2:1 [atomic ratio] or in the vicinity thereof, or Ga:Zn = 2:5 [atomic ratio] or in the vicinity thereof as the semiconductor layer 520c. In addition, as a specific example in the case where the semiconductor layer 520c has a stacked structure, a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof and Ga:Zn = 2:1 [atomic ratio] or in the vicinity thereof, a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof and Ga:Zn = 2:5 [atomic ratio] or in the vicinity thereof, a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof and gallium oxide, etc. can be cited.

[0317] At this time, the main path of carriers is the semiconductor layer 520b. By making the semiconductor layer 520a and the semiconductor layer 520c have the above structures, the density of defect states at the interface between the semiconductor layer 520a and the semiconductor layer 520b and at the interface between the semiconductor layer 520b and the semiconductor layer 520c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and thus the transistor 200E can obtain a large on-state current and high-frequency characteristics. In addition, when the semiconductor layer 520c adopts a stacked structure, the following two effects can be expected: the effect of reducing the density of defect states at the interface between the semiconductor layer 520b and the semiconductor layer 520c and the effect of suppressing the diffusion of the constituent elements of the semiconductor layer 520c to the insulating layer 550 side. More specifically, when the semiconductor layer 520c has a stacked structure, since the oxide not containing In is located above the stacked structure, In that would diffuse to the insulating layer 550 side can be suppressed. The insulating layer 550 is used as a gate insulating layer, and thus in the case of In diffusion, the characteristics of the transistor deteriorate. Therefore, by making the semiconductor layer 520c have a stacked structure, a semiconductor device with high reliability can be provided.

[0318] A conductive layer 542 (conductive layer 542a and conductive layer 542b) serving as a source electrode and a drain electrode is provided on the semiconductor layer 520b. When an oxide semiconductor is used as the semiconductor layer 520b, it is preferable to use a conductive material that is not easily oxidized or a conductive material that maintains conductivity even when absorbing oxygen as the conductive layer 542.

[0319] The region of the semiconductor layer 520 that contacts the conductive layer 542 is used as the source region or the drain region of the transistor 200E. Here, the region between the conductive layer 542a and the conductive layer 542b is formed so as to overlap with the opening of the insulating layer 580. Therefore, the conductive layer 560 can be disposed self-alignedly between the conductive layer 542a and the conductive layer 542b.

[0320] The insulating layer 550 is used as a gate insulating layer. The insulating layer 550 is disposed so as to contact the top surface of the semiconductor layer 520c. The insulating layer 550 can use silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having voids. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 550.

[0321] Similar to the insulating layer 524, as the insulating layer 550, an insulating material with a reduced concentration of impurities such as water or hydrogen in the insulating layer 550 is used. The thickness of the insulating layer 550 is preferably 1 nm or more and 20 nm or less.

[0322] In addition, it is preferable to provide a metal oxide between the insulating layer 550 and the conductive layer 560. By means of this metal oxide, the diffusion of oxygen from the insulating layer 550 to the conductive layer 560 is suppressed. Thereby, the oxidation of the conductive layer 560 caused by oxygen in the insulating layer 550 can be suppressed.

[0323] Although the conductive layer 560 has a two-layer structure in Figures 33A to 33C , it may also have a single-layer structure or a stacked structure of three or more layers.

[0324] As the conductive layer 560a, it is preferable to use the above-mentioned conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, or NO2, etc.) or copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0325] By making the conductive layer 560a have a function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity due to the oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide can be used.

[0326] For example, the conductive layer 560b can use a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductive layer 560 is also used as a wiring, it is preferable to use a conductive layer with high conductivity. In addition, the conductive layer 560b can have a stacked structure, for example, it can have a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0327] AsFigure 33B and Figure 33C As shown in Figure 33B and Figure 33C , in the region of the semiconductor layer 520b that does not overlap with the conductive layer 542 when viewed from the Z direction, that is, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is covered by the conductive layer 560. Thus, the electric field of the conductive layer 560, which can be easily used as the gate electrode of the transistor 200E, can affect the side surface of the semiconductor layer 520. Thus, the on-state current and frequency characteristics of the transistor 200E can be improved.

[0328] Similar to the insulating layer 514 and the like, the insulating layer 554 is an insulating material that suppresses impurities such as water or hydrogen from mixing into the transistor 200E from the side of the insulating layer 580. For example, an insulating material with a lower hydrogen permeability than the insulating layer 524 is used as the insulating layer 554. Furthermore, as Figure 33B and Figure 33C shown in Figure 33B and Figure 33C , the insulating layer 554 is provided in contact with the side surface of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. By adopting this structure, it is possible to suppress hydrogen contained in the insulating layer 580 from entering the semiconductor layer 520 from the top or side surfaces of the conductive layer 542a, the conductive layer 542b, the semiconductor layer 520a, the semiconductor layer 520b, and the insulating layer 524.

[0329] Furthermore, as the insulating layer 554, an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.) (not easily allowing the above-mentioned oxygen to permeate) is used. For example, an insulating material with a lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used as the insulating layer 554.

[0330] When an oxide semiconductor is used as the semiconductor layer 520, the insulating layer 554 can be deposited by a sputtering method. By depositing the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulating layer 524 that contacts the insulating layer 554. Thus, oxygen can be supplied from this region to the semiconductor layer 520 through the insulating layer 524. Here, by making the insulating layer 554 have a function of suppressing the diffusion of oxygen upward, it is possible to prevent oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. In addition, by making the insulating layer 522 have a function of suppressing the diffusion of oxygen downward, it is possible to prevent oxygen from diffusing from the semiconductor layer 520 to the substrate side. In this way, oxygen is supplied to the channel formation region in the semiconductor layer 520. Thus, the oxygen vacancies in the semiconductor layer 520 can be reduced and the constant-on state of the transistor can be suppressed.

[0331] As the insulating layer 554, an insulating layer containing an oxide of one or both of aluminum and hafnium can be deposited, for example. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, alumina, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) can be used, etc.

[0332] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, as the insulating layer 580, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores is used, etc. In particular, silicon oxide and silicon oxynitride have thermal stability, and thus are preferable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores easily form a region containing oxygen that is removed by heating, and thus are preferable.

[0333] Similar to the insulating layer 514 and the like, as the insulating layer 574, an insulating material is used as a barrier insulating film that suppresses impurities such as water or hydrogen from mixing in from above into the insulating layer 580. As the insulating layer 574, for example, an insulating material that can be used for the insulating layer 514 or the insulating layer 554 and the like is used.

[0334] Figures 33A to 33C An example in which an insulating layer 581 serving as an interlayer film is provided over the insulating layer 574 is shown. Similar to the insulating layer 524 and the like, as the insulating layer 581, an insulating material with a reduced concentration of impurities such as water or hydrogen in the film is used.

[0335] The conductive layer 545a and the conductive layer 545b are disposed in the openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layer 545a and the conductive layer 545b are disposed such that the conductive layer 560 is interposed therebetween in a plan view. In addition, the top surfaces of the conductive layer 545a and the conductive layer 545b are preferably located in the same plane as the top surface of the insulating layer 581.

[0336] In addition, an insulating layer 541a is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. The conductive layer 542a is located at at least a part of the bottom of the opening and is in contact with the conductive layer 545a. Similarly, an insulating layer 541b is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. The conductive layer 542b is located at at least a part of the bottom of the opening and is in contact with the conductive layer 545b.

[0337] The conductive layer 545a and the conductive layer 545b preferably use a conductive material mainly composed of tungsten, copper, or aluminum. In addition, both the conductive layer 545a and the conductive layer 545b may have a laminated structure of two or more layers.

[0338] When the conductive layer 545 adopts a laminated structure, as the conductive layer in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581, it is preferable to use the above-mentioned conductive layer having the function of suppressing the diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are used. By using this conductive material, it is possible to prevent oxygen contained in the insulating layer 580 from being absorbed by the conductive layer 545a and the conductive layer 545b. In addition, it is possible to prevent impurities such as water or hydrogen from entering the semiconductor layer 520 from the upper layer of the insulating layer 581 through the conductive layer 545a and the conductive layer 545b.

[0339] As the insulating layer 541a and the insulating layer 541b, for example, an insulating layer that can be used for the insulating layer 554 or the like can be used. Since the insulating layer 541a and the insulating layer 541b are provided in contact with the insulating layer 554, it is possible to suppress impurities such as water or hydrogen from mixing into the semiconductor layer 520 through the conductive layer 545a and the conductive layer 545b from the insulating layer 580 or the like. In addition, the insulating layer 541a and the insulating layer 541b can suppress the oxygen contained in the insulating layer 580 from being absorbed by the conductive layer 545a and the conductive layer 545b.

[0340] <Example of the structure of the transistor 6>

[0341] Figures 34A to 34C Shows Figures 33A to 33C A modified example of the transistor 200E shown. Figure 34A Is a plan view of the transistor 200F which is a modified example of the transistor 200E.

[0342] Figure 34B Is along Figure 34A The cross-sectional view of the dash-dotted line A1 - A2 in. Figure 34C Is along Figure 34A The cross-sectional view of the dash-dotted line A3 - A4 in. Since the transistor 200F is a modified example of the transistor 200E, the differences between the transistor 200F and the transistor 200E will be mainly described.

[0343] The transistor 200F has a structure in which the semiconductor layer 520c and the conductive layer 505c are removed from the structure of the transistor 200E. By reducing the components of the transistor, the production cost can be reduced. When the components of the transistor are reduced, the manufacturing process is shortened, and thus the manufacturing yield is improved.

[0344] In addition, the transistor 200F has a region where the outer insulating layer 554 of the semiconductor layer 520 contacts the insulating layer 522, and the side surface of the insulating layer 524 is covered by the insulating layer 554. When an oxide semiconductor is used as the semiconductor layer 520, by covering the side surface of the insulating layer 524 with the insulating layer 554, it is possible to not only prevent oxygen from diffusing to the outside through the insulating layer 524, but also prevent an excessive supply of oxygen from the insulating layer 524 side to the semiconductor layer 520.

[0345] In addition, it is preferable to provide an insulating layer between the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b and the insulating layer 550. Alumina, hafnium oxide, etc. are preferably used as this insulating layer. By providing this insulating layer, it is possible to suppress the detachment of oxygen from the semiconductor layer 520 to the insulating layer 550 side, the supply of excessive oxygen from the insulating layer 550 side to the semiconductor layer 520, the oxidation of the conductive layer 542, etc.

[0346] <Example structure of a transistor 7>

[0347] Figure 35A is a plan view of the transistor 200G that can be used in a semiconductor device according to one aspect of the present invention. In addition, Figure 35B is a perspective schematic view of the transistor 200G. In addition, Figures 35C to 35E is a cross-sectional view of the transistor 200G. Here, Figure 35C is a cross-sectional view along the dashed line A1 - A2 in Figure 35A , and is also a cross-sectional view in the channel width direction (Y direction) of the transistor 200G. In addition, Figure 35D is a cross-sectional view along the dashed line A3 - A4 in Figure 35A , and is also a cross-sectional view in the channel width direction of the transistor 200G. Additionally, Figure 35E is a cross-sectional view along the dashed line A5 - A6 in Figure 35A , and is also a cross-sectional view in the channel length direction (X direction) of the transistor 200G. Here, the dashed line A5 - A6 is orthogonal to the dashed lines A1 - A2 and A3 - A4, and the dashed lines A1 - A2 and A3 - A4 are parallel to each other. Note that in the plan view of Figure 35A and the perspective schematic view of Figure 35B , the description of some constituent elements is omitted. In addition, Figure 36A shows an enlarged view of the vicinity of the conductive layer 260 in Figure 35E . Additionally, Figure 36B shows an enlarged view of the vicinity of the semiconductor layer 230 in Figure 35C .

[0348] The transistor 200G according to the present embodiment includes an insulating layer 295 on a substrate (not shown), an insulating layer 296 on the insulating layer 295, an insulating layer 291 on the insulating layer 296, an insulating layer 292 on the insulating layer 291, a semiconductor layer 230 on the insulating layer 292, conductive layers 242a and 242b on the semiconductor layer 230 and on the insulating layer 292, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 (conductive layers 260a and 260b) on the insulating layer 250. Note that in this specification, the conductive layers 242a and 242b are sometimes collectively referred to as the conductive layer 242.

[0349] An insulating layer 235 is provided on the conductive layer 242, and an insulating layer 280 is provided on the insulating layer 235. The insulating layer 250 and the conductive layer 260 are provided inside a first opening that passes through the insulating layer 280 and the insulating layer 235 and reaches the semiconductor layer 230. The first opening includes a region overlapping the semiconductor layer 230 and a region extending along the Y direction beyond the end of the semiconductor layer 230 in a plan view. Therefore, the insulating layer 250 and the conductive layer 260 provided inside the first opening also have a region overlapping the semiconductor layer 230 and a region extending along the Y direction beyond the end of the semiconductor layer 230 in a plan view. The conductive layer 260 is also used as a wiring. The insulating layer 250 has a region in contact with the semiconductor layer 230 in the first opening. In addition, an insulating layer 297 is provided on the insulating layer 280 and the conductive layer 260. In addition, an insulating layer 298 is provided on the insulating layer 297.

[0350] In addition, an insulating layer 241a is provided in contact with the inner wall of a second opening that passes through the insulating layer 298, the insulating layer 297, the insulating layer 280, and the insulating layer 235 and reaches the conductive layer 242a, and a conductive layer 245a is provided in contact with the insulating layer 241a. The conductive layer 245a has a region in contact with the conductive layer 242a at the bottom of the first opening.

[0351] In addition, an insulating layer 241b is provided in contact with the inner wall of a third opening that passes through the insulating layer 298, the insulating layer 297, the insulating layer 280, and the insulating layer 235 and reaches the conductive layer 242b, and a conductive layer 245b is provided in contact with the insulating layer 241b. The conductive layer 245b has a region in contact with the conductive layer 242b at the bottom of the second opening.

[0352] In addition, in this specification, the conductive layers 245a and 245b are sometimes collectively referred to as the conductive layer 245. In addition, the insulating layers 241a and 241b are sometimes collectively referred to as the insulating layer 241.

[0353] The semiconductor layer 230 includes the channel formation region of the transistor 200G. In addition, the conductive layer 260 has a region serving as the gate electrode of the transistor 200G. The insulating layer 250 has a region serving as the gate insulating layer of the transistor 200G. In the transistor 200G, the region of the semiconductor layer 230 overlapping with the conductive layer 260 is used as the channel formation region. In addition, the region of the conductive layer 260 overlapping with the semiconductor layer 230 is used as the gate electrode. In addition, the region where the insulating layer 250 and the semiconductor layer 230 overlap with each other and the insulating layer 250 and the conductive layer 260 overlap with each other in the insulating layer 250 is used as the gate insulating layer.

[0354] The conductive layer 242a has a region serving as one of the source electrode and the drain electrode of the transistor 200G. The conductive layer 245a is used as a plug connected to the conductive layer 242a. The conductive layer 242b has a region serving as the other of the source electrode and the drain electrode of the transistor 200G. The conductive layer 245b is used as a plug connected to the conductive layer 242b.

[0355] The semiconductor layer 230 is formed on the insulating layer 292. As Figure 36B shown, the semiconductor layer 230 has a shape with a high aspect ratio in the cross-section in the channel width direction. Thus, it can also be said that the semiconductor layer 230 has a fin shape. In addition, a transistor with a fin-shaped semiconductor layer is also referred to as a "fin-type transistor", "FinFET", "Fin transistor", etc.

[0356] Specifically, a FinFET refers to a transistor in which the channel formation region of the semiconductor layer has two regions (two surfaces) extending in the Z direction in the cross-section in the channel width direction (Y direction), and has a shape in which a length H described later is greater than a length Lx described later. In the cross-section in the channel width direction, when the length H is greater than the length Lx, the channel width per unit area can be increased, so it is preferable.

[0357] In this specification, the maximum value of the length in the Y direction of the semiconductor layer 230 in the channel formation region is defined as the length Lx, and the maximum value of the length in the direction perpendicular to the formation surface (e.g., the top surface of the insulating layer 292) of the semiconductor layer 230 in the channel formation region is defined as the length H.

[0358] Note that the length Lx can also be said to be the maximum width of the semiconductor layer 230 in the channel formation region. Therefore, the "length Lx" can be referred to as the "width Lx". In addition, the length H can also be said to be the maximum height of the semiconductor layer 230 in the channel formation region. Therefore, the "length H" can be referred to as the "height H".

[0359] The ratio of the length H to the length Lx is referred to as the aspect ratio of the semiconductor layer 230. Preferably, the aspect ratio of the semiconductor layer 230 is as large as possible within the range where the semiconductor layer 230 does not fall down during the manufacturing process of the transistor 200G. The aspect ratio of the semiconductor layer 230 is preferably greater than 1 and 400 or less, more preferably 2 or more and 100 or less, still more preferably 5 or more and 40 or less, and even more preferably 10 or more and 20 or less. That is to say, in the channel formation region of the semiconductor layer 230, the height H of the semiconductor layer 230 is preferably at least longer than the length Lx of the semiconductor layer 230. The height H of the semiconductor layer 230 is preferably greater than 1 times and 400 times or less the length Lx of the semiconductor layer 230, more preferably 2 times or more and 100 times or less, still more preferably 5 times or more and 40 times or less, and even more preferably 10 times or more and 20 times or less. In addition, for example, the height H is preferably 2 times or more and 10 times or less the length Lx. For example, the length Lx is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 50 nm or less, still more preferably 10 nm or more and 30 nm or less. Additionally, for example, the height H is preferably 50 nm or more and 2000 nm or less, more preferably 100 nm or more and 1000 nm or less. Additionally, for example, the height H can be 50 nm or more and 100 nm or less.

[0360] As Figure 36B shown, in the cross-section in the channel width direction, the angle θ formed by the formation surface of the semiconductor layer 230 on the insulating layer 292 and the side surface of the semiconductor layer 230 is preferably perpendicular or substantially perpendicular. For example, the angle θ is 80° or more and 100° or less, preferably 85° or more and 95° or less.

[0361] The insulating layer 250, the conductive layer 260, and the conductive layer 242 are provided so as to cover the semiconductor layer 230 having the above aspect ratio. In the transistor 200G, as Figure 36B shown, a part of the insulating layer 250 and the conductive layer 260 is provided in a folded state with the semiconductor layer 230 sandwiched therebetween. Thus, in the cross-section in the channel width direction, the semiconductor layer 230 and the conductive layer 260 are provided opposite to each other with the insulating layer 250 sandwiched between them on each of the upper part of the semiconductor layer 230, the side surface on the A1 side, and the side surface on the A2 side. That is to say, the upper part of the semiconductor layer 230, the side surface on the A1 side, and the side surface on the A2 side are all used as the channel formation region. Therefore, compared with the case where the semiconductor layer 230 is formed in a planar shape, the channel width of the transistor 200G increases by an amount corresponding to the side surfaces on the A1 side and the A2 side of the semiconductor layer 230.

[0362] As described above, by increasing the channel width, the on-state current, transconductance, frequency characteristics, etc. of the transistor 200G can be improved. Thereby, a semiconductor device with a high operating speed can be provided. Further, in the above structure, by providing the semiconductor layer 230, the channel width can be increased without increasing the occupied area of the transistor 200G. Thereby, miniaturization or high integration of the semiconductor device can be achieved.

[0363] Further, as Figure 36B shown, etc., the upper part of the semiconductor layer 230 preferably has a curved shape. By having such a curved shape, formation of defects such as voids in the insulating layer 250 and the conductive layer 242 near the upper part of the semiconductor layer 230 can be prevented. Note that, in Figure 36B etc., a symmetric structure in which both the A1 side (A3 side) and the A2 side (A4 side) of the upper part of the semiconductor layer 230 have a curved shape is adopted, but the present invention is not limited thereto. For example, an asymmetric structure in which one of the A1 side (A3 side) and the A2 side (A4 side) of the upper part of the semiconductor layer 230 has a curved shape may be adopted.

[0364] In addition, when an oxide semiconductor is used as the semiconductor layer 230, as Figure 36A and Figure 36B shown, a structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c disclosed in Embodiment 4 can be adopted.

[0365] In addition, when an oxide semiconductor is used as the semiconductor layer 230, as Figure 36A and Figure 36B shown, the insulating layer 250 preferably has a stacked structure of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250c on the insulating layer 250b, and an insulating layer 250d on the insulating layer 250c. At this time, the insulating layer 250a and the insulating layer 250c preferably have a function of capturing or fixing hydrogen.

[0366] As the insulating layer having a function of capturing or fixing hydrogen, a metal oxide having an amorphous structure can be cited. As the insulating layer 250a and the insulating layer 250c, for example, metal oxides such as oxides containing one or both of aluminum and hafnium, and magnesium oxide are preferably used. The above metal oxide having an amorphous structure sometimes has the following property: oxygen atoms have dangling bonds and capture or fix hydrogen by these dangling bonds. That is to say, the ability of the metal oxide having an amorphous structure to capture or fix hydrogen is high.

[0367] The insulating layer 250a and the insulating layer 250c are preferably made of a high dielectric constant (high-k) material. As an example of the high-k material, there is an oxide containing one or both of aluminum and hafnium. When the high-k material is used for the insulating layer 250a and the insulating layer 250c, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. In addition, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating layer can be reduced.

[0368] As the insulating layer 250a and the insulating layer 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and more preferably to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0369] In this embodiment, alumina is used as the insulating layer 250a. In addition, this alumina preferably has an amorphous structure. Here, by disposing the insulating layer 250a in contact with the semiconductor layer 230, the insulating layer 250a can more effectively capture and fix hydrogen contained in the semiconductor layer 230 or the like.

[0370] In this embodiment, hafnium oxide is used as the insulating layer 250c. Here, by disposing the insulating layer 250c between the insulating layer 250b and the insulating layer 250d, hydrogen contained in the insulating layer 250b or the like can be more effectively captured and fixed.

[0371] Next, as the insulating layer 250b, it is preferable to use a thermally stable insulating layer such as silicon oxide or silicon oxynitride. The silicon oxide film used as the insulating layer 250b is preferably formed by plasma ALD (PEALD: Plasma Enhanced ALD) method.

[0372] In order to suppress the oxidation of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260, it is preferable to provide an oxygen barrier insulator near each of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260. In the semiconductor device described in this embodiment, this insulator is, for example, the insulating layer 250a, the insulating layer 250d, the insulating layer 250c, and the insulating layer 235.

[0373] In this specification and the like, the barrier insulating layer refers to an insulating layer having a barrier property. In this specification and the like, having a barrier property means having the property of hindering the permeation of the corresponding substance (also referred to as low permeability). For example, an insulating layer having a barrier property has the property that the corresponding substance does not easily diffuse into the interior of the insulating layer. For example, an insulating layer having a barrier property has the function of capturing or fixing (also referred to as gettering) the corresponding substance inside the insulating layer.

[0374] As an oxygen barrier insulating layer, for example, oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon oxynitride can be cited. In addition, as oxides containing one or two of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate) can be cited. For example, the insulating layer 250a, the insulating layer 250c, the insulating layer 250d, and the insulating layer 235 preferably adopt a single-layer structure or a stacked structure of the above oxygen barrier insulating layer.

[0375] The insulating layer 250a preferably has oxygen barrier properties. The insulating layer 250a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a has regions in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b. When the insulating layer 250a has oxygen barrier properties, oxidation of the side surfaces of the conductive layer 242a and the conductive layer 242b can be suppressed, and an oxide film can be formed on the side surfaces. Therefore, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200G can be suppressed.

[0376] In addition, the insulating layer 250a is provided so as to be in contact with the top surface and side surfaces of the semiconductor layer 230 and the top surface of the insulating layer 292. When the insulating layer 250a has oxygen barrier properties, oxygen can be suppressed from escaping from the channel formation region of the semiconductor layer 230 during heat treatment or the like. Thereby, oxygen vacancies formed in the semiconductor layer 230 can be reduced.

[0377] In addition, by providing the insulating layer 250a, excessive oxygen is suppressed from being supplied from the insulating layer 280 to the semiconductor layer 230, and an appropriate amount of oxygen can be supplied to the semiconductor layer 230. Thereby, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200G caused by over-oxidation of the source region and the drain region can be suppressed.

[0378] Since oxides containing one or both of aluminum and hafnium have oxygen barrier properties, they can be suitably used as the insulating layer 250a.

[0379] The insulating layer 250d also preferably has oxygen barrier properties. The insulating layer 250d is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260 and between the insulating layer 280 and the conductive layer 260. By adopting this structure, oxygen diffusion from the channel formation region of the semiconductor layer 230 to the conductive layer 260 can be suppressed, and oxygen vacancies can be formed in the channel formation region of the semiconductor layer 230. In addition, oxygen in the semiconductor layer 230 and oxygen in the insulating layer 280 can be suppressed from diffusing to the conductive layer 260, resulting in oxidation of the conductive layer 260. The insulating layer 250d is preferably at least less permeable to oxygen than the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 250d. At this time, the insulating layer 250d is an insulating layer containing at least nitrogen and silicon.

[0380] In addition, the insulating layer 250d preferably has hydrogen barrier properties. Thereby, impurities such as hydrogen contained in the conductive layer 260 can be prevented from diffusing into the semiconductor layer 230.

[0381] The insulating layer 235 also preferably has oxygen barrier properties. The insulating layer 235 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. The insulating layer 235 is provided in contact with the side surfaces of the conductive layer 242, the side surfaces of the semiconductor layer 230, and the top surface of the insulating layer 292. By adopting this structure, the oxygen contained in the insulating layer 280 can be suppressed from diffusing into the conductive layer 242. Therefore, the oxidation of the conductive layer 242 caused by the oxygen contained in the insulating layer 280, which increases the resistivity, can be suppressed. The insulating layer 235 is preferably at least less permeable to oxygen than the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 235. At this time, the insulating layer 235 is an insulating layer containing at least nitrogen and silicon.

[0382] In order to suppress the reduction of the hydrogen concentration in the source region and the drain region in the semiconductor layer 230, a hydrogen barrier insulating layer is preferably provided near the source region and near the drain region. In the semiconductor device described in this embodiment, this hydrogen barrier insulating layer is, for example, the insulating layer 235.

[0383] Examples of the hydrogen barrier insulating layer include oxides such as alumina, hafnium oxide, tantalum oxide, and nitrides such as silicon nitride. For example, the insulating layer 235 preferably adopts a single-layer structure or a stacked structure of the above hydrogen barrier insulating layer.

[0384] By providing the above insulating layer 235, the diffusion of hydrogen in the source region and the drain region to the outside can be reduced, and thus the reduction of the hydrogen concentration in the source region and the drain region can be suppressed. Therefore, the source region and the drain region can be n-type.

[0385] By adopting the above structure, the channel formation region can be made i-type or substantially i-type and the source region and the drain region can be made n-type, thereby providing a semiconductor device having good electrical characteristics. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing the transistor 200G, the high-frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0386] The insulating layers 250a to 250d are used as part of the gate insulating layer. The insulating layers 250a to 250d and the conductive layer 260 are disposed in an opening formed in the insulating layer 280. In order to miniaturize the transistor 200G, the thicknesses of the insulating layers 250a to 250d are preferably small. The thicknesses of the insulating layers 250a to 250d are all preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, still further preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. In addition, at least a part of each of the insulating layers 250a to 250d may include a region having the above-described thickness.

[0387] In addition, the thickness of the silicon oxide film used as the insulating layer 250 is preferably 0.7 nm or more and 3 nm or less.

[0388] In order to reduce the thicknesses of the insulating layers 250a to 250d as described above, deposition is preferably performed by an atomic layer deposition (ALD) method. In addition, in order to dispose the insulating layers 250a to 250d in the opening of the insulating layer 280 or the like, deposition is preferably performed by the ALD method. By using the ALD method, the insulating layer 250 can be deposited with high coverage on the side surface of the first opening formed in the insulating layer 280, the side end portions of the conductive layers 242a and 242b, and the like.

[0389] Note that in the above description, the insulating layer 250 has a four-layer structure of the insulating layers 250a to 250d, but the present invention is not limited thereto. The insulating layer 250 may have a structure including at least one of the insulating layers 250a to 250d. By forming the insulating layer 250 of one layer, two layers, or three layers among the insulating layers 250a to 250d, the manufacturing process of the transistor 200G can be simplified, and thus the productivity of the semiconductor device including the transistor 200G can be improved.

[0390] As Figure 35A shown, the shape of the semiconductor layer 230 in plan view is preferably a circumferential shape (which may also be referred to as a frame shape, a ring shape, a loop shape, or a closed curve shape) with both ends aligned. That is, the semiconductor layer 230 preferably has a structure including a plurality of portions extending in the channel width direction (A1 - A2 direction) and a plurality of portions extending in the channel length direction (A5 - A6 direction). Thereby, when the aspect ratio of the semiconductor layer 230 is high, it is possible to suppress the semiconductor layer 230 from falling down during the manufacturing process of the transistor. In addition, it can also be said that Figure 35A the semiconductor layer 230 shown has an opening in the central portion. In Figure 35AIn [the structure], the shape of the semiconductor layer 230 when viewed from above is an axisymmetric shape centered on A1 - A2, but the present invention is not limited thereto. For example, the shape of the semiconductor layer 230 when viewed from above may also be an asymmetric shape.

[0391] Figure 35A The structure shown is a structure in which two circumferential semiconductor layers 230 are formed in the Y direction. As Figure 35A shown, the semiconductor layer 230 preferably overlaps the conductive layer 260 at two or more locations when viewed from above. Therefore, the conductive layer 260 preferably has two or more regions that overlap the semiconductor layer 230. That is, it preferably has two or more regions where the semiconductor layer 230 and the conductive layer 260 overlap each other.

[0392] By adopting such a structure, as Figure 35B shown, in the cross-section in the channel width direction, a plurality of fin-shaped semiconductor layers 230 are formed. Each of the plurality of fin-shaped semiconductor layers 230 includes a channel formation region. That is, the transistor 200G is used as a multi-channel transistor. Therefore, in the transistor 200G, the channel width can be further increased, so the on-state current can be increased. Therefore, the operating speed of the semiconductor device including the transistor 200G can be improved.

[0393] In addition, in the above, a structure in which two circumferential semiconductor layers 230 are provided is described, but the present invention is not limited thereto. For example, one or three or more circumferential semiconductor layers 230 may be provided. In addition, the circumferential semiconductor layers 230 may be combined to form a semiconductor layer 230 having a shape with a plurality of openings. In addition, when viewed from above, a lattice-shaped semiconductor layer 230 may be used.

[0394] <Example 8 of the transistor structure>

[0395] Next, the transistor 200H, which is a modified example of the transistor 200G, will be described. Figure 37A is a plan view of the transistor 200H that can be used in a semiconductor device according to one aspect of the present invention. In addition, Figure 37B is a perspective schematic view of the transistor 200H. Additionally, Figures 37C to 37E is a cross-sectional view of the transistor 200H. Here, Figure 37C is a cross-sectional view along the dashed line A1 - A2 in Figure 37A , and is also a cross-sectional view in the channel width direction (Y direction) of the transistor 200H. Additionally, Figure 37D is a cross-sectional view along the dashed line A3 - A4 in Figure 37A , and is also a cross-sectional view in the channel width direction of the transistor 200H. In addition, Figure 37E is a cross-sectional view along Figure 37AThe cross-sectional view of the dash-dotted line A5 - A6 is also the cross-sectional view in the channel length direction (X direction) of the transistor 200H. Here, the dash-dotted line A5 - A6 is orthogonal to the dash-dotted lines A1 - A2 and A3 - A4, and the dash-dotted lines A1 - A2 and A3 - A4 are parallel to each other. Note that in Figure 37A the plan view of Figure 37B and Figure 38 the three-dimensional schematic view of Figure 37C the description of some constituent elements is omitted. In addition,

[0396] As Figures 37B to 37E shown, an insulating layer 294 can be provided under the semiconductor layer 230. The planar shape of the insulating layer 294 (the shape when viewed from the Z direction) is the same as that of the semiconductor layer 230. Therefore, the insulating layer 294 overlaps with the semiconductor layer 230 in a top view. The bottom surface of the insulating layer 294 contacts the insulating layer 292, the side surfaces of the insulating layer 294 contact the insulating layer 250 and the conductive layer 242a, and the top surface of the insulating layer 294 contacts the bottom surface of the semiconductor layer 230. In addition, the insulating layer 294 can use the insulating material that can be used for the insulating layer 250b. For example, silicon oxide can be used as the insulating layer 294.

[0397] In addition, Figures 37A to 37E corresponds to Figures 35A to 35E . In addition, Figure 38 corresponds to Figure 36B . Therefore, in the structure regarding Figures 37A to 37E and Figure 38 , for matters not described below, reference can be made to the above description regarding Figures 35A to 35E , Figure 36B and so on.

[0398] Here, as Figure 38 shown, the thickness t2 of the insulating layer 250 at the bottom of the first opening is preferably thinner than the thickness t1 of the insulating layer 294 (the length in the direction perpendicular to the formed surface of the insulating layer 294). By adopting such a structure, the position of the bottom surface of the conductive layer 260 (conductive layer 260a) located in the first opening can be lower than the bottom surface of the semiconductor layer 230 by the difference between the thickness t1 and the thickness t2 (t1 - t2).

[0399] By disposing the bottom surface of the conductive layer 260 below the bottom surface of the semiconductor layer 230, a sufficient gate electric field can be applied from the upper end portion to the lower end portion of the semiconductor layer 230. In other words, the entire semiconductor layer 230 can be electrically surrounded by the electric field of the conductive layer 260 within the opening of the insulating layer 280 or the like and used as a channel formation region. By adopting such a structure, it is possible to prevent the lower end portion of the semiconductor layer 230 from being used as a parasitic channel, thereby reducing the leakage current between the source electrode and the drain electrode. In addition, it is possible to suppress characteristics deterioration such as the normally-on state of the transistor due to the parasitic channel. That is, the electrical characteristics of the transistor 200H can be improved.

[0400] As described above, by using the upper end portion to the lower end portion of the semiconductor layer 230 as a channel formation region, the channel width can be increased. Thereby, the on-state current, transconductance, frequency characteristics, etc. of the transistor 200H can be improved.

[0401] Note that in the present specification and the like, the structure of the transistor in which the channel formation region is electrically surrounded by the electric field of the gate electrode is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is disposed so as to surround at least two or more surfaces of the channel (specifically, two surfaces, three surfaces, four surfaces, etc.). By adopting the S-channel structure, the resistance to the short-channel effect can be improved. In other words, a transistor in which the short-channel effect is not likely to occur can be realized.

[0402] Since the S-channel structure is a structure that electrically surrounds the channel formation region, it can also be said that this structure is substantially the same as the GAA (Gate All Around) structure or the LGAA (Lateral Gate All Around) structure. By making the transistor 200H have an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at the interface or near the interface between the semiconductor layer 230 and the insulating layer 250 serving as a gate insulating layer can be regarded as the entire bulk of the semiconductor layer 230. Therefore, the current density flowing through the transistor can be increased, so an increase in the on-state current of the transistor or an increase in the field-effect mobility of the transistor can be expected. In addition, in one aspect of the present invention, the semiconductor layer 230 has a CAAC structure and a fin structure. By adopting this structure, it is possible that the current path flowing between the source and drain of the transistor is parallel to the ab plane of the crystal axis. In other words, the oxide semiconductor having a CAAC structure and a fin structure has a conduction path that seems to be equivalent to that of a two-dimensional semiconductor material. In addition, by using an oxide semiconductor for the semiconductor layer of such a transistor, a device having two-dimensional conduction performance can be manufactured.

[0403] <Example 9 of transistor structure>

[0404] Figures 39A to 39E Transistor 200I showing a modified example of transistor 200G. Transistor 200I is different from transistor 200G in that in transistor 200I, a conductive layer 205 is included under the insulating layer 291. In addition, Figures 39A to 39E corresponds to Figures 35A to 35E . In the structure regarding Figures 39A to 39E , for matters not described below, reference can be made to the above description regarding Figures 35A to 35E etc.

[0405] The conductive layer 205 has a region overlapping with the channel formation region of the semiconductor layer 230. Therefore, similar to the conductive layer 260, the conductive layer 205 has a region serving as a gate electrode. Sometimes the conductive layer 260 is referred to as the first gate electrode (upper gate electrode) of transistor 200I, and the conductive layer 205 is referred to as the second gate electrode (lower gate electrode) of transistor 200I. In addition, when the conductive layer 260 is referred to as the gate electrode of transistor 200I, the conductive layer 205 is sometimes referred to as the back gate electrode of transistor 200I.

[0406] When a conductive layer 205 is included under the insulating layer 291 as in transistor 200I, similar to the insulating layer 250, both the insulating layer 292 and the insulating layer 291 include regions serving as gate insulating layers. Specifically, the regions of the insulating layer 292 and the insulating layer 291 that overlap with the conductive layer 205 are used as gate insulating layers. In addition, sometimes the insulating layer 250 is referred to as the first gate insulating layer (upper gate insulating layer), and the insulating layer 292 and the insulating layer 291 are referred to as the second gate insulating layer (lower gate insulating layer).

[0407] In transistor 200I, the conductive layer 205 is arranged to overlap with the semiconductor layer 230 and the conductive layer 260. In Figure 39C and Figure 39E , the conductive layer 205 is disposed inside a fourth opening that passes through the insulating layer 296 to reach the insulating layer 295. In addition, the fourth opening includes a region overlapping with the semiconductor layer 230 and a region extending along the Y direction beyond the end of the semiconductor layer 230 in a top view. Therefore, the conductive layer 205 disposed inside the fourth opening also includes a region overlapping with the semiconductor layer 230 and a region extending along the Y direction beyond the end of the semiconductor layer 230 in a top view. The conductive layer 205 is also used as a wiring.

[0408] As Figure 39C and Figure 39EAs shown, the conductive layer 205 preferably includes a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is disposed in contact with the bottom and sidewalls of the fourth opening. The conductive layer 205b is disposed to be embedded in the recess of the conductive layer 205a formed along the bottom and sidewalls of the fourth opening. Here, the top surface of the conductive layer 205 preferably coincides with or is substantially the same as the top surface of the insulating layer 296. That is, when viewed in the Y direction, the shortest distance from the top surface of the substrate (not shown) to the top surface of the insulating layer 296 preferably coincides with or is substantially the same as the shortest distance from the top surface of the substrate to the top surface of the conductive layer 205.

[0409] Here, as the conductive layer 205a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms is preferably included. Alternatively, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably included.

[0410] By using a conductive material having a function of reducing hydrogen diffusion as the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing into the semiconductor layer 230 through the insulating layer 296 or the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion as the conductive layer 205a, oxidation of the conductive layer 205b and a decrease in conductivity can be suppressed. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be cited. The conductive layer 205a can have a single-layer structure or a stacked structure of the above conductive materials. For example, the conductive layer 205a preferably includes titanium nitride.

[0411] In addition, the conductive layer 205b preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductive layer 205b preferably includes tungsten.

[0412] As described above, the conductive layer 205 can be used as the second gate electrode. In this case, by independently changing the potential applied to the conductive layer 205 without linking it to the potential applied to the conductive layer 260, the threshold voltage (Vth) of the transistor 200I can be controlled. In particular, by applying a negative potential to the conductive layer 205, the Vth of the transistor 200I can be further increased and the off-state current can be reduced. Thus, compared with the case where a negative potential is not applied to the conductive layer 205, the drain current when the potential of the conductive layer 260 is 0V can be reduced when a negative potential is applied to the conductive layer 205.

[0413] In addition, considering the potential applied to the conductive layer 205 as described above, the resistivity of the conductive layer 205 is designed, and the thickness of the conductive layer 205 is set according to this resistivity. In addition, the thickness of the insulating layer 296 is substantially the same as that of the conductive layer 205. Here, it is preferable to reduce the thicknesses of the conductive layer 205 and the insulating layer 296 within the range allowed by the design of the conductive layer 205. By reducing the thickness of the insulating layer 296, the absolute amount of impurities such as hydrogen contained in the insulating layer 296 can be reduced, so that the diffusion of the impurities into the semiconductor layer 230 can be suppressed.

[0414] Note that in the above structure, a stacked structure of the conductive layer 205a and the conductive layer 205b is shown, but the present invention is not limited thereto, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 205 has a three-layer stacked structure, a stacked structure in the above conductive layer 205a and conductive layer 205b can be adopted, and a conductive layer containing the same material as the conductive layer 205a can be provided on the conductive layer 205b. At this time, the above conductive layer can be formed in such a manner as to be embedded in a recess formed by the conductive layer 205a and the conductive layer 205b, and the recess is formed in such a manner that the top surface of the conductive layer 205b is lower than the uppermost part of the conductive layer 205a.

[0415] As materials for the conductive layer 205, the conductive layer 242, the conductive layer 245, and the conductive layer 260, in addition to the materials disclosed in the present embodiment, the materials of the conductive layers shown in other embodiments can also be used. As materials for the insulating layer 295, the insulating layer 296, the insulating layer 291, the insulating layer 292, the insulating layer 241, the insulating layer 250, the insulating layer 235, the insulating layer 280, the insulating layer 297, and the insulating layer 298, in addition to the materials disclosed in the present embodiment, the materials of the insulating layers shown in other embodiments can also be used.

[0416] The transistor 200I described in the present embodiment can be used as a transistor constituting the semiconductor device 10. The transistor 200I can increase the on-state current without increasing the occupied area.

[0417] <Constituent materials of the transistor>

[0418] Next, the constituent materials that can be used for the transistor 200 (the transistor 200A, the transistor 200B, the transistor 200C, the transistor 200D, the transistor 200E, the transistor 200F, the transistor 200G, the transistor 200H, and the transistor 200I) will be described.

[0419] [Substrate]

[0420] When a transistor is provided on a substrate, there is no particular limitation on the material for the substrate. The material for the substrate is considered in terms of whether it needs to have light transmissibility and heat resistance such as being able to withstand heat treatment according to the purpose of use. For example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used as the substrate. As the insulator substrate, for example, glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttrium-stabilized zirconia substrates), etc. can be used. In addition, as the substrate, a semiconductor substrate, a flexible substrate, a resin substrate, etc. can be used.

[0421] As the semiconductor substrate, for example, there are semiconductor substrates made of materials such as silicon or germanium, or compound semiconductor substrates made of materials such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. And, a semiconductor substrate having an insulator region inside the above semiconductor substrate, such as a SOI (Silicon On Insulator) substrate, etc. can also be cited. In addition, the semiconductor substrate can be a single-crystal semiconductor or a polycrystalline semiconductor.

[0422] As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Or, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. And, a substrate having a conductive layer or a semiconductor layer provided on an insulator substrate, a substrate having a conductive layer or an insulating layer provided on a semiconductor substrate, a substrate having a semiconductor layer or an insulating layer provided on a conductor substrate, etc. can also be cited.

[0423] As the material for the flexible substrate, resin substrate, etc., for example, polyesters such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofibers, etc. can be used.

[0424] By using the above materials as the substrate, a lightweight semiconductor device can be provided. In addition, by using the above materials as the substrate, a semiconductor device with high impact resistance can be provided. In addition, by using the above materials as the substrate, a semiconductor device that is not easily damaged can be provided. Or, a substrate having elements provided on these substrates can also be used. As the elements provided on the substrate, a capacitor element, a resistor, a switching element, a light-emitting element, a storage element, etc. can be cited.

[0425] [Insulating layer]

[0426] An inorganic insulating film is used as the insulating layer (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 295, insulating layer 296, insulating layer 291, insulating layer 292, insulating layer 294, insulating layer 241, insulating layer 257, insulating layer 250, insulating layer 258, insulating layer 258a, insulating layer 258b, insulating layer 259, insulating layer 264, insulating layer 266, insulating layer 268, insulating layer 516, insulating layer 235, insulating layer 280, insulating layer 297, insulating layer 298, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). As the inorganic insulating film, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitrogen oxide insulating film can be cited. As the oxide insulating film, for example, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film can be cited. As the nitride insulating film, for example, a silicon nitride film and an aluminum nitride film can be cited. As the oxynitride insulating film, for example, a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, a yttrium oxynitride film, and a hafnium oxynitride film can be cited. As the nitrogen oxide insulating film, for example, a silicon nitrogen oxide film and an aluminum nitrogen oxide film can be cited. In addition, an organic insulating film can also be used as the insulating layer included in the semiconductor device.

[0427] Note that in this specification, etc., "oxynitride" refers to a material in which the oxygen content is more than the nitrogen content in its composition, and "nitrogen oxide" refers to a material in which the nitrogen content is more than the oxygen content in its composition. For example, when recorded as "silicon oxynitride", it refers to a material in which the oxygen content is more than the nitrogen content in its composition, and when recorded as "silicon nitrogen oxide", it refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0428] For example, with the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material for the insulating layer such as insulating layer 204 and insulating layer 264 that are used as the gate insulating layer, low voltage operation of the transistor can be achieved while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative dielectric constant for the insulating layer used as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulating layer. In addition, a material with a low relative dielectric constant is also a material with a large dielectric strength.

[0429] As materials with a high relative dielectric constant (high-k), for example, alumina, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium can be cited, etc.

[0430] As materials with a low relative dielectric constant, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin can be cited. In addition, as inorganic insulating materials with a low relative dielectric constant other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, silicon oxide having holes can be cited. In addition, these silicon oxides may also contain nitrogen.

[0431] [Conductive layer]

[0432] As the conductive layer for the transistor 200 (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 242, conductive layer 245, conductive layer 255, conductive layer 260, conductive layer 267, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.), it is preferably to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy composed of the above metal elements, or an alloy combining the above metal elements, etc. As the alloy composed of the above metal elements, a nitride of the alloy or an oxide of the alloy can be used. For example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, a semiconductor with a high conductivity represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can be used.

[0433] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, titanium and aluminum nitride, etc., conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxides, lanthanum and nickel oxides, etc., materials containing metal elements such as titanium, tantalum, ruthenium, etc. are conductive materials that are not easily oxidized, conductive materials having a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when absorbing oxygen, and thus are preferred. Note that, as the conductive material containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO (Indium Tin Oxide)), indium tin oxide containing titanium oxide, indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), indium zinc oxide containing tungsten oxide, etc. may be mentioned. In this specification and the like, a conductive layer formed using a conductive material containing oxygen is sometimes referred to as an oxide conductive layer.

[0434] Conductive materials mainly composed of tungsten, copper, or aluminum have high conductivity and are therefore preferred.

[0435] In addition, a conductive layer formed by laminating a plurality of the above-mentioned materials may also be used. For example, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen may be adopted. In addition, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen may also be adopted. In addition, a laminated structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may also be adopted.

[0436] For example, in the case where an oxide semiconductor, which is one of metal oxides, is used for the semiconductor layer 203 of the transistor 200A or the transistor 200B, as the conductive layer 205, the conductive layer 219, etc. serving as a gate electrode, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably adopted. In this case, it is preferable to dispose the conductive material containing oxygen on the side of the semiconductor layer 203. By disposing the conductive material containing oxygen on the side of the semiconductor layer 203, oxygen released from the conductive material is easily supplied to the channel formation region of the semiconductor layer 203.

[0437] In the case where an oxide semiconductor, which is one of metal oxides, is used as the semiconductor layer 203, semiconductor layer 263, or semiconductor layer 520, since the conductive layers 208a, 208b, 255, 261, 542a, and 542b are all conductive layers in contact with the semiconductor layer 203, semiconductor layer 263, or semiconductor layer 520, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, a conductive metal oxide (also referred to as an oxide conductor), or a conductive material having a function of suppressing oxygen diffusion. As such a conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thereby, a decrease in the conductivity of the conductive layers 208a, 208b, 255, 261, 542a, and 542b can be suppressed.

[0438] By using a conductive material containing oxygen as the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity can be maintained even when the conductive layers 208a, 208b, 255, 261, 542a, and 542b absorb oxygen. For example, in the case where an insulating layer containing excess oxygen is used as the insulating layer in contact with the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductive layers 208a, 208b, 255, 261, 542a, and 542b can also maintain conductivity, so it is preferable. As the conductive layers 208a, 208b, 255, 261, 542a, and 542b, for example, ITO, ITSO, IZO (registered trademark), etc. can all be used.

[0439] [Semiconductor layer]

[0440] As the semiconductor layer (semiconductor layer 203, semiconductor layer 230, semiconductor layer 263, semiconductor layer 520, etc.), a single crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, amorphous semiconductor, etc. can be used alone or in combination. As the semiconductor material, for example, silicon, germanium, etc. can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. As the compound semiconductor, an organic substance having semiconductor characteristics or a metal oxide having semiconductor characteristics (also referred to as an oxide semiconductor) can be used. These semiconductor materials can also contain impurities as dopants.

[0441] In addition, as the semiconductor layer, a semiconductor composed of a single element or a compound semiconductor can be used. As the semiconductor composed of a single element, for example, silicon and germanium can be cited. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be cited. In addition to these, as the compound semiconductor, for example, an organic semiconductor and a nitride semiconductor can be cited. An oxide semiconductor is also a kind of compound semiconductor. These semiconductor materials can also contain impurities as dopants.

[0442] In the case where silicon is used for the semiconductor layer, as the silicon that can be used for the semiconductor layer, single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be cited. As the polycrystalline silicon, for example, low-temperature polycrystalline silicon (LTPS: Low Temperature PolySilicon) can be cited.

[0443] For example, by using silicon for the semiconductor layer 203 of the transistor 200A or the transistor 200B and making the regions 203a and 203c of the semiconductor layer 203 contain phosphorus or arsenic as an n-type dopant, this transistor can be used as an n-type transistor. In addition, by making the regions 203a and 203c of the semiconductor layer 203 contain boron as a p-type dopant, this transistor can be used as a p-type transistor. Note that in the case where both an n-type dopant and a p-type dopant are contained in the regions 203a and 203c of the semiconductor layer 203, the conductivity type of the higher doping concentration is likely to be presented.

[0444] As the semiconductor layer of the transistor, a two-dimensional material used as a semiconductor can also be used. A two-dimensional material is also called a layered substance and is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds weaker than covalent bonds and ionic bonds such as van der Waals bonding. The layered substance has high conductivity in the unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0445] As the above-mentioned layered substances, for example, graphene, silicene, chalcogenides, etc. can be cited. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). In addition, as the chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited. As the transition metal chalcogenides that can be used for the semiconductor layer of the transistor, specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0446] When using an oxide semiconductor as one of the metal oxides for the semiconductor layer, the bandgap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap as the semiconductor layer, the off-state current of the transistor can be significantly reduced. Since the off-state current of the OS transistor is small, the power consumption of the semiconductor device can be reduced. The oxide semiconductor will be described in detail in Embodiment 3.

[0447] The structure shown in this embodiment can be implemented by appropriately combining with the structures shown in other embodiments.

[0448] Embodiment 4

[0449] In this embodiment, an oxide semiconductor layer that can be used as the semiconductor layer of a transistor will be described.

[0450] [Oxide semiconductor layer]

[0451] The oxide semiconductor layer of one aspect of the present invention preferably contains a crystalline metal oxide. As the structure of the crystalline metal oxide, for example, a CAAC (c-axis aligned crystal) structure, a poly-crystal structure, and a nano-crystal (nc) structure can be cited. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Thereby, the reliability of the transistor using the oxide semiconductor layer of one aspect of the present invention can be improved, and thus the reliability of the storage device including the transistor can be improved.

[0452] The oxide semiconductor layer of one aspect of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure means a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected in such a manner that the plurality of microcrystals are not oriented on the a-b plane. In addition, when observing the cross-section of the oxide semiconductor layer having a CAAC structure using a high-resolution transmission electron microscope (TEM: Transmission Electron Microscope) image, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to be a structure having a layered crystalline part.

[0453] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD: X-Ray Diffraction), TEM, or electron diffraction (ED: Electron Diffraction). In addition, it can also be analyzed by combining multiple methods among the above.

[0454] In addition, there is no particular limitation on the crystallinity of the semiconductor material included in the oxide semiconductor layer. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor in which a part has a crystalline region). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can sometimes be suppressed.

[0455] Examples of the metal oxide included in the oxide semiconductor layer as one aspect of the present invention include indium oxide (InO x , where x is an arbitrary number), gallium oxide (GaO x , where x is an arbitrary number), and zinc oxide (ZnO x , where x is an arbitrary number). The metal oxide of one aspect of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. In addition, element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. can be cited. Element M included in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. When element M included in the metal oxide is gallium, the metal oxide of one aspect of the present invention preferably contains any one or more selected from indium, gallium, and zinc. Note that in this specification, etc., metal elements and metalloid elements are sometimes collectively referred to as "metal elements", and the "metal elements" described in this specification, etc. sometimes include metalloid elements.

[0456] As a metal oxide according to one embodiment of the present invention, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (also denoted as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. can be used, for example. In addition, indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can also be mentioned.

[0457] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide, a transistor can achieve a large on-state current and high-frequency characteristics. In addition, in the case where the metal oxide is indium oxide, the transistor can also achieve a large on-state current and high-frequency characteristics.

[0458] In addition, the metal oxide may contain one or more of the metal elements with a large period number in the periodic table instead of indium. Or, the metal oxide may contain one or more of the metal elements with a large period number in the periodic table in addition to indium. There is a tendency that the larger the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Thus, by containing the metal elements with a large period number in the periodic table, the field-effect mobility of the transistor can sometimes be increased. Examples of the metal elements with a large period number in the periodic table include the metal elements belonging to the 5th period and the metal elements belonging to the 6th period. Specifically, examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0459] In addition, the metal oxide may contain one or more of the non-metal elements. When the metal oxide contains non-metal elements, the field-effect mobility of the transistor can sometimes be increased. Examples of the non-metal elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen, for example.

[0460] In addition, by increasing the ratio of the number of atoms of zinc to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, whereby the diffusion of impurities in the metal oxide can be suppressed. Therefore, variations in the electrical characteristics of the transistor are suppressed, whereby reliability can be improved.

[0461] In addition, by increasing the ratio of the number of atoms of element M to the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, whereby a transistor with a small off-state current can be realized. In addition, variations in the electrical characteristics of the transistor are suppressed, so that reliability can be improved.

[0462] In the present embodiment, an example in which the metal oxide is an In-Ga-Zn oxide may be described.

[0463] The oxide semiconductor layer of one embodiment of the present invention has crystallinity. In addition, the oxide semiconductor layer of one embodiment of the present invention preferably has a CAAC structure.

[0464] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods may also be referred to as a Hybrid OS.

[0465] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by the following process: forming a metal oxide as a first layer using a first deposition method, and then forming a metal oxide as a second layer on the first layer using a second deposition method. At this time, as the first deposition method, a deposition method that causes less damage to the surface to be formed than the second deposition method is preferably used. When a deposition method that causes less damage to the surface to be formed is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on the surface to be formed of the oxide semiconductor layer can be suppressed. In addition, the incorporation of impurities such as silicon into the second layer can be suppressed, so that the crystallinity of the oxide semiconductor layer can be improved.

[0466] As the first deposition method, for example, the ALD method, chemical vapor deposition (CVD: Chemical Vapor Deposition) method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, wet method, etc. can be cited. As the CVD method, for example, plasma CVD (PECVD: Plasma Enhanced CVD) method, thermal CVD method, photo-CVD method, metal organic CVD (MOCVD: Metal Organic CVD) method, etc. can be cited. As the wet method, for example, a spraying method, etc. can be cited. Compared with the sputtering method described later, the ALD method and the CVD method can suppress damage to the surface to be formed, so they are suitable for the first deposition method.

[0467] As the ALD method, a thermal ALD (Thermal ALD) method that causes a precursor and a reactant to react only by using heat energy, a PEALD method that uses a reactant excited by plasma, etc. can be cited.

[0468] When using the ALD method, atoms can be deposited layer by layer, so there are the following effects: it can be deposited extremely thinly; it can deposit on a structure with a high aspect ratio or a surface with large steps; it can be deposited by a method with few defects such as pinholes; it can be deposited with high coverage; and it can be deposited at a low temperature; etc. In addition, the PEALD method can be deposited at a lower temperature by using plasma, so it is sometimes preferred. Note that as the precursor used in the ALD method, there is a precursor containing carbon or chlorine. Therefore, compared with the film formed by using other deposition methods, the film formed by using the ALD method sometimes contains more carbon or chlorine. Note that the quantification of these elements can be performed by X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry). In addition, although the deposition method of the metal oxide according to one embodiment of the present invention uses the ALD method, since one or both of the conditions of a high substrate temperature during deposition and an impurity removal treatment are adopted, the content of carbon and chlorine in the film is sometimes less than that in the case of using the ALD method without adopting the above conditions.

[0469] Different from the deposition method of depositing particles released from a target or the like, the ALD method is a deposition method of forming a film by the reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio, etc.

[0470] By using plasma CVD method, a high-quality film can be obtained at a relatively low temperature. In addition, since plasma is not used, thermal CVD method is a deposition method that can reduce plasma damage to the object to be processed. In addition, in the thermal CVD method, plasma damage during formation does not occur, so a film with fewer defects can be obtained.

[0471] As the second deposition method, for example, sputtering method, pulsed laser deposition (PLD: Pulsed Laser Deposition) method, etc. can be cited. The metal oxide formed by the second deposition method easily has a CAAC structure.

[0472] In addition, as the first layer, a metal oxide having a microcrystalline structure or an amorphous structure with a lower crystallinity than the CAAC structure may be formed, for example. By forming a second layer with a high crystallinity on the first layer with a low crystallinity or forming this layer and performing heat treatment on it, the crystallinity of the first layer may be improved with the second layer as a nucleus. Thereby, the crystallinity of the entire oxide semiconductor layer including the vicinity of the interface with the surface to be formed can be improved.

[0473] In addition, a third layer can be formed on the second layer. Since the second layer has high crystallinity, the third layer can crystallize and grow with the crystal of the second layer as a nucleus or seed. Thereby, even if a deposition method that does not easily have crystallinity is used as the deposition method for the third layer, the third layer can be crystallized. Here, for example, when the third layer is formed by a deposition method with higher coverage than the second layer, high crystallinity and high coverage can be achieved in the entire oxide semiconductor layer.

[0474] As an example, an oxide semiconductor layer according to one embodiment of the present invention can be manufactured by the following steps: forming a metal oxide as the first layer using a first deposition method, then forming a metal oxide as the second layer using a second deposition method, and then forming a metal oxide as the third layer using the first deposition method. Specifically, the ALD method can be used as the first deposition method, and the sputtering method can be used as the second deposition method. The ALD method is a deposition method with excellent coverage compared to the sputtering method. When the ALD method is used as the deposition method for the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with a high aspect ratio.

[0475] [Method for manufacturing oxide semiconductor layer]

[0476] The semiconductor layer 230 as the oxide semiconductor layer can be manufactured, for example, through the following process: The semiconductor layer 230a is formed on the layer 229 of the formation surface by ALD method, the semiconductor layer 230b as the oxide semiconductor layer is formed on the semiconductor layer 230a by sputtering method, and the semiconductor layer 230c as the oxide semiconductor layer is formed on the semiconductor layer 230b by ALD method. And it is preferable to perform heat treatment after forming the semiconductor layer 230 as the oxide semiconductor layer. By performing heat treatment, the crystallinity of the semiconductor layer 230 can be improved. The heat treatment described here is not limited to heat treatment. For example, it can also be the heat received during the manufacturing process, etc.

[0477] In addition, the layer 229 corresponds to the insulating layer 202, insulating layer 256, insulating layer 258, etc. described in the above embodiments. The layer 229 does not necessarily have crystallinity. In addition, when the layer 229 has crystallinity, the layer 229 may also have a crystal structure with low lattice integrality with the metal oxide contained in the semiconductor layer 230.

[0478] Refer to Figures 40A to 40D and Figures 41A to 41D An example of the manufacturing method of the semiconductor layer 230 will be described.

[0479] When depositing a metal oxide film by sputtering method, sometimes alloying of the components contained in the metal oxide film and the components contained in the layer of the formation surface occurs due to damage caused by sputtering particles to the formation surface or the energy applied to the substrate side through sputtering particles, etc. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when performing the heat treatment described later. When using an oxide semiconductor layer having an alloyed region for a transistor, there is a concern of having a negative impact on the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying of the components contained in the metal oxide film and the components contained in the layer of the formation surface.

[0480] Therefore, first, the semiconductor layer 230a ( Figure 40A ) is formed on the layer 229 by ALD method. Then, the semiconductor layer 230b ( Figure 40B ) is formed on the semiconductor layer 230a by sputtering method.

[0481] In the manufacturing method of the oxide semiconductor layer of one aspect of the present invention, the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 by a deposition method that causes less damage to the formation surface, thereby suppressing the alloying of the components contained in the semiconductor layer 230 and the components contained in the layer 229, and thus the crystallinity of the semiconductor layer 230 can be further improved.

[0482] By adopting the above structure, the thickness of the alloyed region can be thinned or the alloyed region can be thinned to an undetectable level. For example, the thickness of the alloyed region can be thinned to more than 0 nm and less than 3 nm, preferably more than 0 nm and less than 2 nm, more preferably more than 0 nm and less than 1 nm, and further preferably more than 0 nm and less than 0.3 nm. Note that Figure 40A and Figure 40B show an example of a case where an alloyed region is not formed between the layer 229 and the semiconductor layer 230a.

[0483] Note that the thickness of the alloyed region can sometimes be calculated by the following method: linearly analyze the composition of the region and its vicinity using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0484] For example, perform a linear analysis using EDX on the above region and its vicinity in the direction perpendicular to the formed surface of the semiconductor layer 230a as the depth direction. Then, in the distribution of the quantitative values of each element in the depth direction obtained from this analysis, define the depth (position) of the interface between the above region and the semiconductor layer 230a as the depth at which the quantitative value of the metal (In in the case where the semiconductor layer 230a contains In), which is the main component of the semiconductor layer 230a rather than the main component of the layer of the formed surface (here the layer 229), reaches half value. In addition, define the depth (position) of the interface between the above region and the layer of the formed surface as the depth at which the quantitative value of the element (for example, Si), which is the main component of the layer of the formed surface rather than the main component of the semiconductor layer 230a, reaches half value. Thus, the thickness of the alloyed region can be calculated.

[0485] In the oxide semiconductor layer of one embodiment of the present invention, when observing the thickness of the alloyed region by EDX analysis, for example, the thickness is more than 0 nm and less than 3 nm, preferably more than 0 nm and less than 2 nm, more preferably more than 0 nm and less than 1 nm, and further preferably more than 0 nm and less than 0.3 nm.

[0486] In addition, for example, in the case of using a silicon oxide layer as the layer 229 and performing SIMS analysis on the semiconductor layer 230 formed on the layer 229, regard the depth at which the concentration of silicon reaches 50% of the maximum value of the concentration in the layer 229 as the interface, and reduce the concentration of silicon to 1.0×10 21 atoms / cm 3 , preferably 5.0×10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm3 The distance from the depth at a certain time to the interface is regarded as the thickness t_s2. The thickness t_s2 is preferably 3 nm or less, more preferably 2 nm or less.

[0487] By thinning the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0488] In addition, by thinning the alloyed region, a CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface means, for example, a region that is more than 0 nm and 3 nm or less, preferably more than 0 nm and 2 nm or less, and more preferably 1 nm or more and 2 nm or less in the direction substantially perpendicular to the formation surface of the semiconductor layer 230.

[0489] Note that the CAAC structure near the formation surface can sometimes be confirmed in the observation using TEM. For example, when performing cross-sectional observation of the semiconductor layer 230 using high-resolution TEM, bright spots arranged in layers in the direction parallel to the formation surface are confirmed near the formation surface.

[0490] In addition, when forming the semiconductor layer 230a by ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure is sometimes formed. That is, in Figure 40A the manufacturing stage shown, the semiconductor layer 230a sometimes includes a region with lower crystallinity than the semiconductor layer 230b.

[0491] The semiconductor layer 230b preferably has a composition suitable for the formation of the CAAC structure.

[0492] When forming the semiconductor layer 230b by sputtering method, a mixed layer 231 is formed on the surface or near the surface of the semiconductor layer 230a. In addition, when forming the semiconductor layer 230b, sometimes due to sputtering particles or energy applied to the substrate side through sputtering particles, etc., microcrystalline regions are formed in the mixed layer 231. In the subsequent heat treatment process, sometimes the mixed layer 231 or the microcrystalline regions formed in the mixed layer 231 become nuclei and at least a part of the semiconductor layer 230a crystallizes.

[0493] When depositing the semiconductor layer 230b by sputtering method, it is preferable to heat the substrate. When forming a metal oxide, sometimes a metal oxide with high crystallinity can be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide.

[0494] Next, a semiconductor layer 230c is formed on the semiconductor layer 230b by ALD method ( Figure 40C ). When forming the semiconductor layer 230c by ALD method, the formation method of the semiconductor layer 230a can be referred to.

[0495] When forming the semiconductor layer 230c by ALD method on the semiconductor layer 230b having a CAAC structure, sometimes the semiconductor layer 230c grows epitaxially with the semiconductor layer 230b as the nucleus. Thus, when forming the semiconductor layer 230c, sometimes the semiconductor layer 230c includes a region having a CAAC structure. In addition, this region having a CAAC structure is preferably formed throughout the semiconductor layer 230c.

[0496] Next, a heat treatment process may also be performed. By this heat treatment process, sometimes the crystallinity of this region having a CAAC structure in the semiconductor layer 230c is improved. In addition, when this region is only formed below the semiconductor layer 230c after deposition by ALD method, sometimes this region expands above the semiconductor layer 230c by this heat treatment process ( Figure 40D ). That is, by performing this heat treatment, sometimes a region having a CAAC structure in the semiconductor layer 230c is formed throughout the semiconductor layer 230c.

[0497] In addition, it is preferable that at least a part of the semiconductor layer 230a is CAACified by this heat treatment process ( Figure 40D ). It is expected that the mixed layer 231 formed in the semiconductor layer 230a when depositing the semiconductor layer 230b is used as a nucleus or seed and CAACification is easily achieved. In the semiconductor layer 230a, the larger the CAACified region, the better, and preferably the vicinity of the layer 229 is also CAACified.

[0498] In addition, since CAACification is performed from the upper part to the lower part of the semiconductor layer 230a, it is not limited by the material or crystallinity of the layer 229, and the vicinity of the layer 229 can also be CAACified. For example, even if the layer 229 has an amorphous structure, a semiconductor layer 230a with high crystallinity can be formed. Thus, the manufacturing method of the oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer on the formation surface has an amorphous structure.

[0499] Note that Figures 40A to 40D is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention. In addition, Figures 40A to 40D it can also be regarded as a schematic diagram of a deposition model of a metal oxide according to one embodiment of the present invention. As Figures 40A to 40D shown, the crystallinity of the semiconductor layer 230a and the semiconductor layer 230c is improved with the highly crystalline semiconductor layer 230b as the nucleus or seed. Specifically, the crystallinity of the semiconductor layer 230a is sometimes improved by heat treatment during deposition of the semiconductor layer 230b or after deposition of the semiconductor layer 230c. In addition, the crystallinity of the semiconductor layer 230c is sometimes improved by heat treatment during deposition of the semiconductor layer 230c or after deposition of the semiconductor layer 230c. Note that the above heat treatment has a function of assisting in improving crystallinity.

[0500] Thus, in the method for depositing a metal oxide according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, the semiconductor layers 230a and 230c) can be improved with the highly crystalline semiconductor layer 230b (i.e., CAAC) as a nucleus or seed. Thereby, the crystallinity of the entire oxide semiconductor can be improved. In other words, the upper and lower oxide semiconductors are solid-phase epitaxially grown with the semiconductor layer 230b as a nucleus or seed, whereby a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed by this deposition method, here the CAAC film, can be referred to as Axial Growth CAAC (AG CAAC). Note that Figures 41A to 41D The structure including the semiconductor layers 230a, 230b, and 230c is shown, but it is not limited thereto. For example, the structure including the semiconductor layers 230a and 230b can also be referred to as AG CAAC.

[0501] In the semiconductor layer 230, regions having a CAAC structure are preferably widely present throughout the layer. Figure 41A The state in which the semiconductor layers 230a, 230b, and 230c are all crystallized is shown. At this time, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may sometimes not be observed. In addition, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may sometimes not be observed. The semiconductor layer 230 can sometimes be said to be a layer in which its interface is clearly not observable. The semiconductor layer 230 can sometimes be said to be a layer having a single-layer structure.

[0502] In addition, a part of the semiconductor layer 230a or the semiconductor layer 230c may sometimes not be crystallized. Figure 41B The example shown shows a state in which the vicinity of the interface with the layer 229 in the semiconductor layer 230a is not crystallized. Figure 41C The state in which the vicinity of the surface in the semiconductor layer 230c is not crystallized is shown. Figure 41D The state in which the vicinity of the interface of the semiconductor layer 230a with the layer 229 and the vicinity of the surface of the semiconductor layer 230c are not crystallized is shown.

[0503] By improving the crystallinity of the oxide semiconductor layer, an increase in the resistance of the semiconductor layer of a transistor using the oxide semiconductor layer is suppressed and the initial characteristics of the transistor (especially the on-state current) are improved, whereby a transistor suitable for high-speed driving can be expected to be realized. In addition, the reliability of the transistor can be improved, and the on-state current can be increased.

[0504] In one embodiment of the present invention, the oxide semiconductor layer has high crystallinity throughout the layer. As a result, in the semiconductor layer 230, the boundaries of the stacked films cannot be observed in the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c. In particular, after heat treatment, it is difficult to confirm the boundaries of the stacked films. To confirm the presence or absence of the boundaries of the stacked films, for example, TEM or the like can be used.

[0505] As described above, by using a metal oxide with a high In content rate for the transistor, the field-effect mobility of the transistor can be improved. On the other hand, an oxide semiconductor with a high In content rate has a tendency to polycrystallize. By using a polycrystalline metal oxide for the transistor, it has a negative impact on the initial characteristics or reliability of the transistor. Thus, by using an oxide semiconductor with a high In content rate for one or both of the semiconductor layer 230a and the semiconductor layer 230c, a crystal reflecting the crystal orientation of the semiconductor layer 230b is formed, whereby polycrystallization can be suppressed.

[0506] In addition, the lattice mismatch degree between the crystal of the semiconductor layer 230b and the crystal of the semiconductor layer 230a or the semiconductor layer 230c is preferably small. As a result, the semiconductor layer 230a or the semiconductor layer 230c can form a crystal reflecting the crystal orientation of the semiconductor layer 230b. At this time, for example, when the semiconductor layer 230 is observed in cross section using a high-resolution TEM, bright spots arranged in layers in the direction parallel to the formation surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0507] As long as the lattice mismatch degree between the crystal of the semiconductor layer 230b and the crystal of the semiconductor layer 230a or the semiconductor layer 230c is small, there is no particular limitation on the crystal structure of the semiconductor layer 230a or the semiconductor layer 230c. The crystal structure of the semiconductor layer 230a or the semiconductor layer 230c can also be any one of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0508] [Composition of Oxide Semiconductor Layer]

[0509] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. When forming the semiconductor layer 230b, for example, a sputtering method can be used. The semiconductor layer 230b preferably contains zinc, for example. By containing zinc, a metal oxide with high crystallinity can be achieved. In addition, the semiconductor layer 230b preferably contains an element M in addition to zinc. When the semiconductor layer 230b contains the element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Thereby, the reliability of a transistor using the oxide semiconductor layer can be improved. As the semiconductor layer 230b, specifically, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or around it, In:M:Zn = 1:1:1.2 [atomic ratio] or around it, In:M:Zn = 1:1:0.5 [atomic ratio] or around it, In:M:Zn = 1:1:2 [atomic ratio] or around it, In:M:Zn = 4:2:3 [atomic ratio] or around it, In:M:Zn = 1:3:2 [atomic ratio] or around it, or In:M:Zn = 1:3:4 [atomic ratio] or around it can be used. In addition, the composition around it includes a range of ±30% of the desired atomic ratio. In addition, as the element M, one or more of gallium, aluminum, and tin are preferably used.

[0510] The semiconductor layer 230b can adopt a structure that does not contain the element M. For example, an In-Zn oxide can be used. Specifically, a composition of In:Zn = 1:1 [atomic ratio] or around it, In:Zn = 2:1 [atomic ratio] or around it, or In:Zn = 4:1 [atomic ratio] or around it can be adopted. Alternatively, indium oxide can be used. In addition, a structure containing a trace amount of the element M can be adopted. For example, a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or around it, or In:Ga:Zn = 2:0.1:1 [atomic ratio] or around it can be adopted. In addition, for example, a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or around it, or In:Sn:Zn = 2:0.1:1 [atomic ratio] or around it can be adopted.

[0511] The semiconductor layers 230a and 230c can use a metal oxide with a high proportion of In. When forming the semiconductor layers 230a and 230c, for example, an ALD method can be used. In addition, in particular, a metal oxide with a higher proportion of In than the element M is preferably used. By using a metal oxide with a high proportion of In, the on-state current can be increased and the frequency characteristics can be improved when the oxide semiconductor layer is used for a transistor.

[0512] In addition, the semiconductor layers 230a and 230c may have a structure that does not contain element M. For example, In-Zn oxide can be used. Specifically, a composition of In:Zn = 1:1 [atomic ratio] or around it, a composition of In:Zn = 2:1 [atomic ratio] or around it, or a composition of In:Zn = 4:1 [atomic ratio] or around it can be adopted. Alternatively, indium oxide can be used. In addition, the semiconductor layers 230a and 230c may have a structure that contains a trace amount of element M. Specifically, a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or around it, a composition of In:Ga:Zn = 2:0.1:1 [atomic ratio] or around it, a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or around it, or a composition of In:Sn:Zn = 2:0.1:1 [atomic ratio] or around it can be adopted.

[0513] In addition, by increasing the proportion of zinc in the oxide semiconductor, the crystallinity of the oxide semiconductor can be improved. In particular, a structure in which the semiconductor layer 230a contains zinc is preferably adopted. For example, when the semiconductor layer 230a is formed by the ALD method and the semiconductor layer 230b is formed by the sputtering method, sometimes the zinc contained in the semiconductor layer 230a diffuses into the semiconductor layer 230b. Note that this diffusion is caused by heat treatment during or after sputtering. When zinc diffuses from the semiconductor layer 230a into the semiconductor layer 230b, an improvement in crystallinity is expected. In addition, when zinc diffuses from the semiconductor layer 230a into the semiconductor layer 230b, it is expected that the crystal part with c-axis orientation grows laterally to promote CAAC formation.

[0514] In addition, the semiconductor layers 230a and 230c can be said to be metal oxides with a higher proportion of In compared to the semiconductor layer 230b.

[0515] In addition, for example, as the semiconductor layers 230a and 230c, metal oxides with a higher Ga ratio than that of the semiconductor layer 230b can also be used. For example, the semiconductor layers 230a and 230c preferably use metal oxides having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof, metal oxides having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or a composition in the vicinity thereof, or metal oxides having a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or a composition in the vicinity thereof. By increasing the ratio of Ga, for example, the band gaps of the semiconductor layers 230a and 230c can sometimes be made larger than that of the semiconductor layer 230b. As a result, the semiconductor layer 230b is sandwiched by the semiconductor layers 230a and 230c with larger band gaps, and the semiconductor layer 230b is mainly used as a current path (channel). When the semiconductor layer 230b is sandwiched by the semiconductor layers 230a and 230c, trap levels at the interface of the semiconductor layer 230b and in its vicinity can be reduced. As a result, an embedded channel type transistor with a channel far from the insulator interface can be realized, and thus the field effect mobility can be improved.

[0516] In addition, in the oxide semiconductor layer of one embodiment of the present invention, even if the compositions of the semiconductor layers 230a and 230c are such that it is difficult to form a CAAC structure when formed as a single layer, by crystal growth with the semiconductor layer 230b as a nucleus, a structure in which the entire oxide semiconductor layer including the semiconductor layers 230a and 230c has a CAAC structure can be realized. Alternatively, a region including at least a part of each of the semiconductor layers 230a and 230c and the region of the semiconductor layer 230b can have a CAAC structure.

[0517] In particular, crystallinity suitable for a semiconductor layer used as a transistor can also be achieved in a composition with a high In ratio in the semiconductor layers 230a and 230c. In the oxide semiconductor layer of one embodiment of the present invention, the following effects can be achieved simultaneously: the on-state characteristics of the transistor are improved by increasing the In ratio; the reliability is improved by adopting a highly crystalline CAAC structure.

[0518] Note that the composition of the semiconductor layer 230a can also be different from that of the semiconductor layer 230c.

[0519] In addition, the semiconductor layers 230a and 230c can use metal oxides having the same composition as the semiconductor layer 230b.

[0520] By using the oxide semiconductor layer having a CAAC structure formed by the above two deposition methods in the channel formation region of a transistor, a transistor having excellent characteristics (for example, a transistor having a large on-state current, a transistor having a high field-effect mobility, a transistor having a small S value, a transistor having a high frequency characteristic (also referred to as an f characteristic), a transistor having high reliability, etc.) can be realized.

[0521] When analyzing the composition of the metal oxide used for the semiconductor layer 230, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple of the above methods can be combined for analysis. Note that due to the influence of analysis accuracy, the actual content rate of an element with a sometimes low content rate may be different from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis may sometimes be lower than the actual content rate.

[0522] [c-axis orientation ratio]

[0523] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The degree of crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0524] The crystal orientation can be known using an FFT pattern obtained by performing a fast Fourier transform (FFT) process on a TEM image. Specifically, the FFT pattern is used to obtain the direction of the crystal axis. The FFT pattern obtained by the FFT process reflects the same reciprocal lattice space information as the electron beam diffraction pattern.

[0525] By performing FFT processing on each region of the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area range, a graph showing the crystal orientation can be formed. Specifically, two spots with high intensity are confirmed in the FFT pattern of the region having a layered crystal part. The direction of the crystal axis of this region can be known from the angle of the line segment connecting the two spots.

[0526] By calculating the ratio of the region oriented along the c-axis in the graph showing the crystal orientation, the c-axis orientation ratio can be calculated. Note that here, the region oriented along the c-axis refers to the region whose orientation is the same as the c-axis and the region whose difference from the c-axis is within 20°.

[0527] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation on the cross-section or plane of the oxide semiconductor layer. In addition, the region where FFT is performed (also referred to as the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0528] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio is 60% or more, preferably 70% or more, more preferably 80% or more, still more preferably 90% or more, and further preferably 95% or more.

[0529] In addition, the c-axis orientation ratios of the region where the semiconductor layer 230a is deposited, the region where the semiconductor layer 230b is deposited, and the region where the semiconductor layer 230c is deposited can be Rc1, Rc2, and Rc3, respectively. Both Rc2 and Rc3 are 60% or more, preferably 70% or more, more preferably 80% or more, still more preferably 90% or more, and further preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. In addition, Rc2 / Rc1 is preferably greater than 1.

[0530] Note that in the semiconductor layer 230, the boundaries of the semiconductor layers 230a, 230b, and 230c may not be clearly observable after manufacturing.

[0531] The semiconductor layer 230 of one embodiment of the present invention can be sequentially divided into three regions, a first region, a second region, and a third region, from the layer 229. Each region is a layered region.

[0532] The first region, the second region, and the third region all have a CAAC structure. In addition, the c-axis orientation ratio of the third region is preferably higher than the c-axis orientation ratio of the first region. In addition, the c-axis orientation ratio of the second region is preferably higher than the c-axis orientation ratio of the first region. In addition, the c-axis orientation ratios of the second region and the third region are 80% or more, more preferably 90% or more, and further preferably 95% or more.

[0533] The first region is located in the range of 0 nm or more and 3 nm or less from the top surface of the layer 229, and the third region is located in the range of 0 nm or more and 3 nm or less from the top surface of the semiconductor layer 230.

[0534] Alternatively, the thicknesses of the layers in each region are, for example, substantially the same.

[0535] The structure shown in this embodiment can be implemented in appropriate combination with the structures shown in other embodiments.

[0536] Embodiment 5

[0537] In this embodiment, it will be described Figure 23AAn example of the planar layout and an example of the cross-sectional structure of the semiconductor device 10A shown.

[0538] In the present embodiment, a case will be described in which the transistors 200A shown in Embodiment 3 (refer to Figures 29A to 29C ) are used as the transistors Tr1 to Tr6, and the transistor 200B (refer to Figures 30A to 30C ) is used as the transistor TrD. In addition, in order to avoid redundant description, mainly matters not shown in other embodiments will be described. To understand the matters not shown in the present embodiment, other embodiments can be referred to.

[0539] Figure 42 is a diagram showing Figure 23A an example of the planar layout of the semiconductor device 10A shown. Figure 43A is a diagram enlarging a portion including Figure 42 the transistors Tr1, TrD, the capacitor elements Cs1, and the capacitor element Cs2. Figure 43B is a diagram enlarging a portion including the connection portion of the conductive layer 252 and the conductive layer 289. Figure 44 is a cross-sectional view along the Figure 42 dotted line A1 - A2 in Figure 45 is a cross-sectional view along the Figure 43A dotted line A3 - A4 in

[0540] The semiconductor device 10A shown in the present embodiment includes a conductive layer 299 on the substrate 201.

[0541] On the insulating layer 204, it includes conductive layers 271[1], 271[2], 272[1], 272[2], 273[1], 273[2], 274[1], 274[2], 275[1], 275[2], 276[1], 276[2], 283, 284, 285, 286, 287, 288, 289, 246, 247, 293, and 243.

[0542] The conductive layers 271[1], 271[2], 272[1], 272[2], 273[1], 273[2], 274[1], 274[2], 275[1], 275[2], 276[1], 276[2], 283, 284, 285, 286, 287, 288, 289, 246, 247, 293 and 243 can be formed simultaneously using the same material and the same process.

[0543] In addition, on the insulating layer 206, there are included conductive layers 211[1], 211[2], 211[3], 212[1], 212[2], 212[3], 213[1], 213[2], 213[3], 214[1], 214[2], 214[3], 215[1], 215[2], 215[3], 216[1], 216[2], 216[3], 217, 218, 219, 221, 222, 223, 224, 251, 252, 227, 228, 281, 282 and 244.

[0544] The conductive layers 211[1], 211[2], 211[3], 212[1], 212[2], 212[3], 213[1], 213[2], 213[3], 214[1], 214[2], 214[3], 215[1], 215[2], 215[3], 216[1], 216[2], 216[3], 217, 218, 219, 221, 222, 223, 224, 251, 252, 227, 228, 281, 282 and 244 can be formed simultaneously using the same material and the same process.

[0545] The conductive layer 211[1] is connected to the conductive layer 211[2] through the conductive layer 271[1]. Specifically, in the region overlapping with the conductive layer 271[1], there are openings 225 and 226 provided in a part of the insulating layer 206. In the region overlapping with the opening 225, the conductive layer 211[1] is in contact with the conductive layer 271[1], and in the region overlapping with the opening 226, the conductive layer 211[2] is in contact with the conductive layer 271[1] (refer to Figure 42 and Figure 44 ).

[0546] In addition, a plurality of openings 225 connecting the conductive layer 211[1] and the conductive layer 271[1] can be provided. By providing a plurality of openings 225, the contact resistance between the conductive layer 211[1] and the conductive layer 271[1] can be reduced. Similarly, a plurality of openings 226 connecting the conductive layer 211[2] and the conductive layer 271[1] can be provided. By providing a plurality of openings 226, the contact resistance between the conductive layer 211[2] and the conductive layer 271[1] can be reduced.

[0547] The conductive layer 211[2] is connected to the conductive layer 211[3] through the conductive layer 271[2]. The conductive layer 211[1], the conductive layer 271[1], the conductive layer 211[2], the conductive layer 271[2], and the conductive layer 211[3] are used as the wiring GL1. In Figure 42 , the wiring GL1 extends in the X direction.

[0548] The conductive layer 212[1] is connected to the conductive layer 212[2] through the conductive layer 272[1], and the conductive layer 212[2] is connected to the conductive layer 213[3] through the conductive layer 272[2]. The conductive layer 212[1], the conductive layer 272[1], the conductive layer 212[2], the conductive layer 272[2], and the conductive layer 212[3] are used as the wiring GL2. In Figure 42 , the wiring GL2 extends in the X direction.

[0549] The conductive layer 213[1] is connected to the conductive layer 213[2] through the conductive layer 273[1], and the conductive layer 213[2] is connected to the conductive layer 213[3] through the conductive layer 273[2]. The conductive layer 213[1], the conductive layer 273[1], the conductive layer 213[2], the conductive layer 273[2], and the conductive layer 213[3] are used as the wiring GL3. In Figure 42 , the wiring GL3 extends in the X direction.

[0550] The conductive layer 214[1] is connected to the conductive layer 214[2] through the conductive layer 274[1], and the conductive layer 214[2] is connected to the conductive layer 214[3] through the conductive layer 274[2]. The conductive layer 214[1], the conductive layer 274[1], the conductive layer 214[2], the conductive layer 274[2], and the conductive layer 214[3] are used as the wiring GL4. In Figure 42 the wiring GL4 extends in the X direction.

[0551] The conductive layer 215[1] is connected to the conductive layer 215[2] through the conductive layer 275[1], and the conductive layer 215[2] is connected to the conductive layer 215[3] through the conductive layer 275[2]. The conductive layer 215[1], the conductive layer 275[1], the conductive layer 215[2], the conductive layer 275[2], and the conductive layer 215[3] are used as the wiring GL5. In Figure 42 the wiring GL5 extends in the X direction.

[0552] The conductive layer 216[1] is connected to the conductive layer 216[2] through the conductive layer 276[1], and the conductive layer 216[2] is connected to the conductive layer 216[3] through the conductive layer 276[2]. The conductive layer 216[1], the conductive layer 276[1], the conductive layer 216[2], the conductive layer 276[2], and the conductive layer 216[3] are used as the wiring GL6. In Figure 42 the wiring GL6 extends in the X direction.

[0553] The conductive layer 252 is used as the wiring Pw1. The conductive layer 227 is used as the wiring DL. The conductive layer 228 is used as the wiring Vref3. The conductive layer 281 is used as the wiring Vref1. The conductive layer 282 is used as the wiring Vref2. In Figure 42 the conductive layer 252, the conductive layer 227, the conductive layer 228, the conductive layer 281, and the conductive layer 282 extend in the Y direction.

[0554] The conductive layer 217 is connected to the conductive layer 252 through the conductive layer 287. In addition, a part of the conductive layer 217 is used as one of the source electrode and the drain electrode of the transistor Tr1. The conductive layer 283 is connected to the conductive layer 211[2]. A part of the conductive layer 283 is used as the gate electrode of the transistor Tr1.

[0555] A part of the conductive layer 218 is used as the other of the source electrode and the drain electrode of the transistor Tr1. In addition, another part of the conductive layer 218 is used as one of the source electrode and the drain electrode of the transistor TrD. In addition, still another part of the conductive layer 218 is used as one of the source electrode and the drain electrode of the transistor Tr2.

[0556] Conductive layer 284 is connected to conductive layer 212[2]. A portion of conductive layer 284 is used as the gate electrode of transistor Tr2. A portion of conductive layer 222 is used as the other of the source electrode and the drain electrode of transistor Tr2. In addition, another portion of conductive layer 222 is used as one of the source electrode and the drain electrode of transistor Tr6. In addition, conductive layer 222 is connected to conductive layer 299. In addition, a portion of conductive layer 281 is used as the other of the source electrode and the drain electrode of transistor Tr6. In addition, conductive layer 285 is connected to conductive layer 213[2]. A portion of conductive layer 285 is used as the gate electrode of transistor Tr6.

[0557] Conductive layer 219 is connected to conductive layer 227 through conductive layer 288. In addition, a portion of conductive layer 219 is used as one of the source electrode and the drain electrode of transistor Tr4. Conductive layer 286 is connected to conductive layer 214[2]. A portion of conductive layer 286 is used as the gate electrode of transistor Tr4. In addition, a portion of conductive layer 221 is used as one of the source electrode and the drain electrode of transistor Tr4. In addition, another portion of conductive layer 221 is used as one of the source electrode and the drain electrode of transistor Tr5. In addition, conductive layer 221 is connected to conductive layer 293.

[0558] In addition, a portion of the conductive layer 275[1] is used as a gate electrode of the transistor Tr5. The conductive layer 223 is connected to the conductive layer 252 through the conductive layer 289. A portion of the conductive layer 224 is used as the other of the source electrode and the drain electrode of the transistor TrD. A portion of the conductive layer 293 is used as a gate electrode of the transistor TrD, and a portion of the conductive layer 299 is used as a back gate electrode of the transistor TrD. The conductive layer 224 is connected to the conductive layer 243.

[0559] Conductive layer 244 is connected to conductive layer 243. A portion of conductive layer 244 is used as one of the source electrode and the drain electrode of transistor Tr3. Conductive layer 251 is connected to conductive layer 282 through conductive layer 246. A portion of conductive layer 251 is used as the other of the source electrode and the drain electrode of transistor Tr3. Conductive layer 247 is connected to conductive layer 216[2]. A portion of conductive layer 247 is used as the gate electrode of transistor Tr3.

[0560] Conductive layer 293 and conductive layer 224 have a region where they overlap with each other via insulating layer 206. This region serves as capacitor Cs1. The capacitance of capacitor Cs1 can be set according to the area of the region where conductive layer 293 and conductive layer 224 overlap with each other and the relative dielectric constant and thickness of insulating layer 206.

[0561] The conductive layer 299 and the conductive layer 243 have regions overlapping each other with the insulating layer 202 and the insulating layer 204 therebetween. This region is used as the capacitor element Cs2. The capacitance of the capacitor element Cs2 can be set according to the area of the region where the conductive layer 299 and the conductive layer 243 overlap each other, the relative dielectric constants and thicknesses of the insulating layer 202 and the insulating layer 204.

[0562] The conductive layer 218 is used as the node Na. In addition, the conductive layers 224, 243 and 244 are used as the node Nb. Further, the conductive layers 221 and 293 are used as the node Nc. Additionally, the conductive layers 222 and 299 are used as the node Nd.

[0563] Note that in this specification, the semiconductor layer 203 of the transistor Tr1 is denoted as the semiconductor layer 203[1] (refer to Figure 43A and Figure 45 ). Further, in a plan view, one of the openings 207 overlapping with the semiconductor layer 203[1] is denoted as the opening 207a[1], and the other of the openings 207 overlapping with the semiconductor layer 203[1] is denoted as the opening 207b[1].

[0564] In addition, in this specification, the semiconductor layer 203 of the transistor TrD is denoted as the semiconductor layer 203[D]. Further, in a plan view, one of the openings 207 overlapping with the semiconductor layer 203[D] is denoted as the opening 207a[D], and the other of the openings 207 overlapping with the semiconductor layer 203[D] is denoted as the opening 207b[D].

[0565] In addition, in this embodiment, a structure is shown in which above the insulating layer 209, there is an insulating layer 248 having a flat top surface. The insulating layer 248 is preferably an insulating layer containing an organic material. For example, as the insulating layer 248, acrylic resin, polyimide, polyamide, polyimide amide, epoxy resin, silicone resin, benzocyclobutene resin, phenolic resin or a precursor of the above resins can be used. In addition, the insulating layer 248 can also be formed of an inorganic material, and a CMP process is performed on the top surface of the insulating layer 248. By reducing the unevenness of the top surface of the insulating layer 248, the coverage of the insulating layer and the conductive layer formed later can be improved.

[0566] In the semiconductor device 10A, Figure 43AThe width Wg of the conductive layer 214[2] serving as the wiring GL1 (the length of the conductive layer 214[2] in the Y direction, the length in the direction orthogonal to the extending direction of the conductive layer 214[2]) is preferably greater than the channel length Ls of the transistor connected to the wiring GL1. More specifically, in the semiconductor device 10A, the minimum value of the width Wg is preferably greater than the maximum value of the channel length Ls. Thereby, the signal delay that occurs when supplying signals to the plurality of transistors connected to the wiring GL1 can be reduced. In addition, the same applies to the wirings GL2 to GL6 as to the wiring GL1. Additionally, Figure 43A shows the width Wg of the conductive layer 214[2].

[0567] In the semiconductor device 10A, Figure 43B the width Wp of the conductive layer 252 serving as the wiring Pw1 (the length of the conductive layer 252 in the X direction, the length in the direction orthogonal to the extending direction of the conductive layer 252) is preferably greater than the width Wr of the conductive layer 289 that is connected to the conductive layer 252 and serves as the lead wiring of the semiconductor device 10A (refer to Figure 43B ). More specifically, in the semiconductor device 10A, the minimum value of the width Wp is preferably greater than the maximum value of the width Wr. Thereby, the reduction in the power supply capacity of the conductive layer serving as the power supply line can be reduced, and thus the semiconductor device 10A can operate stably. Therefore, the reliability of the semiconductor device 10A can be improved. In addition, the relationships between the wirings Pw2, DL, Vref1, Vref2, Vref3, and GL1 to GL6 and the conductive layers connected to them can be considered in the same manner.

[0568] As described above, by making the channel lengths of the transistors Tr1 to Tr6 shorter than the channel length of the transistor TrD serving as the driving transistor, the operating speed of the semiconductor device 10A and the reproducibility of the emission luminance of the light-emitting element 61 with respect to the video signal can be improved. For example, it is preferable that the channel length Ls of the transistor Tr1 is shorter than the channel length Ld of the transistor TrD (refer to Figure 43A ).

[0569] The structure shown in this embodiment can be implemented by appropriately combining with the structures shown in other embodiments.

[0570] Embodiment 6

[0571] The semiconductor device according to one aspect of the present invention can be used in a display device or the like. In addition, the semiconductor device according to one aspect of the present invention can be used in a module including the display device (also referred to as a "display module") or the like. In this embodiment, a display device including the semiconductor device according to one aspect of the present invention will be described.

[0572] As a display module, examples include a module in which a flexible printed circuit (FPC) or a connector such as a TCP (Tape Carrier Package) is installed in the display device, a module in which an integrated circuit (IC) is installed by a COG (Chip On Glass) method, a COF (Chip On Film) method, etc.

[0573] <Structural example of a display device>

[0574] Figure 46A FIG. 7 is a perspective view showing a structural example of a display device 400 according to one embodiment of the present invention.

[0575] The display device 400 has a structure in which a substrate 411 and a substrate 451 are bonded. In Figure 46A FIG. 10, the substrate 411 is shown by a dashed line.

[0576] The display device 400 includes a display unit 452, a circuit unit 454a, a circuit unit 454b, a connection unit 457, a wiring unit 458, etc. Figure 46A FIG. 17 shows an example in which an IC 456 and an FPC 459 are installed in the display device 400. Therefore, the Figure 46A structure shown in FIG. 19 can also be referred to as a display module including the display device 400, an IC, and an FPC.

[0577] The circuit unit 454a includes, for example, a scan line driving circuit (also referred to as a gate driver or a scan driver). In addition, the circuit unit 454b includes, for example, a signal line driving circuit (also referred to as a source driver or a data driver).

[0578] The wiring unit 458 has a function of supplying signals and power to the display unit 452, the circuit unit 454a, and the circuit unit 454b. The signals and power are input to the wiring unit 458 from the outside of the display device 400 via the FPC 459 or from the IC 456 to the wiring unit 458.

[0579] Figure 46A FIG. 29 shows an example in which an IC 456 is provided on the substrate 451 by a COG method, a COF method, etc. As the IC 456, for example, an IC including one or both of a scan line driving circuit and a signal line driving circuit can be used. Note that the display device 400 and the display module do not necessarily have to be provided with an IC. In addition, the IC 456 can also be mounted on the FPC by a COF method or the like.

[0580] In addition, the scan line driving circuit can be constituted by one or both of IC456 and the circuit section 454a. In this case, IC456 is sometimes referred to as a gate driver IC. In addition, the signal line driving circuit can be constituted by one or both of IC456 and the circuit section 454b. In this case, IC456 is sometimes referred to as a source driver IC.

[0581] The display section 452 is an image display area in the display device 400 and includes a plurality of pixels 455 arranged periodically. Figure 46A An enlarged view of one pixel 455 is shown.

[0582] Figure 46A The pixel 455 shown includes a pixel 453R that emits red (R) light, a pixel 453G that emits green (G) light, and a pixel 453B that emits blue (B) light. By constituting one pixel 455 with the pixel 453R, the pixel 453G, and the pixel 453B, full-color display can be achieved. The pixel 453R, the pixel 453G, and the pixel 453B are all used as sub-pixels. In Figure 46A In the display device 400 shown, an example is shown in which the pixels 453R, 453B, and 453G used as sub-pixels are arranged in a stripe pattern. Note that the number of sub-pixels constituting one pixel 455 is not limited to three and can be four or more. For example, it can include four sub-pixels that emit light of R, G, B, and white (W) respectively. Or, it can include four sub-pixels that emit light of R, G, B, and yellow (Y) respectively.

[0583] Note that in this specification, sometimes an identification symbol "R" is attached to the elements related to red light, an identification symbol "G" is attached to the elements related to green light, and an identification symbol "B" is attached to the elements related to blue light to explain each content separately. In addition, sometimes these identification symbols are not attached to explain the common content among them. For example, when it is necessary to distinguish multiple pixels 453, they are sometimes shown as pixel 453R, pixel 453G, or pixel 453B. In addition, for example, when it is not necessary to distinguish the pixel 453R, the pixel 453G, and the pixel 453B, they are sometimes simply shown as pixel 453.

[0584] The pixel 453R, the pixel 453G, and the pixel 453B all include a light-emitting element and a circuit that controls the driving of the light-emitting element. As the pixel 453, the semiconductor device 10 (semiconductor devices 10A to 10M) of one aspect of the present invention can be used.

[0585] The connection section 457 is provided outside the display section 452. The connection section 457 can be provided along one or more sides of the display section 452. The connection section 457 can also be one or more. Figure 46AAn example in which the connection portion 457 is provided so as to surround the four sides of the display portion is shown. In the connection portion 457, the common electrode of the display element is connected to the wiring portion 458, and a potential can be supplied to the common electrode.

[0586] Here, for example, the transistors shown in the above-described embodiment can be used for at least a part of the display portion 452, the circuit portion 454a, and the circuit portion 454b included in the display device 400.

[0587] For example, by using the vertical transistors such as the transistor 200C as one or both of the circuit portion 454a and the circuit portion 454b, the occupied area of the circuit portion 454a and the circuit portion 454b can be reduced, and thus a narrow-bezel display device can be realized.

[0588] In addition, for example, by using the vertical transistors such as the transistor 200C or the transistor 200D for the pixel circuit included in the display portion 452, the occupied area of the pixel circuit can be reduced, and thus the clarity of the display device can be improved. For example, a display device having a clarity of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

[0589] The display device according to one aspect of the present invention may also have a function of a touch panel. For example, various detection elements (which may also be referred to as sensor elements) capable of detecting the approach or contact of a detection object such as a finger can also be used for the display device.

[0590] As a sensor method, for example, an electrostatic capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a piezoresistive type can be cited.

[0591] As the electrostatic capacitance type, for example, a surface type electrostatic capacitance type and a projection type electrostatic capacitance type are available. In addition, as the projection type electrostatic capacitance type, for example, a self-capacitance type and a mutual-capacitance type are available. The mutual-capacitance type is preferably used because multi-point sensing can be performed simultaneously.

[0592] As a touch panel, for example, an Out-Cell type, an On-Cell type, and an In-Cell type can be cited. Note that the In-Cell type touch panel refers to a structure in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also referred to as a display device) and a counter substrate.

[0593] [Pixel arrangement]

[0594] Figures 46B to 46F It is a plan view for explaining the pixel arrangement. In the display device according to one aspect of the present invention, the pixel arrangement is not particularly limited, and various arrangements can be adopted. As the pixel arrangement, for example, a stripe arrangement can be cited (see Figure 46B) S stripe arrangement (refer to Figure 46C ) Delta arrangement (refer to Figure 46D ) Zigzag arrangement (refer to Figure 46E ) and Pentile arrangement (refer to Figure 46F ), etc. In addition, for example, a mosaic-like arrangement, a Diamond arrangement, a Bayer arrangement, etc. can be cited.

[0595] In addition, in Figures 46B to 46F , as the top surface shape of each sub-pixel (pixel 453R, pixel 453G, and pixel 453B), for example, polygons such as triangles, quadrilaterals (including rectangles and squares), pentagons, etc., shapes in which the corners of these polygons are rounded, ellipses, circles, etc. can be cited. Here, the top surface shape of each sub-pixel corresponds to the top surface shape of the display area of the display element in each sub-pixel. The top surface shape and size of each sub-pixel can be determined independently. Note that the arrangements of pixel 453R, pixel 453G, and pixel 453B can be appropriately interchanged. In addition, the display element and the pixel circuit can have the same arrangement or different arrangements.

[0596] Here, the Pentile arrangement is a special pixel arrangement that improves sharpness in a pseudo manner. Therefore, in a display device, for example, a stripe arrangement or the like can be adopted. In one aspect of the present invention, by using vertical transistors such as the above-mentioned transistor 200C or transistor 200D as part or all of the transistors constituting the pixel circuit, the occupied area of the pixel circuit can be reduced. Therefore, as the pixel arrangement, for example, a stripe arrangement or the like can be adopted instead of the Pentile arrangement without reducing the sharpness of the display device.

[0597] [Light-emitting element]

[0598] As the light-emitting element, for example, self-luminous light-emitting elements such as LEDs, organic EL elements (also referred to as OLEDs (Organic Light-Emitting Diodes)), semiconductor lasers, etc. can be cited. As an LED, for example, Mini LED, Micro LED, etc. can be used.

[0599] As the light-emitting substance contained in the light-emitting element, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.) can be cited.

[0600] The light-emitting color of the light-emitting element can be infrared, red, green, blue, cyan, magenta, yellow, white, etc. In addition, when the light-emitting element has a microcavity structure, the color purity can be further improved.

[0601] In a pair of electrodes or a pair of terminals included in a light-emitting element, one of the electrodes or terminals is used as an anode (also referred to as an anode electrode) and the other electrode or terminal is used as a cathode (also referred to as a cathode electrode).

[0602] In the present embodiment, the case where an EL element is used as the light-emitting element will be described as an example. Therefore, the display device 400 according to one aspect of the present invention is a display device using an organic EL element.

[0603] The display device 400 according to one aspect of the present invention is suitable for any of the following structures: a top emission type that emits light in a direction opposite to the substrate on which the light-emitting element is formed, a bottom emission type that emits light toward the side of the substrate on which the light-emitting element is formed, and a dual emission type that emits light on both sides.

[0604] By using vertical transistors such as the transistor 200C or the transistor 200D described above, the occupied area of the pixel circuit can be reduced. Therefore, in particular, the aperture ratio of the pixel can be increased in a bottom emission type display device and a dual emission type display device. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0605] Note that in this specification and the like, the aperture ratio refers to the ratio of the area of the region where light is emitted to the pixel area.

[0606] <Structural example of light-emitting element>

[0607] The light-emitting element 61 that can be used in the display device according to one aspect of the present invention will be described.

[0608] As Figure 47A shown, the light-emitting element 61 includes an EL layer 172 between a conductive layer 171 and a conductive layer 173. The EL layer 172 may be composed of a plurality of layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 may include, for example, a layer containing a substance with high electron injection property (electron injection layer) and a layer containing a substance with high electron transport property (electron transport layer). The light-emitting layer 4411 contains a light-emitting compound, for example. The layer 4430 may include, for example, a layer containing a substance with high hole injection property (hole injection layer) and a layer containing a substance with high hole transport property (hole transport layer).

[0609] The structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between the conductive layer 171 and the conductive layer 173 used as electrodes can be used as a single light-emitting unit, and in this specification and the like, Figure 47A the structure is referred to as a single structure.

[0610] Figure 47B is Figure 47A a modified example of the EL layer 172 included in the light-emitting element 61 shown. Specifically, Figure 47B the light-emitting element 61 shown includes a layer 4430-1 on the conductive layer 171, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductive layer 173 on the layer 4420-2. For example, when the conductive layer 171 is an anode and the conductive layer 173 is a cathode, the layer 4430-1 is used as a hole injection layer, the layer 4430-2 is used as a hole transport layer, the layer 4420-1 is used as an electron transport layer, and the layer 4420-2 is used as an electron injection layer. Alternatively, when the conductive layer 171 and the conductive layer 173 are used as a cathode and an anode, respectively, the layer 4430-1 is used as an electron injection layer, the layer 4430-2 is used as an electron transport layer, the layer 4420-1 is used as a hole transport layer, and the layer 4420-2 is used as a hole injection layer. By adopting such a layer structure, carriers can be effectively injected into the light-emitting layer 4411, and the recombination efficiency of carriers in the light-emitting layer 4411 can be improved.

[0611] In addition, as Figure 47C shown, a structure in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between the layer 4420 and the layer 4430 is also a modified example of a single structure.

[0612] As Figure 47D shown, a structure in which a plurality of light-emitting units (EL layer 172a, EL layer 172b) are connected in series with a middle layer (charge generation layer) 4440 interposed therebetween is referred to as a series structure or a stacked structure in this specification and the like. By adopting a series structure, a light-emitting element capable of high-brightness light emission can be realized.

[0613] When the light-emitting element 61 has Figure 47D the series structure shown, it is preferable that the EL layer 172a and the EL layer 172b have the same emission color. For example, it is preferable that the emission colors of the EL layer 172a and the EL layer 172b are both green.

[0614] In addition, by using light-emitting elements 61 that emit red light (R), light-emitting elements 61 that emit green light (G), and light-emitting elements 61 that emit blue light (B) as sub-pixels and forming one pixel from these three sub-pixels, full-color display can be achieved. When one pixel includes these three sub-pixels of R, G, and B, each light-emitting element 61 preferably has a series structure. Specifically, both the EL layer 172a and the EL layer 172b of the sub-pixel of R contain materials capable of emitting red light, both the EL layer 172a and the EL layer 172b of the sub-pixel of G contain materials capable of emitting green light, and both the EL layer 172a and the EL layer 172b of the sub-pixel of B contain materials capable of emitting blue light. In other words, the light-emitting layer 4411 and the light-emitting layer 4412 can have the same material. By making the emission colors of the EL layer 172a and the EL layer 172b the same, the current density per unit emission luminance can be reduced. Therefore, the reliability of the light-emitting element 61 can be improved.

[0615] The emission color of t...

Claims

1. A semiconductor device, comprising: A first transistor including a gate and a back gate; And A light-emitting element, and the semiconductor device is configured to perform: A first operation of supplying a first potential to the back gate of the first transistor; A second operation of fixing the gate potential and the source potential of the first transistor and bringing the drain of the first transistor and the back gate into a conductive state to set the potential of the back gate to a second potential; A third operation of supplying an image signal to the gate of the first transistor; And A fourth operation of supplying a current corresponding to the image signal to the light-emitting element, Wherein the second potential is equivalent to the difference between the source potential and the gate potential of the first transistor, The frequency of performing the second operation is lower than the frequency of performing the third operation, And the frequency of performing the second operation is lower than the frequency of performing the fourth operation.

2. The semiconductor device according to claim 1, Wherein the second potential is lower than the first potential.

3. The semiconductor device according to claim 1, Wherein the first transistor is an n-type transistor.

4. The semiconductor device according to claim 1, Wherein the first transistor includes an oxide semiconductor in a semiconductor layer forming a channel.

5. The semiconductor device according to claim 1, Wherein the light-emitting element is an organic EL element.

6. A semiconductor device, comprising: A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; A first capacitor element and a second capacitor element; And A light-emitting element, Wherein the first transistor includes a gate, a back gate, a first terminal, and a second terminal, The second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the first capacitor element, the second capacitor element, and the light-emitting element all include a first terminal and a second terminal, The first terminal of the first transistor is electrically connected to the second terminal of the second transistor and the first terminal of the third transistor. The second terminal of the third transistor is electrically connected to the back gate of the first transistor, the first terminal of the seventh transistor, and the first terminal of the second capacitor element, The second terminal of the second capacitor element is electrically connected to the first terminal of the fourth transistor, the second terminal of the first transistor, the first terminal of the light-emitting element, and the second terminal of the first capacitor element, The gate of the first transistor is electrically connected to the first terminal of the first capacitor element, the second terminal of the fifth transistor, and the first terminal of the sixth transistor, The W / L of the third transistor is smaller than the W / L of the fifth transistor, The W / L of the third transistor is smaller than the W / L of the sixth transistor, The W / L of the seventh transistor is smaller than the W / L of the fifth transistor, And the W / L of the seventh transistor is smaller than the W / L of the sixth transistor.

7. The semiconductor device according to claim 6, wherein the first capacitor element is configured to maintain a potential difference between the second terminal of the first transistor and the potential of the gate of the first transistor, and the second capacitor element is configured to maintain a potential difference between the potential of the second terminal of the first transistor and the potential of the back gate of the first transistor.

8. The semiconductor device according to claim 6, wherein the first terminal of the second transistor is electrically connected to a first wiring, the first terminal of the fifth transistor is electrically connected to a second wiring, the second terminal of the sixth transistor is electrically connected to a third wiring, the second terminal of the seventh transistor is electrically connected to a fourth wiring, the second terminal of the fourth transistor is electrically connected to a fifth wiring, the second terminal of the light-emitting element is electrically connected to a sixth wiring, the first wiring is configured to supply a first potential, the second wiring is configured to supply an image signal, the third wiring is configured to supply a second potential, the fourth wiring is configured to supply a third potential, the fifth wiring is configured to supply a fourth potential, and the sixth wiring is configured to supply a fifth potential.

9. The semiconductor device according to claim 6, wherein the first transistor includes an oxide semiconductor in a semiconductor layer where a channel is formed.

10. The semiconductor device according to claim 6, wherein the light-emitting element is an organic EL element.

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