Digital waveform generation method and device, electronic equipment and storage medium

Abstract

The invention discloses a digital waveform generation method and device, electronic equipment and a storage medium, and relates to the technical field of signal processing. Sine wave amplitude data of a 1 / 4 period is only stored in a waveform memory, an interval to which a current phase belongs is judged by using a phase sequence, and a complete period waveform is generated in combination with a symmetric transformation rule; the mode that full-period waveform data needs to be stored in a traditional method is avoided, occupation of the storage space of a waveform storage is reduced, the technical problems that in a traditional digital waveform generation system, waveform storage space resources are insufficient, hardware resource consumption is large, and development complexity is high can be solved, and the method is suitable for large-scale popularization and application. The technical effect of remarkably reducing the requirement for the storage capacity of the waveform memory is achieved, the frequency control word is accurately determined according to different waveform generation requirements, and the waveform generation flexibility and accuracy are improved.

Description

Technical Field

[0001] This application relates to the field of signal processing technologies, and in particular, to a digital waveform generation method, apparatus, electronic device, and storage medium. Background Art

[0002] In the fields of electronic engineering, communication, and automatic control, high-precision digital waveform generation technology is the core foundation of systems such as telecommunications, radar, sonar, and test and measurement. Direct Digital Synthesis (DDS) technology has become the mainstream solution for waveform generation due to its advantages such as fast frequency conversion speed, continuous phase, and high resolution. A traditional DDS system realizes waveform synthesis through a phase accumulator, waveform memory, digital-to-analog converter, and low-pass filter. The key lies in that the waveform memory needs to store waveform data for a complete cycle.

[0003] In related technologies, when the amount of waveform data is large, limited by the size of the waveform memory space, other memories are usually used to expand the waveform memory. However, using the hardware expansion method will increase the consumption of hardware resources and the development complexity is relatively high. Summary of the Invention

[0004] This application provides a digital waveform generation method, apparatus, electronic device, and storage medium to at least solve the problems of increasing hardware resource consumption and relatively high development complexity in related technologies.

[0005] This application provides a digital waveform generation method, including:

[0006] When the digital waveform to be generated is a sine wave, only store the sine wave amplitude data for 1 / 4 cycle in the waveform memory;

[0007] Determine control parameters according to the generation requirements of the digital waveform to be generated; wherein, the control parameters at least include a frequency control word;

[0008] Control a phase accumulator to generate a phase sequence according to the frequency control word;

[0009] Judge the 1 / 4 cycle interval to which the current phase belongs according to the high-order bits of the phase sequence;

[0010] Select a symmetry transformation rule according to the 1 / 4 cycle interval to which the current phase belongs;

[0011] Read the sine wave amplitude data for 1 / 4 cycle from the waveform memory according to the symmetry transformation rule to generate the digital waveform to be generated for a complete cycle.

[0012] This application also provides a digital waveform generation apparatus, including:

[0013] A storage module, which is used to store only the amplitude data of a sine wave for 1 / 4 period in a waveform memory when the digital waveform to be generated is a sine wave;

[0014] A determination module, which is used to determine control parameters according to the generation requirements of the digital waveform to be generated; wherein, the control parameters at least include a frequency control word;

[0015] A control module, which is used to control a phase accumulator to generate a phase sequence according to the frequency control word;

[0016] A judgment module, which is used to judge the 1 / 4 period interval to which the current phase belongs according to the high-order bits of the phase sequence;

[0017] A selection module, which is used to select a symmetry transformation rule according to the 1 / 4 period interval to which the current phase belongs;

[0018] A generation module, which is used to read the amplitude data of the sine wave for 1 / 4 period from the waveform memory according to the symmetry transformation rule to generate the digital waveform to be generated for a complete period.

[0019] This application also provides an electronic device, including: a memory, which is used to store a computer program; a processor, which is used to implement the steps of any of the above digital waveform generation methods when executing the computer program.

[0020] This application also provides a computer-readable storage medium, in which a computer program is stored, and wherein the computer program implements the steps of any of the above digital waveform generation methods when executed by a processor.

[0021] This application also provides a computer program product, including a computer program, and the computer program implements the steps of any of the above digital waveform generation methods when executed by a processor.

[0022] Through this application, since only the amplitude data of the sine wave for 1 / 4 period is stored in the waveform memory, and the interval to which the current phase belongs is judged by using the phase sequence, and the complete period waveform is generated in combination with the symmetry transformation rule, it avoids the traditional method of storing the full-period waveform data, reduces the occupation of the storage space of the waveform memory, and can solve the technical problems of insufficient storage space resources of the waveform memory, large consumption of hardware resources, and high development complexity in the traditional digital waveform generation system, achieving the technical effect of significantly reducing the storage capacity requirement of the waveform memory. And, by accurately determining the frequency control word according to different waveform generation requirements, the flexibility and accuracy of waveform generation are improved. Description of the Drawings

[0023] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a schematic diagram of the processing flow of DDS technology;

[0025] Figure 2 It is a schematic diagram of the structure of the digital waveform generation system based on the embodiments of the present application;

[0026] Figure 3 It is a schematic diagram of the flow of the digital waveform generation method provided by the embodiments of the present application;

[0027] Figure 4 It is a schematic diagram of the structure of an exemplary digital waveform generation system provided by the embodiments of the present application;

[0028] Figure 5 It is a schematic diagram of the application flow of the digital waveform generation system provided by the embodiments of the present application;

[0029] Figure 6 It is a schematic diagram of the structure of the digital waveform generation device provided by the embodiments of the present application;

[0030] Figure 7 It is a schematic diagram of the structure of the electronic device provided by the embodiments of the present application. Detailed implementation manners

[0031] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0032] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0033] The DDS technology has the advantages of short frequency conversion time, continuous phase, high precision, etc., and is very suitable for waveform generation fields such as signal testing, sonar, and radar. The principle of the DDS technology is to first collect the amplitude values of the continuous signal within one period, store the amplitude data in the waveform memory (Read-Only Memory, abbreviated as: ROM), and obtain the waveform of the required frequency by changing the read address of the ROM. Then, the obtained digital waveform is converted into an analog signal through digital-to-analog conversion, and finally, it is output through a low-pass filter. The DDS technology mainly includes a phase accumulator, a ROM look-up table, a DAC digital-to-analog converter, and a low-pass filter according to its functions, and its processing flow is as Figure 1 shown, Figure 1 which is a schematic diagram of the processing flow of the DDS technology, Figure 1 and each module works under the control of the clock. When generating a digital waveform, after each valid edge of the clock arrives, the DDS reads the frequency control word and assigns it to the phase accumulator; the ROM look-up table (waveform memory) stores the waveform amplitude values corresponding to each phase of the waveform within one period; the output value of the phase accumulator is input as the read address of the ROM look-up table. As the clock gradually increases, the phase accumulator keeps accumulating and can output the digital waveform of the required signal.

[0034] In order to enable those skilled in the art to better understand the solution of this application, the following will further elaborate on this application in combination with the accompanying drawings and specific implementation manners.

[0035] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the digital waveform generation method depends, the specific application environment architecture or specific hardware architecture will be described here.

[0036] First, the structure of the digital waveform generation system based on this application will be described:

[0037] The digital waveform generation method, device, electronic device, and storage medium provided by the embodiments of this application are applicable to the generation of sine waveforms using the DDS technology. As Figure 2 shown, it is a schematic diagram of the structure of the digital waveform generation system based on the embodiments of this application, mainly including a data acquisition device, a waveform memory, and a digital waveform generation device. The data acquisition device is used to collect the amplitude data (waveform data) of the digital waveform to be generated and send the collected amplitude data to the digital waveform generation device. When the digital waveform generation device determines that the digital waveform to be generated is a sine wave, it stores only 1 / 4 cycle of the sine wave amplitude data in the waveform memory for subsequent generation of the digital waveform to be generated.

[0038] An embodiment of the present application provides a digital waveform generation method for generating a sine waveform using DDS technology. The execution subject of the embodiment of the present application is an electronic device, such as a server, a desktop computer, a laptop computer, a tablet computer, and other electronic devices that can be used to generate a sine waveform using DDS technology.

[0039] As Figure 3 shown, it is a schematic flowchart of the digital waveform generation method provided by the embodiment of the present application. The method includes:

[0040] Step 301, when the digital waveform to be generated is a sine wave, only store the amplitude data of the sine wave for 1 / 4 cycle in the waveform memory.

[0041] It should be noted that in the embodiment of the present application, only the amplitude data of the sine wave for 1 / 4 cycle is stored in the waveform memory, which is the amplitude data of the first 1 / 4 cycle of the sine wave, that is, the amplitude data in the interval of 0 to π / 2 of the sine waveform. Among them, the sine wave has symmetry, and the waveform of one complete cycle can be obtained from the waveform data of 1 / 4 cycle.

[0042] Specifically, after obtaining the amplitude data of the sine wave for the first 1 / 4 cycle (interval of 0 to π / 2), the amplitude data of the sine wave corresponding to different phases in this interval is quantized, converted into digital quantities, and then stored in the waveform memory (ROM). In this way, compared with storing the amplitude data of the complete cycle of the sine wave, about 75% of the storage space can be saved.

[0043] Step 302, determine the control parameters according to the generation requirements of the digital waveform to be generated.

[0044] Among them, the control parameters at least include a frequency control word.

[0045] Specifically, the generation requirements of the digital waveform to be generated are provided by the host computer. In practical applications, the control parameters can also be directly provided by the host computer.

[0046] Among them, the frequency control word determines the frequency of the output waveform. In DDS technology, the frequency of the output waveform is directly proportional to the frequency control word. The larger the frequency control word, the faster the phase growth rate of the phase accumulator, and the higher the frequency of the output waveform; conversely, the smaller the frequency control word, the lower the frequency of the output waveform.

[0047] Step 303, control the phase accumulator to generate a phase sequence according to the frequency control word.

[0048] It should be noted that the basic principle of the phase accumulator is to add the frequency control word M to the current phase value in each clock cycle to achieve a gradual increase in phase per cycle. Since the number of bits of the phase accumulator is limited, when the accumulated value exceeds its maximum representation range, an overflow will occur, thus forming a periodic phase change.

[0049] Specifically, in one embodiment, the frequency control word can be accumulated to the current phase value of the phase accumulator in each clock cycle, so that the phase accumulator generates a phase sequence according to the current phase value in each clock cycle.

[0050] Wherein, the phase sequence includes the read address of the sine wave amplitude data in the waveform memory, and each clock cycle represents a fixed time interval.

[0051] It should be noted that in DDS technology, to generate digital waveforms such as sine waves with specific frequencies, a series of continuous phase values need to be generated by using a phase accumulator, and the sequence formed by these phase values is the phase sequence. Each value of this phase sequence will be used as the read address (the read address of the sine wave amplitude data) to read the corresponding sine wave amplitude data from the waveform memory, thereby generating a complete digital waveform.

[0052] Specifically, as the clock cycle progresses, the phase accumulator continuously performs an accumulation operation, thereby obtaining a series of continuous phase values. These phase values are arranged in chronological order to form a phase sequence. Since the number of bits N of the phase accumulator is limited, when the accumulated value exceeds its maximum representation range, an overflow will occur and the counting will start from the initial bit again, so that the phase sequence shows a periodic change corresponding to the period of the output waveform.

[0053] Step 304: Determine the 1 / 4 cycle interval to which the current phase belongs according to the high-order bits of the phase sequence.

[0054] Specifically, the phase value generated by the phase accumulator is a binary number, and its high-order bits can reflect the position of the current phase in a complete cycle of the sine wave. Among them, assuming that the phase accumulator is N bits, the high 2 bits are taken. If the high 2 bits are "00", it means that the 1 / 4 cycle interval to which the current phase belongs is the first interval (0 to π / 2); if it is "01", it is the second interval (π / 2 to π); if it is "10", it is the third interval (π to 3π / 2); if it is "11", it is the fourth interval (3π / 2 to 2π).

[0055] Step 305: Select a symmetry transformation rule according to the 1 / 4 cycle interval to which the current phase belongs.

[0056] It should be noted that since only the sine wave amplitude data of 1 / 4 cycle is stored in the waveform memory, it is necessary to select the corresponding symmetry transformation rule according to the 1 / 4 cycle interval to which the current phase belongs, so that the amplitude data actually read from the waveform memory matches the 1 / 4 cycle interval to which its current phase belongs.

[0057] Step 306: Read the sine wave amplitude data for a 1 / 4 cycle from the waveform memory according to the symmetry transformation rule to generate the digital waveform to be generated for a complete cycle.

[0058] It should be noted that through the previous steps, the 1 / 4 cycle interval to which the current phase belongs and the corresponding symmetry transformation rule are determined. By processing the 1 / 4 cycle sine wave amplitude data stored in the waveform memory using these rules, the sine wave amplitude data for a complete cycle can be obtained, thereby generating the digital waveform to be generated for a complete cycle.

[0059] Specifically, according to the symmetry transformation rule selected in step 305, read the amplitude data from the waveform memory, arrange the read amplitude data in chronological order to obtain the digital waveform of the sine wave for a complete cycle, convert the digital waveform into an analog waveform through a digital-to-analog converter (DAC), and then perform filtering processing through a low-pass filter to obtain a smooth analog sine wave output.

[0060] Based on the above embodiments, as an implementable manner, in one embodiment, according to the generation requirements of the digital waveform to be generated, determine the control parameters, including:

[0061] Step 3021: When the digital waveform to be generated is a single-frequency digital waveform, determine the frequency control word based on the following formula:

[0062]

[0063] where M represents the frequency control word, N represents the number of bits of the phase accumulator, f 0ut represents the desired output frequency, f clk represents the clock frequency, and the generation requirements of the digital waveform to be generated include the number of bits of the phase accumulator, the desired output frequency, and the clock frequency.

[0064] It should be noted that the number of bits of the phase accumulator determines the quantization accuracy and representation range of the phase. The larger N is, the higher the phase resolution is, and the higher the frequency accuracy that can be generated is; the desired output frequency is the frequency of the single-frequency digital waveform that the user expects to generate; the clock frequency is the clock signal frequency, which is used to provide a time reference for the entire digital waveform generation system.

[0065] Specifically, by calculating the frequency control word through the above formula, the phase growth rate of the phase accumulator can be accurately controlled according to the desired output frequency set by the user, thereby realizing the accurate control of the frequency of the output single-frequency digital waveform.

[0066] Correspondingly, in one embodiment, when the digital waveform to be generated is a linear frequency modulation digital waveform, determine the frequency control word based on the following formula:

[0067]

[0068] Among them, M represents the frequency control word, N represents the number of bits of the phase accumulator, and f out represents the desired output frequency, f clk represents the clock frequency, u represents the adjustment step size of the frequency control word, B represents the signal bandwidth, T represents the signal pulse width, and the generation requirements for the digital waveform to be generated include the number of bits of the phase accumulator, the desired output frequency, the clock frequency, the signal bandwidth, and the signal pulse width.

[0069] It should be noted that the adjustment step size of the frequency control word is used to dynamically adjust the frequency control word to achieve the effect of linear frequency modulation; the signal bandwidth represents the frequency change range of the linear frequency modulation signal, that is, the difference between the starting frequency and the ending frequency; the signal pulse width represents the duration of the linear frequency modulation signal. A linear frequency modulation signal (linear frequency modulation digital waveform) means that the signal frequency changes linearly with time. Similar to the method of generating a single-frequency signal (single-frequency digital waveform), the frequency control word is fixed within one transmission period of the single-frequency signal, and the linear frequency modulation signal achieves linear frequency change by changing the frequency control word.

[0070] Specifically, as time goes by, due to the existence of the adjustment step size of the frequency control word, the frequency control word will change continuously, so that the frequency of the output waveform changes linearly. By introducing the adjustment step size of the frequency control word in the embodiments of the present application, the frequency control word can be dynamically adjusted, so that the frequency of the output waveform changes linearly with time, thereby realizing the generation of a linear frequency modulation digital waveform, meeting the requirements for linear frequency modulation signals in fields such as radar and communication, and improving the flexibility of the digital waveform generation method provided by the embodiments of the present application.

[0071] Based on the above embodiments, as an implementable manner, in one embodiment, according to the 1 / 4 cycle interval to which the current phase belongs, a symmetric transformation rule is selected, including:

[0072] Step 3051, when the 1 / 4 cycle interval to which the current phase belongs is the first interval, select the direct reading rule;

[0073] Step 3052, when the 1 / 4 cycle interval to which the current phase belongs is the second interval, select the mirror reading rule;

[0074] Step 3053, when the 1 / 4 cycle interval to which the current phase belongs is the third interval, select the rule of taking the inverse after direct reading;

[0075] Step 3054, when the 1 / 4 cycle interval to which the current phase belongs is the fourth interval, select the rule of taking the inverse after mirror reading.

[0076] Among them, the symmetry transformation rules include the direct reading rule, the mirror reading rule, the rule of taking the inverse after direct reading, and the rule of taking the inverse after mirror reading. The first interval is the 0 to π / 2 interval of the sine period, the second interval is the π / 2 to π interval of the sine period, the third interval is the π to 3π / 2 interval of the sine period, and the fourth interval is the 3π / 2 to 2π interval of the sine period.

[0077] Specifically, in the embodiment of the present application, according to the high 2 bits (P[N-1:N-2]) of the phase accumulator, different rules are used to read and calculate the current waveform value from the waveform memory:

[0078] (1) 0 to π / 2 interval of the sine period (P[N-1:N-2] = 00):

[0079] out = ROM[P[N-3:0]] + 2 n -1

[0080] That is, the direct reading rule is adopted to directly read the amplitude data at the corresponding address in the waveform memory (ROM).

[0081] (2) π / 2 to π interval of the sine period (P[N-1:N-2] = 01):

[0082] out = ROM[2 N-2 -1 - P[N-3:0]] + 2 n -1

[0083] That is, the mirror reading rule is adopted to read the amplitude data at the mirror address in the ROM.

[0084] (3) π to 3π / 2 interval of the sine period (P[N-1:N-2] = 10):

[0085] out = 2 n -1 - ROM[P[N-3:0]]

[0086] That is, the rule of taking the inverse after direct reading is adopted to read the amplitude data at the corresponding address in the ROM and take the inverse.

[0087] (4) 3π / 2 to 2π interval of the sine period (P[N-1:N-2] = 11):

[0088] out = 2 n -1 - ROM[2 N-2 -1 - P[N-3:0]]

[0089] That is, the rule of taking the inverse after mirror reading is adopted to read the amplitude data at the mirror address in the ROM and take the inverse.

[0090] Among them, out represents the result of reading the sine wave amplitude data, 2 n-1 represents the maximum value of the amplitude data, that is, the numerical range of the amplitude data is 0 to 2 n -1, and the ROM address range is 0 to (2 N-2 -1), that is, the number of sampling points in the ROM is 2 N-2 , the waveform amplitudes stored in the ROM are the sampling points of the first 1 / 4 cycle of the sine wave signal. ROM[addr] is the addr-th amplitude data stored in the ROM. The amplitudes of the digital waveforms generated in the embodiments of the present application all use an offset, that is, 2 n -1 is added to each output waveform value, and then the voltage range of the output signal is adjusted by an operational amplifier.

[0091] Specifically, the embodiments of the present application formulate a variety of symmetry transformation rules based on the symmetry of the sine wave, ensuring that amplitude data consistent with the actual sine wave can be accurately obtained at each phase point. Regardless of which 1 / 4 cycle interval of the sine wave the current phase is in, the required amplitude can be correctly extracted or transformed from the stored first 1 / 4 cycle data through the corresponding rules, thereby generating a complete and accurate sine wave digital waveform to meet various application scenarios.

[0092] On the basis of the above embodiments, as an implementable manner, in one embodiment, the control parameter further includes an initial phase control word, and the method further includes:

[0093] Step 401, configure the phase accumulator according to the initial phase control word, so that the phase accumulator adjusts the starting phase of the phase sequence according to the initial phase control word.

[0094] Specifically, the initial phase control word can be assigned to the phase accumulator before the waveform is generated. Since the phase accumulator performs an accumulation operation (accumulating the frequency control word to the current phase value) in each clock cycle, the initial phase control word sets the initial value at the start of the accumulation operation.

[0095] Among them, by setting the initial phase control word to adjust the starting phase of the phase sequence, the phase of the generated waveform can be precisely controlled, which is beneficial to ensuring the synchronization between the transmitted and received signals and improving the performance and reliability of the system.

[0096] Specifically, in one embodiment, the control parameter further includes a delay control word, and the start time of generating the digital waveform to be generated can be controlled according to the delay control word to delay the generation of the digital waveform to be generated.

[0097] Specifically, a timer can be designed. When the transmit waveform command is received, the timer starts timing. When the timing reaches the required delay time (delay control word), the waveform generation starts to delay the generation of the digital waveform to be generated.

[0098] Specifically, in one embodiment, parameters such as the frequency control word, the initial phase control word, and the delay control word are usually fixed. Although they can meet the requirements of some scenarios, they lack flexibility and adaptability in some complex and changeable environments. The embodiment of the present application introduces an adaptive algorithm to dynamically adjust these control parameters according to the environmental factors monitored in real time or the feedback information of the output waveform. By monitoring in real time and dynamically adjusting the control parameters, the actual generation result of the digital waveform can automatically compensate for the influence of environmental factors and internal circuit changes represented by the feedback information on waveform generation, ensuring that parameters such as the frequency, phase, and amplitude of the output waveform always remain within the expected range, and improving the stability and accuracy of waveform generation.

[0099] Exemplarily, as Figure 4 shown, it is a schematic structural diagram of an exemplary digital waveform generation system provided by the embodiment of the present application. The system consists of two parts: a host computer and a digital waveform generator. The host computer is designed by QT software and runs on a computer. As the system input end for interacting with the user, the functions that the host computer needs to implement are the closing and opening of the UART serial port, baud rate, number of data bits, parity bit selection, stop bit, and data transmission, etc. Then, on this basis, the transmission of relevant parameter control words is implemented; the digital waveform generator is mainly implemented through the logic resources and storage resources in the FPGA, and can generate corresponding single-frequency digital waveforms or linear frequency modulation waveforms according to the input parameters. The host computer is connected to the digital waveform generator through a serial port, and various parameter control words required by the digital waveform generator are transmitted to the digital waveform generator at the FPGA end through a predetermined data format in the host computer.

[0100] Among them, as Figure 5 shown, it is a schematic diagram of the application process of the digital waveform generation system provided by the embodiment of the present application. When the system runs, it is first necessary to set various parameters of the waveform to be generated on the QT host computer interface, and then open the UART interface communication module to send the parameters to the FPGA for caching through the UART interface. When the parameters are sent, a waveform generation command will be automatically added at the end to prompt the FPGA to generate the corresponding digital waveform. Finally, the UART interface is closed to complete a waveform generation task.

[0101] The digital waveform generator mainly includes a clock frequency division module, a digital waveform amplitude storage module, a waveform generation command judgment module, a parameter control word storage module, and a waveform generation module.

[0102] Among them, the clock frequency division module is mainly implemented by using a Phase Locked Loop (PLL for short). The phase-locked loop is a feedback control circuit that can realize functions such as frequency division and frequency multiplication of the clock signal.

[0103] The digital waveform amplitude storage module in the digital waveform generator is mainly a ROM waveform memory. The memory stores the sine wave amplitude data for the first 1 / 4 cycle. According to the symmetry characteristics of the sine wave signal, only the signal for this 1 / 4 cycle needs to be flipped and translated (mirrored and / or inverted) to obtain a complete sine signal waveform for one cycle. The amplitude data of the sine wave signal can be sampled and generated by MATLAB or other software. First, according to the address depth of the amplitude storage module (such as 2 N-2 ) set an equal number of sampling points for the sine signal to obtain the corresponding sampling data, and then scale and shift the sampling data proportionally so that its maximum value is the maximum value that the waveform output channel can output.

[0104] The waveform generation command judgment module is used to generate the excitation signal for the waveform generation module. When receiving data in a specific format from the UART interface, this module will pull up the excitation signal to prompt the waveform generation module to start generating the corresponding digital waveform.

[0105] The parameter control word storage module is mainly composed of registers. The data received by the UART interface will be cached in this module in sequence for the waveform generation module to read and use. The parameter control words include the frequency control word, the initial phase control word, and the delay control word, etc. The frequency control word controls the frequency of generating the digital waveform, the initial phase control word controls the initial phase of generating the waveform, and the delay control word can delay the waveform generation time.

[0106] Among them, the waveform generation module mainly includes the implementation of DDS technology. Taking the generation of a single-frequency digital waveform as an example, the design idea is to define a frequency control word M and an N-bit phase accumulator. Normally, the number of amplitude value samples stored in the ROM within one cycle is 2 N . In the embodiment of the present application, using the symmetry of the sine function and taking the amplitude quantization accuracy of 16 bits as an example, the ROM storage space only needs 2 N-2 ×16b□, which is 1 / 4 of the original, greatly saving the ROM storage resources.

[0107] When generating a waveform, first, an N-bit phase accumulator continuously accumulates a frequency control word. Since only the sine wave amplitude data for the first 1 / 4 cycle is stored in the ROM, the data in the ROM needs to be read 4 times to generate one cycle of the waveform. The valid bit of the ROM read address is N - 2 bits. Therefore, the actual value of the ROM read address should be calculated based on the high 2 bits of the phase accumulator (the high-order bits of the phase sequence) combined with the remaining N - 2 bits. Thus, the output value of the ROM memory is the amplitude value of the required digital waveform. In addition, the waveform generation module also needs to identify the initial phase control word and assign it to the phase accumulator before waveform generation. When the control parameter also includes a delay control word, a timer needs to be designed to time the delay time. When the generator receives the command to transmit the waveform, the timer starts timing. When the timing reaches the required delay time, the waveform generation begins.

[0108] A digital waveform generation method provided by an embodiment of the present application. When the digital waveform to be generated is a sine wave, only the sine wave amplitude data for 1 / 4 cycle is stored in the waveform memory; according to the generation requirements of the digital waveform to be generated, control parameters are determined, where the control parameters at least include a frequency control word; according to the frequency control word, the phase accumulator is controlled to generate a phase sequence; according to the high-order bits of the phase sequence, the 1 / 4 cycle interval to which the current phase belongs is judged; according to the 1 / 4 cycle interval to which the current phase belongs, a symmetry transformation rule is selected; according to the symmetry transformation rule, the sine wave amplitude data for 1 / 4 cycle is read from the waveform memory to generate the digital waveform to be generated for a complete cycle. The method provided by the above solution, by only storing the sine wave amplitude data for 1 / 4 cycle in the waveform memory, and using the phase sequence to judge the interval to which the current phase belongs, combines the symmetry transformation rule to generate a complete cycle waveform, that is, by using the period and symmetry characteristics of the sine wave signal, reduces the amplitude data and phase space required to be stored in the ROM, realizes the flexible generation of the required digital waveform with fewer resources, avoids the traditional method of storing the full-cycle waveform data, reduces the occupation of the storage space of the waveform memory, can solve the technical problems of insufficient waveform memory space resources, large consumption of hardware resources, and high development complexity in the traditional digital waveform generation system, achieves the technical effect of significantly reducing the storage capacity requirement of the waveform memory, and moreover, by accurately determining the frequency control word according to different waveform generation requirements, improves the flexibility and accuracy of waveform generation. And by flexibly adjusting the initial phase and delay time, it can be applied to many signal test and detection scenarios.

[0109] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0110] An embodiment of the present application further provides a digital waveform generation device for performing the digital waveform generation method provided in the above embodiment.

[0111] As Figure 6 shown, it is a schematic structural diagram of the digital waveform generation device provided by the embodiment of the present application. The digital waveform generation device 60 includes: a storage module 601, a determination module 602, a control module 603, a judgment module 604, a selection module 605, and a generation module 606.

[0112] Among them, the storage module is used to store only the amplitude data of a 1 / 4 cycle of the sine wave in the waveform memory when the digital waveform to be generated is a sine wave; the determination module is used to determine the control parameters according to the generation requirements of the digital waveform to be generated, where the control parameters at least include a frequency control word; the control module is used to control the phase accumulator to generate a phase sequence according to the frequency control word; the judgment module is used to judge the 1 / 4 cycle interval to which the current phase belongs according to the high-order bits of the phase sequence; the selection module is used to select a symmetry transformation rule according to the 1 / 4 cycle interval to which the current phase belongs; the generation module is used to read the amplitude data of a 1 / 4 cycle of the sine wave from the waveform memory according to the symmetry transformation rule to generate the digital waveform to be generated for a complete cycle.

[0113] For the description of the features in the corresponding embodiment of the digital waveform generation device, reference can be made to the relevant description in the corresponding embodiment of the digital waveform generation method, which will not be elaborated here one by one.

[0114] An embodiment of the present application further provides an electronic device, as Figure 7 shown, it is a schematic structural diagram of the electronic device provided by the embodiment of the present application, including a processor 10 and a memory 20. A computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any one of the above embodiments of the digital waveform generation method.

[0115] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, where the computer program is configured to execute the steps in any one of the above embodiments of the digital waveform generation method when running.

[0116] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0117] Embodiments of the present application further provide a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the embodiments of the above digital waveform generation method are implemented.

[0118] Embodiments of the present application further provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the embodiments of the above digital waveform generation method are implemented.

[0119] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0120] The above has introduced in detail a digital waveform generation method, apparatus, electronic device, and storage medium provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A digital waveform generation method, characterized in that, Including: When the digital waveform to be generated is a sine wave, only the amplitude data of the sine wave for 1 / 4 period is stored in the waveform memory; Determine control parameters according to the generation requirements of the digital waveform to be generated; wherein, the control parameters at least include a frequency control word; Control a phase accumulator to generate a phase sequence according to the frequency control word; Judge the 1 / 4 period interval to which the current phase belongs according to the high bits of the phase sequence; Select a symmetry transformation rule according to the 1 / 4 period interval to which the current phase belongs; Read the amplitude data of the sine wave for the 1 / 4 period from the waveform memory according to the symmetry transformation rule to generate the digital waveform to be generated for a complete period.

2. The digital waveform generation method according to claim 1, wherein The determining control parameters according to the generation requirements of the digital waveform to be generated includes: When the digital waveform to be generated is a single-frequency digital waveform, determine the frequency control word based on the following formula: Wherein, M represents the frequency control word, N represents the number of bits of the phase accumulator, f out represents the desired output frequency, f clk represents the clock frequency, and the generation requirements for the digital waveform to be generated include the number of bits of the phase accumulator, the desired output frequency, and the clock frequency.

3. The digital waveform generation method according to claim 1, wherein The determining control parameters according to the generation requirements of the digital waveform to be generated includes: When the digital waveform to be generated is a chirp digital waveform, determine the frequency control word based on the following formula: where M represents the frequency control word, N represents the number of bits of the phase accumulator, f out represents the desired output frequency, f clk represents the clock frequency, u represents the frequency control word adjustment step, B represents the signal bandwidth, T represents the signal pulse width, and the generation requirements of the digital waveform to be generated include the number of bits of the phase accumulator, the desired output frequency, the clock frequency, the signal bandwidth, and the signal pulse width.

4. The digital waveform generation method according to claim 1, wherein The controlling the phase accumulator to generate a phase sequence according to the frequency control word includes: In each clock cycle, accumulate the frequency control word to the current phase value of the phase accumulator, so that the phase accumulator generates the phase sequence according to the current phase value in each clock cycle; Wherein, the phase sequence includes the read address of the amplitude data of the sine wave in the waveform memory.

5. The digital waveform generation method according to claim 1, characterized in that The selecting a symmetry transformation rule according to the 1 / 4 period interval to which the current phase belongs includes: When the 1 / 4 period interval to which the current phase belongs is the first interval, select the direct reading rule; When the 1 / 4 period interval to which the current phase belongs is the second interval, select the mirror reading rule; When the 1 / 4 period interval to which the current phase belongs is the third interval, select the rule of taking the inverse after direct reading; When the 1 / 4 period interval to which the current phase belongs is the fourth interval, select the rule of taking the inverse after mirror reading; Wherein, the symmetry transformation rules include the direct reading rule, the mirror reading rule, the rule of taking the inverse after direct reading, and the rule of taking the inverse after mirror reading. The first interval is the 0-π / 2 interval of the sine period, the second interval is the π / 2-π interval of the sine period, the third interval is the π-3π / 2 interval of the sine period, and the fourth interval is the 3π / 2-2π interval of the sine period.

6. The digital waveform generation method according to claim 1, characterized in that The control parameters further include an initial phase control word, and the method further includes: Configure the phase accumulator according to the initial phase control word, so that the phase accumulator adjusts the starting phase of the phase sequence according to the initial phase control word.

7. The digital waveform generation method according to claim 1, wherein The control parameters further include a delay control word, and the method further includes: Control the start time of generating the digital waveform to be generated according to the delay control word to delay the generation of the digital waveform to be generated.

8. A digital waveform generating device, characterized in that, Including: A storage module, configured to, when the digital waveform to be generated is a sine wave, only store the amplitude data of the sine wave for 1 / 4 period in the waveform memory; A determination module, configured to determine a control parameter according to the generation requirement of the to-be-generated digital waveform; wherein, the control parameter at least includes a frequency control word; A control module, configured to control a phase accumulator to generate a phase sequence according to the frequency control word; A judgment module, configured to judge the 1 / 4 cycle interval to which the current phase belongs according to the high-order bit of the phase sequence; A selection module, configured to select a symmetry transformation rule according to the 1 / 4 cycle interval to which the current phase belongs; A generation module, configured to read the sine wave amplitude data of the 1 / 4 cycle from the waveform memory according to the symmetry transformation rule to generate a to-be-generated digital waveform of a complete cycle.

9. An electronic device, characterized in that, including: A memory, configured to store a computer program; A processor, configured to implement the steps of the digital waveform generation method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the digital waveform generation method according to any one of claims 1 to 7 when executed by a processor.

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