Chip control method and device, chip, electronic equipment and storage medium
By identifying and skipping exception codes in the ROM, reading and executing the second object code from the set storage space, the chip operation problem caused by ROM exceptions is solved, and low-cost and fast chip repair is achieved.
Patent Information
- Application Number
- CN202410110752.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-25
- Publication Date
- 2025-07-29
AI Technical Summary
In the prior art, abnormal codes in the ROM may cause the chip to fail to operate normally, and the chip replacement is expensive and time-consuming.
By reading the first object code from the read-only memory ROM of the chip, it is determined whether it is an exception code. If it is an exception, the code will not be executed, and the second object code will be read and executed from the set storage space.
It avoids abnormal chip operation caused by abnormal codes, reduces the cost and time of replacing chips, and ensures the normal operation of the chip.
Smart Images
Figure CN120386701A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of chip technology, and in particular, to a control method, device, chip, electronic device, and storage medium for a chip. Background Art
[0002] At present, ROM (Read-Only Memory) has the advantages of fast speed, simple structure, low power consumption, etc., and is widely used in electronic devices such as chips. For example, ROM is used to store codes that do not need to be changed. However, if there is an abnormality in the codes in the ROM, it may cause the chip to malfunction. Summary of the Invention
[0003] The present disclosure provides a control method, device, chip, electronic device, computer-readable storage medium, and computer program product for a chip, so as to at least solve the problem that if there is an abnormality in the codes in the ROM in the related art, it may cause the chip to malfunction. The technical solutions of the present disclosure are as follows:
[0004] According to a first aspect of an embodiment of the present disclosure, a control method for a chip is provided, including: reading a first target code from a read-only memory ROM of the chip; identifying whether the first target code is an abnormal code; if the first target code is an abnormal code, not executing the first target code; reading a second target code from a set storage space of the chip, and executing the second target code.
[0005] In an embodiment of the present disclosure, the identifying whether the first target code is an abnormal code includes: obtaining a code library, where each code in the code library is marked as an abnormal code; identifying whether the first target code exists in the code library; if the first target code exists in the code library, identifying the first target code as an abnormal code; if the first target code does not exist in the code library, identifying the first target code as a non-abnormal code.
[0006] In an embodiment of the present disclosure, the method further includes: obtaining a mapping relationship between an identifier of a first candidate code and an identifier of a second candidate code; obtaining an identifier of the first target code; and determining the second target code from a plurality of the second candidate codes based on the identifier of the first target code and the mapping relationship.
[0007] In one embodiment of the present disclosure, reading the second target code from the set storage space of the chip includes: reading the second target code from the first storage space of the chip, where the first storage space is a storage space for non-executable code; storing the read second target code into the second storage space of the chip, where the second storage space is a storage space for executable code; and reading the second target code from the second storage space.
[0008] In one embodiment of the present disclosure, the method further includes: determining the second storage space based on the second target code.
[0009] In one embodiment of the present disclosure, the method further includes: if the storage capacity occupied by the second target code is less than or equal to a set threshold, regarding the second target code as the first type of code; if the storage capacity occupied by the second target code is greater than the set threshold, regarding the second target code as the second type of code.
[0010] In one embodiment of the present disclosure, determining the second storage space based on the second target code includes: if the second target code is the first type of code, regarding the third storage space as the second storage space; if the second target code is the second type of code, regarding the fourth storage space as the second storage space, where the storage capacity of the third storage space is less than the storage capacity of the fourth storage space.
[0011] In one embodiment of the present disclosure, if the second target code is the second type of code, before reading the second type of code from the fourth storage space, it further includes: reading a third target code from the first storage space, where the third target code is used to indicate reading the second type of code from the fourth storage space; storing the read third target code into the third storage space; reading the third target code from the third storage space and executing the third target code.
[0012] In one embodiment of the present disclosure, the method further includes: if the first target code is a non-abnormal code, executing the first target code.
[0013] According to the second aspect of the embodiments of the present disclosure, there is provided a control device for a chip, including: a reading module configured to read a first target code from a read-only memory (ROM) of the chip; an identification module configured to identify whether the first target code is an abnormal code; a processing module configured to, if the first target code is an abnormal code, not execute the first target code; and the processing module is further configured to read a second target code from the set storage space of the chip and execute the second target code.
[0014] In one embodiment of the present disclosure, the recognition module is further configured to perform: obtaining a code library, wherein each code in the code library is marked as an abnormal code; recognizing whether the first target code exists in the code library; if the first target code exists in the code library, recognizing the first target code as an abnormal code; if the first target code does not exist in the code library, recognizing the first target code as a non-abnormal code.
[0015] In one embodiment of the present disclosure, the processing module is further configured to perform: obtaining a mapping relationship between the identifier of the first candidate code and the identifier of the second candidate code; obtaining the identifier of the first target code; and determining the second target code from a plurality of the second candidate codes based on the identifier of the first target code and the mapping relationship.
[0016] In one embodiment of the present disclosure, the processing module is further configured to perform: reading the second target code from a first storage space of the chip, wherein the first storage space is a storage space for non-executable codes; storing the read second target code in a second storage space of the chip, wherein the second storage space is a storage space for executable codes; and reading the second target code from the second storage space.
[0017] In one embodiment of the present disclosure, the processing module is further configured to perform: determining the second storage space based on the second target code.
[0018] In one embodiment of the present disclosure, the processing module is further configured to perform: if the storage capacity occupied by the second target code is less than or equal to a set threshold, regarding the second target code as a first type of code; if the storage capacity occupied by the second target code is greater than the set threshold, regarding the second target code as a second type of code.
[0019] In one embodiment of the present disclosure, the processing module is further configured to perform: if the second target code is a first type of code, regarding a third storage space as the second storage space; if the second target code is a second type of code, regarding a fourth storage space as the second storage space, wherein the storage capacity of the third storage space is less than the storage capacity of the fourth storage space.
[0020] In an embodiment of the present disclosure, if the second target code is a second type of code, before reading the second type of code from the fourth storage space, the processing module is further configured to perform: reading a third target code from the first storage space, where the third target code is used to indicate reading the second type of code from the fourth storage space; storing the read third target code in the third storage space; reading the third target code from the third storage space and executing the third target code.
[0021] In an embodiment of the present disclosure, the processing module is further configured to perform: if the first target code is a non-exception code, execute the first target code.
[0022] According to a third aspect of the embodiments of the present disclosure, a chip is provided, including: a central processing unit (CPU), a read-only memory (ROM), and a set storage space; wherein, the CPU is configured to implement the steps of the method described in the first aspect of the embodiments of the present disclosure.
[0023] In an embodiment of the present disclosure, the set storage space includes: a first storage space, where the first storage space is a storage space for non-executable codes; a second storage space, where the second storage space is a storage space for executable codes.
[0024] In an embodiment of the present disclosure, the first storage space includes a one-time programmable memory.
[0025] In an embodiment of the present disclosure, the second storage space includes: a third storage space and a fourth storage space, where the storage capacity of the third storage space is less than the storage capacity of the fourth storage space.
[0026] In an embodiment of the present disclosure, the fourth storage space includes a random access memory (RAM).
[0027] According to a fourth aspect of the embodiments of the present disclosure, an electronic device is provided, including a processor; a memory for storing processor-executable instructions; wherein, the processor is configured to implement the steps of the method described in the first aspect of the embodiments of the present disclosure.
[0028] According to a fifth aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and when the program instructions are executed by a processor, the steps of the method described in the first aspect of the embodiments of the present disclosure are implemented.
[0029] According to a sixth aspect of the embodiments of the present disclosure, a computer program product is provided, including a computer program, characterized in that when the computer program is executed by a processor of an electronic device, the steps of the method described in the first aspect of the embodiments of the present disclosure are implemented.
[0030] The technical solutions provided by the embodiments of the present disclosure at least bring the following beneficial effects: when the first target code read from the ROM of the chip is an abnormal code, the first target code is not executed, and the second target code is continuously read from the set storage space of the chip and executed. This can avoid the problem that the chip runs abnormally due to the execution of the first target code, ensuring the normal operation of the chip. Moreover, compared with the related art where the chip is re-flown when the code in the ROM of the chip is abnormal, resulting in high costs and long time consumption, this solution does not require the chip to be re-flown and has the advantages of low cost and short time consumption.
[0031] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure and do not constitute an improper limitation of the present disclosure.
[0033] Figure 1 is a flowchart of a control method for a chip shown according to an exemplary embodiment.
[0034] Figure 2 is a flowchart of a control method for a chip shown according to another exemplary embodiment.
[0035] Figure 3 is a flowchart of a control method for a chip shown according to another exemplary embodiment.
[0036] Figure 4 is a flowchart of a control method for a chip shown according to another exemplary embodiment.
[0037] Figure 5 is a block diagram of a control device for a chip shown according to an exemplary embodiment.
[0038] Figure 6 is a block diagram of a chip shown according to an exemplary embodiment.
[0039] Figure 7 is a block diagram of a chip shown according to another exemplary embodiment.
[0040] Figure 8 is a block diagram of an electronic device shown according to an exemplary embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0041] To enable those of ordinary skill in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings.
[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0043] In the technical solutions of the present disclosure, the acquisition, storage, use, processing, etc. of data all comply with the provisions of relevant laws and regulations.
[0044] Figure 1 is a flowchart of a control method for a chip shown according to an exemplary embodiment. As Figure 1 shown, the control method for the chip in the embodiments of the present disclosure includes the following steps.
[0045] S101, read the first target code from the read-only memory (ROM) of the chip.
[0046] It should be noted that the execution subject of the control method for the chip in the embodiments of the present disclosure is an electronic device, where the electronic device includes a chip, a mobile phone, a notebook, a desktop computer, a vehicle-mounted terminal, a smart home appliance, a wearable device, etc. Among them, the wearable device may include a wrist-worn device (such as a smart watch, a smart bracelet), a head-mounted device, a foot-worn device, etc. The control method for the chip in the embodiments of the present disclosure can be executed by the control device for the chip in the embodiments of the present disclosure, and the control device for the chip in the embodiments of the present disclosure can be configured in any electronic device to execute the control method for the chip in the embodiments of the present disclosure.
[0047] It should be noted that the chip includes a ROM (Read-Only Memory). Any ROM in related technologies can be used for the ROM. For example, it can include a Mask ROM (Mask Read-Only Memory), a PROM (Programmable ROM), etc., and no excessive limitation is made here. The ROM stores codes. The first target code is part or all of the codes in the ROM. The first target code refers to the code in the ROM to be read currently. No excessive limitation is made on the quantity of the first target code or the programming language used. For example, the first target code can include at least one code, code blocks, etc., and the first target code can be written in programming languages such as C, C++, Java, etc.
[0048] In one implementation, reading the first target code from the read-only memory ROM of the chip includes obtaining the storage location of the first target code in the ROM and reading the first target code from the storage location of the first target code in the ROM.
[0049] In some examples, obtaining the storage location of the first target code in the ROM includes obtaining the mapping relationship between the identifiers of the codes in the ROM and the storage locations of the codes in the ROM, obtaining the identifier of the first target code, and determining the storage location of the first target code in the ROM based on the identifier of the first target code and the mapping relationship. For example, the storage location mapped by the identifier of the first target code can be used as the storage location of the first target code in the ROM. It should be noted that no excessive limitation is made on the identifier of the code. For example, it can include the name, number, etc. of the code.
[0050] In some examples, obtaining the storage location of the first target code in the ROM includes obtaining the storage location of the third target code read from the ROM of the chip last time, and using the next storage location of the storage location of the third target code in the ROM as the storage location of the first target code in the ROM.
[0051] S102, identify whether the first target code is an abnormal code.
[0052] It should be noted that identifying whether the first target code is an abnormal code can be implemented by using any detection method for abnormal codes in related technologies, and no excessive limitation is made here.
[0053] In one implementation, identifying whether the first target code is an abnormal code includes identifying whether the first target code includes a set keyword. If the first target code includes the set keyword, identify the first target code as an abnormal code. If the first target code does not include the set keyword, identify the first target code as a non-abnormal code. It should be noted that no excessive limitation is made on the set keyword.
[0054] In one implementation, identifying whether the first target code is an abnormal code includes inputting the first target code into a target model, and the target model identifies whether the first target code is an abnormal code. For example, the target model can output an identification result of the first target code, and the identification result is used to indicate whether the first target code is an abnormal code. There are no excessive restrictions on the identification result. For example, it may include the reason for the abnormality of the first target code, the abnormal content in the first target code, etc.
[0055] In one implementation, identifying whether the first target code is an abnormal code includes obtaining a code library. Among them, each code in the code library is marked as an abnormal code. Identify whether the first target code exists in the code library. If the first target code exists in the code library, identify the first target code as an abnormal code. If the first target code does not exist in the code library, identify the first target code as a non-abnormal code. Thus, a code library can be preset, and each code in the code library is marked as an abnormal code. Identify whether the first target code exists in the code library to identify whether the first target code is an abnormal code.
[0056] In some examples, obtaining the code library includes reading the fourth target code from the ROM of the chip, testing the fourth target code. If the fourth target code fails the test, mark the fourth target code as an abnormal code and add the fourth target code to the code library. It should be noted that the fourth target code is part or all of the code in the ROM, and the fourth target code refers to the code in the ROM currently to be tested. Testing the fourth target code can be implemented by any code testing method in related technologies, and there are no excessive restrictions here.
[0057] In some examples, before reading the fourth target code from the ROM of the chip, it also includes identifying that the chip's tape-out process is completed. Thus, in this method, after the chip's tape-out is completed, the code in the chip's ROM can be tested to establish a code library for identifying whether the code in the ROM is an abnormal code.
[0058] S103, if the first target code is an abnormal code, do not execute the first target code.
[0059] S104, read the second target code from the set storage space of the chip and execute the second target code.
[0060] It should be noted that the chip includes a set storage space, and the set storage space stores code. The second target code is part or all of the code in the set storage space. The second target code refers to the code in the set storage space currently to be read, and the second target code is a non-abnormal code.
[0061] For example, the chip includes a CPU (Central Processing Unit), taking the CPU in the chip as the execution entity. The CPU can read the first target code from the ROM of the chip. The CPU identifies whether the first target code is an abnormal code. If the first target code is an abnormal code, the CPU does not execute the first target code. Instead, the CPU reads the second target code from the set storage space in the chip and executes the second target code.
[0062] In one implementation, there is a corresponding relationship between the first target code and the second target code.
[0063] In one implementation, the method further includes obtaining the mapping relationship between the identifier of the first candidate code and the identifier of the second candidate code, obtaining the identifier of the first target code, and determining the second target code from multiple second candidate codes based on the identifier of the first target code and the mapping relationship. For example, the second candidate code mapped by the identifier of the first target code can be used as the second target code. It should be noted that the first candidate code is part or all of the codes in the ROM, the first target code is part of the first candidate codes, the second candidate code is part or all of the codes in the set storage space, and the second target code is part of the second candidate codes. Thus, the second target code can be determined from multiple second candidate codes based on the mapping relationship between the identifier of the first candidate code and the identifier of the second candidate code, as well as the identifier of the first target code.
[0064] In one implementation, before executing the second target code, it further includes replacing the read first target code with the read second target code.
[0065] In one implementation, after executing the second target code, it further includes returning to execute reading the first target code from the ROM of the chip and its subsequent steps until a set end condition is reached. It should be noted that the set end condition is not overly limited. For example, it can include that there is no first target code in the ROM, the codes in the ROM have been executed to the end, etc. Thus, after executing the second target code, steps such as code reading, abnormal identification, and code execution can be repeated.
[0066] The control method for a chip provided by an embodiment of the present disclosure reads a first target code from the read-only memory (ROM) of the chip, identifies whether the first target code is an abnormal code. If the first target code is an abnormal code, the first target code is not executed, and a second target code is read from the set storage space of the chip and the second target code is executed. Thus, when the first target code read from the ROM of the chip is an abnormal code, the first target code is not executed, and the second target code is continuously read from the set storage space of the chip and the second target code is executed, which can avoid the problem that the abnormal operation of the chip is caused by executing the first target code, ensure the normal operation of the chip, and compared with the problem of high cost and long time consumption caused by re-flowing the chip when the code in the ROM of the chip is abnormal in the related art, this solution does not require re-flowing the chip and has the advantages of low cost and short time consumption.
[0067] Figure 2 is a flowchart of a control method for a chip shown according to another exemplary embodiment, as Figure 2 shown, the control method for the chip according to the embodiment of the present disclosure includes the following steps.
[0068] S201, read a first target code from the read-only memory (ROM) of the chip.
[0069] S202, identify whether the first target code is an abnormal code.
[0070] S203, if the first target code is an abnormal code, do not execute the first target code.
[0071] For the relevant content of steps S201 - S203, reference can be made to the above embodiment and will not be elaborated here.
[0072] S204, read a second target code from the first storage space of the chip, where the first storage space is a storage space for non-executable codes.
[0073] It should be noted that the chip includes a first storage space, the first storage space stores codes, the second target code is part or all of the codes in the first storage space, and the first storage space is a storage space for non-executable codes. There are no excessive limitations on the first storage space. For example, the first storage space includes a one-time programmable memory. For example, it may include an eFuse (electronic fuse).
[0074] S205, store the read second target code into the second storage space of the chip, where the second storage space is a storage space for executable codes.
[0075] It should be noted that the chip includes a second storage space which stores code. The second target code is part or all of the code in the second storage space, and the second storage space is a storage space for executable code. There are no excessive limitations on the second storage space. For example, the second storage space includes RAM (Random Access Memory). In this embodiment, the set storage space includes a first storage space and a second storage space.
[0076] S206, Read the second target code from the second storage space and execute the second target code.
[0077] For example, the chip includes a CPU. Taking the CPU in the chip as the execution subject, the CPU can read the first target code from the ROM of the chip. The CPU identifies whether the first target code is an abnormal code. If the first target code is an abnormal code, the CPU does not execute the first target code. The CPU reads the second target code from the first storage space of the chip, where the first storage space is a storage space for non-executable code. The CPU stores the read second target code into the second storage space of the chip, where the second storage space is a storage space for executable code. The CPU reads the second target code from the second storage space and executes the second target code.
[0078] The control method of the chip provided by the embodiment of the present disclosure reads the second target code from the first storage space of the chip, where the first storage space is a storage space for non-executable code, stores the read second target code into the second storage space of the chip, where the second storage space is a storage space for executable code, and reads the second target code from the second storage space. Thus, when the first target code read from the ROM of the chip is an abnormal code, the second target code can continue to be read from the non-executable code storage space (i.e., the first storage space), the read second target code is stored into the executable code storage space (i.e., the second storage space), and the second target code continues to be read from the executable code storage space (i.e., the second storage space) to realize the reading of the second target code.
[0079] Figure 3 is a flowchart of a control method of a chip shown according to another exemplary embodiment. As Figure 3 shown, the control method of the chip in the embodiment of the present disclosure includes the following steps.
[0080] S301, Read the first target code from the read-only memory ROM of the chip.
[0081] S302, Identify whether the first target code is an abnormal code.
[0082] S303, if the first target code is an exception code, do not execute the first target code.
[0083] S304, read the second target code from the first storage space of the chip, where the first storage space is a storage space for non-executable code.
[0084] For the relevant content of steps S301 - S304, reference can be made to the above embodiments and will not be elaborated here.
[0085] S305, determine the second storage space based on the second target code.
[0086] In one implementation manner, determining the second storage space based on the second target code includes determining the second storage space based on the category of the second target code. It can be understood that different categories of second target codes can correspond to different second storage spaces.
[0087] In one implementation manner, determining the second storage space based on the second target code includes determining the second storage space based on the quantity of the second target code. For example, the mapping relationship between the candidate intervals and the candidate storage spaces can be obtained, the target interval in which the quantity of the second target code is located can be determined from multiple candidate intervals, and the second storage space can be determined based on the target interval and the mapping relationship. For example, the candidate storage space mapped by the target interval can be used as the second storage space.
[0088] In one implementation manner, the method further includes: if the storage capacity occupied by the second target code is less than or equal to the set threshold, regarding the second target code as the first type of code; if the storage capacity occupied by the second target code is greater than the set threshold, regarding the second target code as the second type of code. Thus, the size relationship between the storage capacity occupied by the second target code and the set threshold can be considered, and the second target code can be regarded as the first type of code or the second type of code.
[0089] In some examples, determining the second storage space based on the second target code includes: if the second target code is the first type of code, using the third storage space as the second storage space; if the second target code is the second type of code, using the fourth storage space as the second storage space, where the storage capacity of the third storage space is less than that of the fourth storage space. Thus, when the second target code is the first type of code, the third storage space with a smaller storage capacity can be used as the second storage space; when the second target code is the second type of code, the fourth storage space with a larger storage capacity can be used as the second storage space.
[0090] It should be noted that the chip includes a third storage space and a fourth storage space. Either the third storage space or the fourth storage space is the second storage space (i.e., the set storage space), and no excessive limitations are imposed on the third storage space and the fourth storage space. For example, the fourth storage space includes RAM.
[0091] S306, store the read second target code into the second storage space of the chip, where the second storage space is the storage space for executable code.
[0092] S307, read the second target code from the second storage space and execute the second target code
[0093] For the relevant content of steps S306 - S307, reference can be made to the above embodiments, and details are not described here again.
[0094] The control method of the chip provided by the embodiment of the present disclosure determines the second storage space based on the second target code. Thus, considering the second target code, the second storage space can be determined, improving the flexibility of the second storage space.
[0095] Based on any of the above embodiments, if the second target code is a second - type code, before reading the second - type code from the fourth storage space, it further includes reading a third target code from the first storage space, where the third target code is used to indicate reading the second - type code from the fourth storage space, storing the read third target code into the third storage space, reading the third target code from the third storage space, and executing the third target code. Thus, when the second target code is a second - type code, the third target code can also be read from the first storage space, stored into the third storage space, read from the third storage space, and executed, so as to read the second - type code from the fourth storage space subsequently.
[0096] It should be noted that the third target code is part or all of the code in the first storage space and the third storage space.
[0097] Based on any of the above embodiments, the method further includes executing the first target code if the first target code is a non - abnormal code. Thus, when the first target code read from the ROM of the chip is a non - abnormal code, the first target code can be executed.
[0098] In some examples, after executing the first target code, it further includes returning to execute the first target code read from the ROM of the chip and its subsequent steps until a set end condition is reached. It should be noted that no excessive limitations are imposed on the set end condition. For example, it may include that there is no first target code in the ROM, the code execution in the ROM ends, etc. Thus, after executing the first target code, steps such as code reading, exception recognition, and code execution can be repeated.
[0099] Figure 4 is a flowchart of a control method for a chip shown according to another exemplary embodiment. As Figure 4 shown, the control method for the chip according to the embodiments of the present disclosure includes the following steps.
[0100] S401, read a first target code from the read-only memory (ROM) of the chip;
[0101] S402, identify whether the first target code is an abnormal code.
[0102] If it is, then execute step S403; if not, then execute step S411.
[0103] S403, do not execute the first target code, and read a second target code from the first storage space of the chip, where the first storage space is a storage space for non-executable codes.
[0104] S404, if the second target code is a first type of code, store the read first type of code in the third storage space of the chip.
[0105] S405, read the first type of code from the third storage space and execute the first type of code.
[0106] S406, if the second target code is a second type of code, store the read second type of code in the fourth storage space of the chip.
[0107] S407, read a third target code from the first storage space, where the third target code is used to indicate reading the second type of code from the fourth storage space.
[0108] S408, store the read third target code in the third storage space.
[0109] S409, read the third target code from the third storage space and execute the third target code.
[0110] S410, read the second type of code from the fourth storage space and execute the second type of code.
[0111] S411, execute the first target code.
[0112] For the relevant content of steps S401 - S411, reference can be made to the above embodiments and will not be elaborated here.
[0113] It should be noted that after executing the first type of code in step S405, after executing the second type of code in step S410, and after executing the first target code in step S411, it is possible to return to execute step S401 and its subsequent steps until a set end condition is reached.
[0114] Figure 5 It is a block diagram of a control device for a chip shown according to an exemplary embodiment. Referring to Figure 5 , the control device 100 for the chip according to the embodiments of the present disclosure includes: a reading module 110, an identification module 120, and a processing module 130.
[0115] The reading module 110 is configured to read a first target code from the read-only memory (ROM) of the chip;
[0116] The identification module 120 is configured to identify whether the first target code is an abnormal code;
[0117] The processing module 130 is configured to, if the first target code is an abnormal code, not execute the first target code;
[0118] The processing module 130 is further configured to read a second target code from the set storage space of the chip and execute the second target code.
[0119] In an embodiment of the present disclosure, the identification module 120 is further configured to: obtain a code library, where each code in the code library is marked as an abnormal code; identify whether the first target code exists in the code library; if the first target code exists in the code library, identify the first target code as an abnormal code; if the first target code does not exist in the code library, identify the first target code as a non-abnormal code.
[0120] In an embodiment of the present disclosure, the processing module 130 is further configured to: obtain the mapping relationship between the identifier of the first candidate code and the identifier of the second candidate code; obtain the identifier of the first target code; and determine the second target code from multiple second candidate codes based on the identifier of the first target code and the mapping relationship.
[0121] In an embodiment of the present disclosure, the processing module 130 is further configured to: read the second target code from the first storage space of the chip, where the first storage space is a storage space for non-executable codes; store the read second target code in the second storage space of the chip, where the second storage space is a storage space for executable codes; and read the second target code from the second storage space.
[0122] In an embodiment of the present disclosure, the processing module 130 is further configured to: determine the second storage space based on the second target code.
[0123] In one embodiment of the present disclosure, the processing module 130 is further configured to perform: if the storage capacity occupied by the second target code is less than or equal to a set threshold, use the second target code as the first type of code; if the storage capacity occupied by the second target code is greater than the set threshold, use the second target code as the second type of code.
[0124] In one embodiment of the present disclosure, the processing module 130 is further configured to perform: if the second target code is the first type of code, use the third storage space as the second storage space; if the second target code is the second type of code, use the fourth storage space as the second storage space, where the storage capacity of the third storage space is less than the storage capacity of the fourth storage space.
[0125] In one embodiment of the present disclosure, if the second target code is the second type of code, before reading the second type of code from the fourth storage space, the processing module 130 is further configured to perform: read a third target code from the first storage space, where the third target code is used to indicate reading the second type of code from the fourth storage space; store the read third target code in the third storage space; read the third target code from the third storage space and execute the third target code.
[0126] In one embodiment of the present disclosure, the processing module 130 is further configured to perform: if the first target code is a non-abnormal code, execute the first target code.
[0127] Regarding the device in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.
[0128] The control device of the chip provided by the embodiment of the present disclosure reads a first target code from the read-only memory (ROM) of the chip, identifies whether the first target code is an abnormal code. If the first target code is an abnormal code, the first target code is not executed, and a second target code is read from the set storage space of the chip and the second target code is executed. Thus, when the first target code read from the ROM of the chip is an abnormal code, the first target code is not executed, and the second target code is continuously read from the set storage space of the chip and the second target code is executed, which can avoid the problem that the chip runs abnormally due to the execution of the first target code, ensuring the normal operation of the chip. Moreover, compared with the related art where when the code in the ROM of the chip is abnormal, re-flowing the chip causes high costs and long time consumption, this solution does not require re-flowing the chip and has the advantages of low cost and short time consumption.
[0129] Figure 6It is a block diagram of a chip shown according to an exemplary embodiment.
[0130] As Figure 6 shown, the above chip includes: a central processing unit CPU, a read-only memory ROM, and a set storage space; wherein, the CPU is configured to implement the steps of the control method of the chip of the present disclosure embodiment.
[0131] In one embodiment, the set storage space includes: a first storage space, wherein the first storage space is a storage space for non-executable code; a second storage space, wherein the second storage space is a storage space for executable code.
[0132] In one embodiment, the first storage space includes a one-time programmable memory.
[0133] In one embodiment, the second storage space includes: a third storage space and a fourth storage space, wherein the storage capacity of the third storage space is less than the storage capacity of the fourth storage space.
[0134] In one embodiment, the fourth storage space includes a random access memory RAM.
[0135] For example, as Figure 7 shown, the chip includes a central processing unit CPU, a read-only memory ROM, an electronic fuse eFuse, a mapping memory, and a random access memory RAM. Among them, the mapping memory is respectively connected to the CPU and the ROM, the ROM and the RAM are respectively connected to the eFuse, and the RAM is connected to the CPU. It should be noted that the eFuse is the first storage space, the mapping memory is the third storage space, and the RAM is the fourth storage space.
[0136] For the chip provided by the embodiment of the present disclosure, the CPU in the chip can execute the control method of the chip as described above, read the first target code from the read-only memory ROM of the chip, identify whether the first target code is an abnormal code, if the first target code is an abnormal code, do not execute the first target code, read the second target code from the set storage space of the chip, and execute the second target code. Thus, when the first target code read from the ROM of the chip is an abnormal code, the first target code is not executed, and the second target code is continuously read from the set storage space of the chip and executed, which can avoid the problem that the chip runs abnormally caused by executing the first target code, ensure the normal operation of the chip, and compared with the problem of high cost and long time-consuming caused by re-flowing the chip when the code in the ROM of the chip is abnormal in the related art, this solution does not require re-flowing the chip and has the advantages of low cost and short time-consuming.
[0137] Figure 8 It is a block diagram of an electronic device shown according to an exemplary embodiment.
[0138] As shown in Figure 8 the above-mentioned electronic device 200 includes:
[0139] a memory 210 and a processor 220, and a bus 230 connecting different components (including the memory 210 and the processor 220). The memory 210 stores a computer program, and when the processor 220 executes the program, it implements the control method of the chip described in the embodiments of the present disclosure.
[0140] The bus 230 represents one or more of several types of bus architectures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus architecture in a variety of bus architectures. By way of example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
[0141] The electronic device 200 typically includes a variety of electronically readable media. These media can be any available media accessible by the electronic device 200, including volatile and non-volatile media, removable and non-removable media.
[0142] The memory 210 may also include a computer system readable medium in the form of volatile memory, such as random access memory (RAM) 240 and / or cache memory 250. The electronic device 200 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 260 may be used to read and write non-removable, non-volatile magnetic media ( Figure 8 not shown, commonly referred to as a "hard disk drive"). Although Figure 8 not shown in, a disk drive for reading and writing removable non-volatile disks (such as "floppy disks") and an optical disk drive for reading and writing removable non-volatile optical disks (such as CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 230 through one or more data media interfaces. The memory 210 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present disclosure.
[0143] A program / utility 280 having a set (at least one) of program modules 270 can be stored in, for example, the memory 210. Such program modules 270 include—but are not limited to—an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 270 generally execute the functions and / or methods in the embodiments described in this disclosure.
[0144] The electronic device 200 can also communicate with one or more external devices 290 (such as a keyboard, a pointing device, a display 291, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 200, and / or communicate with any device that enables the electronic device 200 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through an input / output (I / O) interface 292. Moreover, the electronic device 200 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 293. As Figure 8 shown, the network adapter 293 communicates with other modules of the electronic device 200 through the bus 230. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.
[0145] The processor 220 executes various functional applications and data processing by running programs stored in the memory 210.
[0146] It should be noted that for the implementation process and technical principle of the electronic device in this embodiment, refer to the foregoing explanation of the control method of the chip in the embodiments of this disclosure, and details are not repeated here.
[0147] The electronic device provided by the embodiments of the present disclosure can execute the control method of the chip as described above, read the first target code from the read-only memory (ROM) of the chip, identify whether the first target code is an abnormal code. If the first target code is an abnormal code, the first target code is not executed, and the second target code is read from the set storage space of the chip and the second target code is executed. Thus, when the first target code read from the ROM of the chip is an abnormal code, the first target code is not executed, and the second target code is continuously read from the set storage space of the chip and the second target code is executed, which can avoid the problem that the abnormal operation of the chip is caused by executing the first target code, ensure the normal operation of the chip, and compared with the problem of high cost and long time consumption caused by re-fabricating the chip when the code in the ROM of the chip is abnormal in the related art, this solution does not require re-fabricating the chip and has the advantages of low cost and short time consumption.
[0148] To implement the above embodiments, the present disclosure also proposes a computer-readable storage medium, on which computer program instructions are stored, and when the program instructions are executed by a processor, the steps of the control method of the chip provided by the present disclosure are implemented.
[0149] Optionally, the computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.
[0150] To implement the above embodiments, the present disclosure also provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor of an electronic device, the control method of the chip as described above is implemented.
[0151] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and embodiments are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.
[0152] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.
Claims
1. A control method for a chip, characterized in that, Including: Read the first target code from the read-only memory (ROM) of the chip; Identify whether the first target code is an abnormal code; If the first target code is an abnormal code, do not execute the first target code; Read the second target code from the set storage space of the chip and execute the second target code.
2. The method according to claim 1, characterized in that The identifying whether the first target code is an abnormal code includes: Obtain a code library, wherein each code in the code library is marked as an abnormal code; Identify whether the first target code exists in the code library; If the first target code exists in the code library, identify the first target code as an abnormal code; If the first target code does not exist in the code library, identify the first target code as a non-abnormal code.
3. The method according to claim 1, characterized in that, The method further includes: Obtain the mapping relationship between the identifier of the first candidate code and the identifier of the second candidate code; Obtain the identifier of the first target code; Based on the identifier of the first target code and the mapping relationship, determine the second target code from multiple second candidate codes.
4. The method according to claim 1, wherein The reading the second target code from the set storage space of the chip includes: Read the second target code from the first storage space of the chip, where the first storage space is a storage space for non-executable codes; Store the read second target code into the second storage space of the chip, where the second storage space is a storage space for executable codes; Read the second target code from the second storage space.
5. The method according to claim 4, wherein The method further includes: Determine the second storage space based on the second target code.
6. The method according to claim 5, wherein The method further includes: If the storage capacity occupied by the second target code is less than or equal to the set threshold, regard the second target code as the first type of code; If the storage capacity occupied by the second target code is greater than the set threshold, regard the second target code as the second type of code.
7. The method according to claim 6, wherein The determining the second storage space based on the second target code includes: If the second target code is the first type of code, regard the third storage space as the second storage space; If the second target code is the second type of code, regard the fourth storage space as the second storage space, where the storage capacity of the third storage space is less than the storage capacity of the fourth storage space.
8. The method according to claim 7, wherein If the second target code is the second type of code, before reading the second type of code from the fourth storage space, it further includes: Read the third target code from the first storage space, where the third target code is used to indicate reading the second type of code from the fourth storage space; Store the read third target code into the third storage space; Read the third target code from the third storage space and execute the third target code.
9. The method according to any one of claims 1 to 8, characterized in that The method further includes: If the first target code is a non-abnormal code, execute the first target code.
10. A control device for a chip, characterized in that, Including: A reading module configured to read the first target code from the read-only memory (ROM) of the chip; An identifying module configured to identify whether the first target code is an abnormal code; The processing module is configured to, if the first target code is an exception code, not execute the first target code; The processing module is further configured to read a second target code from a set storage space of the chip and execute the second target code.
11. A chip, characterized in that, Comprising: A central processing unit (CPU), a read-only memory (ROM), and a set storage space; wherein, The CPU is configured to: Implement the steps of the method according to any one of claims 1-9.
12. The chip according to claim 11, wherein, The set storage space includes: A first storage space, wherein the first storage space is a storage space for non-executable code; A second storage space, wherein the second storage space is a storage space for executable code.
13. The chip according to claim 12, characterized in that, The first storage space includes a one-time programmable memory.
14. The chip according to claim 12, wherein The second storage space includes: A third storage space and a fourth storage space, wherein the storage capacity of the third storage space is smaller than the storage capacity of the fourth storage space.
15. The chip according to claim 14, characterized in that, The fourth storage space includes a random access memory (RAM).
16. An electronic device, characterized in that, Comprising: A processor; A memory for storing processor-executable instructions; Wherein, the processor is configured to: Implement the steps of the method according to any one of claims 1-9.
17. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the program instruction is executed by the processor, it implements the steps of the method according to any one of claims 1-9.