Memory device for supporting new command input scheme and operating method thereof

Abstract

A memory device including a row pin and a column pin and a method of operating the same are provided, the method including receiving a first activation command through the row pin during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pin during one cycle of the clock signal, receiving a first pre-charge command through the row pin during 0.5 cycles of the clock signal corresponding to a rising edge of the clock signal, receiving a second activation command through the row pin during 1.5 cycles of the clock signal, and receiving a second read command or a second write command through the column pin during one cycle of the clock signal, and receive a second pre-charge command through the row pin during 0.5 cycles of the clock signal corresponding to a falling edge of the clock signal.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202110072030.3, titled "Memory Device for Supporting New Command Input Scheme and Its Operating Method", with a filing date of January 19, 2021.

[0002] Cross - reference to related applications

[0003] This application claims the priority of Korean Patent Application Nos. 10 - 2020 - 0008110 and 10 - 2020 - 0103438, filed on January 21, 2020 and August 18, 2020 respectively, the disclosures of which are incorporated herein by reference in their entireties. Technical field

[0004] The inventive concept relates to a semiconductor device, and more particularly, to a memory device for supporting a new command input scheme and its operating method. Background art

[0005] Electronic devices such as smart phones, graphics accelerators, and artificial intelligence (AI) accelerators process data by using a memory device such as dynamic random access memory (DRAM). As the amount of data to be processed by electronic devices increases, memory devices with high capacity and bandwidth are required. In particular, for high - speed data processing, the use of memory devices providing high - throughput input / output with a multi - channel interface method (such as the high - bandwidth memory (HBM) standard) has increased. With the increasing use of such memory devices, an efficient input / output interface method is required between a host device (e.g., a memory controller) and the memory device. Summary of the invention

[0006] According to an aspect of the inventive concept, a method of operating a memory device is provided. The memory device includes a row pin for receiving a row command and a column pin for receiving a column command different from the row command. The method includes: receiving a first activation command for one bank through the row pin during one and a half (1.5) cycles of a clock signal; after receiving the first activation command, receiving a first read command or a first write command for the one bank through the column pin during one (1) cycle of the clock signal; after receiving the first read command or the first write command, receiving a first precharge command for the one bank through the row pin during a half (0.5) cycle of the clock signal corresponding to the rising edge of the clock signal; receiving a second activation command for the one bank through the row pin during 1.5 cycles of the clock signal; after receiving the second activation command, receiving a second read command or a second write command for the one bank through the column pin during 1 cycle of the clock signal; and after receiving the second read command or the second write command, receiving a second precharge command for the one bank through the row pin during a half (0.5) cycle of the clock signal corresponding to the falling edge of the clock signal.

[0007] According to an aspect of the inventive concept, a memory device is provided, including: a clock pin for receiving a clock signal; a row pin for receiving a row command; a column pin for receiving a column command different from the row command; and an interface circuit for receiving a first activation command through the row pin during 1.5 cycles of 2 cycles of the clock signal, receiving a first precharge command during a remaining half (0.5) cycle corresponding to the falling edge of the clock signal, receiving a first write command or a first read command through the column pin during 1 cycle of the 2 cycles, and receiving a second write command or a second read command during a remaining 1 cycle.

[0008] According to an aspect of the inventive concept, there is provided a memory device including: a clock pin that receives a clock signal; a row pin that receives a row command; a column pin that receives a column command different from the row command; and an interface circuit that, during a first period including a first rising edge and a first falling edge of the clock signal, receives a first row command through the row pin at the first rising edge of the clock signal, receives a second row command at the first falling edge of the clock signal, receives a first column command through the column pin during the first period, and during a second period including a second rising edge and a second falling edge of the clock signal, receives a third row command through the row pin at the second rising edge of the clock signal, receives a fourth row command at the second falling edge of the clock signal, and receives a second column command through the column pin during the second period. The second row command and the third row command are specific commands representing the same operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing a memory system according to an example embodiment;

[0011] Figure 2 is a block diagram of a Figure 1 memory device according to an example embodiment;

[0012] Figure 3A , Figure 3B and Figure 3C show examples of timing diagrams of a Figure 1 memory device receiving commands according to an example embodiment;

[0013] Figure 4A and Figure 4B show examples of timing diagrams of a Figure 1 memory device receiving commands for one bank according to an example embodiment;

[0014] Figure 5 is a flowchart showing the operation of a Figure 1 memory device according to an example embodiment;

[0015] Figure 6 is a block diagram of a Figure 2 control logic circuit according to an example embodiment;

[0016] Figure 7 is a block diagram showing a stacked memory device according to an example embodiment;

[0017] Figure 8 is a according to an example embodimentFigure 7 Block diagram of a stacked memory device;

[0018] Figure 9 is a block diagram showing an enlarged example of a Figure 8 stacked memory device according to an exemplary embodiment;

[0019] Figure 10 is a block diagram showing an enlarged example of a Figure 8 stacked memory device according to an exemplary embodiment;

[0020] Figure 11A and Figure 11B shows an example of a timing diagram of a Figure 7 stacked memory device receiving a command according to an exemplary embodiment;

[0021] Figure 12A is a table showing row commands according to an exemplary embodiment;

[0022] Figure 12B is a table showing an example of column commands according to an exemplary embodiment;

[0023] Figure 13 is a circuit diagram of a control logic circuit for sensing a precharge command based on a Figure 12A row command according to an exemplary embodiment;

[0024] Figure 14 is a diagram showing a semiconductor package according to an exemplary embodiment;

[0025] Figure 15 is a diagram showing an implementation example of a semiconductor package according to an exemplary embodiment;

[0026] Figure 16 is a view showing a semiconductor package according to another exemplary embodiment; and

[0027] Figure 17 is a block diagram showing a computing system according to an exemplary embodiment. Detailed Description

[0028] Hereinafter, exemplary embodiments of the inventive concept will be described so that those skilled in the art can easily implement the inventive concept.

[0029] Figure 1 is a block diagram showing a memory system 10 according to an exemplary embodiment. Refer to Figure 1, the memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may control the overall operation of the memory device 200. The memory controller 100 may control the memory device 200 such that data is output from or stored in the memory device 200, and the memory controller 100 may be implemented as part of a system on chip (SoC). However, the example embodiments are not limited thereto.

[0030] The memory controller 100 may include a host interface circuit 110 and clock pins CK_P', row pins R_P', column pins C_P', and data pins D_P'. The host interface circuit 110 may send a clock signal CK to the memory device 200 through the clock pin CK_P'. The clock signal CK may periodically switch between a high level and a low level. For example, the clock signal CK may be one of the differential signals in a differential pair.

[0031] The host interface circuit 110 may send a row command CMD_r and / or a row address ADD_r (hereinafter referred to as the row command CMD_r / row address ADD_r) to the memory device 200 through the row pins R_P'. For example, the row command CMD_r may include an activate command ACT and a precharge command PRE. For example, the row address ADD_r may include a bank address corresponding to the row command CMD_r. The host interface circuit 110 may send the row command CMD_r / row address ADD_r to the memory device 200 based on the switching timing of the clock signal CK.

[0032] The host interface circuit 110 may send a column command CMD_c and / or a column address ADD_c (hereinafter referred to as the column command CMD_c / column address ADD_c) to the memory device 200 through the column pins C_P'. For example, the column command CMD_c may include a read command RD and a write command WR. The row command CMD_r and the column command CMD_c may include different commands. For example, the column address ADD_c may include a bank address corresponding to the column command CMD_c. The host interface circuit 110 may send the column command CMD_c / column address ADD_c to the memory device 200 based on the switching timing of the clock signal CK.

[0033] The host interface circuit 110 may send data DATA to the memory device 200 through the data pins D_P'. The host interface circuit 110 may send the data DATA to the memory device 200 based on the switching timing of an additional data clock signal (e.g., a write data strobe signal WDQS). The host interface circuit 110 may receive the data DATA from the memory device 200 through the data pins D_P'.

[0034] The memory device 200 may operate under the control of the memory controller 100. For example, the memory device 200 may output stored data under the control of the memory controller 100, or may store data received from the memory controller 100.

[0035] The memory device 200 may include a memory interface circuit 210 and a bank array 220. The memory device 200 may also include a clock pin CK_P, a row pin R_P, a column pin C_P, and a data pin D_P corresponding to the clock pin CK_P', row pin R_P', column pin C_P', and data pin D_P' of the memory controller 100. The memory interface circuit 210 may receive a clock signal CK from the memory controller 100 through the clock pin CK_P.

[0036] The memory interface circuit 210 may receive a row command CMD_r / row address ADD_r from the memory controller 100 through the row pin R_P. For example, the memory interface circuit 210 may sample the row command CMD_r / row address ADD_r based on the switching timing of the clock signal CK. According to an exemplary embodiment, the row command CMD_r / row address ADD_r may be transmitted to the memory device 200 through multiple signal lines. In this case, the row pin R_P may include multiple pins corresponding to the multiple signal lines. For example, the row pin R_P may include 10 pins. However, the inventive concept is not limited thereto.

[0037] The memory interface circuit 210 may receive a column command CMD_c / column address ADD_c from the memory controller 100 through the column pin C_P. For example, the memory interface circuit 210 may sample the column command CMD_c / column address ADD_c based on the switching timing of the clock signal CK. According to an exemplary embodiment, the column command CMD_c / column address ADD_c may be transmitted to the memory device 200 through multiple signal lines. In this case, the column pin C_P may include multiple pins corresponding to the multiple signal lines. For example, the column pin C_P may include 8 pins. However, the inventive concept is not limited thereto.

[0038] The memory interface circuit 210 may receive data DATA from the memory controller 100 through the data pin D_P. The memory interface circuit 210 may sample the data DATA based on the switching timing of an additional data clock signal (e.g., write data strobe signal WDQS). The memory interface circuit 210 may send the data DATA to the memory controller 100 through the data pin D_P. For example, the memory interface circuit 210 may send the data DATA to the memory controller 100 based on the switching timing of an additional data clock signal (e.g., write data strobe signal WDQS). According to an example embodiment, the data DATA may be received by or sent from the memory device 200 through multiple signal lines. In this case, the data pin D_P may include multiple pins corresponding to the multiple signal lines. For example, the data pin D_P may include 64 or 128 pins. However, the inventive concept is not limited thereto.

[0039] The memory interface circuit 210 may generate a control signal iCTRL based on the row command CMD_r and the column command CMD_c received from the memory controller 100, and may control the operation of the banks of the bank array 220 based on the control signal iCTRL.

[0040] The bank array 220 may include one or more banks. A bank may include multiple memory cells connected to word lines and bit lines. For example, the multiple memory cells may be dynamic random access memory (DRAM) cells. In this case, the host interface circuit 110 and the memory interface circuit 210 may communicate with input and output signals based on one of standards such as the double data rate (DDR) standard, the low power double data rate (LPDDR) standard, the graphics double data rate (GDDR) standard, the wide I / O standard, the high bandwidth memory (HBM) standard, and the hybrid memory cube (HMC) standard. However, the inventive concept is not limited thereto. The memory cells may be at least one of various memory cells, such as static RAM (SRAM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0041] In response to the control signal iCTRL, the banks of the bank array 220 may write the data DATA into the memory cells or read the data DATA from the memory cells.

[0042] According to an example embodiment, the host interface circuit 110 may transmit a specific command (e.g., a precharge command PRE) of the row command CMD_r at the rising edge and / or falling edge of the clock signal CK. The host interface circuit 110 may start transmitting the specific command at a timing corresponding to the rising edge and / or falling edge of the clock signal CK. For example, the host interface circuit 110 may transmit the specific command at a timing corresponding to the rising edge of the clock signal CK in a first time period, and may transmit the specific command at a timing corresponding to the falling edge of the clock signal CK in a second time period. The host interface circuit 110 may transmit the remaining commands of the row command CMD_r other than the specific command and the column command CMD_c at the rising edge of the clock signal CK. The host interface circuit 110 may start transmitting the remaining commands of the row command CMD_r and the column command CMD_c at a timing corresponding to the rising edge of the clock signal CK.

[0043] According to an example embodiment, although the specific command is transmitted from the memory controller 100 at any timing, the memory interface circuit 210 may still sense the specific command. Although the specific command is received at a timing corresponding to the rising edge and / or falling edge of the clock signal CK, the memory interface circuit 210 may still sense the specific command. For example, the memory interface circuit 210 may sense the specific command transmitted at each of the two timings by decoding the row command CMD_r.

[0044] Hereinafter, for convenience, transmitting or receiving a specific command at the rising edge and / or falling edge of the clock signal CK may mean starting to transmit or receive the specific command at a timing corresponding to the rising edge and / or falling edge of the clock signal CK.

[0045] Figure 2 is Figure 1 An example block diagram of the memory device 200. Refer to Figure 2 , the memory device 200 may include a bank array 220, a control logic circuit 230, and an input / output (I / O) circuit 240. The bank array 220 may include a plurality of banks 220a to 220n. Each of the plurality of banks 220a to 220n may include a memory cell array 221, a row decoder 222, a column decoder 223, and a sense amplifier / write driver (SA / WD) 224. The control logic circuit 230 and the input / output circuit 240 may be included in Figure 1 the memory interface circuit 210 of

[0046] According to an exemplary embodiment, a plurality of banks 220a to 220n may be divided into a plurality of bank groups. For example, each bank group may include four banks. However, the inventive concept is not limited thereto. When the plurality of banks 220a to 220n are divided into a plurality of bank groups, timing parameters for access within the same bank group may be set to be different from timing parameters for accessing different bank groups.

[0047] The memory cell array 221 may include a plurality of memory cells. The plurality of memory cells may be formed at intersections of word lines WL and bit lines BL.

[0048] The row decoder 222 may be connected to the memory cell array 221 through the word lines WL. The row decoder 222 may control the voltage of the word lines WL in response to the control of the control logic circuit 230.

[0049] The column decoder 223 may be connected to the memory cell array 221 through the bit lines BL. The column decoder 223 may select at least one of the bit lines BL in response to the control of the control logic circuit 230. The sense amplifier / write driver 224 may sense or control the voltage or current of the bit line selected by the column decoder 223.

[0050] The control logic circuit 230 may receive a row command CMD_r / row address ADD_r and a column command CMD_c / column address ADD_c from Figure 1 the memory controller 100. The control logic circuit 230 may decode the row command CMD_r / row address ADD_r and the column command CMD_c / column address ADD_c. According to an exemplary embodiment, the control logic circuit 230 may decode the row command CMD_r through a row command decoder and may decode the column command CMD_c through a column command decoder. For example, the control logic circuit 230 may sense an activation command ACT or a precharge command PRE by decoding the row command CMD_r. The control logic circuit 230 may sense a write command WR or a read command RD by decoding the column command CMD_c.

[0051] The control logic circuit 230 may generate control signals for controlling a plurality of memory banks 220a to 220n based on the decoding result. For example, when an activation command ACT is sensed, the control logic circuit 230 may generate a control signal for activating a specific word line of a specific memory bank. In this case, a specific word line of a specific memory bank may be activated according to the row address ADD_r corresponding to the activation command ACT. For example, when a precharge command PRE is sensed, the control logic circuit 230 may generate a control signal for precharging at least one memory bank. In this case, according to the row address ADD_r corresponding to the precharge command PRE, a specific memory bank or all memory banks may be precharged. For example, when a write command WR or a read command RD is sensed, the control logic circuit 230 may generate a control signal to write data DATA to a specific memory bank or read data DATA from a specific memory bank. In this case, according to the column address ADD_c corresponding to the write command WR or the read command RD, data DATA may be written to or read from a memory cell corresponding to the column address ADD_c.

[0052] According to an exemplary embodiment, the control logic circuit 230 may include a specific command decoding circuit for decoding a specific command (e.g., a precharge command PRE) received at the rising edge and / or falling edge of a clock signal CK in a row command CMD_r. Therefore, although the row command CMD_r indicating a specific command is received at any timing, the control logic circuit 230 may sense the specific command.

[0053] The input / output circuit 240 may send data DATA to an external device (e.g., the memory controller 100) and receive data DATA from the external device (e.g., the memory controller 100) through a plurality of data lines. The input / output circuit 240 may include an input / output buffer for temporarily storing read data provided from a plurality of memory banks 220a to 220n and write data provided from an external device.

[0054] Figures 3A to 3C Illustrating according to an exemplary embodiment Figure 1 of an example timing diagram of a memory device receiving commands. Specifically, Figure 3A is a timing diagram showing the reception of a precharge command PRE at the rising edge of a clock signal CK_c, Figure 3B is a timing diagram showing the reception of a precharge command PRE at the falling edge of a clock signal CK_c. Figure 3C is a timing diagram showing the reception of a precharge command PRE at both the rising edge and the falling edge of a clock signal CK_c.

[0055] Referring to Figures 3A to 3C, receive the clock signals CK_c and CK_t as a differential pair through two signal lines. For example, the clock signal CK_c can correspond to the Figure 1 clock signal CK. Receive the row command CMD_r and the column command CMD_c based on the switching timing of the clock signals CK_c and CK_t. Receive the activation command ACT and the precharge command PRE as the row command CMD_r, and receive the write command WR and the read command RD as the column command CMD_c. Receive the activation command ACT during 1.5 cycles corresponding to two rising edges and one falling edge of the clock signal CK_c, and receive the precharge command PRE during 0.5 cycles corresponding to one rising edge or one falling edge of the clock signal CK_c. Receive the write command WR and the read command RD during 1 cycle corresponding to one rising edge and one falling edge of the clock signal CK_c.

[0056] Refer to Figure 1 and Figure 3A , the memory device 200 can receive the activation command ACTa and the write command WR at the first time point t1 corresponding to the rising edge of the clock signal CK_c. The memory device 200 can receive the activation command ACTa and the write command WR in parallel at the first time point t1. In this case, the bank address corresponding to the activation command ACTa can be different from the bank address corresponding to the write command WR. For example, the activation command ACTa can correspond to the first bank address BA1, and the write command WR can correspond to the second bank address BA2. Since the activation command ACTa is received during 1.5 cycles, the activation command ACTa can be received until the second time point t2.

[0057] The memory device 200 can receive the read command RD at the second time point t2. The memory device 200 can receive the activation command ACTa and the read command RD in parallel at the second time point t2. In this case, the bank address corresponding to the activation command ACTa can be different from the bank address corresponding to the read command RD. For example, the activation command ACTa can correspond to the first bank address BA1, and the read command RD can correspond to the third bank address BA3.

[0058] As Figure 3AAs shown, when the read command RD is received without delay after the write command WR is fully received (i.e., when the time interval between the write command WR and the read command RD is 1tCK (i.e., 1 cycle of the clock signal CK_c)), the bank address corresponding to the write command WR can be different from the bank address corresponding to the read command RD. For example, the write command WR can correspond to the second bank address BA2, and the read command RD can correspond to the third bank address BA3. For example, when the bank is divided into a plurality of bank groups, the bank group corresponding to the write command WR can be different from the bank group corresponding to the read command RD. Therefore, the bank addresses corresponding to the activation command ACTa, the write command WR, and the read command RD can be different from each other.

[0059] The memory device 200 may not receive the row command CMD_r indicating a specific operation at the third time point t3 corresponding to the falling edge of the clock signal CK_c. For example, the memory device 200 may receive a no-operation row command (e.g., Figure 12A RNOP) indicating no operation at the third time point t3.

[0060] The memory device 200 may receive the precharge command PREb at the fourth time point t4 corresponding to the rising edge of the clock signal CK_c. After the activation command ACTa is fully received, the precharge command PREb may be received with a delay of 0.5 cycles. In this case, the bank address corresponding to the activation command ACTa can be different from the bank address corresponding to the precharge command PREb. For example, the activation command ACTa can correspond to the first bank address BA1, and the precharge command PREb can correspond to the fourth bank address BA4. However, the inventive concept is not limited thereto. The precharge command PREb can correspond to the second bank address BA2 corresponding to the write command WR received at the first time point t1 or the third bank address BA3 corresponding to the read command RD received at the second time point t2.

[0061] The memory device 200 may not receive the row command CMD_r indicating a specific operation at the fifth time point t5 corresponding to the falling edge of the clock signal CK_c. For example, the memory device 200 may receive the no-operation row command RNOP at the fifth time point t5. The memory device 200 may receive the activation command ACTc at the sixth time point t6 corresponding to the rising edge of the clock signal CK_c, and may receive the precharge command PREd at the seventh time point t7 corresponding to the rising edge of the clock signal CK_c.

[0062] As described above, when receiving a precharge command PRE at the rising edge of the clock signal CK_c, the precharge command PRE can be received after fully receiving the activation command ACT with a delay (e.g., 0.5 cycles).

[0063] Reference Figure 1 and Figure 3B , the memory device 200 can receive an activation command ACTa and a write command WR at a first time point t1 corresponding to the rising edge of the clock signal CK_c, and can receive an activation command ACTa and a read command RD at a second time point t2.

[0064] The memory device 200 can receive a precharge command PREb at a third time point t3 corresponding to the falling edge of the clock signal CK_c. The precharge command PREb can be received without delay after fully receiving the activation command ACTa. Therefore, at the third time point t3, the precharge command PREb and the read command RD can be received in parallel.

[0065] According to Figure 3B an example embodiment, the bank address corresponding to the activation command ACTa can be different from the bank address corresponding to the write command WR. Additionally, the bank address corresponding to the activation command ACTa, the bank address corresponding to the precharge command PREb, and the bank address corresponding to the read command RD can be different from each other. For example, the activation command ACTa can correspond to a first bank address BA1, the write command WR can correspond to a second bank address BA2, the read command RD can correspond to a third bank address BA3, and the precharge command PREb can correspond to a fourth bank address BA4. However, the inventive concept is not limited thereto. The precharge command PREb can correspond to the second bank address BA2 corresponding to the write command WR received at the first time point t1.

[0066] After fully receiving the precharge command PREb, the memory device 200 can receive an activation command ACTc without delay at a fourth time point t4 corresponding to the rising edge of the clock signal CK_c. After fully receiving the activation command ACTc, the memory device 200 can receive a precharge command PREd without delay at a fifth time point t5 corresponding to the falling edge of the clock signal CK_c.

[0067] As described above, when receiving a precharge command PRE at the falling edge of the clock signal CK_c, the precharge command PRE can be received without delay after fully receiving the activation command ACT.

[0068] Reference Figure 1 and Figure 3C, the memory device 200 may receive an activation command ACTa from a first time point t1 corresponding to the rising edge of the clock signal CK_c to a second time point t2. The memory device 200 may receive a write command WR from the second time point t2 to a third time point t3. The memory device 200 may receive a precharge command PREb at the third time point t3 corresponding to the falling edge of the clock signal CK_c. Accordingly, during one cycle of the clock signal CK_c corresponding to the second time point t2 and the third time point t3, the activation command ACTa, the precharge command PREb, and the write command WR may be received. In this case, the bank address corresponding to the activation command ACTa, the bank address corresponding to the precharge command PREb, and the bank address corresponding to the write command WR may be different from each other. For example, the activation command ACTa may correspond to a first bank address BA1, the write command WR may correspond to a second bank address BA2, and the precharge command PREb may correspond to a third bank address BA3.

[0069] After completely receiving the precharge command PREb, the memory device 200 may receive an activation command ACTc without delay at a fourth time point t4. After completely receiving the activation command ACTc, the memory device 200 may receive a no-operation row command RNOP at a fifth time point t5 corresponding to the falling edge of the clock signal CK_c, and may receive a precharge command PREd at a sixth time point t6 corresponding to the rising edge of the clock signal CK_c. After completely receiving the activation command ACTc, the precharge command PREd may be received with a delay of 0.5 cycles. After completely receiving the precharge command PREd, the memory device 200 may receive a no-operation row command RNOP at a seventh time point t7 corresponding to the falling edge of the clock signal CK_c. The memory device 200 may receive a read command RD from the sixth time point t6 to the seventh time point t7. Accordingly, during one cycle of the clock signal CK_c corresponding to the sixth time point t6 and the seventh time point t7, the precharge command PREd, the no-operation row command RNOP, and the read command RD may be received.

[0070] As described above, when receiving the precharge command PRE at the rising edge and the falling edge of the clock signal CK_c, the precharge command PRE may be received without delay or with a delay after completely receiving the activation command ACT.

[0071] In Figures 3A to 3C , receiving the precharge command PRE for one bank is shown. However, the inventive concept is not limited thereto. For example, the memory device 200 may receive the precharge command PRE corresponding to all banks at the rising edge and / or the falling edge of the clock signal CK_c.

[0072] As described above, when the activation command ACT is received during 1.5 cycles of the clock signal CK_c and the precharge command PRE is received during 0.5 cycles of the clock signal CK_c, the precharge command PRE can be received at the rising edge and / or falling edge of the clock signal CK_c. The memory device 200 can receive the precharge command PRE selectively transmitted by the memory controller 100 at a timing between the rising edge and the falling edge of the clock signal CK_c.

[0073] As described above, when the precharge command PRE is received at the falling edge of the clock signal CK_c, the activation command ACT can be fully received during 1.5 cycles, the precharge command PRE can be received without delay during 0.5 cycles, and after the precharge command PRE is fully received, the activation command ACT can be received without delay. Additionally, at the timing of receiving the activation command ACT or the precharge command PRE, the write command WR or the read command RD can be received in parallel. Therefore, when performing memory accesses continuously through operations such as bank interleaving or bank group interleaving, commands corresponding to multiple banks can be received quickly. Thus, the operation speed of the memory device 200 can be increased.

[0074] Figure 4A and Figure 4B shows an example of a timing diagram of the memory device 200 according to an exemplary embodiment receiving commands for one bank. Specifically, Figure 1 is a timing diagram showing the reception of the precharge command PRE1 at the rising edge of the clock signal CK_c, and Figure 4A is a timing diagram showing the reception of the precharge command PRE2 at the falling edge of the clock signal CK_c. Figure 4B

[0075] Figure 4A ​​, during 1.5 cycles of the clock signal CK_c from the first time point t1 to the second time point t2, the memory device 200 may receive an activation command ACT1. The memory device 200 may receive a read command RD1 or a write command WR1 at a third time point t3 according to the activation command ACT1. After completely receiving the read command RD1 or the write command WR1, the memory device 200 may receive a precharge command PRE1 during a 0.5-cycle period at a fourth time point t4 corresponding to the rising edge of the clock signal CK_c. In this case, the minimum time interval tRASa between the activation command ACT1 and the precharge command PRE1 (i.e., the minimum time interval for sending the precharge command PRE1 after sending the activation command ACT1) may correspond to the time interval between the second time point t2 corresponding to the rising edge of the clock signal CK_c and the fourth time point t4 corresponding to the rising edge of the clock signal CK_c. For example, the minimum time interval tRASa may be determined by a standard.

[0076] After completely receiving the precharge command PRE1, the memory device 200 may receive an activation command ACTa from a fifth time point t5 to a sixth time point t6. In this case, the minimum time interval tRPa between the precharge command PRE1 and the activation command ACTa (i.e., the minimum time interval for sending the activation command ACTa after sending the precharge command PRE1) may correspond to the time interval between the fourth time point t4 corresponding to the rising edge of the clock signal CK_c and the sixth time point t6 corresponding to the rising edge of the clock signal CK_c. For example, the minimum time interval tRPa may be determined by a standard.

[0077] As described above, when two activation commands ACT1 and ACTa are received for the same bank, the minimum time interval tRCa between the activation command ACT1 and the activation command ACTa (i.e., the minimum time interval for sending the activation command ACTa after sending the activation command ACT1) may correspond to the time interval between the second time point t2 and the sixth time point t6. For example, the minimum time interval tRCa may be determined by a standard.

[0078] Reference Figure 4B, the memory device 200 may receive an activation command ACT2 during 1.5 cycles of the clock signal CK_c from the seventh time point t7 to the eighth time point t8. The memory device 200 may receive a read command RD2 or a write command WR2 according to the activation command ACT2 at the ninth time point t9. After completely receiving the read command RD2 or the write command WR2, the memory device 200 may receive a precharge command PRE2 during 0.5 cycles at the tenth time point t10 corresponding to the falling edge of the clock signal CK_c. In this case, the minimum time interval tRASb between the activation command ACT2 and the precharge command PRE2 (i.e., the minimum time interval for sending the precharge command PRE2 after sending the activation command ACT2) may correspond to the time interval between the eighth time point t8 corresponding to the rising edge of the clock signal CK_c and the tenth time point t10 corresponding to the falling edge of the clock signal CK_c. For example, the minimum time interval tRASb may be determined by a standard. In this case, Figure 4A the minimum time interval tRASa may be different from Figure 4B the minimum time interval tRASb. For example, the minimum time interval tRASa may be 0.5 cycles of the clock signal CK_c larger than the minimum time interval tRASb.

[0079] After completely receiving the precharge command PRE2, the memory device 200 may receive an activation command ACTb from the eleventh time point t11 to the thirteenth time point t13. In this case, the minimum time interval tRPb between the precharge command PRE2 and the activation command ACTb (i.e., the minimum time interval for sending the activation command ACTb after sending the precharge command PRE2) may correspond to the time interval between the tenth time point t10 corresponding to the falling edge of the clock signal CK_c and the twelfth time point t12 corresponding to the falling edge of the clock signal CK_c. For example, the minimum time interval tRPb may be determined by a standard. In this case, Figure 4A the minimum time interval tRPa may be equal to Figure 4B the minimum time interval tRPb.

[0080] As described above, when two activation commands ACT2 and ACTb are received for the same bank, the minimum time interval tRCb between the activation command ACT2 and the activation command ACTb (i.e., the minimum time interval for sending the activation command ACTb after sending the activation command ACT2) may correspond to the time interval between the eighth time point t8 and the thirteenth time point t13. For example, the minimum time interval tRCb may be determined by a standard. In this case, Figure 4A the minimum time interval tRCa may be equal to Figure 4B the minimum time interval tRCb. However, the inventive concept is not limited thereto.

[0081] Figure 5 is a flowchart illustrating exemplary operations of Figure 1 a memory device. Specifically, Figure 5 illustrates memory access operations for one bank of the memory device 200 as referenced Figure 4A and Figure 4B described. Referring to Figure 1 and Figure 5 , in operation S201, the memory device 200 may receive an activate command ACT via a row pin R_P. In this case, the memory device 200 may also receive a row address ADD_r including a specific bank address together with the activate command ACT. The memory device 200 may activate a specific word line of a specific bank in response to the activate command ACT.

[0082] In operation S202, the memory device 200 may receive a read command RD or a write command WR via a column pin C_P. In this case, the memory device 200 may also receive a column address ADD_c including a specific bank address together with the read command RD or the write command WR. The memory device 200 may read data DATA from the memory cells of a specific bank or write data DATA into the memory cells of a specific bank in response to the read command RD or the write command WR.

[0083] In operation S203, the memory device 200 may receive a precharge command PRE via a row pin R_P at the rising edge or the falling edge of a clock signal CK. The memory device 200 may also receive a row address ADD_r including a specific bank address together with the precharge command PRE. The memory device 200 may precharge the memory cells of a specific bank in response to the precharge command PRE. For example, as Figures 3A to 4B shown, when the precharge command PRE is received during 0.5 cycles of the clock signal CK, the memory device 200 may fully receive the precharge command PRE at the rising edge or the falling edge of the clock signal CK. For another example, when the precharge command PRE is received during a cycle of the clock signal CK greater than 0.5 cycles, the memory device 200 may start to receive the precharge command PRE at the rising edge or the falling edge of the clock signal CK.

[0084] Figure 6 is Figure 2 a block diagram of the control logic circuit 230 of Figure 6, the control logic circuit 230 may include a row command decoder 230a and a column command decoder 230b. The row command decoder 230a may decode the row command CMD_r received through the row pin R_P based on the clock signal CK received through the clock pin CK_P. The column command decoder 230b may decode the column command CMD_c received through the column pin C_P based on the clock signal CK received through the clock pin CK_P.

[0085] The row command decoder 230a may decode a specific command (e.g., a precharge command PRE) received at the rising edge and / or falling edge of the clock signal CK in the row command CMD_r. The row command decoder 230a may include a first specific command decoder 231, a second specific command decoder 232, a comparator 233, and an inverter 234 to decode the specific command.

[0086] The first specific command decoder 231 may receive the clock signal CK and the row command CMD_r, and may output a first decoding result DR1 indicating whether the row command CMD_r is a specific command based on the rising edge of the clock signal CK.

[0087] The second specific command decoder 232 may receive the signal obtained by inverting the clock signal CK through the inverter 234 and the row command CMD_r. Thus, the second specific command decoder 232 may output a second decoding result DR2 indicating whether the row command CMD_r is a specific command based on the falling edge of the clock signal CK. In Figure 6 , the clock signal CK is shown as being input to the second specific command decoder 232 through the inverter 234. However, the inventive concept is not limited thereto. For example, as described in reference Figures 3A to 3C , when the clock signal CK is formed of a differential pair, the clock signal CK_c may be input to the first specific command decoder 231, and the clock signal CK_t may be input to the second specific command decoder 232.

[0088] The comparator 233 may generate an internal command iCMD by comparing the first decoding result DR1 with the second decoding result DR2. For example, when the first decoding result DR1 or the second decoding result DR2 indicates that the row command CMD_r is a specific command, the comparator 233 may generate an internal command iCMD corresponding to the specific command. Thus, the memory device 200 may perform a corresponding operation in response to the internal command iCMD. For example, when the internal command iCMD indicates a precharge command PRE, the memory device 200 may perform a precharge operation.

[0089] As described above, the control logic circuit 230 may sense a specific command received at the rising edge of the clock signal CK and a specific command received at the falling edge of the clock signal CK through a specific command decoder. Additionally, as described in Figures 3A to 3C , although the row command CMD_r and the column command CMD_c are received in parallel, the control logic circuit 230 may decode the row command CMD_r and the column command CMD_c in parallel through the row command decoder 230a and the column command decoder 230b.

[0090] Figure 7 is a block diagram showing a stacked memory device 300 according to an exemplary embodiment. Referring to Figure 7 , the stacked memory device 300 may correspond to the memory device 200 of Figure 1 . The stacked memory device 300 may include a buffer die 310 and first to fourth core dies 320 to 350. For example, the buffer die 310 may be referred to as an interface die, a base die, a logic die, or a master die, and each of the first to fourth core dies 320 to 350 may be referred to as a memory die or a slave die. In Figure 7 , the stacked memory device 300 is shown as including four core dies, namely, the first to fourth core dies 320 to 350. However, the number of core dies may vary. For example, the stacked memory device 300 may include 8, 12, or 16 core dies.

[0091] The buffer die 310 and the first to fourth core dies 320 to 350 may be stacked through through-silicon vias (TSVs) and may be electrically connected to each other. Accordingly, the stacked memory device 300 may have a three-dimensional memory structure in which a plurality of dies, namely, the first to fourth core dies 320 to 350, are stacked. For example, the stacked memory device 300 may be implemented based on the HBM standard or the HMC standard.

[0092] The stacked memory device 300 may support a plurality of functionally independent channels (or vaults). For example, as in Figure 7As shown, the stacked memory device 300 may support the first channel CH0 to the sixteenth channel CH15. When each of the first channel CH0 to the sixteenth channel CH15 supports 64 data paths (i.e., when 64 data pins are provided for each of the first channel CH0 to the sixteenth channel CH15), the stacked memory device 300 including the first channel CH0 to the sixteenth channel CH15 may support 1,024 data paths. However, the inventive concept is not limited thereto. The stacked memory device 300 may support not less than 1,024 data paths and various numbers of channels (e.g., eight channels). For example, when the stacked memory device 300 supports eight channels and each of the eight channels supports 128 data paths, the stacked memory device 300 may support 1,024 data paths.

[0093] Each of the first core die 320 to the fourth core die 350 may support at least one channel. For example, as Figure 7 shown, each of the first core die 320 to the fourth core die 350 may support four channels CH0 to CH3, CH4 to CH7, CH8 to CH11, or CH12 to CH15. In this case, the first core die 320 to the fourth core die 350 may support different channels. However, the inventive concept is not limited thereto. At least two of the first to fourth core dies may support the same channel. For example, when the stacked memory device 300 includes eight core dies, one of the four core dies forming one stack and one of the four core dies forming another stack may support the same channel. In this case, the core dies supporting the same channel may be distinguished by a stack ID (SID).

[0094] Each channel may include an independent command and data interface. For example, the channels may be independently clock-controlled based on independent timing requirements and may be asynchronous with each other.

[0095] Each channel may include a plurality of banks 301. For example, the banks 301 included in one channel may correspond to Figure 1 the memory bank array 220. Each of the plurality of banks 301 may include memory cells connected to word lines and bit lines, a row decoder, a column decoder, and sense amplifiers. For example, each of the first channel CH0 to the sixteenth channel CH15 may include 32 banks 301. However, the inventive concept is not limited thereto. Each of the first channel CH0 to the sixteenth channel CH15 may include not less than eight banks 301. In Figure 7In [the figure], it is shown that the memory banks 301 included in one channel are included in one core die. However, the memory banks 301 included in one channel may be distributed among multiple core dies. For example, when two of the first to fourth core dies support the first channel CH0, the memory banks 301 included in the first channel CH0 may be distributed among the two core dies.

[0096] According to an exemplary embodiment, the memory banks 301 included in one channel may be divided into multiple memory bank groups. For example, each of the multiple memory bank groups may include four memory banks. However, the inventive concept is not limited thereto.

[0097] According to an exemplary embodiment, one channel may be divided into two independently operating pseudo-channels. For example, the pseudo-channels may share the command and clock inputs of the channel (e.g., the clock signal CK and / or the clock enable signal CKE), but may decode and execute commands independently. For example, when one channel supports 64 data paths, each pseudo-channel may support 32 data paths. For example, when one channel includes 32 memory banks 301, each pseudo-channel may include 16 memory banks 301.

[0098] The buffer die 310 and the first to fourth core dies 320 - 350 may include TSV regions 302. The TSVs formed to pass through the first to fourth core dies 320 - 350 may be arranged in the TSV regions 302. The buffer die 310 may send various signals to the first to fourth core dies 320 - 350 via the TSVs, and receive various signals from the first to fourth core dies 320 - 350. The first to fourth core dies 320 - 350 may send signals to the buffer die 310 and other core dies via the TSVs, and receive signals from the buffer die 310 and other core dies. In this case, signals may be independently sent and received via the corresponding TSVs by channel. For example, when an external host device (e.g., Figure 1 the memory controller 100) sends a data signal to the first channel CH0 to store the data in the storage units of the first channel CH0, the buffer die 310 may store the data in the storage units of the first channel CH0 by sending the data signal to the first core die 320 via the TSV corresponding to the first channel CH0.

[0099] According to an exemplary embodiment, in order to send signals via the TSVs, the power supply voltage VDDQL may be used. The power supply voltage VDDQL may be less than the power supply voltage VDDQ for the overall operation of the buffer die 310. For example, the power supply voltage VDDQ may be 1.1V and the power supply voltage VDDQL may be 0.4V.

[0100] The buffer die 310 may include a physical layer (PHY) 311. The physical layer 311 may include interface circuitry for communicating with an external host device. According to an example embodiment, the physical layer 311 may include interface circuitry corresponding to each of the first channel CH0 to the sixteenth channel CH15. For example, the interface circuitry corresponding to one channel may correspond to Figure 1 the memory interface circuitry 210. Signals received from the external host device through the physical layer 311 may be sent to the first core die 320 to the fourth core die 350 via the TSVs.

[0101] According to an example embodiment, the buffer die 310 may include channel controllers corresponding to each channel. The channel controllers may manage memory reference operations of the corresponding channels and may determine timing requirements of the corresponding channels.

[0102] According to an example embodiment, the buffer die 310 may include a plurality of pins for receiving signals from an external host device. The buffer die 310 may receive a clock signal CK, a command / address signal C / A, a write data strobe signal WDQS, and data signals DQ through the plurality of pins and may send a read data strobe signal RDQS and data signals DQ. For example, the buffer die 310 may include two pins (e.g., Figure 1 the clock pin CK_P) for receiving the clock signal CK, 18 pins (e.g., row pins R_P and column pins C_P) for receiving the command / address signal C / A, four pins for receiving the write data strobe signal WDQS, four pins for sending the read data strobe signal RDQS, and 64 pins (e.g., Figure 1 the data pins D_P) for sending and receiving the data signals DQ.

[0103] According to an example embodiment, the stacked memory device 300 may further include an error correction code (ECC) circuit for detecting and correcting errors of data. For example, in a write operation, the ECC circuit may generate parity bits for data sent from the host device. In a read operation, the ECC circuit may detect and correct errors of data sent from one of the first core die 320 to the fourth core die 350 by using the parity bits and may send the error-corrected data to the external host device.

[0104] According to an example embodiment, as referenced in Figures 1 to 6As described, the stacked memory device 300 may receive a row command CMD_r through a row pin R_P and may receive a column command CMD_c through a column pin C_P. The stacked memory device 300 may receive a specific command of the row command CMD_r at a rising edge and / or a falling edge of a clock signal CK. The stacked memory device 300 may sense the specific command from the row command CMD_r transmitted at one of the rising edge and the falling edge of the clock signal CK. For example, the specific command may be a precharge command PRE.

[0105] According to an example embodiment, the stacked memory device 300 may include a specific command decoder for sensing a specific command by decoding the row command CMD_r at the rising edge of the clock signal CK and sensing the specific command by decoding the row command CMD_r at the falling edge of the clock signal CK, as Figure 6 shown.

[0106] Figure 8 is Figure 7 an example block diagram of the stacked memory device 300. Referring to Figure 8 , the stacked memory device 400 may include a buffer die 410 and a core die 420. The core die 420 may support a channel CHa among a plurality of channels. The buffer die 410 and the core die 420 may communicate through TSVs 401 to 404 located in a TSV region. The TSVs 401 to 404 may be located in the TSV region corresponding to the channel CHa. For example, the buffer die 410 may send the clock signal CK to the core die 420 through the TSV 401, may send the row command CMD_r / row address ADD_r to the core die 420 through the TSV 402, may send the column command CMD_c / column address ADD_c to the core die 420 through the TSV 403, and may send the data DATA to the core die 420 or receive the data DATA from the core die 420 through the TSV 404. In Figure 8 , each of the TSVs 401 to 404 is implemented by one TSV. However, each of the TSVs 401 to 404 may be implemented by various numbers of TSVs.

[0107] The buffer die 410 may include a memory interface circuit 411 corresponding to the channel CHa. The memory interface circuit 411 may correspond to Figure 1The memory interface circuit 210. The memory interface circuit 411 can receive the clock signal CK, row command CMD_r / row address ADD_r, column command CMD_c / column address ADD_c, and data DATA sent to channel Cha through the clock pin CK_P, row pin R_P, column pin C_P, and data pin D_P corresponding to channel CHa. The memory interface circuit 411 can send the clock signal CK, row command CMD_r / row address ADD_r, column command CMD_c / column address ADD_c, and data DATA to the core die 420 through TSVs 401 to 404. According to an exemplary embodiment, the memory interface circuit 411 can send the clock signal CK, row command CMD_r / row address ADD_r, column command CMD_c / column address ADD_c, and data DATA after signal processing to the core die 420. The memory interface circuit 411 can send the data DATA sent from the core die 420 to an external host device (e.g., Figure 1 the memory controller 100) through TSV 404.

[0108] The core die 420 can include a control logic circuit 421, a data input / output circuit 422, and a memory cell array 423. The control logic circuit 421, the data input / output circuit 422, and the memory cell array 423 can support channel CHa. The memory cell array 423 can be included in one of the banks included in channel CHa. The control logic circuit 421, the data input / output circuit 422, and the memory cell array 423 can respectively correspond to Figure 2 the control logic circuit 230, the input / output circuit 240, and the memory cell array 221 described above. Therefore, the description given above can be omitted.

[0109] The control logic circuit 421 can receive the clock signal CK, row command CMD_r / row address ADD_r, and column command CMD_c / column address ADD_c sent from the buffer die 410 through TSVs 401 to 403. The control logic circuit 421 can decode the row command CMD_r / row address ADD_r and the column command CMD_c / column address ADD_c. According to an exemplary embodiment, the control logic circuit 421 can sense a specific command (e.g., precharge command PRE) by decoding the row command CMD_r received at the rising edge of the clock signal CK, and can sense a specific command by decoding the row command CMD_r received at the falling edge of the clock signal CK, as referred to in Figure 6 the description. The control logic circuit 421 can control the data input / output circuit 422 and the memory cell array 423 based on the decoding result.

[0110] The data input / output circuit 422 can send data DATA to the buffer die 410 and receive data DATA from the buffer die 410 through the TSV 404. In a write operation, the data input / output circuit 422 can send the data DATA sent from the buffer die 410 to the memory cell array 423 through the TSV 404. Accordingly, the memory cell array 423 can store the data DATA. In a read operation, the data input / output circuit 422 can send the data DATA output from the memory cell array 423 to the buffer die 410 through the TSV 404.

[0111] In Figure 8 it is shown that the row command CMD_r and the column command CMD_c are decoded by the core die 420 through the control logic circuit 421 of the core die 420. However, the inventive concept is not limited thereto. For example, the row command CMD_r and the column command CMD_c can be decoded by a command decoder included in the memory interface circuit 411 of the buffer die 410.

[0112] Figure 9 is a block diagram showing Figure 8 an enlarged example of the stacked memory device 400. Referring to Figure 9 , the stacked memory device 400a can include a buffer die 410 and a core die 420a. The core die 420a can support a channel CHa divided into a first pseudo-channel PC0 and a second pseudo-channel PC1. The core die 420a can include a control logic circuit 421, a data input / output circuit 422, and a memory cell array 423 that support the first pseudo-channel PC0, and a control logic circuit 424, a data input / output circuit 425, and a memory cell array 426 that support the second pseudo-channel PC1. Since the control logic circuit 424, the data input / output circuit 425, and the memory cell array 426 respectively correspond to the control logic circuit 421, the data input / output circuit 422, and the memory cell array 423, they will not be described in detail.

[0113] The control logic circuit 421 can receive a clock signal CK, a row command CMD_r / row address ADD_r, and a column command CMD_c / column address ADD_c from the buffer die 410 through the TSVs 401 to 403. When the row address ADD_r indicates the first pseudo-channel PC0, the control logic circuit 421 can decode the row command CMD_r. When the column address ADD_c indicates the first pseudo-channel PC0, the control logic circuit 421 can decode the column command CMD_c. That is, the control logic circuit 421 can decode the row command CMD_r and the column command CMD_c corresponding to the first pseudo-channel PC0, and can control the data input / output circuit 422 and the memory cell array 423 according to the decoding result.

[0114] The control logic circuit 424 can receive the clock signal CK, row command CMD_r / row address ADD_r, and column command CMD_c / column address ADD_c transmitted from the buffer die 410 through the TSVs 401 to 403. When the row address ADD_r represents the second pseudo-channel PC1, the control logic circuit 424 can decode the row command CMD_r. When the column address ADD_c represents the second pseudo-channel PC1, the control logic circuit 424 can decode the column command CMD_c. That is, the control logic circuit 424 can decode the row command CMD_r and the column command CMD_c corresponding to the second pseudo-channel PC1, and can control the data input / output circuit 425 and the memory cell array 426 according to the decoding results.

[0115] Figure 10 is shown Figure 8 a block diagram of an enlarged example of the stacked memory device 400a. Refer to Figure 10 , the stacked memory device 400b may include a buffer die 410, a first core die 420, and a second core die 430. The first core die 420 and the second core die 430 may support the same channel CHa among a plurality of channels. The first core die 420 may be included in one stack including a plurality of core dies, and the second core die 430 may be included in another stack including a plurality of core dies. In this case, the first core die 420 and the second core die 430 can be distinguished by the stack ID (SID). For example, the first core die 420 may correspond to the first stack ID SID0, and the second core die 430 may correspond to the second stack ID SID1. In Figure 10 , it is shown that no other core dies are located between the first core die 420 and the second core die 430. However, other core dies may be located between the first core die 420 and the second core die 430.

[0116] The buffer die 410, the first core die 420, and the second core die 430 can communicate through the TSVs 401 to 404 located in the TSV region. For example, the buffer die 410 can send the clock signal CK to the first core die 420 and the second core die 430 through the TSV 401, can send the row command CMD_r / row address ADD_r to the first core die 420 and the second core die 430 through the TSV 402, can send the column command CMD_c / column address ADD_c to the first core die 420 and the second core die 430 through the TSV 403, and can send the data DATA to the first core die 420 and the second core die 430 and receive the data DATA from the first core die 420 and the second core die 430 through the TSV 404. In Figure 10 it, it is shown that the buffer die 410 communicates with the first core die 420 and the second core die 430 by using the TSVs 401 to 404. However, the buffer die 410 can communicate with the first core die 420 and the second core die 430 by using separate TSVs corresponding to the first core die 420 and the second core die 430.

[0117] The first core die 420 can include a control logic circuit 421 that supports the channel CHa, a data input / output circuit 422, and a memory cell array 423, and the second core die 430 can include a control logic circuit 431 that supports the channel CHa, a data input / output circuit 432, and a memory cell array 433. Since the control logic circuit 431, the data input / output circuit 432, and the memory cell array 433 respectively correspond to the control logic circuit 421, the data input / output circuit 422, and the memory cell array 423, their detailed descriptions will be omitted.

[0118] The control logic circuit 421 can receive the clock signal CK, the row command CMD_r / row address ADD_r, and the column command CMD_c / column address ADD_c from the buffer die 410 through the TSVs 401 to 403. When the address ADD_r represents the first stack ID SID0, the control logic circuit 421 can decode the row command CMD_r. When the column address ADD_c represents the first stack ID SID0, the control logic circuit 421 can decode the column command CMD_c. That is, the control logic circuit 421 can decode the row command CMD_r and the column command CMD_c corresponding to the first stack ID SID0, and can control the data input / output circuit 422 and the memory cell array 423 according to the decoding result.

[0119] The control logic circuit 431 can receive the clock signal CK, row command CMD_r / row address ADD_r, and column command CMD_c / column address ADD_c from the buffer die 410 through the TSVs 401 to 403. When the address ADD_r represents the second stack ID SID1, the control logic circuit 431 can decode the row command CMD_r. When the column address ADD_c represents the second stack ID SID1, the control logic circuit 431 can decode the column command CMD_c. That is, the control logic circuit 431 can decode the row command CMD_r and the column command CMD_c corresponding to the second stack ID SID1, and can control the data input / output circuit 432 and the memory cell array 433 according to the decoding result.

[0120] Figure 11A and Figure 11B illustrates an example of a timing diagram of a stacked memory device 300 receiving commands according to an exemplary embodiment. Specifically, Figure 7 illustrates an example of receiving a write command WR for the first bank group BG1 to the third bank group BG3. Figure 11A illustrates an example of receiving a write command WR for different pseudo-channels PC0 and PC1. Figure 11B

[0121] Referring to Figure 11A and Figure 11B the stacked memory device 300 can receive an activation command ACT in 1.5 cycles, can receive a precharge command PRE in 0.5 cycles, and can receive a write command WR in 1 cycle. The stacked memory device 300 can receive the precharge command PRE at the rising edge and the falling edge of the clock signal CK_c. For example, as Figure 11A and 11B shown, after completely receiving the activation command ACTa, the stacked memory device 300 can receive the precharge command PREb without delay at the falling edge of the clock signal CK_c. After completely receiving the precharge command PREb, the stacked memory device 300 can receive the activation command ACTc without delay. After completely receiving the activation command ACTc, the stacked memory device 300 can receive the precharge command PREd with a 0.5-cycle delay at the rising edge of the clock signal CK_c. In this case, since Figure 11A and Figure 11B the example of the row command CMD_c corresponds to Figure 3C the example of the row command CMD_c, its detailed description will be omitted. In Figure 11A and Figure 11B examples of receiving the write command WR are described. However, the inventive concept is not limited thereto. For example, the write command WR can be changed to a read command RD.

[0122] Reference Figure 7 and Figure 11A As shown in Figure 11A , the stacked memory device 300 may receive an activation command ACTa and a first write command WR1 at a first time point t1. In this case, the first write command WR1 may correspond to one memory bank of the first bank group BG1. After the first write command WR1 is completely received, the stacked memory device 300 may receive an activation command ACTc and a second write command WR2 at a second time point t2. In this case, the second write command WR2 may correspond to one memory bank of the second bank group BG2. After the second write command WR2 is completely received, the stacked memory device 300 may receive a precharge command PREd and a third write command WR3 at a third time point t3. In this case, the third write command WR3 may correspond to one memory bank of the third bank group BG3. For example, as Figure 11A shown, the time interval for receiving different write commands may be 2tCK (i.e., two cycles of the clock signal CK_c).

[0123] As described above, when continuously receiving write commands WR or read commands RD for different bank groups, after one write command WR or one read command RD is completely received, the stacked memory device 300 may receive another write command WR or another read command RD with a delay.

[0124] Reference Figure 7 and Figure 11B As shown in Figure 11B , the stacked memory device 300 may sequentially receive a first write command WR1 to a fifth write command WR5 from a first time point t1 to a fifth time point t5. The time interval for receiving different write commands may be 1tCK (i.e., one cycle of the clock signal CK_c). For example, as Figure 11B shown, after one write command is completely received, another write command may be received immediately. In this case, two consecutively received write commands may correspond to different pseudo-channels. For example, the first write command WR1, the third write command WR3, and the fifth write command WR5 may correspond to one memory bank of the first pseudo-channel PC0, and the second write command WR2 and the fourth write command WR4 may correspond to one memory bank of the second pseudo-channel PC1.

[0125] As described above, when continuously receiving write commands WR or read commands RD for different pseudo-channels, after one write command WR or one read command RD is completely received, the stacked memory device 300 may receive another write command WR or another read command RD without a delay. Therefore, when continuously performing memory access through an operation such as pseudo-channel interleaving, the stacked memory device 300 may receive commands quickly.

[0126] Figure 12Ais a table showing examples of row commands according to an example embodiment, and Figure 12B is a table showing examples of column commands according to an example embodiment.

[0127] Referring Figure 12A , the row commands may include a no-operation row command RNOP, an activation command ACT, a precharge command PREpb for a specific bank, a precharge command PREab for all banks, a refresh command REFpb for a specific bank, a refresh command REFab for all banks, a refresh management command RFMpb for a specific bank, a refresh management command RFMab for all banks, a power-down entry command PDE, a self-refresh entry command SRE, a power-down exit command PDX, and a self-refresh exit command SRX.

[0128] The no-operation row command RNOP, the precharge commands PREpb and PREab, the refresh commands REFpb and REFab, the refresh management commands RFMpb and RFMab, the power-down exit command PDX, and the self-refresh exit command SRX may be received in 0.5 cycles of the clock signal CK. In this case, as described in reference Figures 3A to 3C , the no-operation row command RNOP and the precharge commands PREpb and PREab may be received at the rising edge R or the falling edge F of the clock signal CK. The refresh management commands RFMpb and RFMab, the power-down exit command PDX, and the self-refresh exit command SRX may be received at the rising edge R of the clock signal CK.

[0129] The activation command ACT may be received in 1.5 cycles of the clock signal CK. For example, the activation command ACT may be received corresponding to two rising edges R and one falling edge F of the clock signal CK. The power-down entry command PDE and the self-refresh entry command SRE may be received in 1 cycle of the clock signal CK. For example, the power-down entry command PDE and the self-refresh entry command SRE may be received corresponding to one rising edge R and one falling edge F of the clock signal CK.

[0130] Each command may be distinguished based on the signal values received through the first row pin R_P0 to the tenth row pin R_P9. For example, when signal values corresponding to the high level H are received through the first row pin R_P0 to the fourth row pin R_P3 at the rising edge R or the falling edge F of the clock signal CK, the row command may be sensed as the no-operation row command RNOP. In this case, through the fifth row pin R_P4 to the tenth row pin R_P9, signal values corresponding to valid values V (e.g., high level H or low level L) may be received.

[0131] For example, when a signal value corresponding to a low level L is received through a first row pin R_P0 at a first rising edge R of a clock signal CK and signal values corresponding to a high level H are received through a second row pin R_P1 and a third row pin R_P2, the row command can be sensed as an activation command ACT. In this case, a pseudo-channel PC can be received through a fourth row pin R_P3, a stack ID SID can be received through a fifth row pin R_P4 and a sixth row pin R_P5, and a bank address BA can be received through a seventh row pin R_P6 to a tenth row pin R_P9. For example, when the stacked memory device 300 is implemented by one stack, a valid value V can be received through the fifth row pin R_P4 and the sixth row pin R_P5 instead of the stack ID SID. During the reception of the activation command ACT after the first rising edge R of the clock signal CK (i.e., at a first falling edge F and a second rising edge R of the clock signal CK), signal values corresponding to a high level H can be received through the first row pin R_P0 and the second row pin R_P1, and a row address RA can be received through the third row pin R_P2 to the tenth row pin R_P9.

[0132] For example, when a signal value corresponding to a high level H is received through a first row pin R_P0 at a rising edge R or a falling edge F of a clock signal CK and signal values corresponding to a low level L are received through a second row pin R_P1 and a third row pin R_P2, the row command can be sensed as a precharge command PREpb. In this case, a pseudo-channel PC can be received through a fourth row pin R_P3, a stack ID SID can be received through a fifth row pin R_P4 and a sixth row pin R_P5, and a bank address BA can be received through a seventh row pin R_P6 to a tenth row pin R_P9. For example, when the stacked memory device 300 is implemented by one stack, a valid value V can be received through the fifth row pin R_P4 and the sixth row pin R_P5 instead of the stack ID SID.

[0133] For example, when signal values corresponding to a high level H are received through a first row pin R_P0 and a third row pin R_P2 at a rising edge R or a falling edge F of a clock signal CK and a signal value corresponding to a low level L is received through a second row pin R_P1, the row command can be sensed as a precharge command PREab. In this case, a pseudo-channel PC can be received through a fourth row pin R_P3, and valid values V can be received through the fifth row pin R_P4 to the tenth row pin R_P9.

[0134] Based on the signal values received through the first row pins R_P0 to the tenth row pin R_P9, a row command can be sensed as one of a refresh command REFpb and REFab, a refresh management command RFMpb and RFMab, a power-down entry command PDE, a self-refresh entry command SRE, a power-down exit command PDX, and a self-refresh exit command SRX.

[0135] Reference Figure 12B , the column commands can include a no-operation column command CNOP, read commands RD and RDA, write commands WR and WRA, a mode register set command MRS, and a mode register read command MRR. Here, the read command RDA and the write command WRA indicate an auto-precharge operation together with a read operation and a write operation. Each command can be received in one cycle corresponding to the rising edge R and the falling edge F of the clock signal CK.

[0136] Each command can be distinguished based on the signal values received through the first column pins C_P0 to the eighth column pin C_P7. For example, when signal values corresponding to a high level H are received through the first column pin C_P0 and the third column pin C_P2 and signal values corresponding to a low level L are received through the second column pin C_P1 and the fourth column pin C_P3 at the rising edge R of the clock signal CK, the column command can be sensed as a read command RD. For example, when a signal value corresponding to a high level H is received through the first column pin C_P0 and signal values corresponding to a low level L are received through the second column pin C_P1 to the fourth column pin C_P3 at the rising edge R of the clock signal CK, the column command can be sensed as a write command WR.

[0137] When a read command RD or a write command WR is sensed through the first column pins C_P0 to the fourth column pins C_P3, a pseudo-channel PC can be received through the fifth column pin C_P4, a stack ID SID can be received through the sixth column pin C_P5 and the seventh column pin C_P6, and a part of a bank address BA can be received through the eighth column pin C_P7. For example, when the stacked memory device 300 is implemented by one stack, valid values V can be received through the sixth column pin C_P5 and the seventh column pin C_P6 instead of the stack ID SID. While receiving a read command RD or a write command WR after the rising edge R of the clock signal CK (i.e., at the falling edge F of the clock signal CK), the remaining part of the bank address BA can be received through the first column pins C_P0 to the third column pins C_P2, and the column address CA can be received through the fourth column pins C_P3 to the eighth column pins C_P7.

[0138] Based on the signal values received through the first column pins C_P0 to the eighth column pins C_P7, a column command can be sensed as one of a no-operation column command CNOP, a read command RDA, a write command WRA, a mode register set command MRS, and a mode register read command MRR. Here, a mode register address MA and setting information OP can be received together with the reception of the mode register set command MRS, and a mode register address MA can be received together with the reception of the mode register read command MRR.

[0139] Figure 13 is an example circuit diagram of a control logic circuit 440 for sensing a precharge command according to Figure 12A a row command. Specifically, Figure 13 is an example circuit diagram of a specific command decoder for sensing a precharge command PREpb for a specific bank. Referring to Figure 13 , the control logic circuit 440 can correspond to Figures 8 to 10 at least one of the control logic circuits 421, 424, and 431. The control logic circuit 440 can include inverters 441 to 447, NAND gates 448 and 449, flip-flops 451 and 452, and an OR gate 453. The inverters 441, 442, and 446, the NAND gate 448, and the flip-flop 451 can correspond to Figure 6 the first specific command decoder 231, the inverters 443, 444, and 447, the NAND gate 449, and the flip-flop 452 can correspond to Figure 6 the second specific command decoder 232, and the OR gate 453 can correspond to Figure 6 the comparator 233.

[0140] When a precharge command PREpb indicating a row command is received, as described with reference to Figure 12A , signal values corresponding to a high level H, a low level L, and a low level L can be received through the first row pin R_P0 to the third row pin R_P2, respectively. The signal value received through the first row pin R_P0 can be input to each of the NAND gates 448 and 449, and the signal values received through the second row pin R_P1 and the third row pin R_P2 can be inverted by the inverters 441 to 444 and can be input to the NAND gates 448 and 449, respectively. Accordingly, a signal value corresponding to the high level H can be input to each of the NAND gates 448 and 449, and a signal value corresponding to the low level L can be output from each of the NAND gates 448 and 449. The signal values output from the NAND gates 448 and 449 can be inverted by the inverters 446 and 447 and can be input to the input terminals D of the flip-flops 451 and 452.

[0141] The flip-flop 451 may output, as a first decoding result DR1, the signal value input to the input terminal D to the output terminal Q based on the rising edge R of the clock signal CK received through the clock pin CK_P. For example, when a row command representing the precharge command PREpb is received at the rising edge R of the clock signal CK, the flip-flop 451 may output the first decoding result DR1 corresponding to the high level H. For example, when a row command representing the precharge command PREpb is not received at the rising edge R of the clock signal CK, the flip-flop 451 may output the first decoding result DR1 corresponding to the low level L.

[0142] The flip-flop 452 may receive the signal obtained by inverting the clock signal CK by the inverter 445. That is, the flip-flop 452 may output, as a second decoding result DR2, the signal value input to the input terminal D to the output terminal Q based on the falling edge F of the clock signal CK. For example, when a row command representing the precharge command PREpb is received at the falling edge F of the clock signal CK, the flip-flop 452 may output the second decoding result DR2 corresponding to the high level H. For example, when a row command representing the precharge command PREpb is not received at the falling edge F of the clock signal CK, the flip-flop 452 may output the second decoding result DR2 corresponding to the low level L.

[0143] The OR gate 453 may output an internal command iCMD representing the precharge command PREpb by comparing the first decoding result DR1 or the second decoding result DR2. For example, when the first decoding result DR1 or the second decoding result DR2 is at the high level H (i.e., when the row command represents the precharge command PREpb), the OR gate 453 may output the internal command iCMD at the high level H, indicating that the precharge command PREpb is sensed.

[0144] Figure 13 The illustrated control logic circuit 440 is merely an example. The inventive concept is not limited thereto. For example, the control logic circuit 440 may include a plurality of logic gates capable of performing a first logical operation (e.g., a logical AND operation) to replace the NAND gates 448 or 449, or include a plurality of logic gates capable of performing a second logical operation (e.g., a logical OR operation) to replace the OR gate 453.

[0145] Figure 14 is a view showing a semiconductor package 1000 according to an exemplary embodiment of the inventive concept. Refer to Figure 14, the semiconductor package 1000 may include a stacked memory device 1100, a system-on-chip (SoC) 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer die 1110 and core dies 1120 to 1150. The stacked memory device 1100 may correspond to the stacked memory devices 300, 400, 400a, and 400b described with reference to Figures 7 to Described stacked memory devices 300, 400, 400a, and 400b.

[0146] Each of the core dies 1120 to 1150 may include memory cells for storing data. The buffer die 1110 may include a physical layer (PHY) 1111 and a direct access area DAB 1112. The physical layer (PHY) 1111 may be electrically connected to the physical layer (PHY) 1210 of the SoC 1200 through the interposer 1300. The stacked memory device 1100 may receive signals from the SoC 1200 or send signals to the SoC 1200 through the physical layer 1111. The physical layer 1111 may include the memory interface circuit 411 of the buffer die 410 described with reference to ​ Described buffer die 410.

[0147] The direct access area 1112 may provide an access route capable of testing the stacked memory device 1100 without going through the SoC 1200. The direct access area 1112 may include conductive units (e.g., ports or pins) capable of directly communicating with an external test device. The test signals received through the direct access area 1112 may be sent to the core dies 1120 to 1150 through the TSVs 1101. The data read from the core dies 1120 to 1150 for testing the core dies 1120 to 1150 may be sent to the external test device through the TSVs 1101 and the direct access area 1112. Therefore, a direct access test of the core dies 1120 to 1150 may be performed.

[0148] The buffer die 1110 and the core dies 1120 to 1150 may be electrically connected to each other through the TSVs 1101 and the bumps 1102. The buffer die 1110 may receive the signals respectively provided to the channels from the SoC 1200 through the bumps 1102 assigned to the channels, or may send signals to the SoC 1200 through the bumps 1102. For example, the bumps 1102 may be micro-bumps.

[0149] The SoC 1200 can execute applications supported by the semiconductor package 1000 by using the stacked memory device 1100. For example, the SoC 1200 can execute dedicated operations including at least one processor among a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), and a digital signal processor (DSP).

[0150] The SoC 1200 can control the overall operation of the stacked memory device 1100. The SoC 1200 can correspond to ​ the memory controller 100. The SoC 1200 can include a physical layer 1210. The physical layer 1210 can include interface circuits for transmitting signals to and receiving signals from the physical layer 1111 of the stacked memory device 1100. For example, the physical layer 1210 can include ​ the host interface circuit 110. The SoC 1200 can provide various signals to the physical layer 1111 through the physical layer 1210. The signals provided to the physical layer 1111 can also be sent to the core dies 1120 to 1150 through the interface circuit of the physical layer 1111 and the TSV 1101.

[0151] The inserter 1300 can connect the stacked memory device 1100 to the SoC 1200. The inserter 1300 can connect the physical layer 1111 of the stacked memory device 1100 to the physical layer 1210 of the SoC 1200, and can provide a physical routing formed by using a conductive material. Accordingly, the stacked memory device 1100 and the SoC 1200 can be stacked on the inserter 1300 and can send and receive signals to and from each other.

[0152] The bumps 1103 can be attached to the package substrate 1400, and the solder balls 1104 can be attached under the package substrate 1400. For example, the bumps 1103 can be flip chip bumps. The inserter 1300 can be stacked on the package substrate 1400 through the bumps 1103. The semiconductor package 1000 can send signals to and receive signals from another external package or semiconductor device through the solder balls 1104. For example, the package substrate 1400 can be a printed circuit board (PCB).

[0153] According to an example embodiment, as referred to in ​As described, the physical layer 1111 of the buffer die 1110 may receive row commands and column commands from the SoC 1200 via the bumps 1102. The physical layer 1111 may receive a specific command among the row commands (e.g., a precharge command PRE) at the rising edge R or the falling edge F of the clock signal CK.

[0154] ​ FIG. is a diagram illustrating an implementation example of a semiconductor package 2000 according to an exemplary embodiment. Refer to ​ , the semiconductor package 2000 may include a plurality of stacked memory devices 2100 and an SoC 2200. Each of the plurality of stacked memory devices 2100 may correspond to ​ the stacked memory device 1100, and the SoC 2200 may correspond to ​ the SoC 1200. The plurality of stacked memory devices 2100 and the SoC 2200 may be stacked on an interposer 2300, and the interposer 2300 may be stacked on a package substrate 2400. The semiconductor package 2000 may send signals to or receive signals from another external package or semiconductor device via the solder balls 2001 attached under the package substrate 2400.

[0155] Each of the plurality of stacked memory devices 2100 may be implemented based on the HBM standard. However, the inventive concept is not limited thereto. Each of the plurality of stacked memory devices 2100 may be implemented based on the GDDR standard, the HMC standard, or the wide I / O standard.

[0156] The SoC 2200 may include at least one processor, such as a CPU, an AP, a GPU, or an NPU, and a plurality of memory controllers for controlling the plurality of stacked memory devices 2100. The SoC 2200 may send signals to and receive signals from the corresponding stacked memory device via the memory controller.

[0157] ​ FIG. is a view illustrating a semiconductor package 3000 according to another exemplary embodiment. Refer to ​ , the semiconductor package 3000 may include a stacked memory device 3100, a main host die 3200, and a package substrate 3300. The stacked memory device 3100 may include a buffer die 3110 and core dies 3120 to 3150. The buffer die 3110 may include a physical layer 3111 (PHY) for communicating with the host die 3200, and each of the core dies 3120 to 3150 may include memory cells for storing data. The stacked memory device 3100 may correspond to the stacked memory devices 300, 400, 400a, and 400b described with reference to ​ .

[0158] The host die 3200 may include a physical layer (PHY) 3210 for communicating with the stacked memory device 3100. The physical layer 3111 and the physical layer 3210 may communicate with each other through the TSV 3001. The host die 3200 may correspond to ​ the memory controller 100, and the physical layer 3111 may correspond to ​ the host interface circuit 110. The host die 3200 may include a processor for controlling the overall operation of the semiconductor package 3000 and executing applications supported by the semiconductor package 3000. For example, the host die 3200 may include at least one processor, such as a CPU, an AP, a GPU, or an NPU.

[0159] The stacked memory device 3100 may be disposed on the host die 3200 based on the TSV 3001 and may be vertically stacked on the host die 3200. Accordingly, the buffer die 3110, the core dies 3120 to 3150, and the host die 3200 may be electrically connected to each other through the TSV 3001 and the bumps 3002 without an inserter. For example, the bump 3002 may be a micro-bump.

[0160] The bump 3003 may be attached to the package substrate 3300, and the solder ball 3004 may be attached under the package substrate 3300. For example, the bump 3003 may be a flip chip bump. The main chip 3200 may be stacked on the package substrate 3300 through the bump 3003. The semiconductor package 3000 may send signals to and receive signals from another external package or semiconductor device through the solder ball 3004.

[0161] According to an example embodiment, as described with reference to ​ the physical layer 3111 of the buffer die 3110 may receive row commands and column commands from the host die 3200 through the TSV 3001. The physical layer 3111 may receive a specific command (e.g., a precharge command PRE) among the row commands at the rising edge R or the falling edge F of the clock signal CK.

[0162] According to another embodiment, the stacked memory device 3100 may be implemented only by the core dies 3120 to 3150 without the buffer die 3110. In this case, each of the core dies 3120 to 3150 may further include an interface circuit for communicating with the host die 3200. In this case, each of the core dies 3120 to 3150 may send signals to and receive signals from the physical layer 3210 of the host die 3200 through the TSV 3001.

[0163] ​ is a block diagram showing a computing system 4000 according to an exemplary embodiment. The computing system 4000 may be implemented by one electronic device or may be distributed across two or more electronic devices. For example, the computing system 4000 may be implemented by at least one of various electronic devices such as a desktop computer, a laptop computer, a tablet computer, a smart phone, an autonomous vehicle, a digital camera, a wearable device, a healthcare device, a server system, a data center, a drone, a handheld game console, an Internet of Things (IoT) device, a graphics accelerator, and an artificial intelligence (AI) accelerator.

[0164] Referring ​ , the computing system 4000 may include a host 4100, an accelerator subsystem 4200, and an interconnect 4300. The host 4100 may control the overall operation of the accelerator subsystem 4200, and the accelerator subsystem 4200 may operate according to the control of the host 4100. The host 4100 and the accelerator subsystem 4200 may be connected through the interconnect 4300. Various signals and data may be transmitted and received between the host 4100 and the accelerator subsystem 4200 through the interconnect 4300.

[0165] The host 4100 may include a host processor 4110, a host memory controller 4120, a host memory 4130, and an interface circuit 4140. The host processor 4110 may control the overall operation of the computing system 4000. The host processor 4110 may control the host memory 4130 through the host memory controller 4120. The host processor 4110 may control the accelerator subsystem 4200 connected through the interconnect 4300. For example, the host processor 4110 may allocate work to the accelerator subsystem 4200 by sending commands to the accelerator subsystem 4200.

[0166] The host processor 4110 may be a general-purpose processor or a main processor that performs general operations related to various operations of the computing system 4000. For example, the host processor 4110 may be a CPU or an AP.

[0167] The host memory 4130 may be the main memory of the computing system 4000. The host memory 4130 may store data processed by the host processor 4110 or data received from the accelerator subsystem 4200. For example, the host memory 4130 may be implemented by DRAM. However, the inventive concept is not limited thereto. The host memory 4130 may include at least one of a volatile memory such as SRAM and a non-volatile memory such as flash memory, PRAM, RRAM, or MRAM.

[0168] The interface circuit 4140 can be formed such that the host 4100 communicates with the accelerator subsystem 4200. The host processor 4110 can send control signals and data to the accelerator subsystem 4200 through the interface circuit 4140, and receive control signals and data from the accelerator subsystem 4200. In an example embodiment, the host processor 4110, the host memory controller 4120, and the interface circuit 4140 can be implemented by one chip.

[0169] The accelerator subsystem 4200 can perform specific functions according to the control of the host 4100. For example, the accelerator subsystem 4200 can perform operations dedicated to a specific application according to the control of the host 4100. The accelerator subsystem 4200 can be physically or electrically connected to the host 4100, or can be implemented in various forms, such as a module, a card, a package, a chip, and devices connected by wire or wirelessly. For example, the accelerator subsystem 4200 can be implemented by a graphics card or an accelerator card. For example, the accelerator subsystem 4200 can be implemented based on a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0170] According to an example embodiment, the accelerator subsystem 4200 can be implemented based on at least one of various packaging technologies. For example, the accelerator subsystem 4200 can be implemented by packaging technologies such as ball grid array (BGA), multi-chip package (MCP), system-in-package (SOP), system-in-a-package (SIP), package-on-package (POP), chip-scale package (CSP), wafer-level package (WLP), or panel-level package (PLP). For example, some or all components of the accelerator subsystem 4200 can be connected by copper-to-copper bonding. For example, some or all components of the accelerator subsystem 4200 can be connected by an inserter such as a silicon inserter, an organic inserter, a glass inserter, or an active inserter. For example, some or all components of the accelerator subsystem 4200 can be stacked based on through-silicon vias (TSV). For example, some or all components of the accelerator subsystem 4200 can be connected by a high-speed link (e.g., a silicon bridge).

[0171] The accelerator subsystem 4200 can include a dedicated processor 4210, a local memory controller 4220, a local memory 4230, and a host interface circuit 4240. The dedicated processor 4210 can operate according to the control of the host processor 4110. For example, the dedicated processor 4210 can read data from the local memory 4230 through the local memory controller 4220 in response to a command from the host processor 4110. The dedicated processor 4210 can process data by performing operations based on the read data. The dedicated processor 4210 can send the processed data to the host processor 4110, or can write the processed data to the local memory 4230.

[0172] The dedicated processor 4210 may perform operations dedicated to a specific application based on values stored in the local memory 4230. For example, the dedicated processor 4210 may perform operations dedicated to applications such as AI, stream analysis, video transcoding, data indexing, data encoding / decoding, and data encryption. Thus, the dedicated processor 4210 may process various forms of data, such as image data, audio data, motion data, biometric data, and key values. For example, the dedicated processor 4210 may include at least one of a GPU, an NPU, a TPU, a VPU, an ISP, and a DSP.

[0173] The dedicated processor 4210 may include a processor core or multiple processor cores, such as dual-core, quad-core, and six-core. According to an example embodiment, the dedicated processor 4210 may include more cores than the host processor 4110 for operations dedicated to parallelization. For example, the dedicated processor 4210 may include 1000 or more cores.

[0174] The local memory controller 4220 may control the overall operation of the local memory 4230. According to an example embodiment, the local memory controller 4220 may perform error correction code (ECC) encoding and ECC decoding, may perform data verification by a cyclic redundancy check (CRC) method, or may perform data encryption and data decryption. The local memory controller 4220 may correspond to ​ the memory controller 100.

[0175] The local memory 4230 may be exclusively used by the dedicated processor 4210. The local memory 4230 may be implemented by DRAM. However, the inventive concept is not limited thereto. For example, the local memory 4230 may be implemented by at least one of a volatile memory such as SRAM and a non-volatile memory such as flash memory, PRAM, RRAM, or MRAM. According to an example embodiment, the local memory 4230 may be mounted on a substrate together with the dedicated processor 4210, or may be implemented in various forms, such as a chip, a package, a module, a card, and a device connected to the dedicated processor 4210 based on a separate connector. The local memory 4230 may correspond to the memory device 200 or the stacked memory device 300 or 400 described with reference to ​ the description.

[0176] According to an example embodiment, the local memory 4230 may include logic circuitry capable of performing some operations. The logic circuitry may perform linear operations, comparison operations, compression operations, data conversion operations, and arithmetic operations on data read from or to be written to the local memory 4230. Thus, the size of the data processed by the logic circuitry can be reduced. When the size of the data is reduced, the bandwidth efficiency between the local memory 4230 and the local memory controller 4220 can be improved.

[0177] The host interface circuit 4240 may be formed such that the accelerator subsystem 4200 communicates with the host 4100. The accelerator subsystem 4200 may send control signals and data to the host 4100 through the host interface circuit 4240, and receive control signals and data from the host 4100. In one example embodiment, the dedicated processor 4210, the local memory controller 4220, and the host interface circuit 4240 may be implemented by one chip.

[0178] The interconnect 4300 may provide a data transfer path between the host 4100 and the accelerator subsystem 4200, and may be used as a data bus or a data link. The data transfer path may be formed wired or wirelessly. The interface circuit 4140 and the host interface circuit 4240 may communicate through the interconnect 4300 based on a predetermined code. For example, the interface circuit 4140 and the host interface circuit 4240 may communicate based on one of various standards, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), Advanced eXtensible Interface (AXI), ARM Microcontroller Bus Architecture (AMBA), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Storage (UFS), CompactFlash (CF), and Gen-Z. Alternatively, the interface circuit 4140 and the host interface circuit 4240 may communicate based on an inter-device communication link such as Open Coherent Accelerator Processor Interface (openCAPI), Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), and NVLINK. Alternatively, the interface circuit 4140 and the host interface circuit 4240 may communicate based on wireless communication technologies such as Long-Term Evolution (LTE), 5G, LTE-M, NB-IoT, LPWAN, Bluetooth, Near Field Communication (NFC), Zigbee, Z-Wave, or WLAN.

[0179] According to an example embodiment, the accelerator subsystem 4200 may further include sensors capable of sensing image data, audio data, motion data, biometric data, and peripheral environment information. According to an example embodiment, when the sensors are included in the accelerator subsystem 4200, the sensors may be connected to other components (e.g., the dedicated processor 4210 and the local memory 4230) based on the above-described packaging technology. The accelerator subsystem 4200 may process the data sensed by the sensors based on a specific operation.

[0180] In ​ , it is shown that the dedicated processor 4210 uses a local memory 4230 through a local memory controller 4220. However, the inventive concept is not limited thereto. For example, the dedicated processor 4210 may use a plurality of local memory components through a local memory controller 4220. As another example, the dedicated processor 4210 may use a local memory corresponding to each of the plurality of local memory controllers through a plurality of local memory controllers.

[0181] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: A clock pin configured to receive a clock signal; A row pin configured to receive a first activation command and a first precharge command during a first time period, and to receive a second activation command and a second precharge command during a second time period; And A column pin configured to receive a first read command or a first write command during the first time period, and to receive a second read command or a second write command during the second time period, Wherein during the first time period, the row pin is configured to receive the first activation command during a first sub-period, and after receiving the first activation command, to receive the first precharge command during a second sub-period corresponding to the rising edge of the clock signal, and the column pin is configured to receive the first read command or the first write command during a third sub-period, Wherein during the second time period, the row pin is configured to receive the second activation command during a fourth sub-period, and after receiving the second activation command, to receive the second precharge command during a fifth sub-period corresponding to the falling edge of the clock signal, and the column pin is configured to receive the second read command or the second write command during a sixth sub-period, Wherein the length of each of the first sub-period and the fourth sub-period is 1.5 cycles of the clock signal, the length of each of the second sub-period and the fifth sub-period is 0.5 cycles of the clock signal, and the length of each of the third sub-period and the sixth sub-period is 1 cycle of the clock signal.

2. The memory device according to claim 1, wherein, 1.5 cycles of the clock signal include two rising edges and one falling edge.

3. The memory device according to claim 1, wherein, A first minimum time interval between the first activation command and the first precharge command is different from a second minimum time interval between the second activation command and the second precharge command.

4. The memory device according to claim 3, wherein, The first minimum time interval is larger than the second minimum time interval by 0.5 cycles of the clock signal.

5. The memory device according to claim 1, wherein, The number of the row pins is 10, and the number of the column pins is 8.

6. The memory device according to claim 1, wherein, The memory device is configured to communicate with an external host device based on a high bandwidth memory HBM interface.

7. A memory controller, comprising: A clock pin configured to send a clock signal to a memory device; A row pin configured to send a first activation command for the memory device and a first precharge command for the memory device during a first time period, and to send a second activation command for the memory device and a second precharge command for the memory device during a second time period; And A column pin configured to send a first read command or a first write command for the memory device during the first time period, and to send a second read command or a second write command for the memory device during the second time period, During the first time period, the row pin is configured to send the first activation command to the memory device during a first sub - period, and after sending the first activation command, send the first pre - charge command to the memory device during a second sub - period corresponding to the rising edge of the clock signal, and the column pin is configured to send the first read command or the first write command to the memory device during a third sub - period. During the second time period, the row pin is configured to send the second activation command to the memory device during a fourth sub - period, and after sending the second activation command, send the second pre - charge command to the memory device during a fifth sub - period corresponding to the falling edge of the clock signal, and the column pin is configured to send the second read command or the second write command to the memory device during a sixth sub - period. The length of each of the first sub - period and the fourth sub - period is 1.5 cycles of the clock signal, the length of each of the second sub - period and the fifth sub - period is 0.5 cycles of the clock signal, and the length of each of the third sub - period and the sixth sub - period is 1 cycle of the clock signal.

8. The memory controller according to claim 7, wherein, 1.5 cycles of the clock signal include two rising edges and one falling edge.

9. The memory controller according to claim 7, wherein, The first minimum time interval between the first activation command and the first pre - charge command is different from the second minimum time interval between the second activation command and the second pre - charge command.

10. The memory controller according to claim 9, wherein, The first minimum time interval is 0.5 cycles of the clock signal larger than the second minimum time interval.

11. The memory controller according to claim 7, wherein, The number of the row pins is 10, and the number of the column pins is 8.

12. The memory controller according to claim 7, wherein, The memory controller is configured to communicate with the memory device based on a high - bandwidth memory (HBM) interface.

13. A memory system, comprising: A package substrate; An inserter stacked on the package substrate; A memory device stacked on the inserter, the memory device including clock pins, row pins and column pins; And A memory controller stacked on the inserter, the memory controller being configured to send a first row command to the memory device during a first time period, send a second row command to the memory device during a second time period, and send a clock signal to the memory device. Wherein the inserter is configured to connect the memory device to the memory controller. Wherein the memory device is configured to decode the first row command received through the row pin during the first time period and decode the second row command received through the row pin during the second time period. Wherein the first row command is sent during a first sub - period corresponding to the rising edge of the clock signal. Wherein the second row command is sent during a second sub - period corresponding to the falling edge of the clock signal, and Wherein the first row command corresponds to a first pre - charge command, and the second row command corresponds to a second pre - charge command. The length of each of the first sub - period and the second sub - period is 0.5 cycles of the clock signal.

14. The memory system according to claim 13, wherein, During the first time period, the memory device is configured to receive a first activation command through the row pin during a third sub - period, and after receiving the first activation command, receive the first pre - charge command during the first sub - period, and During the second time period, the memory device is configured to receive a second activation command through the row pin during a fourth sub - period, and after receiving the second activation command, receive the second pre - charge command during the second sub - period. The length of each of the third sub - period and the fourth sub - period is 1.5 cycles of the clock signal.

15. The memory system according to claim 14, wherein, During the first time period, the memory device is further configured to receive a first read command or a first write command through the column pin during a fifth sub - period, and During the second time period, the memory device is further configured to receive a second read command or a second write command through the column pin during a sixth sub - period. The length of each of the fifth sub - period and the sixth sub - period is 1 cycle of the clock signal.

16. The memory system according to claim 14, wherein, During the first time period, the memory device is further configured to receive a first read command or a first write command through the column pin during the fifth sub - period after receiving the first activation command and before receiving the first pre - charge command, and During the second time period, the memory device is further configured to receive a second read command or a second write command through the column pin during the sixth sub - period after receiving the second activation command and before receiving the second pre - charge command. The length of each of the fifth sub - period and the sixth sub - period is 1 cycle of the clock signal.

17. The memory system according to claim 14, wherein, 1.5 cycles of the clock signal include two rising edges and one falling edge.

18. The memory system according to claim 14, wherein, The first minimum time interval between the first activation command and the first pre - charge command is different from the second minimum time interval between the second activation command and the second pre - charge command.

19. The memory system according to claim 13, wherein, The number of row pins is 10, and the number of column pins is 8.

20. The memory system according to claim 13, wherein The memory device is configured to communicate with the memory controller based on a High Bandwidth Memory (HBM) interface.

Images