A low-power, high-flexibility SSD main control chip computing acceleration circuit

Abstract

The present invention discloses a low-power and high-flexibility SSD main control chip computing acceleration circuit, which includes a main control unit, a switch unit and a processing unit. The main control unit includes a plurality of triggers, a plurality of computing chips, a plurality of multiplexing chips and a plurality of diodes. The D pin of the trigger U1 in the plurality of triggers is connected to the Q inverted pin, the CLK pin is connected to the CLK pin of the computing chip U3, the CLK pin of the computing chip U4 and the P1 end, and the Q pin is connected to the A pin of the multiplexing chip U7 and the CLK pin of the trigger U9; the D pin of the trigger U9 is connected to the Q inverted pin, and the Q pin is connected to the B pin of the multiplexing chip U7; the D pin of the trigger U10 is connected to the Q inverted pin, the CLK pin is connected to the cathode of the diode D9 and the cathode of the diode D10, and the Q pin is connected to the S1 pin and S2 pin of the multiplexing chip U5 and the S1 pin and S2 pin of the multiplexing chip U6; the Q4 pin of the computing chip U4 is connected to the anode of the diode D10, and the Q8 pin and the MR pin are connected to the anode of the diode D9.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a low-power and high-flexibility SSD main control chip computing acceleration circuit. Background Art

[0002] In the field of modern information security, encryption technology is the core means to ensure data security, which mainly includes three categories: symmetric encryption, asymmetric encryption and hash algorithms. Symmetric encryption (such as AES, ChaCha20) uses the same key for encryption and decryption, which is fast and efficient, and is suitable for large-scale data encryption, but key management is a key challenge; asymmetric encryption (such as RSA, ECC) uses public key encryption and private key decryption to solve the key distribution problem, and is widely used in digital signatures and key exchange, but the computational overhead is large; hash algorithms (such as SHA-256, BLAKE2) generate irreversible unique digests, which are often used for data integrity verification and password storage (must be combined with salt value to prevent cracking). In addition, hybrid encryption (such as TLS protocol) combines the advantages of symmetric and asymmetric encryption.

[0003] Taking into account both security and performance, the national secret algorithms (SM4, SM2) and post-quantum cryptography (such as lattice cryptography) respectively meet specific compliance requirements and future requirements for anti-quantum attacks. Existing SSD hard drives need to integrate one or more encryption algorithms when encrypting data. Due to the different rules of different encryption algorithms, different control circuits need to be integrated for each encryption algorithm. Therefore, a low-power, high-flexibility SSD main control chip computing acceleration circuit is proposed, which can adapt and control different encryption rules without switching. Summary of the Invention

[0004] In view of the above technical problems, the purpose of the present invention is to provide a low-power and high-flexibility SSD main control chip computing acceleration circuit, including a main control unit, a switch unit and a processing unit. The main control unit includes a number of triggers, a number of computing chips, a number of multiplexing chips, and a number of diodes. The D pin of the trigger U1 in the number of triggers is connected to the Q inverse pin, the CLK pin is connected to the CLK pin of the computing chip U3, the CLK pin of the computing chip U4, and the P1 end, and the Q pin is connected to the A pin of the multiplexing chip U7 and the CLK pin of the trigger U9; the D pin of the trigger U9 is connected to the Q inverse pin, and the Q pin is connected to the B pin of the multiplexing chip U7; the D pin of the trigger U10 is connected to the Q inverse pin, the CLK pin is connected to the cathode of the diode D9 and the cathode of the diode D10, and the Q pin is connected to the

[0005] The S1 and S2 pins of the multiplexing chip U5, and the S1 and S2 pins of the multiplexing chip U6; the Q4 pin of the computing chip U4 is connected to the anode of the diode D10, and the Q8 pin and MR pin are connected to the anode of the diode D9; the A1 pin of the multiplexing chip U5 is connected to the 2_1 terminal, and the corresponding pins Y1 to Y4 are respectively connected to the corresponding pins 2X0 to 2X3 of the multiplexing chip U7; the Y1 pin of the multiplexing chip U6 is connected to the 1X0 pin of the multiplexing chip U7, and the corresponding pins Y2 to Y4 are respectively connected to the corresponding pins 1X3 to 1X1 of the multiplexing chip U7; the Q8 pin of the computing chip U3 is connected to the MR pin and the OE inverse pin of the computing chip U8; the corresponding pins Q0 to Q7 of the computing chip U3 are respectively connected to the control terminal in the switch unit; the Q0 to Q7 pins of the computing chip U8 are respectively connected to the anodes of the diodes D1 to D8, Pins D0 to D7 of the computing chip U8 are connected to the cathodes of diodes D1 to D8 and the output end of the switch unit respectively; the E pin of the computing chip U3 and the E pin of the computing chip U4 are grounded.

[0006] Furthermore, the processing unit includes an XOR gate, the XOR gate U2 has an input end connected to the 1Y pin and the 2Y pin of the multiplexing chip U7, and an output end connected to the input end of the switch unit.

[0007] Furthermore, the switch unit includes a plurality of transistors, the input ends of the transistors are connected in parallel to the output end of the XOR gate U2, the control ends are connected to the Q0 to Q7 pins of the computing chip U3 respectively, and the output ends are connected to the cathodes of diodes D1 to D8.

[0008] Furthermore, the main control unit also includes several resistors, among which one end of resistor R1 is connected to the P1 end; one end of resistor R2 is connected to the Q pin of trigger U1; one end of resistor R3 is connected to the S1 pin of multiplexing chip U5; one end of resistor R4 is connected to the MR pin of computing chip U3; one end of resistor R5 is connected to the P1 end; one end of resistor R6 is connected to the 1E pin and the 2E pin of multiplexing chip U7; one end of resistor R7 is connected to the cathode of diode D9; and the other ends of resistors R1 to R7 are grounded.

[0009] Furthermore, a finite field multiplier is included, the output end of the multiplexing chip U7 corresponds to the input end of the finite field multiplier, and the output end of the finite field multiplier is fed back to the switch unit.

[0010] Furthermore, the P1 is connected to a clock signal.

[0011] Furthermore, the circuit is powered by 5V.

[0012] The beneficial effects of the present invention compared with the prior art are:

[0013] The present invention can adapt to different encryption rules through one-byte encryption control, and can reduce the number of required integrated control circuits when multiple encryption rules are adopted. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, a brief introduction is given below to the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] FIG1 is a circuit structure diagram provided by the present invention. DETAILED DESCRIPTION

[0016] In order to make the objects and advantages of the present invention more clearly understood, the present invention is described in detail below with reference to the embodiments. It should be understood that the following text is only used to describe one or several specific implementation methods of the present invention and does not strictly limit the scope of protection specifically requested by the present invention.

[0017] The present invention discloses a low-power and high-flexibility SSD main control chip computing acceleration circuit, which includes a main control unit, a switch unit and a processing unit. The main control unit includes a plurality of triggers, a plurality of computing chips, a plurality of multiplexing chips and a plurality of diodes. The D pin of the trigger U1 in the plurality of triggers is connected to the Q inverse pin, the CLK pin is connected to the CLK pin of the computing chip U3, the CLK pin of the computing chip U4 and the P1 end, the Q pin is connected to the A pin of the multiplexing chip U7 and the CLK pin of the trigger U9; the D pin of the trigger U9 is connected to the Q inverse pin, and the Q pin is connected to the B pin of the multiplexing chip U7; the D pin of the trigger U10 is connected to the Q inverse pin, the CLK pin is connected to the cathode of the diode D9 and the cathode of the diode D10, the Q pin is connected to the S1 pin and S2 pin of the multiplexing chip U5, and the S1 pin and S2 pin of the multiplexing chip U6; the Q4 pin of the computing chip U4 is connected to the diode D10. Anode, Q8 pin and MR pin are connected to the anode of diode D9; A1 pin of multiplexing chip U5 is connected to 2_1 terminal, Y1 to Y4 corresponding pins are connected to 2X0 to 2X3 corresponding pins of multiplexing chip U7 respectively; Y1 pin of multiplexing chip U6 is connected to 1X0 pin of multiplexing chip U7, and Y2 to Y4 corresponding pins are connected to 1X3 to 1X1 corresponding pins of multiplexing chip U7 respectively; Q8 pin of computing chip U3 is connected to MR pin and OE inverse pin of computing chip U8; Q0 to Q7 corresponding pins of computing chip U3 are connected to the control end in the switch unit respectively; Q0 ​​to Q7 pins of computing chip U8 are connected to the anode of diode D1 to diode D8 respectively, and D0 to D7 pins of computing chip U8 are connected to the cathode of diode D1 to diode D8 and the output end of the switch unit respectively; E pin of computing chip U3 and E pin of computing chip U4 Pin is grounded.

[0018] Specifically, the processing unit includes an XOR gate, an input end of the XOR gate U2 is connected to the 1Y pin and the 2Y pin of the multiplexing chip U7, and an output end is connected to the input end of the switch unit.

[0019] Specifically, the switch unit includes a plurality of transistors, the input ends of the transistors are connected in parallel to the output end of the XOR gate U2, the control ends are connected to the Q0 to Q7 pins of the computing chip U3 respectively, and the output ends are connected to the cathodes of diodes D1 to D8.

[0020] Specifically, the main control unit also includes several resistors, among which resistor R1 has one end connected to terminal P1; resistor R2 has one end connected to the Q pin of trigger U1; resistor R3 has one end connected to the S1 pin of multiplexing chip U5; resistor R4 has one end connected to the MR pin of computing chip U3; resistor R5 has one end connected to terminal P1; resistor R6 has one end connected to the 1E pin and the 2E pin of multiplexing chip U7; resistor R7 has one end connected to the cathode of diode D9; and the other ends of resistors R1 to R7 are grounded.

[0021] Specifically, a finite field multiplier is also included, the output end of the multiplexing chip U7 corresponds to the input end of the finite field multiplier, and the output end of the finite field multiplier is fed back to the switch unit.

[0022] Specifically, the P1 is connected to a clock signal.

[0023] Specifically, the circuit is powered by 5V.

[0024] In this application, 1_1 is used to input a plaintext bit sequence (encrypted plaintext and initial round plaintext data in round transformation), 2_1 inputs a key bit sequence (initial key and expanded key), and when the circuit is cyclically expanded (each round is multiplexed, for example, each round transformation in AES encryption uses a processing circuit), a main control unit can be used, and all output pins of the computing chip U8 of each main control unit correspond to a byte of 8-bit data or 8 units are used. The same output pins of the computing chip U8 in each main control unit constitute a byte of data. When full expansion is used, the corresponding number is set according to the size of the byte matrix of the key bit number. Among them, P1 inputs a clock signal. Taking the ASCII code decimal value 97 as an example, the corresponding binary value is 01100001, and the initial round key of one byte is 11110000, which is explained by XOR processing. The multiplexing chip U6 is used to input a plaintext bit sequence, and its input pins A series input the first 4 bits in sequence, and the B series pins input the last 4 bits in sequence, that is, the data bits corresponding to the A pin are 0110, and the B pins are 01110. The data corresponding to the pin is 0001. The multiplexing chip U5 is used to input the key bit sequence. Its input pin A series inputs the first 4 bits in sequence, and the B series pins input the last 4 bits in sequence. That is, the data bit corresponding to the A pin is 1111, and the data corresponding to the B pin is 0000.

[0025] The pin output signal is fed back to the trigger U10 through the diode D9, and the Q pin of the trigger U10 is set to 0. The multiplexing chip U6 and the multiplexing chip U5 are reset to the A series pin output. At the same time, the Q8 pin of the computing chip U4 is also fed back to the MR pin for reset. After the computing chip U3 and the computing chip U8 are input through P1, the Q8 pin of the computing chip U3 is input to the MR pin and the OE inverse pin of the computing chip U8. The computing chip U3 is reset and the computing chip U8 is erased. When the circuit is multiplexed to the column mixing step, the XOR gate U2 is removed and the output end of the multiplexing chip U7 is connected to the finite field multiplier. When one bit is used, the output end of the multiplexing chip U7 corresponds to the input end of the finite field multiplier. The output end of the finite field multiplier is fed back to the switch unit. 8 bits can also be used. The connection method is that the 1Y pin of the multiplexing chip U7 of each main control unit is input to the first group of input ends of the finite field multiplier, and 2Y The pins are input to the second group of input terminals of the finite field multiplier. When an 8-bit finite field multiplier is used, the 8 main control units are connected in sequence, and the output terminal of the multiplier is directly fed back to the input pin of the computing chip U8. The finite field multiplier is not shown in the attached figure.

[0026] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed therein. No sign in a claim should be construed as limiting the claim to which it relates.

Claims

1. A low-power, high-flexibility SSD master chip computing acceleration circuit, characterized by: It includes a main control unit, a switch unit and a processing unit. The main control unit includes several triggers, several computing chips, several multiplexing chips and several diodes. The D pin of the trigger U1 in the several triggers is connected to the Q inverse pin, the CLK pin is connected to the CLK pin of the computing chip U3, the CLK pin of the computing chip U4 and the P1 end, and the Q pin is connected to the A pin of the multiplexing chip U7 and the CLK pin of the trigger U9; the D pin of the trigger U9 is connected to the Q inverse pin, and the Q pin is connected to the B pin of the multiplexing chip U7; the D pin of the trigger U10 is connected to the Q inverse pin, and the CLK pin is connected to the A pin of the multiplexing chip U7. The K pin is connected to the cathode of diode D9 and the cathode of diode D10, and the Q pin is connected to the S1 pin and S2 pin of multiplexing chip U5, and the S1 pin and S2 pin of multiplexing chip U6; the Q4 pin of computing chip U4 is connected to the anode of diode D10, and the Q8 pin and MR pin are connected to the anode of diode D9; the A1 pin of multiplexing chip U5 is connected to the 2_1 terminal, and the corresponding pins Y1 to Y4 are respectively connected to the corresponding pins 2X0 to 2X3 of multiplexing chip U7; the Y1 pin of multiplexing chip U6 is connected to the 1X0 pin of multiplexing chip U7, and the corresponding pins Y2 to Y4 are respectively connected to the multiplexing The 1X3 to 1X1 corresponding pins of chip U7; the Q8 pin of computing chip U3 is connected to the MR pin and the OE inverse pin of computing chip U8; the Q0 to Q7 corresponding pins of computing chip U3 are respectively connected to the control end of the switch unit; the Q0 to Q7 corresponding pins of computing chip U8 are respectively connected to the anode of diode D1 to diode D8, and the D0 to D7 pins of computing chip U8 are respectively connected to the cathode of diode D1 to diode D8 and the output end of the switch unit; the E pin of computing chip U3 and the E pin of computing chip U4 are grounded, and after the circuit is powered on, the multiplexing chip U6 and The multiplexing chip U5 inputs the corresponding 1_1 plaintext bit sequence data and the first digits of the 2_1 key bit sequence data into 1X0 to 1X3 and 2X0 to 2X3 of the multiplexing chip U7. The multiplexing chip U7 inputs 1X0 and 2X0 into the XOR gate U2 through the 1Y and 2Y pins for XOR processing. The processing result is fed back to the switch unit. At the same time, the Q0 pin of the computing chip U3 is output to the transistor Q1 in the corresponding switch unit. The transistor Q1 is turned on, and the XOR gate U2 outputs the data result 1 or 0 high or low level to the D0 pin of the computing chip U8.

2. The low-power, high-flexibility SSD main control chip computing acceleration circuit according to claim 1, characterized in that: The processing unit includes an XOR gate, the XOR gate U2 has an input end connected to the 1Y pin and the 2Y pin of the multiplexing chip U7, and an output end connected to the input end of the switch unit.

3. The low-power, high-flexibility SSD main control chip computing acceleration circuit according to claim 1, characterized in that: The switch unit includes a plurality of transistors, the input ends of the plurality of transistors are connected in parallel to the output end of the XOR gate U2, the control ends are respectively connected to the Q0 to Q7 pins of the computing chip U3, and the output ends are connected to the cathodes of the diodes D1 to D8.

4. The low-power, high-flexibility SSD main control chip computing acceleration circuit according to claim 1, characterized in that: The main control unit also includes several resistors, among which one end of resistor R1 is connected to the P1 end; one end of resistor R2 is connected to the Q pin of trigger U1; one end of resistor R3 is connected to the S1 pin of multiplexing chip U5; one end of resistor R4 is connected to the MR pin of computing chip U3; one end of resistor R5 is connected to the P1 end; one end of resistor R6 is connected to the 1E pin and the 2E pin of multiplexing chip U7; one end of resistor R7 is connected to the cathode of diode D9; and the other ends of resistors R1 to R7 are grounded.

5. The low-power, high-flexibility SSD main control chip computing acceleration circuit according to claim 2, characterized in that: It also includes a finite field multiplier, the output end of the multiplexing chip U7 corresponds to the input end of the finite field multiplier, and the output end of the finite field multiplier is fed back to the switch unit.

6. The low-power, high-flexibility SSD main control chip computing acceleration circuit according to claim 1, characterized in that: The P1 is connected to a clock signal.

7. The low-power, high-flexibility SSD main control chip computing acceleration circuit according to claim 1, characterized in that: The circuit is powered by 5V.

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