Design method of domestic multi-channel arbitrary wave generation module

Abstract

The invention relates to the technical field of signal generators, in particular to a design method of a domestic multi-channel arbitrary wave generation module. Through domestic replacement device type selection and domestic chip software and hardware collaborative optimization design, the problems that imported components are high in supply chain risk, poor in communication compatibility and low in waveform generation efficiency when used in cooperation with foreign devices are solved, and the method has the advantages of being autonomous, controllable, good in signal quality and the like. The method can be widely applied to waveform generation requirements in the fields of radar signal simulation, communication test, electronic test and measurement and the like. The invention discloses a design method of a domestic multichannel arbitrary wave generation module. The domestic design mainly comprises two parts, namely an upper computer supporting a domestic operating system and a domestic arbitrary wave output module.

Description

Technical Field

[0001] The present invention relates to the technical field of signal generators, and particularly relates to a design method for a domestic multi-channel arbitrary waveform generation module, which is applicable to scenarios such as radar signal simulation, communication testing, electronic testing and measurement, etc. Background Art

[0002] Currently, most of the arbitrary waveform generation modules on the market basically use foreign MCUs, DSPs or FPGAs as the control core, and foreign semiconductor chips such as DACs, ADCs, and operational amplifiers as the design and development devices of the system. The use of semiconductor devices depends entirely on imports, resulting in problems such as high supply chain risks and uncontrollable costs. Moreover, in the existing domestic technologies:

[0003] There are problems of poor compatibility and low waveform generation efficiency in the hardware modular design of domestic devices and foreign devices, and it is difficult to adapt to different domestic chip platforms.

[0004] In addition, there are differences in the computing power between domestic chips and imported chips, and direct substitution is likely to cause waveform distortion or a decrease in response speed.

[0005] Therefore, there is an urgent need for specialized domestic selection analysis and design for arbitrary waveform generation modules to solve problems such as high supply chain risks caused by the dependence on imported components in existing modules, and low waveform generation efficiency caused by poor communication compatibility when using domestic and foreign devices in combination. Summary of the Invention

[0006] In order to solve the problems mentioned in the background art, in view of the existing arbitrary waveform signal generators on the market and the urgent need for arbitrary waveform signal generators in fields such as military, aviation, and transportation manufacturing, the present invention proposes a design method for a domestic multi-channel arbitrary waveform generation module. By selecting domestic replacement devices and carrying out collaborative optimization design of software and hardware for domestic chips, the waveform generation efficiency of the domestic arbitrary waveform generation module is improved, and the dependence on imported components is reduced.

[0007] A design method for a domestic multi-channel arbitrary waveform generation module is characterized in that it is mainly divided into two parts: a host computer and an arbitrary waveform output module, and the host computer and the arbitrary waveform generation module are connected through a gigabit Ethernet and a USB3.0 communication bus.

[0008] Further, a design method for a domestic multi-channel arbitrary waveform generation module is characterized in that the host computer supports a domestic operating system (such as Kylin OS), includes a waveform configuration tool, supports waveform parameter setting, and provides a standard waveform library and a user-defined waveform editing function.

[0009] Further, the domestic multi-channel arbitrary waveform generation module is characterized in that the domestic design includes the following units:

[0010] Domestic FPGA main control unit, domestic power management unit, domestic level conversion unit, domestic interface unit, domestic waveform output unit.

[0011] Among them, the domestic FPGA main control unit is used to complete communication and data processing functions, and quickly transmit data to the domestic high-speed DAC chip for output.

[0012] The domestic power management unit uses domestic power management chips to provide multiple independent voltage outputs for the FPGA and peripheral circuits.

[0013] The domestic level conversion unit uses domestic level conversion chips and level driver chips to adapt to domestic chips in different voltage domains.

[0014] The domestic interface unit uses domestic communication interface control chips to achieve domestic design and compatibility optimization of communication circuits.

[0015] The domestic waveform output unit uses domestic high-speed DAC chips and domestic high-speed operational amplifiers, and the two cooperate to perform signal conditioning such as amplifying and filtering on the output waveform signal.

[0016] Furthermore, in view of the current situation of the low slew rate or insufficient bandwidth at high gain of domestic high-speed operational amplifiers, and in order to adapt to the high output voltage swing and high output frequency of the arbitrary waveform generation module, a multi-stage operational amplifier circuit is adopted in the signal conditioning circuit of the waveform output unit to alleviate the problem of insufficient bandwidth at high gain.

[0017] Furthermore, the domestic multi-channel arbitrary waveform generation module supports real-time data output of multiple types of waveforms, including sine waves, square waves, sawtooth waves, exponential waves, and user-defined waveforms, and has the function of dynamically adjusting frequency, amplitude, and phase. It adopts a waveform generation method based on a look-up table (LUT) and performs piecewise interpolation optimization through the following formula: Reduce the waveform storage capacity, achieve smooth generation and noise suppression of arbitrary waveforms, and be able to conform to actual common signal types and frequency bands.

[0018] Furthermore, the arbitrary waveform signal is generated by the host computer and stored in the host computer. When the waveform needs to be output, the host computer compresses the arbitrary waveform signals of all channels in real time and sends them to the arbitrary waveform generation module through a Gigabit Ethernet or USB3.0 communication bus. The module then decompresses the data and outputs it.

[0019] Furthermore, the upper computer uses an improved LZ4 fast lossless compression algorithm for arbitrary wave data compression, and the lower computer realizes fast data decompression through the cooperation of FPGA to complete the output of the desired waveform.

[0020] Furthermore, the domestic FPGA master control unit realizes functions such as upper computer command parsing, waveform data reception, waveform data decompression, external trigger, and DDS output control, and completes the output of the waveform through the following steps:

[0021] S1: Receive the data sent by the upper computer and parse the upper computer configuration command and waveform data.

[0022] S2: Distribute the waveform data to the data decompression modules of the corresponding channels to perform real-time decompression on the waveform data.

[0023] S3: The DDS output module configures the channel parameters according to the configuration information, and waits to output the digital waveform to the DAC module when the enable command or the external trigger command arrives. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0025] Figure 1 It is a structural block diagram of a design method for a domestic arbitrary wave generation module provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] To make the above objects, features, and functions of the present invention more clearly understood, the drawings required for the description of the embodiments will be briefly introduced below.

[0027] It should be noted that the following detailed descriptions are all exemplary and are intended to provide further explanations of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the specification without creative efforts fall within the scope of protection of this application.

[0028] Embodiment 1.

[0029] As Figure 1 shown, this embodiment provides a design method for a domestic multi-channel arbitrary wave generation module, which is mainly divided into two parts: an upper computer and an arbitrary wave output module. The upper computer and the arbitrary wave generation module are connected through a gigabit Ethernet and a USB3.0 communication bus.

[0030] The upper computer supports a domestic operating system (such as Kylin OS), includes a waveform configuration tool, supports waveform parameter setting, and provides a standard waveform library and a user-defined waveform editing function.

[0031] The domesticated multi-channel arbitrary waveform generation module, the domesticated design includes the following units: a domesticated FPGA main control unit, a domesticated power management unit, a domesticated level conversion unit, a domesticated interface unit, and a domesticated waveform output unit.

[0032] The domesticated FPGA main control unit uses PG2L200H of Unisoc. It should be noted that the domesticated FPGA mainly realizes functions such as host computer command parsing, waveform data reception, waveform data decompression, external trigger, and DDS output control, and completes the output of the waveform through the following steps:

[0033] S1: Receive the data sent by the host computer and parse the host computer configuration command and waveform data.

[0034] S2: Distribute the waveform data to the data decompression module of the corresponding channel to perform real-time decompression on the waveform data.

[0035] S3: The DDS output module configures the channel parameters according to the configuration information, and waits to output the digital quantity waveform to the DAC module when the enable command or external trigger command arrives.

[0036] The domesticated multi-channel arbitrary waveform generation module supports the real-time data output of various types of waveforms, including sine waves, square waves, sawtooth waves, exponential waves, and user-defined waveforms, and has the functions of dynamically adjusting frequency, amplitude, and phase. It adopts a waveform generation method based on a look-up table (LUT) and optimizes through piecewise interpolation: Reduce the waveform storage capacity, realize the smooth generation of arbitrary waveforms and noise suppression, and can conform to the actual common signal types and frequency bands.

[0037] Furthermore, the arbitrary wave signal is generated by the host computer and stored in the host computer. When the waveform needs to be output, the host computer compresses the arbitrary wave signals of all channels in real time and sends them to the arbitrary waveform generation module through a Gigabit Ethernet or USB3.0 communication bus. The module then decompresses the data and outputs it.

[0038] It should be noted that the host computer uses an improved LZ4 fast lossless compression algorithm for arbitrary wave data compression, and the lower computer cooperates with the FPGA to achieve fast data decompression, and completes the output of the desired waveform to the DAC.

[0039] The domestic power management unit selects a suitable power management chip according to the power supply requirements of the module. For example, for the required positive voltage, the GM1205 ultra-low noise linear voltage regulator of domestic common-mode semiconductors can be used, which can meet wide voltage input, step down the input voltage and output it stably, providing 8V, 5V, 3.3V, and 1.8V power supplies, and providing multiple independent voltage outputs for the FPGA and peripheral circuits.

[0040] For the negative voltage power supply of the operational amplifier, the SGM2209 low-dropout linear voltage regulator of Shengbang can be used in cooperation with the K7812 switching voltage regulator of Jin Shengyang, which can meet the requirements of wide voltage input and wide negative voltage output, and meet the negative voltage power supply requirements of the operational amplifier.

[0041] The domestic level conversion unit, according to different MUC level standards, such as using the two-way level conversion transceiver chip 74AVC16T245 of domestic Shengbang, is used to adapt the connection and communication between the FPGA and domestic chips in different voltage domains.

[0042] The domestic interface unit can use the domestic USB3.0 chip T630 of Fang Cun Wei and the gigabit Ethernet chip YT8511C of Yu Tai Wei to carry out domestic adaptation and domestic compatibility design for the communication interface.

[0043] The domestic waveform output unit needs to use a high-speed DAC to perform digital-to-analog conversion on the signal. The domestic high-speed DAC BL1031 can be used, with a maximum update rate of 250MSPS, which can achieve high-speed data update and output a large signal frequency.

[0044] Furthermore, the domestic waveform output unit needs to condition the output signal waveform, such as amplification, filtering, etc. For high-frequency signals, a high-speed operational amplifier is required. The high-bandwidth high-speed operational amplifier of Shengbang, such as SGM80581, can be used.

[0045] Furthermore, whether a high-performance arbitrary waveform generation module can be completed depends on a high-performance high-speed operational amplifier. For the current situation of insufficient low slew rate and bandwidth at high gain of domestic high-speed operational amplifiers in the domestic waveform output unit, and in order to adapt to the high output voltage swing and high output frequency of the arbitrary waveform generation module, a multi-stage operational amplifier circuit can be used in the signal conditioning circuit of the waveform output unit to alleviate the problem of insufficient bandwidth in a single-stage high-gain operational amplifier.

[0046] Furthermore, the improved LZ4 fast lossless compression algorithm is used for arbitrary wave data compression by the host computer, and the lower computer realizes fast data decompression through the cooperation of the FPGA to complete the output of the desired waveform.

[0047] Furthermore, the electronic components selected in the present invention are all domestic chip components, which can be fully realized independently and controllably.

[0048] It should be noted that the types or models of the domestic devices in the domestic multi-channel arbitrary waveform generation module provided by the embodiments of the present invention are not limited to the above examples, and there may be other implementation manners.

[0049] The above is only the preferred implementation manner of the present invention. In addition, for those of ordinary skill in the art, various modifications and variations can be made to the invention while maintaining the principle of the present invention. If the modifications and variations fall within the scope of the claims of the present invention and their equivalent technologies, these modifications and variations should also be regarded as within the protection scope of the present invention.

Claims

1. A design method for a domestic multi-channel arbitrary waveform generation module, characterized in that It is mainly divided into two parts: the host computer and the arbitrary waveform output module. The host computer and the arbitrary waveform generator module are connected through a gigabit Ethernet and a USB3.0 communication bus.

2. The design method of a domestic multi-channel arbitrary waveform generation module according to claim 1, characterized in that The host computer supports domestic operating systems, includes a waveform configuration tool, supports waveform parameter settings, and provides a standard waveform library and user-defined waveform editing functions.

3. A design method for a domestic multi-channel arbitrary waveform generation module according to claim 1, characterized in that The domestic design includes the following units: a domestic FPGA main control unit, a domestic power management unit, a domestic level conversion unit, a domestic interface unit, and a domestic waveform output unit; Among them, the domestic FPGA main control unit is used to complete communication and data processing functions, and quickly transmit data to a domestic high-speed DAC chip for output; The domestic power management unit uses domestic power management chips to provide multiple independent voltage outputs for the FPGA and peripheral circuits; The domestic level conversion unit uses domestic level conversion chips and level driver chips to adapt to domestic chips in different voltage domains; The domestic interface unit uses domestic communication interface control chips to achieve domestic design and compatibility optimization of communication circuits; The domestic waveform output unit uses a domestic high-speed DAC chip and a domestic high-speed operational amplifier, and the two cooperate to perform signal conditioning such as amplifying and filtering the output waveform signal.

4. The module according to claim 1, wherein The arbitrary waveform signal is generated by the host computer and stored in the host computer. When a waveform needs to be output, the host computer compresses the arbitrary waveform signals of all channels in real time and sends them to the arbitrary waveform generator module through the gigabit Ethernet or USB3.0 communication bus. This module then decompresses the data and outputs it.

5. The module according to claim 3, wherein The domestic multi-channel arbitrary waveform generator module supports real-time data output of various types of waveforms, including sine waves, square waves, sawtooth waves, exponential waves, and user-defined waveforms, and has the function of dynamically adjusting frequency, amplitude, and phase. It uses a waveform generation method based on a look-up table (LUT) and performs piecewise interpolation optimization through the following formula: Reduce the waveform storage capacity, achieve smooth generation and noise suppression of arbitrary waveforms, and be able to conform to actual commonly used signal types and frequency bands.

6. The module according to claim 3, characterized in that The domestic FPGA main control unit mainly realizes functions such as host computer command parsing, waveform data reception, waveform data decompression, external triggering, and DDS output control, and completes waveform output through the following steps: S1: Receive the data sent by the host computer and parse the host computer configuration command and waveform data; S2: Distribute the waveform data to the data decompression module of the corresponding channel to decompress the waveform data in real time; S3: The DDS output module configures the channel parameters according to the configuration information, and waits for the enable command or external trigger command to arrive to output the digital waveform to the DAC module.

7. The module according to claim 4, characterized in that The host computer uses an improved LZ4 fast lossless compression algorithm for arbitrary waveform data compression, and the lower computer cooperates with the FPGA to achieve fast data decompression to complete the output of the desired waveform.

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