Innovative gate-level inverter optimal-inferior trend analysis method, system and terminal

Abstract

The invention provides an innovative gate-level inverter optimal-inferior trend analysis method and system and a terminal, and the method comprises the steps: collecting the electrical characteristic data and electrical measurement data of a device test key of an inverter, and constructing a physical model for a typical process corner and a variation model for other process corners based on the data; a mature SPICE model verified by a factory is used for gate-level circuit simulation, a trend angle is calculated, and an optimal trend angle is analyzed and determined, so that the device optimization direction is defined. And further correcting the device design according to the optimization direction, and optimizing the manufacturing process parameters of the inverter. According to the method, when the performance of the gate-level inverter is analyzed, the comprehensive influence of local and global deviations is fully considered, the performance change under different process corners is comprehensively evaluated, the accuracy of an optimization result is ensured, and the performance and reliability of a device are effectively improved. Meanwhile, through benchmarking a gate level trend angle and a device process angle, a device optimization direction is defined, clear guidance is provided for a factory device manufacturing direction, device TT value adjustment is assisted, and device performance optimization is promoted.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a method, system and terminal for analyzing the superiority-inferiority trend of innovative gate-level inverters. Background Art

[0002] In semiconductor manufacturing, chip manufacturing is a complex physical process with various process deviations, including doping concentration, diffusion depth, etching degree, etc. These deviations result in different situations between different batches, between different wafers in the same batch, and between different chips on the same wafer, thus causing significant variations in the parameters of MOSFETS. To alleviate the difficulty of circuit design tasks to a certain extent, process engineers need to ensure that the performance of the device is within a certain range. If the device performance exceeds this range, this IC will be scrapped, and in this way, the yield of the IC is guaranteed. This performance range provided to designers is mainly applicable to digital circuits and is given in the form of "process corners". The idea is to limit the speed fluctuation range of NMOS and PMOS transistors within a rectangle determined by four corners, which are: fast NMOS and fast PMOS (FF), slow NMOS and slow PMOS (SS), fast NMOS and slow PMOS (FS), and slow NMOS and fast PMOS (SF). For example, transistors with a thinner gate oxide and a lower threshold voltage fall near the fast corner. When extracting device models corresponding to each corner from the wafer, the on-chip NMOS and PMOS test structures show different gate delays, and the actual selection of these corners is to obtain an acceptable yield. Therefore, only wafers that meet these performance indicators are considered qualified. Simulating the circuit under various process corners and extreme temperature conditions is the basis for determining the yield.

[0003] Process deviations can be divided into two categories: global variation and local variation. Global variation refers to the deviations between die-to-die, wafer-to-wafer, and lot-to-lot caused by process shifts. For example, the channel lengths of all transistors on the same chip are larger or smaller than the typical value. Local variation refers to the different effects of process deviations on different transistors on the same chip. For example, on the same chip, the channel lengths of some transistors are smaller, while those of some transistors are larger. Obviously, the impact of local variation is usually smaller than that of global variation.

[0004] However, when analyzing the performance of gate-level inverters in the prior art, it usually only relies on limited process corner simulations (such as TT, FF, SS, etc.), ignoring the combined effects of local and global variations on device performance. In old processes, since the local variations are very small, both local and global variations are taken into account when constructing the K library. However, in new processes, the local variations increase significantly. If the worst-case model is still used, it will lead to overly pessimistic analysis results and cannot accurately reflect the device performance changes under actual manufacturing conditions. In addition, when determining the device optimization direction, the existing methods lack a comprehensive evaluation of the performance changes under different process corners, resulting in inaccurate optimization results and unable to effectively improve the device performance and reliability. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an innovative method, system and terminal for analyzing the good-bad trends of gate-level inverters, which are used to solve the technical problems in the prior art that when analyzing the performance of gate-level inverters, it only relies on limited process corner simulations, ignores the combined effects of local and global variations and cannot accurately reflect the device performance changes under actual manufacturing conditions, and lacks a comprehensive evaluation when determining the optimization direction, resulting in inaccurate optimization results.

[0006] To achieve the above object and other related objects, the present invention provides an innovative method for analyzing the good-bad trends of gate-level inverters, the method comprising: collecting the electrical characteristic data of device test keys for manufacturing inverters, and performing electrical measurements on device test keys at different process levels to obtain electrical measurement data; based on the electrical characteristic data and the electrical measurement data, constructing a physical model for typical process corner simulations and variant models for other different process corner simulations; using the SPICE model to perform gate-level circuit simulations on the inverter to calculate the trend angle, and performing good-bad trend analysis to obtain the optimal trend angle, so as to determine the device optimization direction; based on the device optimization direction, correcting the device design parameters to optimize the manufacturing process parameters of the inverter.

[0007] In an embodiment of the present invention, the variant models include: a first variant model and a second variant model; the first variant model simulates the performance changes of other different process corners for asymmetric process local variations and process global variations; wherein, the other process corners simulated by the first variant model include: FF, FS, SF, and SS; the second variant model is used to simulate the performance changes of different process corners based on only considering asymmetric process global variations and a statistical manufacturing variation method for compensating process local variations; wherein, the other process corners simulated by the second variant model include: FFG, FSG, SFG, and SSG.

[0008] In an embodiment of the present invention, a SPICE model is used to perform gate-level circuit simulation on an inverter to calculate the trend angle, and perform an analysis of the advantages and disadvantages trends to obtain the optimized trend angle, so as to determine the device optimization direction, including: designing the gate-level schematic diagram of the inverter; setting the simulation conditions according to the designed gate-level schematic diagram; based on the constructed physical model and the variation model, performing gate-level circuit simulation on the inverter according to the simulation conditions set by the designed gate-level schematic diagram to obtain the delays and power consumptions of each process corner, so as to determine the gate-level trend angle; using the Monte Carlo method to verify the distribution of the gate-level trend angle; verifying the gate-level trend angle after verification by Best_Worstcase analysis, determining the optimized trend angle, and determining the device optimization direction.

[0009] In an embodiment of the present invention, the set simulation conditions include: DC simulation conditions and transient simulation conditions; the DC simulation conditions are used to obtain the optimal area efficiency ratio of the N-type transistor and the P-type transistor through DC simulation; the transient simulation conditions are used to obtain the power consumption and delay data of each process corner through transient simulation.

[0010] In an embodiment of the present invention, the performing gate-level circuit simulation on the inverter according to the simulation conditions set by the designed gate-level schematic diagram based on the constructed physical model and the variation model to obtain the delays and power consumptions of each process corner, so as to determine the gate-level trend angle includes: based on the constructed physical model and the variation model, performing transient simulation on the inverter to obtain the delays and power consumption values of each process corner, and obtaining the typical trend angle, the total trend angle, and the global trend angle; wherein, the delays and power consumption values of the typical process corner are used as the values of the typical trend angle, the delays and power consumption values of each process corner of the first variation model simulation are used as the values of each trend angle, and the delays and power consumption values of each process corner of the second variation model simulation are used as the values of the global trend angle.

[0011] In an embodiment of the present invention, the using the Monte Carlo method to verify the distribution of the gate-level trend angle includes: using the Monte Carlo method to perform multiple transient simulations to obtain the delay and power consumption values of each simulation; jointly correcting all the delay and power consumption values obtained by the simulation for time; merging the corrected delay and power consumption values of each simulation with the global trend angle to obtain the global trend angle verification result.

[0012] In an embodiment of the present invention, the determining the optimized trend angle by verifying the gate-level trend angle after Best_Worst case analysis, and taking the direction of approaching the value of the optimized trend angle from the value of the typical trend angle as the device optimization direction includes: obtaining the optimized adjustment trend and the worst-case adjustment trend by performing Best_Worst case analysis on the verification results of the typical trend angle, the total trend angle, and the global trend angle, and determining SF and SFG as the optimized trend angles; taking the direction of approaching the values of SF and SFG from the value of the typical trend angle as the device optimization direction.

[0013] In an embodiment of the present invention, collecting the electrical characteristic data of the device test keys for manufacturing the inverter and performing electrical measurements on the device test keys of different process levels to obtain electrical measurement data includes: collecting the electrical characteristic data of the device test keys for manufacturing the inverter; wherein, the electrical characteristic data includes: capacitance, voltage, and current; based on the electrical characteristic data, performing electrical measurements at the Die to Die, Wafer to Wafer, and Lot to Lot levels to obtain electrical measurement data.

[0014] To achieve the above object and other related objects, the present invention provides an innovative gate-level inverter good-bad trend analysis system, the system includes: a data collection module, configured to collect the electrical characteristic data of the device test keys for manufacturing the inverter and perform electrical measurements on the device test keys of different process levels to obtain electrical measurement data; a data analysis module, connected to the data collection module, configured to construct a physical model for typical process corner simulation and a variation model for other different process corner simulations based on the electrical characteristic data and the electrical measurement data; a simulation and trend analysis module, connected to the data analysis module, configured to use the SPICE model to perform gate-level circuit simulation on the inverter to calculate the trend angle and perform good-bad trend analysis to obtain the optimized trend angle to determine the device optimization direction; an optimization module, connected to the simulation and trend analysis module, configured to correct the device design based on the device optimization direction to optimize the manufacturing process parameters of the inverter.

[0015] To achieve the above object and other related objects, the present invention provides an electronic terminal, including: one or more memories and one or more processors; the one or more memories are configured to store computer programs; the one or more processors, connected to the memories, are configured to run the computer programs to execute the innovative gate-level inverter good-bad trend analysis method.

[0016] As described above, the present invention is an innovative method, system, and terminal for analyzing the good-bad trends of gate-level inverters, and has the following beneficial effects: By collecting the electrical characteristic data of the device test keys of the inverter and performing electrical measurements on the test keys of different process levels, the present invention obtains electrical measurement data. Based on these data, a physical model for typical process corners and a variation model for other process corners are constructed. Using a mature SPICE model verified by the factory for gate-level circuit simulation, the trend angle is calculated, the optimal trend angle is analyzed and determined, thereby clarifying the device optimization direction. Further, the device design is corrected according to the optimization direction, and the manufacturing process parameters of the inverter are optimized. When analyzing the performance of the gate-level inverter, the present invention fully considers the comprehensive influence of local and global deviations, comprehensively evaluates the performance changes under different process corners, ensures the accuracy of the optimization results, and effectively improves the device performance and reliability. At the same time, by comparing the gate-level trend angle with the device process angle, the device optimization direction is clarified, providing clear guidance for the factory device manufacturing direction, facilitating the adjustment of the device TT value, and promoting the optimization of the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It shows a schematic flow chart of the innovative method for analyzing the good-bad trends of gate-level inverters in an embodiment of the present invention.

[0018] Figure 2 It shows a distribution diagram of the gate-level trend angle of 28nm_2XINV in an embodiment of the present invention.

[0019] Figure 3 It shows a distribution diagram of the virtual experimental data generated by Monte Carlo simulation in an embodiment of the present invention.

[0020] Figure 4 It shows a distribution diagram of the virtual experimental correction data generated by Monte Carlo simulation in an embodiment of the present invention.

[0021] Figure 5 It shows a schematic diagram of combining the corrected data with the trend angle in an embodiment of the present invention.

[0022] Figure 6 It shows a schematic diagram of adjusting the trend by Best-Worst Case analysis in an embodiment of the present invention.

[0023] Figure 7 It shows a schematic diagram of adjusting towards the device optimization direction in an embodiment of the present invention.

[0024] Figure 8 It shows a schematic structural diagram of the innovative system for analyzing the good-bad trends of gate-level inverters in an embodiment of the present invention.

[0025] Figure 9It shows a schematic structural diagram of an electronic terminal in an embodiment of the present invention. Detailed implementation manners

[0026] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0027] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments can also be used, and mechanical composition, structure, electrical, and operational changes can be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is only defined by the claims of the published patent. The terms used here are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "beneath", "lower part", "above", "upper part", etc., can be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0028] Throughout the specification, when it is said that a part is "connected" to another part, this includes not only the case of "direct connection", but also the case of "indirect connection" with other elements placed in between. In addition, when it is said that a certain part "includes" a certain constituent element, unless there is a particularly contrary record, it does not mean excluding other constituent elements, but means that other constituent elements can also be included.

[0029] The first, second, and third, etc. terms mentioned therein are used to illustrate various parts, components, regions, layers, and / or segments, but are not limited thereto. These terms are only used to distinguish a part, component, region, layer, or segment from other parts, components, regions, layers, or segments. Therefore, the first part, component, region, layer, or segment described below can refer to the second part, component, region, layer, or segment without exceeding the scope of the present invention.

[0030] Furthermore, as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the terms "comprises" and "comprising" specify the presence of the stated features, operations, elements, components, items, kinds, and / or groups, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be construed as inclusive, meaning either any one or any combination. Thus, "A, B, or C" or "A, B, and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition occur only when the combinations of elements, functions, or operations are inherently mutually exclusive in some way.

[0031] The present invention provides an innovative method for analyzing the good-bad trend of a gate-level inverter. By collecting the electrical characteristic data of the device test keys of the inverter and performing electrical measurements on the test keys of different process levels, electrical measurement data is obtained. Based on these data, a physical model for typical process corners and a variation model for other process corners are constructed. Using a mature SPICE model verified by the factory for gate-level circuit simulation, the trend angle is calculated, the optimal trend angle is analyzed and determined, so as to clarify the device optimization direction. Further, the device design is corrected according to the optimization direction, and the manufacturing process parameters of the inverter are optimized. When analyzing the performance of the gate-level inverter, the present invention fully considers the comprehensive influence of local and global deviations, comprehensively evaluates the performance changes under different process corners, ensures the accuracy of the optimization results, and effectively improves the device performance and reliability. At the same time, by comparing the gate-level trend angle with the device process angle, the device optimization direction is clarified, providing clear guidance for the device manufacturing direction of the factory, assisting in adjusting the TT value of the device, and promoting the optimization of the device performance.

[0032] The following will be described in detail with reference to the accompanying drawings for the embodiments of the present invention, so that those skilled in the art in the technical field of the present invention can easily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0033] As Figure 1 A schematic flow chart showing an innovative method for analyzing the good-bad trend of a gate-level inverter in an embodiment of the present invention.

[0034] The method includes:

[0035] Step S1: Collect the electrical characteristic data of the device test keys for manufacturing the inverter, and perform electrical measurements on the device test keys of different process levels to obtain electrical measurement data.

[0036] In one embodiment, collecting the electrical characteristic data of the device test keys for manufacturing the inverter and performing electrical measurements on the device test keys at different process levels to obtain electrical measurement data includes:

[0037] Collecting the electrical characteristic data of the device test keys for manufacturing the inverter; wherein, the electrical characteristic data includes: capacitance, voltage, and current; these parameters can comprehensively reflect the electrical performance of the device under different process conditions.

[0038] Performing electrical measurements at the Die to Die, Wafer to Wafer, and Lot to Lot levels based on the electrical characteristic data to obtain electrical measurement data.

[0039] Specifically, for the electrical measurement at the Die to Die level, it is to perform electrical measurements on the test keys of different chips on the same wafer to evaluate the performance differences between different chips within the same wafer. For the electrical measurement at the Wafer to Wafer level, it is to perform electrical measurements on the test keys of different wafers to evaluate the performance differences between different wafers. For the electrical measurement at the Lot to Lot level, it is to perform electrical measurements on the test keys of wafers from different batches to evaluate the performance differences between different batches. Specifically, the electrical measurement data includes: Delay, Power, Threshold Voltage, Drain Current, and Input Capacitance, etc.

[0040] Step S2: Based on the electrical characteristic data and the electrical measurement data, construct a physical model for typical process corner simulation and variant models for other different process corner simulations.

[0041] Specifically, based on the electrical characteristic data (such as capacitance, voltage, current) and the electrical measurement data (such as delay, power), construct a physical model for the typical process corner (TT). This model can accurately describe the electrical behavior of the device under typical process conditions. Based on the electrical characteristic data (such as capacitance, voltage, current) and the electrical measurement data (such as delay, power), construct variant models for other different process corners. These models can accurately describe the electrical behavior of the device under different process conditions.

[0042] In one embodiment, the variant models include: a first variant model and a second variant model;

[0043] In the old process, the local deviation is relatively small, and the global deviation is the main influencing factor. When constructing the K library, both local deviation and global deviation are considered, and the performance changes of the device under different process corners (FF, FS, SF, SS) are evaluated through simulation. The first variation model is mainly for the process corner simulation of the old process and is used for the K library considering local deviation (local variation) and global deviation (global variation) with asymmetry taken into account. The performance changes at other different process corners are obtained through simulation.

[0044] Other process corners simulated by the first variation model include:

[0045] FF (Fast nMOS - Fast pMOS): Fast NMOS and Fast PMOS.

[0046] FS (Fast nMOS - Slow pMOS): Fast NMOS and Slow PMOS.

[0047] SF (Slow nMOS - Fast pMOS): Slow NMOS and Fast PMOS.

[0048] SS (Slow nMOS - Slow pMOS): Slow NMOS and Slow PMOS.

[0049] In the new process, the local deviation increases significantly, and the worst - case model is too conservative. When constructing the K library, only the global process deviation with asymmetry is considered, and the local deviation is compensated by the statistical OCV (process variation) method. The performance changes of the device under different process corners (FFG, FSG, SFG, SSG) are evaluated through simulation. The second variation model is for the process corner simulation of the new process and is used for the K library considering only the global process deviation (global variation) with asymmetry and the statistical OCV methods such as SOCV (Static - process variation) and POCV (Parametric - process variation) for compensating the local process deviation (local variation). The performance changes at different process corners are obtained through simulation;

[0050] Among them, other process corners simulated by the second variation model include:

[0051] FFG (Fast nMOS - Fast pMOS - Global): Fast NMOS and Fast PMOS, considering global deviation.

[0052] FSG (Fast nMOS - Slow pMOS - Global): Fast NMOS and Slow PMOS, considering global deviation.

[0053] SFG (Slow nMOS-Fast pMOS-Global): Slow NMOS and Fast PMOS, considering global deviation.

[0054] SSG (Slow nMOS-Slow pMOS-Global): Slow NMOS and Slow PMOS, considering global deviation.

[0055] By constructing the first variation model and the second variation model, the present invention can comprehensively evaluate the performance changes of gate-level inverters under different process conditions. The first variation model is applicable to the case of small local deviation, while the second variation model is applicable to the case of a significant increase in local deviation. The combination of these two models ensures the accuracy and reliability of device performance evaluation, providing a solid foundation for subsequent optimization.

[0056] Step S3: Use the SPICE model to perform gate-level circuit simulation on the inverter to calculate the trend angle, and conduct an analysis of the advantages and disadvantages trends to obtain the optimal trend angle, so as to determine the device optimization direction.

[0057] Among them, SPICE (Simulation Program with Integrated Circuit Emphasis) is a widely used circuit simulation software, mainly used to simulate and analyze the electrical behavior of integrated circuits. The SPICE model describes the behavior of circuit elements (such as resistors, capacitors, inductors, transistors, etc.) through mathematical equations, and can perform direct current (DC), alternating current (AC), and transient simulations on the circuit.

[0058] In an embodiment, step S3 is the main innovative content of the present invention, which is mainly implemented through the SPICE model. The steps include:

[0059] Step S31: Design the gate-level schematic diagram of the inverter; specifically, the gate-level schematic diagram needs to meet the design specifications and functional requirements, which is the basis for subsequent simulations and requires a detailed definition of the circuit structure and connection method of the inverter.

[0060] Step S32: Set the simulation conditions according to the designed gate-level schematic diagram; specifically, according to the designed gate-level schematic diagram, set the simulation conditions, including logic gate type, standard threshold voltage, external capacitor, simulation period, rise and fall time setting, total simulation time, operating voltage, etc. These conditions will be used for subsequent gate-level circuit simulations to ensure that the simulation results can accurately reflect the device performance under actual working conditions.

[0061] Step S33: Based on the constructed physical model and variation model, perform gate-level circuit simulation on the inverter according to the simulation conditions set by the designed gate-level schematic diagram to obtain the delay and energy consumption of each process corner, so as to determine the gate-level trend angle;

[0062] Step S34: Use the Monte Carlo method to verify the distribution of the gate-level trend angles;

[0063] Step S35: Determine the optimal trend angle through the verified gate-level trend angles by Best_Worst case analysis, and determine the device optimization direction.

[0064] In one embodiment, the set simulation conditions include: DC simulation conditions and transient simulation conditions;

[0065] The DC simulation conditions are used to obtain the best area efficiency ratio (βratio) of N-type transistors and P-type transistors through DC simulation; through DC simulation, the device performance under different area ratios can be evaluated, so as to determine the best area efficiency ratio to optimize the device design.

[0066] The transient simulation conditions are used to obtain the power consumption and delay data of each process corner through transient simulation. Through transient simulation, the power consumption and delay performance of the inverter under different process corners can be evaluated, providing data support for subsequent trend angle analysis and optimization.

[0067] In one embodiment, step S33 includes:

[0068] Based on the constructed physical model, perform transient simulation on the inverter to obtain the delay and energy consumption values of the typical process corner (TT), and use the delay and energy consumption values of the typical process corner (TT) as the values of the typical trend angles. The typical trend angles reflect the performance trends of the device under standard process conditions.

[0069] Based on the constructed first variation model and second variation model, perform transient simulation on the inverter to obtain the delay and energy consumption values of the process corners (FF, FS, SF, SS) of the first variation model and the process corners (FFG, FSG, SFG, SSG) of the second variation model. Use the delay and energy consumption values of each process corner (such as FF, FS, SF, SS) simulated by the first variation model as the values of each total trend angle, and use the delay and energy consumption values of each process corner (such as FFG, FSG, SFG, SSG) simulated by the second variation model as the values of each global trend angle. The total trend angles reflect the performance trends of the device under different process conditions, and the global trend angles reflect the performance trends of the device under different process conditions considering global effects.

[0070] In one embodiment, the Monte Carlo method is mainly used to verify the distribution of each global trend angle. Step S34 includes:

[0071] Use the Monte Carlo method to perform multiple transient simulations (e.g., 5000 times) to evaluate the impact of random variables (such as random variations in device parameters) on the performance of the inverter. In each simulation, record the delay and power consumption values of the inverter. Obtain the delay and power consumption values for each simulation; the Monte Carlo method is a statistical method that evaluates the impact of random variables on circuit performance through random sampling.

[0072] Collectively correct all the delay and power consumption values obtained from the simulations with respect to time. Use the power consumption value of each simulation as the abscissa and the delay value as the ordinate to form multiple data points. Generate the corrected data points, which reflect the dynamic performance of the circuit under different random conditions. Collectively correct all the delay and power consumption values obtained from the simulations with respect to time to ensure that all simulation data is aligned on the time axis and eliminate possible time biases.

[0073] Combine the corrected data points with the global trend angle to obtain the global trend angle verification result, and generate a comprehensive analysis chart to visually display the relationship between the Monte Carlo simulation results and the global trend angle.

[0074] This process ensures that the global trend angle can accurately reflect the device performance changes under actual manufacturing conditions, providing a scientific basis for subsequent optimization.

[0075] In one embodiment, step S35 includes:

[0076] Analyze the typical trend angle, each total trend angle, and the global trend angle verification result through Best_Worst case to obtain the optimized adjustment trend (short delay, low energy consumption) and the worst-case adjustment trend (long delay, high energy consumption), and determine SF and SFG as the optimized trend angles;

[0077] Take the direction of making the value of the typical trend angle (TT) approach the values of SF and SFG as the device optimization direction. Specifically, by adjusting the value of the typical trend angle (TT) to make it approach the values of the optimized trend angles (SF and SFG), the gate-level delay and energy consumption can achieve the optimized results.

[0078] Step S4: Modify the device design parameters based on the device optimization direction to optimize the manufacturing process parameters of the inverter.

[0079] Specifically, determine the optimized trend angles (SF and SFG) through step 3. These trend angles represent the best states of the inverter performance under different process conditions. The goal is to adjust the value of the typical trend angle (TT) to make it as close as possible to the values of SF and SFG, thereby achieving the optimization of the gate-level delay and energy consumption.

[0080] The adjustable device design parameters include: adjusting the doping concentration to change the threshold voltage and mobility of the device. For example, increasing the doping concentration can shift the device performance towards "fast", thus approaching the optimized trend angle; optimizing the oxide layer thickness to affect the capacitance and threshold voltage of the device, and further adjusting the switching speed and power consumption; controlling the heat treatment process (such as annealing temperature and time) to improve the crystal structure and electrical properties of the device; adjusting the precision of the lithography and etching processes to reduce the variation in device performance. These measures work together to effectively optimize the performance trend angle of the device and make it closer to the optimization target.

[0081] To better illustrate the method for analyzing the advantages and disadvantages trend of the innovative gate-level inverter, the following specific embodiments are now used for specific illustration.

[0082] Embodiment: A method for analyzing the advantages and disadvantages trend of a 28-node logic gate-level inverter (28nm_2XINV).

[0083] The method includes:

[0084] 1. Data collection and analysis: Collect the capacitance, voltage, current, etc. of the device test keys of 28nm_2XINV, perform electrical measurements at the Die to Die, Wafer to Wafer, and Lot to Lot levels to obtain electrical measurement data, and construct a physical model for typical process angle simulation and variation models for other different process angles (FF, FS, SF, SS) and (FFG, FSG, SFG, SSG).

[0085] 2. Use a mature and factory-verified SPICE model for gate-level simulation to generate trend angles, and perform a benchmark analysis of the gate-level trend angles (delay and power consumption) with the device process angles (current and voltage).

[0086] 2.1 Gate-level schematic design and simulation condition setting;

[0087] Design the gate-level schematic of 28nm_2XINV and set the simulation conditions. The specific DC simulation conditions and transient simulation conditions are shown in Table 1.

[0088] Table 1: Simulation condition parameter table

[0089]

[0090] 2.2 Gate-level circuit simulation and trend angle determination;

[0091] Based on the constructed physical model and variation model, gate-level circuit simulation of the inverter is carried out according to the set simulation conditions to obtain the delay and power consumption at each process corner, so as to determine the gate-level trend angle. As shown in Table 2, the TT / FF / SS / FS / SF values are generated by device simulation (N-channel and P-channel process corners), and the FFG / SSG / FSG / SFG values are generated after adding the global effects of the device (N-channel and P-channel process corners). The delay and power consumption of the generated device process corners are regarded as the gate-level trend angles, including the typical trend angle TT, each total trend angle Total corner, and each global trend angle Global corner, and a trend angle diagram is generated with power consumption and delay as the horizontal and vertical coordinates, such as Figure 2 . Through the above simulation, the generated trend angle diagram can intuitively display the delay and power consumption under different process corners. The comparative analysis of the typical trend angle TT, the total trend angle Total corner, and the global trend angle Global corner helps to identify the best and worst performance conditions and provides a basis for subsequent device optimization and manufacturing process adjustment.

[0092] Table 2: Delay and power consumption values at each process corner

[0093]

[0094] 3. Analyze and verify the global trend angle distribution by MC;

[0095] Use the Monte Carlo simulation method to analyze and verify the global trend angle distribution. Monte Carlo simulation is a method that simulates the system behavior through random sampling and can effectively evaluate the impact of process variations on circuit performance. The more simulation times, the more accurate the results. In this experiment, a total of 5000 simulations were carried out to ensure the reliability of the results. Use Monte Carlo simulation to generate virtual experimental data. The simulation results show the delay and power distribution under different process variations, such as Figure 3 shown. Since the simulation is a transient simulation, the common X coordinate of delay and power is time. Correct the delay and power simulation results with respect to time to eliminate the effects of time offset and noise, so as to obtain the corrected data diagram, such as Figure 4 shown. Combine the 5000 corrected data points with the trend angle data obtained from device simulation before to generate a comprehensive trend angle distribution diagram, such as Figure 5 shown. Through this combined analysis, the performance distribution under different process corners can be evaluated more comprehensively.

[0096] 4. Best-Worst case analysis;

[0097] Using the completed simulation diagrams, analyze the delays and power consumptions at different process corners. Determine that the process corner with the shortest delay and the lowest power consumption is the Best - case, and the process corner with the longest delay and the highest power consumption is the Worst - case. From the simulation results, the Best - case and Worst - case can be intuitively identified from Figure 6 According to the simulation results, it is determined that SFG (Slow - Fast Global) and SF (Slow - Fast) are the most optimized trend corners (Best - case) at the INV gate level. These trend corners perform best in terms of delay and power consumption, as shown in Table 3.

[0098] Table 3: Delay and Power Consumption Table of Trend Corners and Process Corners at INV Gate Level

[0099]

[0100] Four process corners, namely FF, SS, FS, and SF, are derived from the typical process corner through three - times standard deviation. As Figure 7 As long as the value of the typical trend corner (TT) is made closer to the values of SF and SFG, the optimal results (Best - case) for gate - level delay and power consumption can be achieved.

[0101] Similar to the principle of the above - mentioned embodiment, the present invention provides an innovative system for analyzing the best - worst trends of gate - level inverters.

[0102] The following provides specific embodiments in conjunction with the accompanying drawings:

[0103] As Figure 8 shows a schematic structural diagram of an innovative system for analyzing the best - worst trends of gate - level inverters in an embodiment of the present invention.

[0104] The system includes:

[0105] A data collection module 1, which is used to collect the electrical characteristic data of the device test keys for manufacturing inverters, and perform electrical measurements on the device test keys at different process levels to obtain electrical measurement data;

[0106] A data analysis module 2, connected to the data collection module 1, which is used to construct a physical model for simulating the typical process corner and a variation model for simulating other different process corners based on the electrical characteristic data and the electrical measurement data;

[0107] A simulation and trend analysis module 3, connected to the data analysis module 2, which is used to perform gate - level circuit simulation of the inverter using the SPICE model to calculate the trend corners, and perform best - worst trend analysis to obtain the most optimized trend corners to determine the device optimization direction;

[0108] Optimization module 4, connected to the simulation and trend analysis module 3, is used to correct the device design based on the device optimization direction to optimize the manufacturing process parameters of the inverter.

[0109] Since the implementation principle of the innovative gate-level inverter good-bad trend analysis system has been described in the foregoing embodiments, it will not be repeated here.

[0110] The innovative gate-level inverter good-bad trend analysis method provided by the embodiments of the present invention can be implemented on the terminal side or the server side. In terms of the hardware structure of the electronic terminal, please refer to Figure 8 , which is an optional hardware structure schematic diagram of the electronic terminal 1000 provided by the embodiments of the present invention. The terminal 1000 can be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010, and a user interface 1009. Each component in the device is coupled together through a bus system 1005. It can be understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1005 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, in Figure 7 all kinds of buses are labeled as the bus system.

[0111] Among them, the user interface 1009 may include a display, a keyboard, a mouse, a trackball, a click gun, a key, a button, a touchpad, or a touch screen, etc.

[0112] It can be understood that the memory 1002 can be a volatile memory or a non-volatile memory, and may also include both a volatile and a non-volatile memory. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM, Static Random Access Memory), synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory). The memory described in the embodiments of the present invention is intended to include but not be limited to these and any other suitable categories of memory.

[0113] The memory 1002 in the embodiments of the present invention is used to store various types of data to support the operation of the terminal 1000. Examples of such data include: any executable programs for operating on the terminal 1000, such as the operating system 10021 and application programs 10022; the operating system 10021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application programs 10022 may include various application programs, such as a MediaPlayer, a Browser, etc., for implementing various application services. The innovative gate-level inverter good-bad trend analysis method provided by the embodiments of the present invention may be included in the application program 10022.

[0114] The method disclosed in the above embodiments of the present invention may be applied to the processor 1001 or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method may be completed by the integrated logic circuit in the hardware of the processor 1001 or instructions in software form. The above-mentioned processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 may implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The processor 1001 may be a microprocessor or any conventional processor, etc. Combining the steps of the accessory optimization method provided by the embodiments of the present invention may be directly embodied as being completed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, and this storage medium is located in the memory. The processor reads the information in the memory and combines its hardware to complete the steps of the foregoing method.

[0115] In an exemplary embodiment, the terminal 1000 may be one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs) for executing the foregoing method.

[0116] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to a computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including those of the above method embodiments; and the aforementioned storage medium includes: various media such as ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0117] In the embodiments provided in the present application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM, or other optical disc storage devices, magnetic disk storage devices, or other magnetic storage devices, flash memory, USB flash drives, mobile hard disks, or any other medium that can be used to store desired program codes in the form of instructions or data structures and can be accessed by a computer. Additionally, any connection can be appropriately referred to as a computer-readable medium. For example, if instructions are sent from a website, server, or other remote source using coaxial cables, fiber optic cables, twisted pairs, digital subscriber lines (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cables, fiber optic cables, twisted pairs, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended to refer to non-transient, tangible storage media. As used in the application, magnetic disks and optical discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where magnetic disks typically replicate data magnetically, while optical discs optically replicate data using lasers.

[0118] In summary, the innovative gate-level inverter good-bad trend analysis method, system, and terminal of the present invention collect the electrical characteristic data of the device test keys of the inverter, and perform electrical measurements on the test keys of different process levels to obtain electrical measurement data. Based on these data, a physical model for typical process corners and a variation model for other process corners are constructed. Using a mature SPICE model verified by the factory for gate-level circuit simulation, the trend angle is calculated, the optimal trend angle is analyzed and determined, thereby clarifying the device optimization direction. Further, the device design is corrected according to the optimization direction, and the manufacturing process parameters of the inverter are optimized. When analyzing the performance of the gate-level inverter, the present invention fully considers the comprehensive influence of local and global deviations, comprehensively evaluates the performance changes under different process corners, ensures the accuracy of the optimization results, and effectively improves the device performance and reliability. At the same time, by comparing the gate-level trend angle with the device process angle, the device optimization direction is clarified, providing a clear guidance for the factory device manufacturing direction, assisting in the adjustment of the device TT value, and promoting the optimization of the device performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0119] The above embodiments are only used to exemplarily illustrate the principles and effects of the present invention, rather than to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An innovative method for analyzing the superiority and inferiority trends of gate-level inverters, characterized in that, The method includes: Collecting the electrical characteristic data of the device test keys for manufacturing the inverter, and performing electrical measurements on the device test keys of different process levels to obtain electrical measurement data; Based on the electrical characteristic data and the electrical measurement data, constructing a physical model for typical process corner simulation and variant models for other different process corner simulations; Using the SPICE model to perform gate-level circuit simulation on the inverter to calculate the trend angle, and performing advantage and disadvantage trend analysis to obtain the optimized trend angle to determine the device optimization direction; Based on the device optimization direction, correcting the device design parameters to optimize the manufacturing process parameters of the inverter.

2. The innovative gate-level inverter advantage-disadvantage trend analysis method according to claim 1, characterized in that, The variant models include: a first variant model and a second variant model; The first variant model simulates the performance changes of other different process corners for the process local deviation and process global deviation of asymmetry; among them, the other process corners simulated by the first variant model include: FF, FS, SF, and SS; The second variant model is used to simulate the performance changes of different process corners based on only considering the process global deviation of asymmetry and the statistical process variation method for compensating the process local deviation; among them, the other process corners simulated by the second variant model include: FFG, FSG, SFG, and SSG.

3. The innovative gate-level inverter advantage-disadvantage trend analysis method according to claim 2, characterized in that Using the SPICE model to perform gate-level circuit simulation on the inverter to calculate the trend angle, and performing advantage and disadvantage trend analysis to obtain the optimized trend angle to determine the device optimization direction includes: Designing the gate-level schematic diagram of the inverter; Setting the simulation conditions according to the designed gate-level schematic diagram; Based on the constructed physical model and variant models, performing gate-level circuit simulation on the inverter according to the simulation conditions set by the designed gate-level schematic diagram to obtain the delay and power consumption of each process corner to determine the gate-level trend angle; Using the Monte Carlo method to verify the distribution of the gate-level trend angle; Verifying the gate-level trend angle after the Best_Worst case analysis, determining the optimized trend angle, and determining the device optimization direction.

4. The innovative gate-level inverter good-bad trend analysis method according to claim 3, characterized in that The set simulation conditions include: DC simulation conditions and transient simulation conditions; the DC simulation conditions are used to obtain the optimal area efficiency ratio of the N-type transistor and the P-type transistor through DC simulation; the transient simulation conditions are used to obtain the power consumption and delay data of each process corner through transient simulation.

5. The innovative gate-level inverter advantage-disadvantage trend analysis method according to claim 4, characterized in that The performing gate-level circuit simulation on the inverter according to the simulation conditions set by the designed gate-level schematic diagram based on the constructed physical model and variant models to obtain the delay and power consumption of each process corner to determine the gate-level trend angle includes: Based on the constructed physical model and variant models, performing transient simulation on the inverter to obtain the delay and power consumption values of each process corner, and obtaining the typical trend angle, total trend angle, and global trend angle; among them, using the delay and power consumption values of the typical process corner as the values of the typical trend angle, using the delay and power consumption values of each process corner simulated by the first variant model as the values of each trend angle, and using the delay and power consumption values of each process corner simulated by the second variant model as the values of the global trend angle.

6. The innovative gate-level inverter advantage-disadvantage trend analysis method according to claim 5, characterized in that The using the Monte Carlo method to verify the distribution of the gate-level trend angle includes: Performing multiple transient simulations using the Monte Carlo method to obtain the delay and power consumption values of each simulation; Commonly correct the time for all the obtained delay and power consumption values from the simulation; Merge the corrected delay and power consumption values of each simulation with the global trend angle to obtain the global trend angle verification result.

7. The innovative gate-level inverter advantage-disadvantage trend analysis method according to claim 6, characterized in that, The method of determining the optimized trend angle based on the gate-level trend angle verified by the Best_Worst case analysis and making the value of the typical trend angle approach the value of the optimized trend angle as the device optimization direction includes: Obtain the optimized adjustment trend and the worst-case adjustment trend by analyzing the typical trend angle, the total trend angle, and the global trend angle verification result through the Best_Worst case analysis, and determine SF and SFG as the optimized trend angles; Take the direction in which the value of the typical trend angle approaches the values of SF and SFG as the device optimization direction.

8. The innovative gate-level inverter good-bad trend analysis method according to claim 1, wherein The method of collecting the electrical characteristic data of the device test keys for manufacturing inverters and performing electrical measurements on the device test keys at different process levels to obtain the electrical measurement data includes: Collect the electrical characteristic data of the device test keys for manufacturing inverters; among them, the electrical characteristic data includes: capacitance, voltage, and current; Based on the electrical characteristic data, perform electrical measurements at the Die to Die, Wafer to Wafer, and Lot to Lot levels to obtain the electrical measurement data.

9. An innovative gate-level inverter good-bad trend analysis system, characterized in that, The system includes: A data collection module, configured to collect the electrical characteristic data of the device test keys for manufacturing inverters and perform electrical measurements on the device test keys at different process levels to obtain the electrical measurement data; A data analysis module, connected to the data collection module, configured to construct a physical model for simulating the typical process angle and a variation model for simulating other different process angles based on the electrical characteristic data and the electrical measurement data; A simulation and trend analysis module, connected to the data analysis module, configured to use the SPICE model to perform gate-level circuit simulation on the inverter to calculate the trend angle and perform the best-worst trend analysis to obtain the optimized trend angle so as to determine the device optimization direction; An optimization module, connected to the simulation and trend analysis module, configured to correct the device design based on the device optimization direction to optimize the manufacturing process parameters of the inverter.

10. An electronic terminal, characterized in that, Includes: One or more memories and one or more processors; The one or more memories are used to store computer programs; The one or more processors, connected to the memories, are configured to run the computer programs to execute the method according to any one of claims 1 to 8.

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