Application method and system of high-effect wire bonding technology in storage chip packaging

Abstract

The invention relates to the technical field of microelectronic packaging, and discloses an application method and system of a high-efficiency lead bonding technology in storage chip packaging, and the method comprises the steps: determining a lead high-energy efficiency condition of a storage chip, analyzing the lead performance of a to-be-selected lead, and according to the lead high-energy efficiency condition and the lead performance, determining the high-energy efficiency condition of the to-be-selected lead; screening out a high-energy-efficiency bonding wire of the memory chip from the to-be-selected wires; the bending radius, the lead length and the lead angle of the high-energy-efficiency bonding lead are calculated, and a lead forming control module of the high-energy-efficiency bonding lead is constructed; the bonding parameters and the influence coefficient of the bonding effect are analyzed, and a bonding parameter optimization module of the high-energy-efficiency bonding wire is constructed; determining a packaging temperature range of the storage chip, monitoring real-time temperature data of a packaging area corresponding to the storage chip, and constructing a thermal management module of the storage chip and the high-energy-efficiency bonding wire; and the packaging control module of the integrated storage chip is used for executing packaging control of the storage chip. According to the invention, the packaging efficiency and quality of the storage chip can be improved.

Description

Technical Field

[0001] The present invention relates to an application method and system of a high-efficiency wire bonding technology in the packaging of memory chips, belonging to the field of microelectronic packaging technology. Background Art

[0002] Memory chip packaging is a branch of semiconductor packaging technology, which involves packaging memory chips (such as DRAM, NAND Flash, NOR Flash, etc.) in a protective housing and providing electrical connections to external circuits. The packaging not only protects the chip from physical and environmental damage but also ensures the electrical and thermal performance of the chip.

[0003] Currently, memory chip packaging mainly uses plastic packaging and ceramic packaging. This method mainly uses traditional wire bonding technology for connection, resulting in a slow bonding speed and poor heat conduction, which causes the chip to overheat and the chip packaging effect to be poor.

[0004] Therefore, there is an urgent need for a solution to improve the efficiency and quality of memory chip packaging. Summary of the Invention

[0005] The present invention provides an application method and system of a high-efficiency wire bonding technology in the packaging of memory chips, and its main purpose is to improve the efficiency and quality of memory chip packaging.

[0006] To achieve the above object, an application method of a high-efficiency wire bonding technology in the packaging of memory chips provided by the present invention includes: Clarify the packaging requirements of the memory chip. Based on the packaging requirements, determine the high-energy efficiency conditions of the leads of the memory chip, obtain the candidate leads of the memory chip, analyze the lead performance of the candidate leads, and screen out the high-energy efficiency bonding leads of the memory chip from the candidate leads according to the lead high-energy efficiency conditions and the lead performance; Identify the chip pad positions of the memory chip and the substrate pad positions of the corresponding packaging substrate of the memory chip. According to the chip pad positions and the substrate pad positions, calculate the bending radius, lead length, and lead angle of the high-energy efficiency bonding leads, and construct a lead forming control module for the high-energy efficiency bonding leads according to the bending radius, the lead length, and the lead angle; Obtain the wire bonding data of the memory chip, identify the bonding parameters and bonding effects in the wire bonding data, analyze the influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data, and construct a bonding parameter optimization module for the high-energy efficiency bonding leads according to the influence coefficients; Analyze the chip thermal characteristics of the storage chip and the lead thermal characteristics of the high-energy efficiency bonding leads. According to the chip thermal characteristics and the lead thermal characteristics, determine the packaging temperature range of the storage chip, construct a packaging temperature monitoring unit for the storage chip, and based on the packaging temperature monitoring unit, monitor the real-time temperature data of the corresponding packaging area of the storage chip in real time. According to the packaging temperature range and the real-time temperature data, construct a thermal management module for the storage chip and the high-energy efficiency bonding leads; Integrate the packaging control module of the storage chip according to the lead forming control module, the bonding parameter optimization module, and the thermal management module, and based on the packaging control module, perform the packaging control of the storage chip.

[0007] Optionally, the analysis of the lead performance of the candidate leads includes: Measure the lead resistance, lead inductance, and lead capacitance of the candidate leads; Determine the electrical performance of the candidate leads according to the lead resistance, the lead inductance, and the lead capacitance; Conduct a thermal performance test on the candidate leads to obtain test data; According to the test data, calculate the thermal conductivity and thermal expansion coefficient of the candidate leads by using the following formula: Wherein, represents the thermal conductivity, represents the thermal expansion coefficient, represents the heat corresponding to the test data, represents the cross-sectional area of the candidate leads, represents the temperature difference, represents the heat conduction distance corresponding to the test data, represents the original length of the candidate leads, represents the length change; Determine the thermal performance of the candidate leads according to the thermal conductivity and the thermal expansion coefficient; Conduct a tensile test on the candidate leads to obtain tensile test data; Analyze the mechanical performance of the candidate leads according to the tensile test data; Determine the lead performance of the candidate leads according to the electrical performance, the thermal performance, and the mechanical performance.

[0008] Optionally, the identification of the chip pad position of the storage chip and the substrate pad position of the packaging substrate corresponding to the storage chip includes: Collect the chip image data of the storage chip and the substrate image data of the packaging substrate; Extract the chip image features of the chip image data and the substrate image features of the substrate image data respectively; Determine the chip pad pixel coordinates of the memory chip according to the chip image features; Determine the substrate pad pixel coordinates of the packaging substrate according to the substrate image features; Determine the chip pad position of the memory chip and the substrate pad position of the packaging substrate according to the chip pad pixel coordinates and the substrate pad pixel coordinates.

[0009] Optionally, calculating the bending radius, lead length and lead angle of the high-energy efficiency bonding lead according to the chip pad position and the substrate pad position includes: Construct a two-dimensional coordinate system of the chip pad position and the substrate pad position; Determine the chip pad coordinates of the chip pad position and the substrate pad coordinates of the substrate pad position according to the two-dimensional coordinate system; Fit the lead bending path of the high-energy efficiency bonding lead according to the chip pad coordinates and the substrate pad coordinates; Fit the path function of the lead bending path, where the path function includes: Wherein, Represents the path function, Represents the position variable of the path function, Represents the bending coefficient of the path function, Represents the abscissa of the vertex of the lead bending path, Represents the ordinate of the vertex of the lead bending path, Represents the exponential parameter of the lead bending path; Calculate the bending radius, lead length and lead angle of the high-energy efficiency bonding lead according to the path function.

[0010] Optionally, constructing the lead forming control module of the high-energy efficiency bonding lead according to the bending radius, the lead length and the lead angle includes: Configure the lead forming machine of the high-energy efficiency bonding lead; Define the lead forming control algorithm of the lead forming machine according to the bending radius, the lead length and the lead angle; Calculate the working parameters of the lead forming machine according to the lead forming control algorithm; Construct a motion monitoring unit of the lead forming machine, and monitor the real-time motion data of the lead forming machine based on the motion monitoring unit; Construct a feedback mechanism for the lead forming machine according to the working parameters and the real-time motion data; Construct a lead forming control module for the high-energy efficiency bonding lead according to the lead forming machine, the lead forming control algorithm, and the feedback mechanism.

[0011] Optionally, the analysis of the influence coefficients of the bonding parameters and the bonding effect based on the lead bonding data includes: Perform data cleaning on the lead bonding data to obtain cleaned data, and normalize the cleaned data to obtain normalized data; Calculate the correlation coefficients of the bonding parameters and the bonding effect according to the normalized data; Construct a regression analysis model for the bonding parameters and the bonding effect; Analyze the influence degree of the bonding parameters on the bonding effect according to the regression analysis model; Determine the influence coefficients of the bonding parameters and the bonding effect according to the correlation coefficients and the influence degree.

[0012] Optionally, the construction of the bonding parameter optimization module for the high-energy efficiency bonding lead according to the influence coefficients includes: Determine the optimization objectives of the bonding parameters corresponding to the high-energy efficiency bonding lead; Analyze the bonding scenarios of the high-energy efficiency bonding lead, and determine the constraint conditions of the high-energy efficiency bonding lead based on the bonding scenarios; Define an optimization algorithm for the bonding parameters according to the constraint conditions and the influence coefficients; Determine the optimization iteration mechanism of the bonding parameters according to the optimization objectives; Construct a bonding parameter optimization module for the high-energy efficiency bonding lead according to the optimization algorithm and the optimization iteration mechanism.

[0013] Optionally, the construction of the package temperature monitoring unit for the storage chip includes: Determine the temperature sensor of the storage chip and the sensor installation position of the temperature sensor; Construct a signal conditioning circuit and a microprocessor for the temperature sensor; Determine the monitoring unit network topology of the storage chip according to the sensor installation position, the temperature sensor, and the microprocessor; Determine the data transmission mode and communication protocol of the temperature sensor; Construct a package temperature monitoring unit for the storage chip according to the monitoring unit network topology, the communication protocol, and the signal conditioning circuit.

[0014] Optionally, based on the encapsulation temperature range and the real-time temperature data, a thermal management module for the storage chip and the high-energy efficiency bonding wire is constructed, including: A temperature regulator for the storage chip and the high-energy efficiency bonding wire; Analyze the temperature difference between the real-time temperature data and the encapsulation temperature range; Based on the temperature difference, define a temperature control algorithm for the storage chip and the high-energy efficiency bonding wire; Based on the temperature control algorithm, determine the temperature control logic for the storage chip and the high-energy efficiency bonding wire; Based on the temperature regulator, the temperature control algorithm, and the temperature control logic, construct a thermal management module for the storage chip and the high-energy efficiency bonding wire.

[0015] To solve the above problems, the present invention also provides an application system of a high-performance wire bonding technology in the encapsulation of a storage chip, and the system includes: A bonding wire determination module, configured to clarify the encapsulation requirements of the storage chip, based on the encapsulation requirements, determine the high-energy efficiency conditions of the leads of the storage chip, obtain the candidate leads of the storage chip, analyze the lead performance of the candidate leads, and screen out the high-energy efficiency bonding wires of the storage chip from the candidate leads according to the lead high-energy efficiency conditions and the lead performance; A lead forming control module, configured to identify the chip pad position of the storage chip and the substrate pad position of the corresponding encapsulation substrate of the storage chip, calculate the bending radius, lead length, and lead angle of the high-energy efficiency bonding wire according to the chip pad position and the substrate pad position, and construct a lead forming control module for the high-energy efficiency bonding wire according to the bending radius, the lead length, and the lead angle; A bonding parameter optimization module, configured to obtain the wire bonding data of the storage chip, identify the bonding parameters and bonding effects in the wire bonding data, analyze the influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data, and construct a bonding parameter optimization module for the high-energy efficiency bonding wire according to the influence coefficients; A thermal management module, configured to analyze the chip thermal characteristics of the storage chip and the lead thermal characteristics of the high-energy efficiency bonding wire, determine the encapsulation temperature range of the storage chip according to the chip thermal characteristics and the lead thermal characteristics, construct an encapsulation temperature monitoring unit for the storage chip, based on the encapsulation temperature monitoring unit, monitor the real-time temperature data of the corresponding encapsulation area of the storage chip in real time, and construct a thermal management module for the storage chip and the high-energy efficiency bonding wire according to the encapsulation temperature range and the real-time temperature data; The encapsulation control module is used to integrate the encapsulation control module of the storage chip according to the lead forming control module, the bonding parameter optimization module, and the thermal management module, and perform the encapsulation control of the storage chip based on the encapsulation control module.

[0016] In the embodiment of the present invention, by screening out the high-energy-efficiency bonding leads of the storage chip from the candidate leads according to the high-energy-efficiency conditions and performance of the leads, signal transmission can be optimized, signal delay and distortion can be reduced, signal integrity can be improved, which helps to conduct heat from the chip to the heat dissipation system faster, reduce the chip operating temperature, and improve reliability; optionally, in the embodiment of the present invention, by calculating the bending radius, lead length, and lead angle of the high-energy-efficiency bonding leads according to the chip pad position and the substrate pad position of the storage chip, the chip pad position of the storage chip and the substrate pad position of the corresponding packaging substrate of the storage chip, the heat flow path can be optimized, the heat conduction efficiency can be improved, which helps the heat dissipation of the chip, and at the same time helps to reduce signal interference and crosstalk, and improve the stability and reliability of the circuit; in the embodiment of the present invention, by analyzing the influence coefficients of the bonding parameters and the bonding effect based on the lead bonding data, it can be accurately identified which bonding parameters have the greatest impact on the solder joint quality, so as to optimize these parameters targeted and improve the consistency and reliability of the solder joints; in the embodiment of the present invention, by analyzing the chip thermal characteristics of the storage chip and the lead thermal characteristics of the high-energy-efficiency bonding leads, it can be ensured that the chip will not be damaged due to overheating during the bonding process, thereby improving the thermal management efficiency, reducing the thermal resistance, and enhancing the overall heat dissipation performance; in the embodiment of the present invention, by constructing the thermal management module of the storage chip and the high-energy-efficiency bonding leads according to the encapsulation temperature range and the real-time temperature data, it can be ensured that during the encapsulation process, the temperatures of the chip and the bonding leads are accurately controlled within the optimal range, avoiding chip or lead damage caused by too high or too low temperatures, thereby improving the encapsulation quality. Finally, in the embodiment of the present invention, by performing the encapsulation control of the storage chip based on the encapsulation control module, the defect rate can be reduced, and the reliability and long-term stability of the encapsulation can be improved through optimizing the encapsulation parameters and process control. Therefore, the application method and system of the high-energy-efficiency lead bonding technology in the storage chip encapsulation provided by the embodiment of the present invention can improve the efficiency and quality of the storage chip encapsulation. Description of the Drawings

[0017] Figure 1 It is a schematic flowchart of the application method of the high-energy-efficiency lead bonding technology in the storage chip encapsulation provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of the module for implementing the application method of the high-energy-efficiency lead bonding technology in the storage chip encapsulation provided by an embodiment of the present invention.

[0018] The implementation, functional features, and advantages of the present invention will be further described in conjunction with embodiments and with reference to the accompanying drawings. Detailed implementation manners

[0019] It should be understood that the specific embodiments described herein are merely used to explain the present invention and are not used to limit the present invention.

[0020] The embodiments of the present application provide an application method of a high-performance wire bonding technology in the packaging of storage chips. The execution subject of the application method of the high-performance wire bonding technology in the packaging of storage chips includes, but is not limited to, at least one of electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiments of the present application. In other words, the application method of the high-performance wire bonding technology in the packaging of storage chips can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to: a single server, a server cluster, a cloud server, or a cloud server cluster, etc.

[0021] Embodiment 1: Referring to Figure 1 As shown, it is a flowchart of an application method of a high-performance wire bonding technology in the packaging of storage chips provided by an embodiment of the present invention. In this embodiment, the application method of the high-performance wire bonding technology in the packaging of storage chips includes: S1. Define the packaging requirements of the storage chip. Based on the packaging requirements, determine the high-energy efficiency conditions of the leads of the storage chip, obtain the candidate leads of the storage chip, analyze the lead performance of the candidate leads, and screen out the high-energy efficiency bonding leads of the storage chip from the candidate leads according to the lead high-energy efficiency conditions and the lead performance.

[0022] By defining the packaging requirements of the storage chip in the embodiments of the present invention, the electrical connection can be optimized, the resistance and signal loss can be reduced, and the performance of the chip can be improved. Among them, the packaging requirements refer to a series of technical specifications and performance targets set for the packaging process of the storage chip to ensure that the packaged chip can meet the requirements of predetermined performance, reliability, cost, and production efficiency, etc.

[0023] By determining the high-energy efficiency conditions of the leads of the storage chip based on the packaging requirements in the embodiments of the present invention, it can help improve the heat conduction efficiency and reduce the thermal resistance, so as to more effectively manage the heat generated by the chip and prevent overheating. Among them, the lead high-energy efficiency conditions refer to a series of technical parameters and standards that must be met in the packaging process of the storage chip to achieve optimal electrical, thermodynamic, mechanical, and reliability performance.

[0024] Optionally, as an embodiment of the present invention, the determining the high-energy efficiency conditions of the leads of the storage chip based on the packaging requirements can be determined by the materials genome project.

[0025] In an embodiment of the present invention, by obtaining the candidate leads of the storage chip, the lead with the highest cost performance can be selected by comparing the costs and performances of different leads, improving the packaging effect and reducing the production cost. Among them, the candidate leads refer to the lead materials or types that are screened out as potential options according to the packaging requirements and design standards during the packaging process of the storage chip.

[0026] In an embodiment of the present invention, by analyzing the lead performance of the candidate leads, the mechanical strength and durability of the leads can be evaluated to ensure that the leads are not easily broken or worn during assembly, transportation, and use, which helps to achieve high performance, high reliability, and low cost of the product. Among them, the lead performance refers to a series of technical indicators that measure the performance of the leads in the packaging of the storage chip, including: electrical performance, thermal performance, and mechanical performance.

[0027] As an embodiment of the present invention, the analysis of the lead performance of the candidate leads includes: Measuring the lead resistance, lead inductance, and lead capacitance of the candidate leads; Determining the electrical performance of the candidate leads according to the lead resistance, the lead inductance, and the lead capacitance; Conducting a thermal performance test on the candidate leads to obtain test data; According to the test data, calculating the thermal conductivity and coefficient of thermal expansion of the candidate leads using the following formula: Among them, represents the thermal conductivity, represents the coefficient of thermal expansion, represents the heat corresponding to the test data, represents the cross-sectional area of the candidate leads, represents the temperature difference, represents the heat conduction distance corresponding to the test data, represents the original length of the candidate leads, represents the length change; Determining the thermal performance of the candidate leads according to the thermal conductivity and the coefficient of thermal expansion; Conducting a tensile test on the candidate leads to obtain tensile test data; Analyzing the mechanical performance of the candidate leads according to the tensile test data; Determining the lead performance of the candidate leads according to the electrical performance, the thermal performance, and the mechanical performance.

[0028] Among them, the lead resistance refers to the resistance value of the lead (or bonding wire, wire) connecting the chip to the external circuit itself. The lead inductance refers to the self-inductance phenomenon generated by the lead (or bonding wire) in the circuit due to the change of its current. The lead capacitance refers to the capacitance effect generated by the charge distribution between the leads (or bonding wires) and between the leads and other conductors (such as chip pads, PCB traces, ground planes, etc.). The electrical performance refers to the electrical-related characteristics exhibited by the leads in an electronic circuit, and these characteristics directly affect the function, reliability, and efficiency of the circuit. The test data refers to the quantitative and qualitative information collected during various thermal performance tests on the candidate leads. The thermal conductivity refers to the amount of heat passing through per unit time per unit length and unit cross-sectional area of a material under a unit temperature difference. The coefficient of thermal expansion refers to the relative change rate of the expansion or contraction of the length or volume of a material when the temperature changes. The thermal conduction distance refers to the distance that heat is transferred through thermal conduction in a material. The thermal performance refers to the performance of a material or device in a thermal environment, which involves how the material or device responds, transfers, and dissipates heat. The tensile test data refers to a series of performance index data collected during the tensile test of a material or component. The mechanical performance refers to various physical characteristics exhibited by a material or structure when subjected to external forces, and these characteristics describe how the material or structure responds to loads, forces, displacements, and deformations.

[0029] Optionally, the measurement of the lead resistance, lead inductance, and lead capacitance of the candidate lead can be performed through electromagnetic field modeling and simulation.

[0030] In an embodiment of the present invention, by screening out the high-energy-efficiency bonding leads of the memory chip from the candidate leads according to the lead high-energy-efficiency conditions and the lead performance, signal transmission can be optimized, signal delay and distortion can be reduced, signal integrity can be improved, which helps to conduct heat from the chip to the heat dissipation system faster, reduce the chip operating temperature, and improve reliability. Among them, the high-energy-efficiency bonding lead refers to a bonding lead with characteristics of data transmission speed and efficient heat dissipation, and can achieve higher energy efficiency.

[0031] Optionally, as an embodiment of the present invention, screening out the high-energy-efficiency bonding leads of the memory chip from the candidate leads according to the lead high-energy-efficiency conditions and the lead performance can be performed through multi-criteria decision analysis.

[0032] S2. Identify the chip pad positions of the memory chip and the substrate pad positions of the corresponding packaging substrate of the memory chip. According to the chip pad positions and the substrate pad positions, calculate the bending radius, lead length, and lead angle of the high-energy-efficiency bonding lead. According to the bending radius, the lead length, and the lead angle, construct a lead forming control module for the high-energy-efficiency bonding lead.

[0033] In an embodiment of the present invention, by identifying the chip pad positions of the memory chip and the substrate pad positions of the packaging substrate corresponding to the memory chip, accurate identification of the pad positions can ensure the correct connection of bonding leads or solder balls to the pads and reduce the risk of poor connection. Among them, the chip pad position refers to a specific area on the surface of an integrated circuit (IC) chip for connecting to other electronic components or a packaging substrate. The substrate pad position refers to a specific area on the packaging substrate (also known as a printed circuit board (PCB), ceramic substrate, or other types of packaging carriers) corresponding to the chip pads and establishing an electrical connection.

[0034] As an embodiment of the present invention, the identifying the chip pad positions of the memory chip and the substrate pad positions of the packaging substrate corresponding to the memory chip includes: Collecting chip image data of the memory chip and substrate image data of the packaging substrate; Respectively extracting chip image features of the chip image data and substrate image features of the substrate image data; Determining the chip pad pixel coordinates of the memory chip according to the chip image features; Determining the substrate pad pixel coordinates of the packaging substrate according to the substrate image features; Determining the chip pad positions of the memory chip and the substrate pad positions of the packaging substrate according to the chip pad pixel coordinates and the substrate pad pixel coordinates.

[0035] Among them, the chip image data refers to the digital image information on the surface of the memory chip obtained by an image acquisition device (such as a camera). The substrate image data refers to the digital image information on the surface of the packaging substrate obtained by an image acquisition device (such as a camera). The chip image features refer to the unique visual attributes that can be recognized in the chip image data and used for image processing and analysis. The substrate image features refer to the unique visual attributes that can be recognized and analyzed in the packaging substrate image data. The chip pad pixel coordinates refer to the position of the center point or specific feature point of the pad in the chip image in the image coordinate system, represented by coordinate values in pixel units. The substrate pad pixel coordinates refer to the position of the center point or specific feature point of the pad in the image of the substrate (also known as a printed circuit board (PCB)) in the image coordinate system.

[0036] Optionally, the respectively extracting the chip image features of the chip image data and the substrate image features of the substrate image data can be performed by a morphological processing method.

[0037] In the embodiments of the present invention, by calculating the bending radius, lead length, and lead angle of the high-efficiency bonding leads based on the chip pad position and the substrate pad position, the heat flow path can be optimized, the heat conduction efficiency can be improved, which helps the heat dissipation of the chip. At the same time, it helps to reduce signal interference and crosstalk, and improve the stability and reliability of the circuit. Wherein, the bending radius refers to the radius of the circle formed by the center line on the inner side of the bent part when the lead or wire is bent at a certain angle. The lead length refers to the actual physical length of the bonding lead from the chip pad to the substrate pad. The lead angle refers to the angle formed by the bonding lead relative to a certain reference direction (usually the horizontal or vertical direction) in the path from the chip pad to the substrate pad.

[0038] As an embodiment of the present invention, calculating the bending radius, lead length, and lead angle of the high-efficiency bonding leads based on the chip pad position and the substrate pad position includes: Construct a two-dimensional coordinate system for the chip pad position and the substrate pad position; According to the two-dimensional coordinate system, determine the chip pad coordinates of the chip pad position and the substrate pad coordinates of the substrate pad position; According to the chip pad coordinates and the substrate pad coordinates, fit the lead bending path of the high-efficiency bonding leads; Fit the path function of the lead bending path, where the path function includes: Wherein, represents the path function, represents the position variable of the path function, represents the bending coefficient of the path function, represents the abscissa of the vertex of the lead bending path, represents the ordinate of the vertex of the lead bending path, represents the exponential parameter of the lead bending path; According to the path function, use the following formula to calculate the bending radius, lead length, and lead angle of the high-efficiency bonding leads: Wherein, represents the bending radius, represents the lead length, represents the lead angle, represents the abscissa of the chip pad corresponding to the chip pad coordinates, represents the abscissa of the substrate pad corresponding to the substrate pad coordinates, represents the ordinate of the chip pad corresponding to the chip pad coordinates, represents the ordinate of the substrate pad corresponding to the substrate pad coordinates, represents the sine function, represents the bending angle of the lead bending path, represents the path function, represents the position variable of the path function, represents the differential of the path function, represents the integration variable, represents the arctangent function.

[0039] Among them, the two-dimensional coordinate system refers to a mathematical system used to describe points on a plane, consisting of two mutually perpendicular number axes. The chip pad coordinates refer to an ordered pair used to accurately describe the position of the chip pad in the two-dimensional coordinate system. The substrate pad coordinates refer to an ordered pair used to accurately describe the position of the substrate pad in the two-dimensional coordinate system. The lead bending path refers to the bending shape and path of the bonding lead (also known as gold wire, copper wire, or aluminum wire, etc.) from the solder joint (or bump) on the chip to the pad on the substrate (such as PCB) during the manufacturing process of a semiconductor device (such as a memory chip). The path function refers to a mathematical function used to describe the lead bending path.

[0040] Optionally, fitting the lead bending path of the high-energy-efficient bonding lead according to the chip pad coordinates and the substrate pad coordinates can be performed by the least squares method.

[0041] In the embodiment of the present invention, by constructing the lead forming control module of the high-energy-efficient bonding lead according to the bending radius, the lead length, and the lead angle, it can ensure that the lead accurately reaches the predetermined pad position, improving the assembly accuracy. Among them, the lead forming control module refers to an integrated hardware and software system used to control and form the geometric shape of the bonding lead (also known as gold wire, copper wire, or aluminum wire) during the semiconductor packaging process.

[0042] As an embodiment of the present invention, constructing the lead forming control module of the high-energy-efficient bonding lead according to the bending radius, the lead length, and the lead angle includes: Configuring the lead forming machine for the high-energy-efficient bonding lead; Defining the lead forming control algorithm of the lead forming machine according to the bending radius, the lead length, and the lead angle; Calculating the working parameters of the lead forming machine according to the lead forming control algorithm; Construct the motion monitoring unit of the lead forming machine, and based on the motion monitoring unit, monitor the real-time motion data of the lead forming machine; According to the working parameters and the real-time motion data, construct the feedback mechanism of the lead forming machine; According to the lead forming machine, the lead forming control algorithm, and the feedback mechanism, construct the lead forming control module for high-energy efficient bonding leads.

[0043] Among them, the lead forming machine refers to a special mechanical device used to precisely bend and form bonding leads (also known as gold wires, copper wires, or aluminum wires, etc.) in the electronics manufacturing industry to connect the pads on the semiconductor chip to the pads on the substrate. The lead forming control algorithm refers to the algorithm used to guide the lead forming machine to perform precise operations, ensuring that the leads meet specific geometric and electrical requirements during the bending and forming process. The working parameters refer to a series of parameters that need to be set or adjusted to achieve the expected performance and results when operating the lead forming control module or any industrial equipment. The motion monitoring unit refers to the system component used to monitor and control the motion state during the lead forming process. The real-time motion data refers to the data related to the motion state of the equipment continuously collected and transmitted by the motion monitoring unit during the lead bonding or other automated manufacturing processes. The feedback mechanism refers to the mechanism used to return the output or result information to the input end to compare the actual performance with the expected performance and make adjustments according to the comparison results.

[0044] S3. Obtain the lead bonding data of the storage chip, identify the bonding parameters and bonding effects in the lead bonding data, based on the lead bonding data, analyze the influence coefficients of the bonding parameters and the bonding effects, and according to the influence coefficients, construct the bonding parameter optimization module for high-energy efficient bonding leads.

[0045] By obtaining the lead bonding data of the storage chip in the embodiments of the present invention, it can help optimize the bonding parameters, such as bonding force, bonding speed, and heating time, to improve production efficiency and product quality. Among them, the lead bonding data refers to various parameters and information related to the manufacturing and packaging processes of the storage chip.

[0046] By identifying the bonding parameters and bonding effects in the lead bonding data in the embodiments of the present invention, it can reduce the rework and scrap rate caused by improper parameters, thereby improving the overall production efficiency. Among them, the bonding parameters refer to the key process variables that affect the bonding quality and effect during the lead bonding process. The bonding effect refers to the actual result achieved after the bonding parameters are set and the process is executed during the lead bonding process.

[0047] Optionally, as an embodiment of the present invention, the bonding parameters and bonding effects in the wire bonding data can be identified through big data analysis.

[0048] By analyzing the influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data, embodiments of the present invention can accurately identify which bonding parameters have the greatest impact on the solder joint quality, thereby optimizing these parameters targeted to improve the consistency and reliability of the solder joints. Among them, the influence coefficient refers to an index used to quantify the influence intensity of the bonding parameters on the bonding effect.

[0049] As an embodiment of the present invention, the analyzing the influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data includes: Performing data cleaning on the wire bonding data to obtain cleaned data, and normalizing the cleaned data to obtain normalized data; Calculating the correlation coefficient between the bonding parameters and the bonding effects according to the normalized data; Constructing a regression analysis model of the bonding parameters and the bonding effects; Analyzing the influence degree of the bonding parameters on the bonding effects according to the regression analysis model; Determining the influence coefficients of the bonding parameters and the bonding effects according to the correlation coefficient and the influence degree.

[0050] Among them, the cleaned data refers to a data set with improved quality after a series of data preprocessing steps. The normalized data refers to the data after specific mathematical transformation processing, so that the numerical range of the data set is scaled to a fixed interval. The correlation coefficient refers to a statistic that measures the strength and direction of the linear relationship between two variables. The regression analysis model refers to a statistical model used to analyze the relationship between two or more variables, especially for predicting or explaining the dependence relationship between one or more dependent variables (response variables) and one or more independent variables (explanatory variables). The influence degree refers to the influence strength of the independent variable (explanatory variable) on the dependent variable (response variable) in a regression analysis model.

[0051] Optionally, the calculating the correlation coefficient between the bonding parameters and the bonding effects according to the normalized data can be calculated through the Pearson correlation coefficient.

[0052] In the embodiments of the present invention, by constructing the bonding parameter optimization module for the high-energy efficiency bonding wire according to the influence coefficient, the parameters affecting the bonding effect can be optimized, the speed of the bonding process can be increased, the energy consumption can be reduced, and thus the overall bonding efficiency can be improved. Among them, the bonding parameter optimization module refers to a software system integrated in the semiconductor packaging or electronic manufacturing process, which is used to analyze and adjust the key parameters in the bonding process (such as ball grid array (BGA), chip scale package (CSP) or other forms of wire bonding) to achieve the best bonding effect.

[0053] As an embodiment of the present invention, the constructing the bonding parameter optimization module for the high-energy efficiency bonding wire according to the influence coefficient includes: Determine the optimization objective of the bonding parameters corresponding to the high-energy efficiency bonding wire; Analyze the bonding scenario of the high-energy efficiency bonding wire, and based on the bonding scenario, determine the constraint conditions of the high-energy efficiency bonding wire; Define the optimization algorithm of the bonding parameters according to the constraint conditions and the influence coefficient; Determine the optimization iteration mechanism of the bonding parameters according to the optimization objective; Construct the bonding parameter optimization module for the high-energy efficiency bonding wire according to the optimization algorithm and the optimization iteration mechanism.

[0054] Among them, the optimization objective refers to the specific performance indicators or results that are expected to be achieved when constructing the bonding parameter optimization module for the high-energy efficiency bonding wire. The bonding scenario refers to the specific environment and conditions of the wire bonding operation in the semiconductor manufacturing or electronic assembly process. The constraint conditions refer to the limiting factors that must be considered when optimizing the bonding parameters, and these conditions are usually determined by factors such as the requirements of the bonding process, equipment capabilities, material properties, production environment, and product quality standards. The optimization algorithm refers to a series of calculation methods and steps used to find the best bonding parameters in order to achieve or approach the predetermined optimization objective under the given constraint conditions. The optimization iteration mechanism refers to the process of repeated calculation and evaluation used to gradually improve the parameter settings to achieve the optimization objective during the bonding parameter optimization process.

[0055] Optionally, the defining the optimization algorithm of the bonding parameters according to the constraint conditions and the influence coefficient can be defined by sequential quadratic programming.

[0056] S4. Analyze the chip thermal characteristics of the storage chip and the lead thermal characteristics of the high - efficiency bonding leads. According to the chip thermal characteristics and the lead thermal characteristics, determine the packaging temperature range of the storage chip, construct a packaging temperature monitoring unit for the storage chip, and based on the packaging temperature monitoring unit, monitor the real - time temperature data of the corresponding packaging area of the storage chip in real time. According to the packaging temperature range and the real - time temperature data, construct a thermal management module for the storage chip and the high - efficiency bonding leads.

[0057] In the embodiment of the present invention, by analyzing the chip thermal characteristics of the storage chip and the lead thermal characteristics of the high - efficiency bonding leads, it can be ensured that the chip will not be damaged due to overheating during the bonding process, thereby improving the thermal management efficiency, reducing the thermal resistance, and enhancing the overall heat dissipation performance. Among them, the chip thermal characteristics refer to the heat generated by the chip during operation and the performance indicators of how this heat is transferred through chip materials, packaging, heat sinks, etc. The lead thermal characteristics refer to the performance indicators of the leads (usually referring to metal wires used for electrical connection, such as gold wires, copper wires, etc., which are used to connect the chip to the external circuit in semiconductor packaging) in terms of heat conduction and thermal management.

[0058] Optionally, as an embodiment of the present invention, the analysis of the chip thermal characteristics of the storage chip and the lead thermal characteristics of the high - efficiency bonding leads can be analyzed by thermal imaging technology.

[0059] In the embodiment of the present invention, by determining the packaging temperature range of the storage chip according to the chip thermal characteristics and the lead thermal characteristics, it can be ensured that the performance of the chip is stable under normal working conditions and avoid performance degradation caused by temperature fluctuations. Among them, the packaging temperature range refers to a set of temperature limits within which the storage chip and its packaging can operate safely and reliably under normal working conditions.

[0060] Optionally, as an embodiment of the present invention, the determination of the packaging temperature range of the storage chip according to the chip thermal characteristics and the lead thermal characteristics can be determined by thermal cycle testing.

[0061] In the embodiment of the present invention, by constructing a packaging temperature monitoring unit for the storage chip, it is possible to monitor the temperature of the storage chip packaging area in real time and ensure that the temperature change is within a safe range. Among them, the packaging temperature monitoring unit refers to a device used to monitor and control the temperature during the packaging process.

[0062] As an embodiment of the present invention, the construction of the packaging temperature monitoring unit for the storage chip includes: Determine the temperature sensor of the storage chip and determine the sensor installation position of the temperature sensor; Construct a signal conditioning circuit and a microprocessor for the temperature sensor; Determine the network topology of the monitoring unit of the storage chip based on the sensor installation position, the temperature sensor, and the microprocessor; Determine the data transmission method and communication protocol of the temperature sensor; Construct the package temperature monitoring unit of the storage chip according to the network topology of the monitoring unit, the communication protocol, and the signal conditioning circuit.

[0063] Among them, the temperature sensor refers to a device that can convert temperature changes into measurable signals. The sensor installation position refers to the specific position selected during the packaging process of the storage chip to accurately monitor the temperature. The signal conditioning circuit refers to an electronic circuit used to process the output signal of the temperature sensor. The microprocessor refers to a small computer integrated on a single chip that can execute computer program instructions to process data. The network topology of the monitoring unit refers to the layout and structure of the temperature monitoring units (including temperature sensors, signal conditioning circuits, microprocessors, etc.) used for connection and communication in a system. The data transmission method refers to the method of transmitting data between different devices or systems. The communication protocol refers to a set of rules and standards that define the format, order, error detection and correction methods, and data exchange mechanism of data transmission between devices.

[0064] In the embodiment of the present invention, by based on the package temperature monitoring unit, the real-time temperature data of the corresponding package area of the storage chip can be monitored in real time. Through real-time monitoring, temperature deviations can be discovered and corrected in a timely manner, thereby improving the packaging quality and reducing the defect rate. Among them, the real-time temperature data refers to the temperature information of the package area continuously collected by the temperature monitoring unit at specific time intervals.

[0065] In the embodiment of the present invention, by constructing the thermal management module of the storage chip and the high-efficiency bonding wire according to the package temperature range and the real-time temperature data, it can ensure that during the packaging process, the temperatures of the chip and the bonding wire are accurately controlled within the optimal range, avoiding damage to the chip or wire caused by too high or too low temperatures, thereby improving the packaging quality. Among them, the thermal management module refers to a subsystem or component specifically used for monitoring and controlling temperature during the packaging process of the storage chip.

[0066] As an embodiment of the present invention, the constructing the thermal management module of the storage chip and the high-efficiency bonding wire according to the package temperature range and the real-time temperature data includes: Configure the temperature regulators of the storage chip and the high-efficiency bonding wire; Analyze the temperature difference between the real-time temperature data and the package temperature range; Define the temperature control algorithm of the storage chip and the high-efficiency bonding wire according to the temperature difference; Based on the temperature control algorithm, determine the temperature control logic for the storage chip and the high-energy efficiency bonding wire; According to the temperature regulator, the temperature control algorithm, and the temperature control logic, construct the thermal management module for the storage chip and the high-energy efficiency bonding wire.

[0067] Among them, the temperature regulator refers to a device for controlling or changing the temperature of a device or system. The temperature difference refers to the difference between the actual temperature and the standard temperature. The temperature control algorithm refers to a series of calculation steps and rules for managing and adjusting the temperature in the storage chip or its packaging environment. The temperature control logic refers to a series of rules and decision-making processes for managing and regulating the temperature of a device (such as a storage chip).

[0068] S5. Integrate the packaging control module of the storage chip according to the lead forming control module, the bonding parameter optimization module, and the thermal management module, and based on the packaging control module, perform the packaging control of the storage chip.

[0069] In the embodiment of the present invention, by integrating the packaging control module of the storage chip according to the lead forming control module, the bonding parameter optimization module, and the thermal management module, the consistency of each bonding process can be ensured, the differences between batches can be reduced, and the overall quality of the product can be improved. Among them, the packaging control module refers to an integrated system for managing and controlling various key steps and parameters in the storage chip packaging process.

[0070] In the embodiment of the present invention, by performing the packaging control of the storage chip based on the packaging control module, the defect rate can be reduced, and the reliability and long-term stability of the packaging can be improved by optimizing the packaging parameters and process control.

[0071] In the embodiments of the present invention, by screening out the high - energy - efficient bonding leads of the memory chip from the candidate leads according to the high - energy - efficient conditions and performance of the leads, signal transmission can be optimized, signal delay and distortion can be reduced, signal integrity can be improved, which helps to conduct heat from the chip to the heat dissipation system faster, reduce the chip operating temperature, and improve reliability. Optionally, in the embodiments of the present invention, by calculating the bending radius, lead length, and lead angle of the high - energy - efficient bonding leads according to the chip pad position and the substrate pad position of the memory chip, the chip pad position of the memory chip and the substrate pad position of the corresponding packaging substrate of the memory chip, the heat - flow path can be optimized, the heat conduction efficiency can be improved, which helps the heat dissipation of the chip, and at the same time helps to reduce signal interference and crosstalk, and improve the stability and reliability of the circuit. In the embodiments of the present invention, by analyzing the influence coefficients of the bonding parameters and the bonding effect based on the lead bonding data, it is possible to accurately identify which bonding parameters have the greatest impact on the solder joint quality, so as to optimize these parameters targeted and improve the consistency and reliability of the solder joints. In the embodiments of the present invention, by analyzing the chip thermal characteristics of the memory chip and the lead thermal characteristics of the high - energy - efficient bonding leads, it is possible to ensure that the chip will not be damaged due to overheating during the bonding process, thereby improving the thermal management efficiency, reducing the thermal resistance, and enhancing the overall heat dissipation performance. In the embodiments of the present invention, by constructing the thermal management module of the memory chip and the high - energy - efficient bonding leads according to the packaging temperature range and the real - time temperature data, it is possible to ensure that during the packaging process, the temperatures of the chip and the bonding leads are accurately controlled within the optimal range, avoiding chip or lead damage caused by too high or too low temperatures, thereby improving the packaging quality. Finally, in the embodiments of the present invention, by executing the packaging control of the memory chip based on the packaging control module, the defect rate can be reduced, and the reliability and long - term stability of the packaging can be improved by optimizing the packaging parameters and process control. Therefore, the application method and system of the high - energy - efficient lead bonding technology in the memory chip packaging provided by the embodiments of the present invention can improve the efficiency and quality of the memory chip packaging.

[0072] Embodiment 2: As Figure 2 shown, it is a functional module diagram of an application system of a high - energy - efficient lead bonding technology in the memory chip packaging according to the present invention.

[0073] The application system 200 of the high - energy - efficient lead bonding technology in the memory chip packaging according to the present invention can be installed in an electronic device. According to the realized functions, the application system of the high - energy - efficient lead bonding technology in the memory chip packaging can include a bonding lead determination module 201, a lead forming control module 202, a bonding parameter optimization module 203, a thermal management module 204, and a packaging control module 205. The modules of the present invention can also be referred to as units, which refer to a series of computer program segments that can be executed by the processor of an electronic device and can complete fixed functions, and are stored in the memory of the electronic device.

[0074] In the embodiments of the present invention, the functions of each module / unit are as follows: The bonding wire determination module 201 is configured to clarify the packaging requirements of the memory chip, determine the high-energy efficiency conditions of the leads of the memory chip based on the packaging requirements, obtain the candidate leads of the memory chip, analyze the lead performance of the candidate leads, and screen out the high-energy efficiency bonding wires of the memory chip from the candidate leads according to the lead high-energy efficiency conditions and the lead performance; The lead forming control module 202 is configured to identify the chip pad position of the memory chip and the substrate pad position of the packaging substrate corresponding to the memory chip, calculate the bending radius, lead length, and lead angle of the high-energy efficiency bonding wire according to the chip pad position and the substrate pad position, and construct a lead forming control module for the high-energy efficiency bonding wire according to the bending radius, the lead length, and the lead angle; The bonding parameter optimization module 203 is configured to obtain the lead bonding data of the memory chip, identify the bonding parameters and bonding effects in the lead bonding data, analyze the influence coefficients of the bonding parameters and the bonding effects based on the lead bonding data, and construct a bonding parameter optimization module for the high-energy efficiency bonding wire according to the influence coefficients; The thermal management module 204 is configured to analyze the chip thermal characteristics of the memory chip and the lead thermal characteristics of the high-energy efficiency bonding wire, determine the packaging temperature range of the memory chip according to the chip thermal characteristics and the lead thermal characteristics, construct a packaging temperature monitoring unit for the memory chip, monitor the real-time temperature data of the corresponding packaging area of the memory chip in real time based on the packaging temperature monitoring unit, and construct a thermal management module for the memory chip and the high-energy efficiency bonding wire according to the packaging temperature range and the real-time temperature data; The packaging control module 205 is configured to integrate the packaging control module of the memory chip according to the lead forming control module, the bonding parameter optimization module, and the thermal management module, and perform the packaging control of the memory chip based on the packaging control module.

[0075] Specifically, each module in the application system 200 of the high-efficiency lead bonding technology in the packaging of memory chips in the embodiments of the present invention uses the same technical means as those Figure 1 described in the application method of the high-efficiency lead bonding technology in the packaging of memory chips, and can produce the same technical effects, which will not be elaborated here.

[0076] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An application method of a high-performance wire bonding technology in the packaging of memory chips, characterized in that, The method includes: clarifying the packaging requirements of the memory chip, determining the high-energy efficiency conditions of the leads of the memory chip based on the packaging requirements, obtaining the candidate leads of the memory chip, analyzing the lead performance of the candidate leads, and screening out the high-energy efficiency bonding leads of the memory chip from the candidate leads according to the lead high-energy efficiency conditions and the lead performance; identifying the chip pad positions of the memory chip and the substrate pad positions of the corresponding packaging substrate of the memory chip, calculating the bending radius, lead length, and lead angle of the high-energy efficiency bonding leads according to the chip pad positions and the substrate pad positions, and constructing a lead forming control module for the high-energy efficiency bonding leads according to the bending radius, the lead length, and the lead angle; obtaining the lead bonding data of the memory chip, identifying the bonding parameters and bonding effects in the lead bonding data, analyzing the influence coefficients of the bonding parameters and the bonding effects based on the lead bonding data, and constructing a bonding parameter optimization module for the high-energy efficiency bonding leads according to the influence coefficients; analyzing the chip thermal characteristics of the memory chip and the lead thermal characteristics of the high-energy efficiency bonding leads, determining the packaging temperature range of the memory chip according to the chip thermal characteristics and the lead thermal characteristics, constructing a packaging temperature monitoring unit for the memory chip, monitoring the real-time temperature data of the corresponding packaging area of the memory chip in real time based on the packaging temperature monitoring unit, and constructing a thermal management module for the memory chip and the high-energy efficiency bonding leads according to the packaging temperature range and the real-time temperature data; integrating a packaging control module of the memory chip according to the lead forming control module, the bonding parameter optimization module, and the thermal management module, and performing the packaging control of the memory chip based on the packaging control module.

2. The application method of the high-performance wire bonding technology in the storage chip package according to claim 1, characterized in that, The analyzing the lead performance of the candidate leads includes: measuring the lead resistance, lead inductance, and lead capacitance of the candidate leads; determining the electrical performance of the candidate leads according to the lead resistance, the lead inductance, and the lead capacitance; performing a thermal performance test on the candidate leads to obtain test data; calculating the thermal conductivity and thermal expansion coefficient of the candidate leads according to the test data by using the following formula: Among them, represents the thermal conductivity, represents the coefficient of thermal expansion, represents the heat corresponding to the test data, represents the cross-sectional area of the lead to be selected, represents the temperature difference, represents the heat conduction distance corresponding to the test data, represents the original length of the lead to be selected, represents the length change; determining the thermal performance of the candidate leads according to the thermal conductivity and the thermal expansion coefficient; performing a tensile test on the candidate leads to obtain tensile test data; analyzing the mechanical performance of the candidate leads according to the tensile test data; determining the lead performance of the candidate leads according to the electrical performance, the thermal performance, and the mechanical performance.

3. The application method of the high-performance wire bonding technology in the storage chip package according to claim 1, characterized in that, The identifying the chip pad positions of the memory chip and the substrate pad positions of the corresponding packaging substrate of the memory chip includes: collecting the chip image data of the memory chip and the substrate image data of the packaging substrate; extracting the chip image features of the chip image data and the substrate image features of the substrate image data respectively; determining the chip pad pixel coordinates of the memory chip according to the chip image features; Determine the substrate pad pixel coordinates of the packaging substrate according to the substrate image features; Determine the chip pad position of the memory chip and the substrate pad position of the packaging substrate according to the chip pad pixel coordinates and the substrate pad pixel coordinates.

4. The application method of the high-performance wire bonding technology in the storage chip package according to claim 1, wherein The calculating the bending radius, lead length, and lead angle of the high-energy-efficiency bonding lead according to the chip pad position and the substrate pad position includes: Construct a two-dimensional coordinate system of the chip pad position and the substrate pad position; Determine the chip pad coordinates of the chip pad position and the substrate pad coordinates of the substrate pad position according to the two-dimensional coordinate system; Fit the lead bending path of the high-energy-efficiency bonding lead according to the chip pad coordinates and the substrate pad coordinates; Fit the path function of the lead bending path, where the path function includes: Among them, represents a path function, represents the position variable of the path function, represents the bending coefficient of the path function, represents the abscissa of the vertex of the lead bending path, represents the ordinate of the vertex of the lead bending path, represents the exponential parameter of the lead bending path; Calculate the bending radius, lead length, and lead angle of the high-energy-efficiency bonding lead according to the path function.

5. The application method of the high-performance wire bonding technology in the storage chip package according to claim 1, characterized in that The constructing the lead forming control module of the high-energy-efficiency bonding lead according to the bending radius, the lead length, and the lead angle includes: Configure the lead forming machine of the high-energy-efficiency bonding lead; Define the lead forming control algorithm of the lead forming machine according to the bending radius, the lead length, and the lead angle; Calculate the working parameters of the lead forming machine according to the lead forming control algorithm; Construct a motion monitoring unit of the lead forming machine, and monitor the real-time motion data of the lead forming machine based on the motion monitoring unit; Construct a feedback mechanism of the lead forming machine according to the working parameters and the real-time motion data; Construct the lead forming control module of the high-energy-efficiency bonding lead according to the lead forming machine, the lead forming control algorithm, and the feedback mechanism.

6. The application method of the high-performance wire bonding technology in the storage chip package according to claim 1, wherein The analyzing the influence coefficients of the bonding parameters and the bonding effect based on the lead bonding data includes: Perform data cleaning on the lead bonding data to obtain cleaned data, and normalize the cleaned data to obtain normalized data; Calculate the correlation coefficients of the bonding parameters and the bonding effect according to the normalized data; Construct a regression analysis model of the bonding parameters and the bonding effect; Analyze the influence degree of the bonding parameters on the bonding effect according to the regression analysis model; Determine the influence coefficients of the bonding parameters and the bonding effect according to the correlation coefficients and the influence degree.

7. The application method of the high-performance wire bonding technology in the storage chip package according to claim 1, characterized in that, The constructing the bonding parameter optimization module of the high-energy-efficiency bonding lead according to the influence coefficients includes: Determine the optimization objectives of the bonding parameters corresponding to the high-energy-efficiency bonding lead; Analyze the bonding scenarios of the high-energy-efficiency bonding lead, and determine the constraint conditions of the high-energy-efficiency bonding lead based on the bonding scenarios; Define the optimization algorithm of the bonding parameters according to the constraint conditions and the influence coefficients; Determine the optimization iteration mechanism of the bonding parameters according to the optimization objectives; Construct the bonding parameter optimization module of the high-energy-efficiency bonding lead according to the optimization algorithm and the optimization iteration mechanism.

8. The application method of the high-performance wire bonding technology in the storage chip package according to claim 1, characterized in that The constructing the packaging temperature monitoring unit of the memory chip includes: Determine the temperature sensor of the storage chip and determine the sensor installation position of the temperature sensor; Construct the signal conditioning circuit and microprocessor of the temperature sensor; Determine the monitoring unit network topology of the storage chip according to the sensor installation position, the temperature sensor, and the microprocessor; Determine the data transmission method and communication protocol of the temperature sensor; Construct the packaged temperature monitoring unit of the storage chip according to the monitoring unit network topology, the communication protocol, and the signal conditioning circuit; 9. The application method of the high-performance wire bonding technology in the storage chip packaging according to claim 1, characterized in that The constructing the thermal management module of the storage chip and the high-efficiency bonding wire according to the packaged temperature range and the real-time temperature data includes: Configure the temperature regulators of the storage chip and the high-efficiency bonding wire; Analyze the temperature difference between the real-time temperature data and the packaged temperature range; Define the temperature control algorithm of the storage chip and the high-efficiency bonding wire according to the temperature difference; Determine the temperature control logic of the storage chip and the high-efficiency bonding wire based on the temperature control algorithm; Construct the thermal management module of the storage chip and the high-efficiency bonding wire according to the temperature regulator, the temperature control algorithm, and the temperature control logic; 10. An application system of a high-performance wire bonding technology in the packaging of memory chips, characterized in that, The system includes: A bonding wire determination module for clarifying the packaging requirements of the storage chip, determining the high-efficiency conditions of the bonding wire of the storage chip based on the packaging requirements, obtaining the candidate bonding wires of the storage chip, analyzing the wire performance of the candidate bonding wires, and screening out the high-efficiency bonding wires of the storage chip from the candidate bonding wires according to the wire high-efficiency conditions and the wire performance; A wire forming control module for identifying the chip pad position of the storage chip and the substrate pad position of the packaging substrate corresponding to the storage chip, calculating the bending radius, wire length, and wire angle of the high-efficiency bonding wire according to the chip pad position and the substrate pad position, and constructing the wire forming control module of the high-efficiency bonding wire according to the bending radius, the wire length, and the wire angle; A bonding parameter optimization module for obtaining the wire bonding data of the storage chip, identifying the bonding parameters and bonding effects in the wire bonding data, analyzing the influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data, and constructing the bonding parameter optimization module of the high-efficiency bonding wire according to the influence coefficients; A thermal management module for analyzing the chip thermal characteristics of the storage chip and the wire thermal characteristics of the high-efficiency bonding wire, determining the packaged temperature range of the storage chip according to the chip thermal characteristics and the wire thermal characteristics, constructing the packaged temperature monitoring unit of the storage chip, monitoring the real-time temperature data of the corresponding packaging area of the storage chip in real time based on the packaged temperature monitoring unit, and constructing the thermal management module of the storage chip and the high-efficiency bonding wire according to the packaged temperature range and the real-time temperature data; The encapsulation control module is used to integrate the encapsulation control module of the storage chip according to the lead forming control module, the bonding parameter optimization module, and the thermal management module, and perform the encapsulation control of the storage chip based on the encapsulation control module.

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