Application method and system of high-performance wire bonding technology in memory chip packaging

Abstract

The present invention relates to the field of microelectronic packaging technology and discloses a method and system for applying high-efficiency wire bonding technology to memory chip packaging. The method comprises the following steps: determining the high energy efficiency conditions of the memory chip leads, analyzing the lead performance of the candidate leads, and selecting high energy efficiency bonding leads for the memory chip from the candidate leads based on the high energy efficiency conditions and lead performance; calculating the bending radius, lead length, and lead angle of the high energy efficiency bonding leads, and constructing a lead forming control module for the high energy efficiency bonding leads; analyzing the influencing coefficients of the bonding parameters and the bonding effect, and constructing a bonding parameter optimization module for the high energy efficiency bonding leads; determining the packaging temperature range of the memory chip, monitoring the real-time temperature data of the corresponding packaging area of ​​the memory chip, and constructing a thermal management module for the memory chip and the high energy efficiency bonding leads; and integrating the packaging control module of the memory chip to execute the packaging control of the memory chip. The present invention can improve the efficiency and quality of memory chip packaging.

Description

Technical Field

[0001] The present invention relates to an application method and system of high-efficiency wire bonding technology in memory chip packaging, belonging to the technical field of microelectronic packaging. Background Art

[0002] Memory chip packaging is a branch of semiconductor packaging technology that involves encapsulating memory chips (such as DRAM, NAND Flash, NOR Flash, etc.) in a protective casing and providing electrical connections to external circuits. The package not only protects the chip from physical and environmental damage, but also ensures the chip's electrical and thermal performance.

[0003] Currently, memory chip packaging is mainly achieved through plastic packaging and ceramic packaging. This method mainly uses traditional wire bonding technology for connection, resulting in slow bonding speed and poor heat conduction, which causes chip overheating and poor chip packaging effect.

[0004] Therefore, there is an urgent need for a solution that can improve the efficiency and quality of memory chip packaging. Summary of the Invention

[0005] The present invention provides a method and system for applying high-performance wire bonding technology in memory chip packaging, the main purpose of which is to improve the efficiency and quality of memory chip packaging.

[0006] To achieve the above objectives, the present invention provides a method for applying high-efficiency wire bonding technology in memory chip packaging, comprising:

[0007] Clarifying packaging requirements for a memory chip, determining high energy efficiency conditions for leads of the memory chip based on the packaging requirements, obtaining candidate leads for the memory chip, analyzing lead performance of the candidate leads, and selecting high energy efficiency bonding leads for the memory chip from the candidate leads based on the high energy efficiency conditions and the lead performance;

[0008] Identifying a chip pad position of the memory chip and a substrate pad position of a packaging substrate corresponding to the memory chip, calculating a bending radius, a lead length, and a lead angle of the high-efficiency bonding wire based on the chip pad position and the substrate pad position, and constructing a lead forming control module for the high-efficiency bonding wire based on the bending radius, the lead length, and the lead angle;

[0009] Acquiring wire bonding data of the memory chip, identifying bonding parameters and bonding effects in the wire bonding data, analyzing influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data, and constructing a bonding parameter optimization module for the high-efficiency bonding wire according to the influence coefficients;

[0010] Analyzing the chip thermal characteristics of the memory chip and the lead thermal characteristics of the high-efficiency bonding wire, determining the packaging temperature range of the memory chip based on the chip thermal characteristics and the lead thermal characteristics, constructing a packaging temperature monitoring unit for the memory chip, monitoring real-time temperature data of a packaging area corresponding to the memory chip based on the packaging temperature monitoring unit, and constructing a thermal management module for the memory chip and the high-efficiency bonding wire based on the packaging temperature range and the real-time temperature data;

[0011] According to the lead forming control module, the bonding parameter optimization module and the thermal management module, a packaging control module of the memory chip is integrated, and based on the packaging control module, packaging control of the memory chip is performed.

[0012] Optionally, analyzing the lead performance of the lead to be selected includes:

[0013] measuring the lead resistance, lead inductance, and lead capacitance of the lead to be selected;

[0014] determining the electrical performance of the lead to be selected according to the lead resistance, the lead inductance, and the lead capacitance;

[0015] Performing a thermal performance test on the lead to be selected to obtain test data;

[0016] Based on the test data, the thermal conductivity and thermal expansion coefficient of the selected lead are calculated using the following formula:

[0017]

[0018]

[0019] in, represents thermal conductivity, represents the coefficient of thermal expansion, Indicates the heat corresponding to the test data, represents the cross-sectional area of ​​the lead to be selected, Represents the temperature difference, Indicates the heat conduction distance corresponding to the test data, Indicates the original length of the lead to be selected, Indicates length change;

[0020] Determining the thermal performance of the lead to be selected according to the thermal conductivity and the thermal expansion coefficient;

[0021] Performing a tensile test on the selected lead to obtain tensile test data;

[0022] Analyzing the mechanical properties of the lead to be selected based on the tensile test data;

[0023] The lead performance of the lead to be selected is determined according to the electrical performance, the thermal performance, and the mechanical performance.

[0024] Optionally, identifying a chip pad position of the memory chip and a substrate pad position of a packaging substrate corresponding to the memory chip includes:

[0025] collecting chip image data of the memory chip and substrate image data of the packaging substrate;

[0026] respectively extracting chip image features of the chip image data and substrate image features of the substrate image data;

[0027] determining pixel coordinates of chip pads of the memory chip according to the chip image features;

[0028] determining pixel coordinates of substrate pads of the package substrate according to the substrate image features;

[0029] The chip pad position of the memory chip and the substrate pad position of the packaging substrate are determined according to the chip pad pixel coordinates and the substrate pad pixel coordinates.

[0030] Optionally, the calculating the bending radius, lead length, and lead angle of the high-efficiency bonding wire according to the chip pad position and the substrate pad position includes:

[0031] Constructing a two-dimensional coordinate system of the chip pad position and the substrate pad position;

[0032] Determining chip pad coordinates of the chip pad position and substrate pad coordinates of the substrate pad position according to the two-dimensional coordinate system;

[0033] Fitting a wire bending path of the high-efficiency bonding wire according to the chip pad coordinates and the substrate pad coordinates;

[0034] Fitting a path function of the lead bending path, wherein the path function includes:

[0035]

[0036] in, represents the path function, represents the position variable of the path function, represents the curvature coefficient of the path function, Indicates the horizontal coordinate of the vertex of the lead bending path, Indicates the vertical coordinate of the vertex of the lead bending path, An exponential parameter representing the bending path of the lead;

[0037] The bending radius, wire length, and wire angle of the energy-efficient bonding wire are calculated according to the path function.

[0038] Optionally, constructing the lead forming control module of the high-energy-efficiency bonding wire according to the bending radius, the lead length, and the lead angle includes:

[0039] A wire forming machine equipped with the energy-efficient bonding wire;

[0040] defining a lead forming control algorithm of the lead forming machine according to the bending radius, the lead length, and the lead angle;

[0041] Calculating the operating parameters of the lead forming machine according to the lead forming control algorithm;

[0042] Constructing a motion monitoring unit of the lead forming machine, and monitoring real-time motion data of the lead forming machine based on the motion monitoring unit;

[0043] constructing a feedback mechanism of the lead forming machine based on the operating parameters and the real-time motion data;

[0044] According to the wire forming machine, the wire forming control algorithm and the feedback mechanism, a wire forming control module for the high energy efficiency bonding wire is constructed.

[0045] Optionally, analyzing the bonding parameters and the influence coefficient of the bonding effect based on the wire bonding data includes:

[0046] performing data cleaning on the wire bonding data to obtain cleaned data, and normalizing the cleaned data to obtain normalized data;

[0047] Calculating a correlation coefficient between the bonding parameter and the bonding effect based on the normalized data;

[0048] Constructing a regression analysis model of the bonding parameters and the bonding effect;

[0049] Analyzing the influence of the bonding parameters on the bonding effect according to the regression analysis model;

[0050] The bonding parameter and the influence coefficient of the bonding effect are determined according to the correlation coefficient and the influence degree.

[0051] Optionally, constructing a bonding parameter optimization module for the high-energy-efficiency bonding wire according to the influence coefficient includes:

[0052] Determining an optimization target for bonding parameters corresponding to the energy-efficient bonding wire;

[0053] Analyzing a bonding scenario of the high-energy-efficiency bonding wire, and determining a constraint condition of the high-energy-efficiency bonding wire based on the bonding scenario;

[0054] Defining an optimization algorithm for the bonding parameters according to the constraint conditions and the influence coefficients;

[0055] Determining an optimization iterative mechanism for the bonding parameters according to the optimization goal;

[0056] According to the optimization algorithm and the optimization iteration mechanism, a bonding parameter optimization module for the high-energy-efficiency bonding wire is constructed.

[0057] Optionally, the packaging temperature monitoring unit for the memory chip includes:

[0058] Determining a temperature sensor of the memory chip and determining a sensor installation position of the temperature sensor;

[0059] Constructing a signal conditioning circuit and a microprocessor for the temperature sensor;

[0060] Determining a monitoring unit network topology of the storage chip according to the sensor installation position, the temperature sensor, and the microprocessor;

[0061] Determining a data transmission method and a communication protocol for the temperature sensor;

[0062] A packaging temperature monitoring unit for the memory chip is constructed according to the monitoring unit network topology, the communication protocol, and the signal conditioning circuit.

[0063] Optionally, constructing a thermal management module for the memory chip and the high-efficiency bonding wire according to the packaging temperature range and the real-time temperature data includes:

[0064] A temperature regulator configured for the memory chip and the energy-efficient bonding wire;

[0065] Analyzing a temperature difference between the real-time temperature data and the package temperature range;

[0066] defining a temperature control algorithm for the memory chip and the energy-efficient bonding wire according to the temperature difference;

[0067] Determining temperature control logic for the memory chip and the energy-efficient bonding wire based on the temperature control algorithm;

[0068] A thermal management module for the memory chip and the energy-efficient bonding wire is constructed according to the temperature regulator, the temperature control algorithm, and the temperature control logic.

[0069] In order to solve the above problems, the present invention further provides an application system of high-efficiency wire bonding technology in memory chip packaging, the system comprising:

[0070] a bonding wire determination module, configured to determine packaging requirements for a memory chip, determine high energy efficiency conditions for leads of the memory chip based on the packaging requirements, obtain candidate leads for the memory chip, analyze lead performance of the candidate leads, and select high energy efficiency bonding wires for the memory chip from the candidate leads based on the high energy efficiency conditions and the lead performance;

[0071] a lead forming control module, configured to identify a chip pad position of the memory chip and a substrate pad position of a packaging substrate corresponding to the memory chip, calculate a bending radius, a lead length, and a lead angle of the high-efficiency bonding wire based on the chip pad position and the substrate pad position, and construct a lead forming control module for the high-efficiency bonding wire based on the bending radius, the lead length, and the lead angle;

[0072] a bonding parameter optimization module, configured to obtain wire bonding data of the memory chip, identify bonding parameters and bonding effects in the wire bonding data, analyze influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data, and construct a bonding parameter optimization module for the high-energy-efficiency bonding wire according to the influence coefficients;

[0073] a thermal management module configured to analyze chip thermal characteristics of the memory chip and lead thermal characteristics of the high-efficiency bonding wire, determine a packaging temperature range of the memory chip based on the chip thermal characteristics and the lead thermal characteristics, construct a packaging temperature monitoring unit for the memory chip, monitor real-time temperature data of a packaging area corresponding to the memory chip based on the packaging temperature monitoring unit, and construct a thermal management module for the memory chip and the high-efficiency bonding wire based on the packaging temperature range and the real-time temperature data;

[0074] A packaging control module is used to integrate the packaging control module of the memory chip according to the lead forming control module, the bonding parameter optimization module and the thermal management module, and perform packaging control of the memory chip based on the packaging control module.

[0075] The embodiment of the present invention can optimize signal transmission, reduce signal delay and distortion, improve signal integrity, and help to conduct heat from the chip to the heat dissipation system more quickly, reduce the chip operating temperature, and improve reliability by screening out the high-energy-efficiency bonding wires of the memory chip from the candidate wires according to the high-energy-efficiency conditions of the wires and the performance of the wires. Optionally, the embodiment of the present invention can optimize the heat flow path, improve the heat conduction efficiency, help dissipate heat of the chip, and help reduce signal interference and crosstalk, thereby improving the stability and reliability of the circuit by calculating the bending radius, lead length, and lead angle of the high-energy-efficiency bonding wires according to the chip pad position and the substrate pad position, the chip pad position of the memory chip, and the substrate pad position of the packaging substrate corresponding to the memory chip. This helps reduce signal interference and crosstalk, and improves the stability and reliability of the circuit. The embodiment of the present invention can accurately identify which bonding parameters are important by analyzing the bonding parameters and the influencing coefficient of the bonding effect based on the wire bonding data. The number has the greatest impact on the quality of the solder joints, so these parameters can be optimized in a targeted manner to improve the consistency and reliability of the solder joints. This embodiment of the present invention can ensure that the chip will not be damaged due to overheating during the bonding process by analyzing the chip thermal characteristics of the memory chip and the wire thermal characteristics of the high-efficiency bonding wire, thereby improving thermal management efficiency, reducing thermal resistance, and improving overall heat dissipation performance. This embodiment of the present invention can ensure that the temperature of the chip and the bonding wire is accurately controlled within the optimal range during the packaging process by constructing a thermal management module for the memory chip and the high-efficiency bonding wire based on the packaging temperature range and the real-time temperature data, thereby avoiding damage to the chip or wire caused by excessively high or low temperatures, thereby improving packaging quality. Finally, this embodiment of the present invention can optimize packaging parameters and process control to reduce defect rates and improve packaging reliability and long-term stability by executing packaging control of the memory chip based on the packaging control module. Therefore, the application method and system of high-efficiency wire bonding technology in memory chip packaging provided by the embodiment of the present invention can improve the efficiency and quality of memory chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 A schematic flow chart of a method for applying high-performance wire bonding technology in memory chip packaging according to an embodiment of the present invention;

[0077] Figure 2 A schematic diagram of a module for implementing a method for applying the high-performance wire bonding technology in memory chip packaging according to an embodiment of the present invention.

[0078] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0079] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0080] The embodiments of the present application provide a method for applying high-performance wire bonding technology to memory chip packaging. The execution subject of the method for applying high-performance wire bonding technology to memory chip packaging includes, but is not limited to, at least one of electronic devices such as a server and a terminal that can be configured to execute the method provided by the embodiments of the present application. In other words, the method for applying high-performance wire bonding technology to memory chip packaging can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0081] Example 1:

[0082] Reference Figure 1 FIG2 is a flow chart of a method for applying high-performance wire bonding technology to memory chip packaging according to an embodiment of the present invention. In this embodiment, the method for applying high-performance wire bonding technology to memory chip packaging includes:

[0083] S1. Clarify the packaging requirements of the memory chip, determine the high-energy-efficiency conditions of the leads of the memory chip based on the packaging requirements, obtain the candidate leads of the memory chip, analyze the lead performance of the candidate leads, and screen out high-energy-efficiency bonding leads for the memory chip from the candidate leads based on the high-energy-efficiency conditions of the leads and the lead performance.

[0084] By clarifying the packaging requirements of memory chips, embodiments of the present invention can optimize electrical connections, reduce resistance and signal loss, and improve chip performance. These packaging requirements refer to a series of technical specifications and performance targets set for the memory chip packaging process to ensure that the packaged chips meet predetermined performance, reliability, cost, and production efficiency requirements.

[0085] By determining the high-energy-efficiency lead conditions for the memory chip based on the packaging requirements, embodiments of the present invention can help improve heat conduction efficiency and reduce thermal resistance, thereby more effectively managing chip heat and preventing overheating. The high-energy-efficiency lead conditions refer to a series of technical parameters and standards that must be met during the memory chip packaging process to achieve optimal electrical, thermodynamic, mechanical, and reliability performance.

[0086] Optionally, as an embodiment of the present invention, the determination of the high energy efficiency condition of the leads of the memory chip based on the packaging requirements may be determined by material genome engineering.

[0087] By obtaining candidate leads for the memory chip, embodiments of the present invention can compare the cost and performance of different leads to select the most cost-effective leads, thereby improving packaging performance and reducing production costs. The candidate leads refer to lead materials or types that have been screened as potential options based on packaging requirements and design standards during the memory chip packaging process.

[0088] By analyzing the lead performance of the candidate leads, embodiments of the present invention can assess the mechanical strength and durability of the leads, ensuring that the leads are not susceptible to breakage or wear during assembly, transportation, and use, thereby contributing to achieving high performance, high reliability, and low cost for the product. The lead performance refers to a series of technical indicators that measure the performance of the leads in memory chip packaging, including electrical, thermal, and mechanical properties.

[0089] According to one embodiment of the present invention, the step of analyzing the lead performance of the candidate lead includes:

[0090] measuring the lead resistance, lead inductance, and lead capacitance of the lead to be selected;

[0091] determining the electrical performance of the lead to be selected according to the lead resistance, the lead inductance, and the lead capacitance;

[0092] Performing a thermal performance test on the lead to be selected to obtain test data;

[0093] Based on the test data, the thermal conductivity and thermal expansion coefficient of the selected lead are calculated using the following formula:

[0094]

[0095]

[0096] in, represents thermal conductivity, represents the coefficient of thermal expansion, Indicates the heat corresponding to the test data, represents the cross-sectional area of ​​the lead to be selected, Represents the temperature difference, Indicates the heat conduction distance corresponding to the test data, Indicates the original length of the lead to be selected, Indicates length change;

[0097] Determining the thermal performance of the lead to be selected according to the thermal conductivity and the thermal expansion coefficient;

[0098] Performing a tensile test on the selected lead to obtain tensile test data;

[0099] Analyzing the mechanical properties of the lead to be selected based on the tensile test data;

[0100] The lead performance of the lead to be selected is determined according to the electrical performance, the thermal performance, and the mechanical performance.

[0101] Lead resistance refers to the resistance of the leads (also known as bond wires or conductors) connecting the chip to external circuits. Lead inductance refers to the self-inductance of the leads (or bond wires) due to current changes in the circuit. Lead capacitance refers to the capacitance effect caused by charge distribution between leads (or bond wires) and between leads and other conductors (such as chip pads, PCB traces, and ground planes). Electrical performance refers to the electrical properties exhibited by leads in electronic circuits, which directly affect the circuit's functionality, reliability, and efficiency. Test data refers to the quantitative and qualitative information collected during various thermal performance tests on selected leads. Thermal conductivity refers to the amount of heat that passes through a material per unit length and cross-sectional area per unit time under a unit temperature difference. The coefficient of thermal expansion refers to the relative rate of change in the length or volume of a material as it expands or contracts with temperature changes. Thermal conduction distance refers to the distance heat is transferred through a material by thermal conduction. Thermal performance refers to the behavior of a material or device in a thermal environment, involving how it responds, transfers, and dissipates heat. Tensile test data refers to a series of performance index data collected when a material or component is subjected to a tensile test. Mechanical properties refer to the various physical characteristics exhibited by a material or structure when subjected to external forces. These characteristics describe how the material or structure responds to loads, forces, displacements, and deformations.

[0102] Optionally, the measuring of the lead resistance, lead inductance and lead capacitance of the lead to be selected may be performed through electromagnetic field modeling and simulation.

[0103] By selecting high-energy-efficiency bonding wires for the memory chip from the candidate wires based on the wire high-efficiency conditions and wire performance, the embodiments of the present invention can optimize signal transmission, reduce signal delay and distortion, improve signal integrity, and facilitate faster heat transfer from the chip to the heat dissipation system, thereby lowering the chip's operating temperature and improving reliability. The high-energy-efficiency bonding wires are characterized by high data transmission speeds and efficient heat dissipation, while also achieving higher energy efficiency.

[0104] Optionally, as an embodiment of the present invention, the screening of the high energy efficiency bonding wires for the memory chip from the candidate wires based on the wire high energy efficiency condition and the wire performance may be performed by multi-criteria decision analysis.

[0105] S2. Identify the chip pad position of the memory chip and the substrate pad position of the packaging substrate corresponding to the memory chip, calculate the bending radius, lead length and lead angle of the high-efficiency bonding lead according to the chip pad position and the substrate pad position, and construct a lead forming control module for the high-efficiency bonding lead according to the bending radius, the lead length and the lead angle.

[0106] By accurately identifying the chip pad locations of the memory chip and the substrate pad locations of the corresponding packaging substrate, embodiments of the present invention can ensure proper connection between bonding wires or solder balls and pads, thereby minimizing the risk of poor connection. The chip pad locations refer to specific areas on the surface of an integrated circuit (IC) chip used for connection to other electronic components or a packaging substrate. The substrate pad locations refer to specific areas on a packaging substrate (also known as a printed circuit board (PCB), ceramic substrate, or other type of packaging carrier) used to correspond to and establish electrical connections with chip pads.

[0107] As an embodiment of the present invention, the identifying the chip pad position of the memory chip and the substrate pad position of the packaging substrate corresponding to the memory chip includes:

[0108] collecting chip image data of the memory chip and substrate image data of the packaging substrate;

[0109] respectively extracting chip image features of the chip image data and substrate image features of the substrate image data;

[0110] determining pixel coordinates of chip pads of the memory chip according to the chip image features;

[0111] determining pixel coordinates of substrate pads of the package substrate according to the substrate image features;

[0112] The chip pad position of the memory chip and the substrate pad position of the packaging substrate are determined according to the chip pad pixel coordinates and the substrate pad pixel coordinates.

[0113] The chip image data refers to digital image information of the storage chip surface acquired by an image acquisition device (such as a camera). The substrate image data refers to digital image information of the package substrate surface acquired by an image acquisition device (such as a camera). The chip image features refer to unique visual attributes that can be identified in chip image data and used for image processing and analysis. The substrate image features refer to unique visual attributes that can be identified and analyzed in package substrate image data. The chip pad pixel coordinates refer to the position of the pad center point or specific feature point in the chip image in the image coordinate system, expressed in pixel units. The substrate pad pixel coordinates refer to the position of the pad center point or specific feature point in the image of the substrate (also known as a printed circuit board (PCB)) in the image coordinate system.

[0114] Optionally, the extracting of the chip image features of the chip image data and the substrate image features of the substrate image data may be performed by a morphological processing method.

[0115] The embodiment of the present invention can optimize the heat flow path, improve the heat conduction efficiency, and help dissipate heat from the chip by calculating the bending radius, lead length, and lead angle of the high-efficiency bonding wire based on the chip pad position and the substrate pad position, the chip pad position of the memory chip, and the substrate pad position of the packaging substrate corresponding to the memory chip. It helps reduce signal interference and crosstalk, and improves the stability and reliability of the circuit. The bending radius refers to the radius of the circle formed by the center line of the inner side of the bent portion of the wire or conductor when it is bent at a certain angle. The lead length refers to the actual physical length of the bonding wire from the chip pad to the substrate pad. The lead angle refers to the angle formed by the bonding wire relative to a reference direction (usually horizontal or vertical) in the path from the chip pad to the substrate pad.

[0116] As an embodiment of the present invention, the calculating of the bending radius, lead length, and lead angle of the high-efficiency bonding wire according to the chip pad position and the substrate pad position includes:

[0117] Constructing a two-dimensional coordinate system of the chip pad position and the substrate pad position;

[0118] Determining chip pad coordinates of the chip pad position and substrate pad coordinates of the substrate pad position according to the two-dimensional coordinate system;

[0119] Fitting a wire bending path of the high-efficiency bonding wire according to the chip pad coordinates and the substrate pad coordinates;

[0120] Fitting a path function of the lead bending path, wherein the path function includes:

[0121]

[0122] in, represents the path function, represents the position variable of the path function, represents the curvature coefficient of the path function, Indicates the horizontal coordinate of the vertex of the lead bending path, Indicates the vertical coordinate of the vertex of the lead bending path, An exponential parameter representing the bending path of the lead;

[0123] According to the path function, the bending radius, lead length, and lead angle of the energy-efficient bonding wire are calculated using the following formula:

[0124]

[0125]

[0126]

[0127] in, Indicates the bending radius, Indicates the lead length, Indicates the lead angle, Indicates the chip pad horizontal coordinate corresponding to the chip pad coordinate, Indicates the horizontal coordinate of the substrate pad corresponding to the substrate pad coordinate, Indicates the chip pad ordinate corresponding to the chip pad coordinate, Indicates the vertical coordinate of the substrate pad corresponding to the substrate pad coordinate, represents the sine function, Indicates the bending angle of the lead bending path, represents the path function, represents the position variable of the path function, represents the differential of the path function, represents the integration variable, Represents the inverse tangent function.

[0128] The two-dimensional coordinate system refers to a mathematical system used to describe points on a plane, consisting of two mutually perpendicular number axes. The chip pad coordinates refer to ordered pairs of numbers used to accurately describe the positions of chip pads in a two-dimensional coordinate system. The substrate pad coordinates refer to ordered pairs of numbers used to accurately describe the positions of substrate pads in a two-dimensional coordinate system. The wire bending path refers to the curved shape and path of a bonding wire (also known as a gold wire, copper wire, or aluminum wire, etc.) from a solder point (or bump) on a chip to a pad on a substrate (such as a PCB) during the manufacturing process of a semiconductor device (such as a memory chip). The path function refers to a mathematical function used to describe the wire bending path.

[0129] Optionally, fitting the wire bending path of the high-energy-efficiency bonding wire according to the chip pad coordinates and the substrate pad coordinates may be performed by a least squares method.

[0130] By constructing a wire shaping control module for the energy-efficient bonding wire based on the bend radius, wire length, and wire angle, the embodiment of the present invention ensures that the wire accurately reaches the predetermined pad position, thereby improving assembly accuracy. The wire shaping control module is an integrated hardware and software system for controlling and shaping the geometry of bonding wires (also known as gold, copper, or aluminum wires) during the semiconductor packaging process.

[0131] As an embodiment of the present invention, the lead forming control module for constructing the high-efficiency bonding wire according to the bending radius, the lead length, and the lead angle includes:

[0132] A wire forming machine equipped with the energy-efficient bonding wire;

[0133] defining a lead forming control algorithm of the lead forming machine according to the bending radius, the lead length, and the lead angle;

[0134] Calculating the operating parameters of the lead forming machine according to the lead forming control algorithm;

[0135] Constructing a motion monitoring unit of the lead forming machine, and monitoring real-time motion data of the lead forming machine based on the motion monitoring unit;

[0136] constructing a feedback mechanism of the lead forming machine based on the operating parameters and the real-time motion data;

[0137] According to the wire forming machine, the wire forming control algorithm and the feedback mechanism, a wire forming control module for the high energy efficiency bonding wire is constructed.

[0138] The term "wire former" refers to a specialized mechanical device used in the electronics manufacturing industry to precisely bend and shape bonding wires (also known as gold, copper, or aluminum wires) to connect pads on semiconductor chips to pads on substrates. The term "wire forming control algorithm" refers to an algorithm used to guide the precise operation of the wire forming machine, ensuring that the wires meet specific geometric and electrical requirements during the bending and forming process. The term "operating parameters" refers to a set of parameters that must be set or adjusted to achieve the desired performance and results when operating a wire forming control module or any industrial equipment. The term "motion monitoring unit" refers to a system component used to monitor and control the motion state of the wire forming process. Real-time motion data refers to data continuously collected and transmitted by the motion monitoring unit regarding the motion state of the equipment during wire bonding or other automated manufacturing processes. The term "feedback mechanism" refers to a mechanism that returns output or result information to the input terminal to compare actual performance with expected performance and make adjustments based on the comparison results.

[0139] S3. Obtain wire bonding data of the memory chip, identify bonding parameters and bonding effects in the wire bonding data, analyze influence coefficients of the bonding parameters and bonding effects based on the wire bonding data, and construct a bonding parameter optimization module for the high-efficiency bonding wire according to the influence coefficients.

[0140] The embodiments of the present invention can help optimize bonding parameters, such as bonding force, bonding speed, and heating time, by acquiring wire bonding data of the memory chip, thereby improving production efficiency and product quality. The wire bonding data refers to various parameters and information related to the memory chip manufacturing and packaging process.

[0141] By identifying the bonding parameters and bonding effects in the wire bonding data, embodiments of the present invention can reduce rework and scrap rates caused by inappropriate parameters, thereby improving overall production efficiency. The bonding parameters refer to the key process variables that affect the quality and effect of bonding during the wire bonding process. The bonding effect refers to the actual results achieved through the setting of bonding parameters and the execution of the process during the wire bonding process.

[0142] Optionally, as an embodiment of the present invention, the identifying of the bonding parameters and bonding effects in the wire bonding data may be performed through big data analysis.

[0143] By analyzing the bonding parameters and the bonding effect coefficient based on the wire bonding data, embodiments of the present invention can accurately identify which bonding parameters have the greatest impact on solder joint quality, thereby optimizing these parameters in a targeted manner and improving the consistency and reliability of solder joints. The influence coefficient is an indicator used to quantify the strength of the impact of a bonding parameter on the bonding effect.

[0144] As an embodiment of the present invention, analyzing the bonding parameters and the influence coefficient of the bonding effect based on the wire bonding data includes:

[0145] performing data cleaning on the wire bonding data to obtain cleaned data, and normalizing the cleaned data to obtain normalized data;

[0146] Calculating a correlation coefficient between the bonding parameter and the bonding effect based on the normalized data;

[0147] Constructing a regression analysis model of the bonding parameters and the bonding effect;

[0148] Analyzing the influence of the bonding parameters on the bonding effect according to the regression analysis model;

[0149] The bonding parameter and the influence coefficient of the bonding effect are determined according to the correlation coefficient and the influence degree.

[0150] The cleaned data refers to a data set whose quality has been improved after a series of data preprocessing steps. The normalized data refers to data that has been processed through a specific mathematical transformation so that the numerical range of the data set is scaled to a fixed interval. The correlation coefficient refers to a statistic that measures the strength and direction of the linear relationship between two variables. The regression analysis model refers to a statistical model used to analyze the relationship between two or more variables, in particular, to predict or explain the dependency between one or more dependent variables (response variables) and one or more independent variables (explanatory variables). The degree of influence refers to the influence of the independent variable (explanatory variable) on the dependent variable (response variable) in a regression analysis model.

[0151] Optionally, the correlation coefficient between the bonding parameter and the bonding effect calculated based on the normalized data can be calculated by using a Pearson correlation coefficient.

[0152] By constructing a bonding parameter optimization module for energy-efficient bonding wires based on the influence coefficients, the embodiments of the present invention can improve the speed of the bonding process, reduce energy consumption, and thus enhance overall bonding efficiency by optimizing the parameters that affect the bonding effect. The bonding parameter optimization module refers to a software system integrated into the semiconductor packaging or electronics manufacturing process that analyzes and adjusts key parameters during bonding (such as ball grid array (BGA), chip-scale package (CSP), or other forms of wire bonding) to achieve optimal bonding results.

[0153] As an embodiment of the present invention, constructing a bonding parameter optimization module for the energy-efficient bonding wire according to the influence coefficient includes:

[0154] Determining an optimization target for bonding parameters corresponding to the energy-efficient bonding wire;

[0155] Analyzing a bonding scenario of the high-energy-efficiency bonding wire, and determining a constraint condition of the high-energy-efficiency bonding wire based on the bonding scenario;

[0156] Defining an optimization algorithm for the bonding parameters according to the constraint conditions and the influence coefficients;

[0157] Determining an optimization iterative mechanism for the bonding parameters according to the optimization goal;

[0158] According to the optimization algorithm and the optimization iteration mechanism, a bonding parameter optimization module for the high-energy-efficiency bonding wire is constructed.

[0159] Among them, the optimization goal refers to the specific performance indicators or results that are hoped to be achieved when constructing a bonding parameter optimization module for energy-efficient bonding wires. The bonding scenario refers to the specific environment and conditions of wire bonding operations during semiconductor manufacturing or electronic assembly. The constraints refer to the limiting factors that must be considered when optimizing bonding parameters. These conditions are usually determined by factors such as bonding process requirements, equipment capabilities, material properties, production environment, and product quality standards. The optimization algorithm refers to a series of calculation methods and steps used to find the optimal bonding parameters so as to achieve or approach the predetermined optimization goal under given constraints. The optimization iteration mechanism refers to the process of repeated calculation and evaluation used to gradually improve parameter settings to achieve the optimization goal during the bonding parameter optimization process.

[0160] Optionally, the optimization algorithm for defining the bonding parameters according to the constraint conditions and the influence coefficients may be defined by sequential quadratic programming.

[0161] S4. Analyze the chip thermal characteristics of the memory chip and the lead thermal characteristics of the high-efficiency bonding wire, determine the packaging temperature range of the memory chip based on the chip thermal characteristics and the lead thermal characteristics, construct a packaging temperature monitoring unit for the memory chip, monitor the real-time temperature data of the packaging area corresponding to the memory chip based on the packaging temperature monitoring unit, and construct a thermal management module for the memory chip and the high-efficiency bonding wire based on the packaging temperature range and the real-time temperature data.

[0162] By analyzing the chip thermal characteristics of the memory chip and the wire thermal characteristics of the high-efficiency bonding wire, the embodiments of the present invention can ensure that the chip will not be damaged due to overheating during the bonding process, thereby improving thermal management efficiency, reducing thermal resistance, and enhancing overall heat dissipation performance. The chip thermal characteristics refer to the performance indicators of the heat generated by the chip during operation and how this heat is transferred through the chip material, package, heat sink, etc. The wire thermal characteristics refer to the performance indicators of the wire (usually referring to metal wires used for electrical connections, such as gold wires, copper wires, etc., used to connect the chip to the external circuit in semiconductor packaging) in terms of thermal conduction and thermal management.

[0163] Optionally, as an embodiment of the present invention, the analyzing of the chip thermal characteristics of the memory chip and the wire thermal characteristics of the high-efficiency bonding wire may be performed by thermal imaging technology.

[0164] By determining the memory chip's packaging temperature range based on the chip's thermal characteristics and the lead's thermal characteristics, embodiments of the present invention can ensure stable chip performance under normal operating conditions and avoid performance degradation due to temperature fluctuations. The packaging temperature range refers to a set of temperature limits within which the memory chip and its package can safely and reliably operate under normal operating conditions.

[0165] Optionally, as an embodiment of the present invention, determining the packaging temperature range of the memory chip based on the chip thermal characteristics and the lead thermal characteristics may be determined by a thermal cycle test.

[0166] The embodiment of the present invention can monitor the temperature of the memory chip packaging area in real time by constructing the memory chip packaging temperature monitoring unit, ensuring that the temperature changes are within a safe range. The packaging temperature monitoring unit refers to a device used to monitor and control the temperature during the packaging process.

[0167] As an embodiment of the present invention, the packaging temperature monitoring unit for the memory chip includes:

[0168] Determining a temperature sensor of the memory chip and determining a sensor installation position of the temperature sensor;

[0169] Constructing a signal conditioning circuit and a microprocessor for the temperature sensor;

[0170] Determining a monitoring unit network topology of the storage chip according to the sensor installation position, the temperature sensor, and the microprocessor;

[0171] Determining a data transmission method and a communication protocol for the temperature sensor;

[0172] A packaging temperature monitoring unit for the memory chip is constructed according to the monitoring unit network topology, the communication protocol, and the signal conditioning circuit.

[0173] The temperature sensor refers to a device that can convert temperature changes into a measurable signal. The sensor installation location refers to the specific location selected during the memory chip packaging process for accurate temperature monitoring. The signal conditioning circuit refers to an electronic circuit used to process the output signal of the temperature sensor. The microprocessor refers to a small computer integrated on a single chip that can execute computer program instructions to process data. The monitoring unit network topology refers to the layout and structure of temperature monitoring units (including temperature sensors, signal conditioning circuits, microprocessors, etc.) used for connection and communication in a system. The data transmission method refers to the method of transmitting data between different devices or systems. The communication protocol refers to a set of rules and standards that defines the format, sequence, error detection and correction methods, and data exchange mechanism for data transmission between devices.

[0174] In embodiments of the present invention, by using the package temperature monitoring unit to monitor the real-time temperature data of the package area corresponding to the memory chip in real time, temperature deviations can be promptly detected and corrected through real-time monitoring, thereby improving package quality and reducing defect rates. The real-time temperature data refers to the temperature information of the package area continuously collected by the temperature monitoring unit within a specific time interval.

[0175] By constructing a thermal management module for the memory chip and the high-efficiency bonding wires based on the packaging temperature range and real-time temperature data, the embodiments of the present invention can ensure that the temperature of the chip and bonding wires is precisely controlled within an optimal range during the packaging process, avoiding damage to the chip or wires due to excessively high or low temperatures, thereby improving packaging quality. The thermal management module refers to a subsystem or component specifically designed to monitor and control temperature during the memory chip packaging process.

[0176] As an embodiment of the present invention, constructing a thermal management module for the memory chip and the energy-efficient bonding wire according to the packaging temperature range and the real-time temperature data includes:

[0177] A temperature regulator configured for the memory chip and the energy-efficient bonding wire;

[0178] Analyzing a temperature difference between the real-time temperature data and the package temperature range;

[0179] defining a temperature control algorithm for the memory chip and the energy-efficient bonding wire according to the temperature difference;

[0180] Determining temperature control logic for the memory chip and the energy-efficient bonding wire based on the temperature control algorithm;

[0181] A thermal management module for the memory chip and the energy-efficient bonding wire is constructed according to the temperature regulator, the temperature control algorithm, and the temperature control logic.

[0182] The term "temperature regulator" refers to a device used to control or change the temperature of a device or system. The term "temperature gap" refers to the difference between the actual temperature and the target temperature. The term "temperature control algorithm" refers to a series of calculation steps and rules used to manage and adjust the temperature of a memory chip or its packaging environment. The term "temperature control logic" refers to a series of rules and decision-making processes used to manage and adjust the temperature of a device (such as a memory chip).

[0183] S5. Integrate a packaging control module for the memory chip according to the lead forming control module, the bonding parameter optimization module, and the thermal management module, and perform packaging control of the memory chip based on the packaging control module.

[0184] By integrating the lead forming control module, the bonding parameter optimization module, and the thermal management module into the memory chip packaging control module, the embodiments of the present invention ensure consistency in each bonding process, reduce batch-to-batch variability, and improve overall product quality. The packaging control module is an integrated system that manages and controls the key steps and parameters in the memory chip packaging process.

[0185] The embodiment of the present invention can optimize packaging parameters and process control by executing packaging control of the memory chip based on the packaging control module, thereby reducing defect rate and improving reliability and long-term stability of packaging.

[0186] The embodiment of the present invention can optimize signal transmission, reduce signal delay and distortion, improve signal integrity, and help to conduct heat from the chip to the heat dissipation system more quickly, reduce the chip operating temperature, and improve reliability by screening out the high-energy-efficiency bonding wires of the memory chip from the candidate wires according to the high-energy-efficiency conditions of the wires and the performance of the wires. Optionally, the embodiment of the present invention can optimize the heat flow path, improve the heat conduction efficiency, help dissipate heat of the chip, and help reduce signal interference and crosstalk, thereby improving the stability and reliability of the circuit by calculating the bending radius, lead length, and lead angle of the high-energy-efficiency bonding wires according to the chip pad position and the substrate pad position, the chip pad position of the memory chip, and the substrate pad position of the packaging substrate corresponding to the memory chip. This helps reduce signal interference and crosstalk, and improves the stability and reliability of the circuit. The embodiment of the present invention can accurately identify which bonding parameters are important by analyzing the bonding parameters and the influencing coefficient of the bonding effect based on the wire bonding data. The number has the greatest impact on the quality of the solder joints, so these parameters can be optimized in a targeted manner to improve the consistency and reliability of the solder joints. This embodiment of the present invention can ensure that the chip will not be damaged due to overheating during the bonding process by analyzing the chip thermal characteristics of the memory chip and the wire thermal characteristics of the high-efficiency bonding wire, thereby improving thermal management efficiency, reducing thermal resistance, and improving overall heat dissipation performance. This embodiment of the present invention can ensure that the temperature of the chip and the bonding wire is accurately controlled within the optimal range during the packaging process by constructing a thermal management module for the memory chip and the high-efficiency bonding wire based on the packaging temperature range and the real-time temperature data, thereby avoiding damage to the chip or wire caused by excessively high or low temperatures, thereby improving packaging quality. Finally, this embodiment of the present invention can optimize packaging parameters and process control to reduce defect rates and improve packaging reliability and long-term stability by executing packaging control of the memory chip based on the packaging control module. Therefore, the application method and system of high-efficiency wire bonding technology in memory chip packaging provided by the embodiment of the present invention can improve the efficiency and quality of memory chip packaging.

[0187] Example 2:

[0188] like Figure 2 FIG. 1 is a functional module diagram of an application system of a high-performance wire bonding technology in memory chip packaging according to the present invention.

[0189] The system 200 for applying high-performance wire bonding technology to memory chip packaging described in the present invention can be installed in an electronic device. Depending on the functionality implemented, the system can include a bonding wire determination module 201, a wire shaping control module 202, a bonding parameter optimization module 203, a thermal management module 204, and a packaging control module 205. A module, also referred to as a unit, is a series of computer program segments that can be executed by an electronic device processor and perform a fixed function, and is stored in the electronic device's memory.

[0190] In the embodiment of the present invention, the functions of each module / unit are as follows:

[0191] The bonding wire determination module 201 is configured to determine packaging requirements of a memory chip, determine high energy efficiency conditions for wires of the memory chip based on the packaging requirements, obtain candidate wires for the memory chip, analyze wire performance of the candidate wires, and select high energy efficiency bonding wires for the memory chip from the candidate wires based on the high energy efficiency conditions and wire performance.

[0192] The lead forming control module 202 is configured to identify the chip pad position of the memory chip and the substrate pad position of the packaging substrate corresponding to the memory chip, calculate the bending radius, lead length, and lead angle of the high-efficiency bonding wire based on the chip pad position and the substrate pad position, and construct a lead forming control module for the high-efficiency bonding wire based on the bending radius, lead length, and lead angle;

[0193] The bonding parameter optimization module 203 is configured to obtain wire bonding data of the memory chip, identify bonding parameters and bonding effects in the wire bonding data, analyze influence coefficients of the bonding parameters and bonding effects based on the wire bonding data, and construct a bonding parameter optimization module for the high-efficiency bonding wire according to the influence coefficients;

[0194] The thermal management module 204 is configured to analyze the chip thermal characteristics of the memory chip and the lead thermal characteristics of the high-efficiency bonding wire, determine the packaging temperature range of the memory chip based on the chip thermal characteristics and the lead thermal characteristics, establish a packaging temperature monitoring unit for the memory chip, monitor the real-time temperature data of the packaging area corresponding to the memory chip based on the packaging temperature monitoring unit, and establish a thermal management module for the memory chip and the high-efficiency bonding wire based on the packaging temperature range and the real-time temperature data;

[0195] The packaging control module 205 is used to integrate the packaging control module of the memory chip according to the lead forming control module, the bonding parameter optimization module and the thermal management module, and perform packaging control of the memory chip based on the packaging control module.

[0196] In detail, the modules in the application system 200 of the high-performance wire bonding technology in memory chip packaging according to the embodiment of the present invention are used in the same manner as above. Figure 1 The application method of the high-performance wire bonding technology described in the previous section in memory chip packaging is the same technical means and can produce the same technical effects, so it will not be repeated here.

[0197] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0198] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for applying high-performance wire bonding technology in memory chip packaging, characterized in that: The method comprises: Clarifying packaging requirements for a memory chip, determining high energy efficiency conditions for leads of the memory chip based on the packaging requirements, obtaining candidate leads for the memory chip, analyzing lead performance of the candidate leads, and selecting high energy efficiency bonding leads for the memory chip from the candidate leads based on the high energy efficiency conditions and the lead performance; Identifying a chip pad position of the memory chip and a substrate pad position of a packaging substrate corresponding to the memory chip, calculating a bending radius, a lead length, and a lead angle of the high-efficiency bonding wire based on the chip pad position and the substrate pad position, and constructing a lead forming control module for the high-efficiency bonding wire based on the bending radius, the lead length, and the lead angle; Acquiring wire bonding data of the memory chip, identifying bonding parameters and bonding effects in the wire bonding data, analyzing influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data, and constructing a bonding parameter optimization module for the high-efficiency bonding wire according to the influence coefficients; Analyzing the chip thermal characteristics of the memory chip and the lead thermal characteristics of the high-efficiency bonding wire, determining the packaging temperature range of the memory chip based on the chip thermal characteristics and the lead thermal characteristics, constructing a packaging temperature monitoring unit for the memory chip, monitoring real-time temperature data of a packaging area corresponding to the memory chip based on the packaging temperature monitoring unit, and constructing a thermal management module for the memory chip and the high-efficiency bonding wire based on the packaging temperature range and the real-time temperature data; According to the lead forming control module, the bonding parameter optimization module and the thermal management module, a packaging control module of the memory chip is integrated, and based on the packaging control module, packaging control of the memory chip is performed.

2. The method for applying the high-performance wire bonding technology in memory chip packaging according to claim 1, wherein: The analyzing the lead performance of the lead to be selected includes: measuring the lead resistance, lead inductance, and lead capacitance of the lead to be selected; determining the electrical performance of the lead to be selected according to the lead resistance, the lead inductance, and the lead capacitance; Performing a thermal performance test on the lead to be selected to obtain test data; Based on the test data, the thermal conductivity and thermal expansion coefficient of the selected lead are calculated using the following formula: in, represents thermal conductivity, represents the coefficient of thermal expansion, Indicates the heat corresponding to the test data, represents the cross-sectional area of ​​the lead to be selected, Represents the temperature difference, Indicates the heat conduction distance corresponding to the test data, Indicates the original length of the lead to be selected, Indicates length change; Determining the thermal performance of the lead to be selected according to the thermal conductivity and the thermal expansion coefficient; Performing a tensile test on the selected lead to obtain tensile test data; Analyzing the mechanical properties of the lead to be selected based on the tensile test data; The lead performance of the lead to be selected is determined according to the electrical performance, the thermal performance, and the mechanical performance.

3. The method for applying the high-performance wire bonding technology in memory chip packaging according to claim 1, wherein: The identifying the chip pad position of the memory chip and the substrate pad position of the packaging substrate corresponding to the memory chip includes: collecting chip image data of the memory chip and substrate image data of the packaging substrate; respectively extracting chip image features of the chip image data and substrate image features of the substrate image data; determining pixel coordinates of chip pads of the memory chip according to the chip image features; determining pixel coordinates of substrate pads of the package substrate according to the substrate image features; The chip pad position of the memory chip and the substrate pad position of the packaging substrate are determined according to the chip pad pixel coordinates and the substrate pad pixel coordinates.

4. The method for applying high-performance wire bonding technology in memory chip packaging according to claim 1, wherein: The calculating, based on the chip pad position and the substrate pad position, the bending radius, the lead length, and the lead angle of the high-efficiency bonding wire comprises: Constructing a two-dimensional coordinate system of the chip pad position and the substrate pad position; Determining chip pad coordinates of the chip pad position and substrate pad coordinates of the substrate pad position according to the two-dimensional coordinate system; Fitting a wire bending path of the high-efficiency bonding wire according to the chip pad coordinates and the substrate pad coordinates; Fitting a path function of the lead bending path, wherein the path function includes: in, represents the path function, represents the position variable of the path function, represents the curvature coefficient of the path function, Indicates the horizontal coordinate of the vertex of the lead bending path, Indicates the vertical coordinate of the vertex of the lead bending path, An exponential parameter representing the bending path of the lead; The bending radius, wire length, and wire angle of the energy-efficient bonding wire are calculated according to the path function.

5. The method for applying high-performance wire bonding technology in memory chip packaging according to claim 1, wherein: The step of constructing a lead forming control module for the high-efficiency bonding wire according to the bending radius, the lead length, and the lead angle includes: A wire forming machine equipped with the energy-efficient bonding wire; defining a lead forming control algorithm of the lead forming machine according to the bending radius, the lead length, and the lead angle; Calculating the operating parameters of the lead forming machine according to the lead forming control algorithm; Constructing a motion monitoring unit of the lead forming machine, and monitoring real-time motion data of the lead forming machine based on the motion monitoring unit; constructing a feedback mechanism of the lead forming machine based on the operating parameters and the real-time motion data; According to the wire forming machine, the wire forming control algorithm and the feedback mechanism, a wire forming control module for the high energy efficiency bonding wire is constructed.

6. The method for applying high-performance wire bonding technology in memory chip packaging according to claim 1, wherein: The analyzing, based on the wire bonding data, the bonding parameters and the influence coefficients of the bonding effect includes: performing data cleaning on the wire bonding data to obtain cleaned data, and normalizing the cleaned data to obtain normalized data; Calculating a correlation coefficient between the bonding parameter and the bonding effect based on the normalized data; Constructing a regression analysis model of the bonding parameters and the bonding effect; Analyzing the influence of the bonding parameters on the bonding effect according to the regression analysis model; The bonding parameter and the influence coefficient of the bonding effect are determined according to the correlation coefficient and the influence degree.

7. The method for applying high-performance wire bonding technology in memory chip packaging according to claim 1, wherein: The step of constructing a bonding parameter optimization module for the high-energy-efficiency bonding wire according to the influence coefficient includes: Determining an optimization target for bonding parameters corresponding to the energy-efficient bonding wire; Analyzing a bonding scenario of the high-energy-efficiency bonding wire, and determining a constraint condition of the high-energy-efficiency bonding wire based on the bonding scenario; Defining an optimization algorithm for the bonding parameters according to the constraint conditions and the influence coefficients; Determining an optimization iterative mechanism for the bonding parameters according to the optimization goal; According to the optimization algorithm and the optimization iteration mechanism, a bonding parameter optimization module for the high-energy-efficiency bonding wire is constructed.

8. The method for applying high-performance wire bonding technology in memory chip packaging according to claim 1, wherein: The packaging temperature monitoring unit for constructing the memory chip includes: Determining a temperature sensor of the memory chip and determining a sensor installation position of the temperature sensor; Constructing a signal conditioning circuit and a microprocessor for the temperature sensor; Determining a monitoring unit network topology of the storage chip according to the sensor installation position, the temperature sensor, and the microprocessor; Determining a data transmission method and a communication protocol for the temperature sensor; A packaging temperature monitoring unit for the memory chip is constructed according to the monitoring unit network topology, the communication protocol, and the signal conditioning circuit.

9. The method for applying high-performance wire bonding technology in memory chip packaging according to claim 1, wherein: The step of constructing a thermal management module for the memory chip and the energy-efficient bonding wire according to the package temperature range and the real-time temperature data includes: A temperature regulator configured for the memory chip and the energy-efficient bonding wire; Analyzing a temperature difference between the real-time temperature data and the package temperature range; defining a temperature control algorithm for the memory chip and the energy-efficient bonding wire according to the temperature difference; Determining temperature control logic for the memory chip and the energy-efficient bonding wire based on the temperature control algorithm; A thermal management module for the memory chip and the energy-efficient bonding wire is constructed according to the temperature regulator, the temperature control algorithm, and the temperature control logic.

10. An application system of high-performance wire bonding technology in memory chip packaging, characterized in that: The system comprises: a bonding wire determination module, configured to determine packaging requirements for a memory chip, determine high energy efficiency conditions for leads of the memory chip based on the packaging requirements, obtain candidate leads for the memory chip, analyze lead performance of the candidate leads, and select high energy efficiency bonding wires for the memory chip from the candidate leads based on the high energy efficiency conditions and the lead performance; a lead forming control module, configured to identify a chip pad position of the memory chip and a substrate pad position of a packaging substrate corresponding to the memory chip, calculate a bending radius, a lead length, and a lead angle of the high-efficiency bonding wire based on the chip pad position and the substrate pad position, and construct a lead forming control module for the high-efficiency bonding wire based on the bending radius, the lead length, and the lead angle; a bonding parameter optimization module, configured to obtain wire bonding data of the memory chip, identify bonding parameters and bonding effects in the wire bonding data, analyze influence coefficients of the bonding parameters and the bonding effects based on the wire bonding data, and construct a bonding parameter optimization module for the high-energy-efficiency bonding wire according to the influence coefficients; a thermal management module configured to analyze chip thermal characteristics of the memory chip and lead thermal characteristics of the high-efficiency bonding wire, determine a packaging temperature range of the memory chip based on the chip thermal characteristics and the lead thermal characteristics, construct a packaging temperature monitoring unit for the memory chip, monitor real-time temperature data of a packaging area corresponding to the memory chip based on the packaging temperature monitoring unit, and construct a thermal management module for the memory chip and the high-efficiency bonding wire based on the packaging temperature range and the real-time temperature data; A packaging control module is used to integrate the packaging control module of the memory chip according to the lead forming control module, the bonding parameter optimization module and the thermal management module, and perform packaging control of the memory chip based on the packaging control module.

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