Electronic device

Abstract

The invention discloses an electronic device which comprises a first transistor, a second transistor, a plurality of driving units and an electronic unit. The first transistor includes a first control terminal. The second transistor is coupled to the first transistor and includes a second control terminal for receiving the pulse signal. The pulse signal has a pulse width. The driving units are connected in parallel. Each driving unit comprises an input end, an output end and a control end. The input end is coupled to a first control end, the output end is coupled to a node, and the control end receives an enable signal. The electronic unit is coupled to the node. The driving units respectively provide current to the electronic unit according to the received enable signals, and the current passing through the electronic unit is modulated according to the pulse width of the pulse signal.

Description

Technical Field

[0001] The present invention relates to an electronic device, and particularly to an electronic device with a light-emitting function using Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) technologies. Background Art

[0002] A Light-Emitting Diode (LED) display is an electronic device that uses light-emitting diodes as pixels to generate images. The working principle of an LED display is to generate an image by controlling the brightness and color of each pixel. Each pixel can be composed of red, green, and blue LEDs, and these LEDs can be independently controlled to produce different colors. Among them, Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) are both common modulation technologies in LED displays. However, current LED displays only use one of the PAM and PWM modulation technologies, which greatly limits the application of LED displays. Summary of the Invention

[0003] The object of the present invention is to provide an electronic device.

[0004] The present invention provides an electronic device, which includes a first transistor, a second transistor, a plurality of driving units, and an electronic unit. The first transistor includes a first control terminal. The second transistor is coupled to the first transistor and includes a second control terminal for receiving a pulse signal. The pulse signal has a pulse width. The driving units are connected in parallel with each other. Each driving unit includes an input terminal, an output terminal, and a control terminal. The input terminal is coupled to the first control terminal, the output terminal is coupled to a node, and the control terminal receives an enabling signal. The electronic unit is coupled to the node. The driving units respectively provide current to the electronic unit according to the enabling signals received by them, and the current passing through the electronic unit is modulated according to the pulse width of the pulse signal.

[0005] The present invention further provides an electronic device, which includes a first transistor, a second transistor, a driving transistor, and a first electronic unit. The first transistor includes a first terminal and a first control terminal. The second transistor includes a second control terminal. The second control terminal is coupled to the first terminal and is used for receiving a pulse signal. The pulse signal has a pulse width and a pulse amplitude. The driving transistor includes a third control terminal. The third control terminal is coupled to the first control terminal. The first electronic unit is coupled to the driving transistor. Wherein, the magnitude and time of the current passing through the first electronic unit are modulated according to the pulse amplitude and the pulse width respectively. Brief Description of the Drawings

[0006] Figure 1 It is a circuit diagram of an electronic device according to an embodiment of the present invention.

[0007] Figure 2 The Figure 1 timing diagrams of signals and currents of the electronic device shown.

[0008] Figure 3 The circuit diagram of the electronic device according to another embodiment of the present invention.

[0009] Figure 4 The Figure 3 timing diagrams of signals and currents of the electronic device shown.

[0010] Figure 5 The circuit diagram of the memory unit of the electronic device according to another embodiment of the present invention.

[0011] Figure 6 The circuit diagram of the electronic device according to another embodiment of the present invention.

[0012] Figure 7 The Figure 6 timing diagrams of signals and currents of the electronic device shown.

[0013] Figure 8 The circuit diagram of the electronic device according to another embodiment of the present invention.

[0014] Description of reference numerals: 10A, 10B, 10C, 10D - electronic devices; 15 - current source; 20a, 20b, 30a, 30b - driving units; 40a, 40b, 40c - memory units; 42 - first inverter; 44 - second inverter; 80a to 80n - light emitting units; A - input terminal; B - output terminal; C - control terminal; C1 - first control terminal; C2 - second control terminal; C3 - third control terminal; Cst - storage capacitor; D - data terminal; D1 to Dn - electronic units; E1 - first terminal; EM1, EMn - switching signals; I1, I2, I3, Id - currents; Iref - reference current; P - node; P1, P2, P3, P4, P5, P6 - pulses; PVDD - first system voltage terminal; PVSS - second system voltage terminal; Q1, Qn - switching transistors; S1, S2, Sn - enable signals; T1, T1a, T1b - third transistors; T2a, T2b - fourth transistors; Td, Td1, Td2 - driving transistors; T3a, T3b - data transistors; T3 - first data transistor; T4 - second data transistor; Tcm - first transistor; Tsw - second transistor; t1, t2, t3, t4, t5, t6 - time periods; Vcm - voltage; Vdata - data signal; VE1, VE2, VEn - voltages; VF, VF1, VFn - voltages; VG1, VG2 - voltages; VP - pulse signal; W1, W2, W3, W4, W5, W6 - pulse widths. Detailed Description

[0015] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for the convenience of the reader's understanding and the simplicity of the drawings, only a part of the electronic device is shown in the multiple drawings of the present invention, and the specific elements in the drawings are not drawn to actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of the present invention.

[0016] Throughout the specification and the appended claims of the present invention, certain terms will be used to refer to specific elements. Those skilled in the art should understand that electronic device manufacturers may use different names to refer to the same element. The present invention is not intended to distinguish between elements that have the same function but different names.

[0017] In the specification and claims of the present invention, words such as "comprising", "including", "having", etc. are open-ended terms, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the terms "comprising", "including" and / or "having" are used in the description of the present invention, they specify the presence of the corresponding features, regions, steps, operations and / or components, but do not exclude the presence of one or more corresponding features, regions, steps, operations and / or components.

[0018] The directional terms mentioned in the present invention, such as "upper", "lower", "front", "rear", "left", "right", etc., are only with reference to the directions in the drawings. Therefore, the directional terms used are for illustration and are not used to limit the present invention. In the drawings, each drawing shows the general characteristics of the methods, structures and / or materials used in specific embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses and positions of each film layer, region and / or structure may be reduced or enlarged.

[0019] When a corresponding component (such as a film layer or a region) is referred to as "on another component", it can be directly on another component, or there may be other components between the two. On the other hand, when a component is referred to as "directly on another component", there are no components between the two. In addition, when a component is referred to as "on another component", there is an up-and-down relationship between the two in the vertical direction, and this component can be above or below another component, and this up-and-down relationship depends on the orientation of the device.

[0020] It should be understood that when a component or film layer is referred to as "connected to" another component or film layer, it can be directly connected to this other component or film layer, or there are intervening components or film layers between the two. When a component is referred to as "directly connected to" another component or film layer, there are no intervening components or film layers between the two. Additionally, when a component is referred to as "coupled to another component (or its variant)", it can be directly connected to this other component or indirectly connected (e.g., electrically connected) to this other component through one or more components.

[0021] In the present invention, when a component is "electrically connected" to another component, an electrical signal can flow between the two components at at least one moment during normal operation; when a component is "coupled" to another component, an electrical signal can flow between the two components within the specified moment. In the present invention, when a component is "disconnected" from another component, an electrical signal cannot flow between the two components within the specified moment.

[0022] The terms "approximate" or "identical" are generally interpreted as being within the range of plus or minus 20% of the given value, or within the range of plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1%, or plus or minus 0.5% of the given value.

[0023] The ordinal numbers used in the description and claims of the present invention, such as "first", "second", etc., are used to modify elements, and they do not themselves imply or represent that the (or these) elements have any previous ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish an element with a certain name from another element with the same name. The same terms may not be used in the claims and the description. Accordingly, the first component in the description may be the second component in the claims.

[0024] It should be noted that in the following examples, without departing from the spirit of the present invention, the features in several different examples can be replaced, recombined, and mixed to complete other examples. As long as the features between the examples do not violate the spirit of the invention or conflict with each other, they can be arbitrarily mixed and used.

[0025] In the present invention, the electronic device may include a display device, a light-emitting device, a backlight device, a virtual reality device, an augmented reality (AR) device, an antenna device, a sensing device, a splicing device, or any combination thereof, but not limited thereto. The display device may be a non-self-luminous display or a self-luminous display according to requirements, and may be a color display or a monochrome display according to requirements. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device. The sensing device may be a sensing device for sensing capacitance, light, heat energy, or ultrasonic waves. The splicing device may be a display splicing device or an antenna splicing device, but not limited thereto. The electronic units in the electronic device may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode (LED) or a photodiode. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a mini light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED), but not limited thereto. The transistor may include, for example, a top gate thin-film transistor, a bottom gate thin-film transistor, or a dual gate thin-film transistor, but not limited thereto. The electronic device may also include, according to requirements, fluorescence materials, phosphor materials, quantum dot (QD) materials, or other suitable materials, but not limited thereto. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, etc. to support the display device, the antenna device, the wearable device (such as including an augmented reality or virtual reality device), the in-vehicle device (such as including an automotive windshield), or the splicing device.

[0026] In some embodiments, the electronic panel may be a type of electronic device, and the electronic panel may be at least a combination of a display device and a touch sensing device, so that the electronic panel has at least a display function and a touch sensing function. Hereinafter, the present invention will be described by taking the electronic device as an example, but the design of the present invention can be applied to any suitable electronic device.

[0027] In addition, the switching element described in the present invention may be any electronic component having a switching effect. For example, the switching element may be a thin-film transistor. For example, the thin-film transistor may be a top gate thin-film transistor, a bottom gate thin-film transistor, a dual gate thin-film transistor, or other suitable types of transistors.

[0028] Please refer to Figure 1 , Figure 1 which is a circuit diagram of an electronic device 10A according to an embodiment of the present invention. The electronic device 10A includes a first transistor Tcm, a second transistor Tsw, a plurality of driving units 20a and 20b, and an electronic unit D1. The electronic unit D1 may have a light-emitting function. For example, the electronic unit D1 may include a light emitting diode (LED) or a photodiode. In addition, although the electronic device 10A is exemplified as including two driving units 20a and 20b in this embodiment, in other embodiments of the present invention, the electronic device 10A may include three or more driving units. The first transistor Tcm may be a P-type metal-oxide-semiconductor field-effect transistor (abbreviation: PMOS transistor), which includes a first control terminal C1, and the first control terminal C1 may be the gate of the first transistor Tcm. Furthermore, the first end of the first transistor Tcm may be the source of the PMOS transistor and is coupled to the first system voltage terminal PVDD; and the second end of the first transistor Tcm may be the drain of the PMOS transistor and is coupled to the first control terminal C1. The second transistor Tsw may be an N-type metal-oxide-semiconductor field-effect transistor (abbreviation: NMOS transistor), which includes a second control terminal C2, and the second control terminal C2 may be the gate of the second transistor Tsw for receiving a pulse signal VP. In addition, the first end of the second transistor Tsw may be the drain of the NMOS transistor and is coupled to the first control terminal C1; and the second end of the second transistor Tsw may be the source of the NMOS transistor and is coupled to the second system voltage terminal PVSS. The voltage of the second system voltage terminal PVSS is lower than the voltage of the first system voltage terminal PVDD. For example, the voltage of the first system voltage terminal PVDD is a positive voltage, and the voltage of the second system voltage terminal PVSS is a ground voltage. However, the present invention is not limited thereto. In addition, when the pulse signal VP is at a high potential, the second transistor Tsw is turned on, so that the voltage Vcm of the first control terminal C1 is at a low potential, and further the first transistor Tcm is turned on; when the pulse signal VP is at a low potential, the second transistor Tsw is turned off, so that the voltage Vcm of the first control terminal C1 is at a high potential, and further the first transistor Tcm is turned off.

[0029] The driving units 20a and 20b are connected in parallel with each other, and each of the driving units 20a and 20b includes an input terminal A, an output terminal B, and a control terminal C. Among them, the input terminal A is coupled to the first control terminal C1, the output terminal B is coupled to the node P, and the control terminal C receives an enabling signal. For example, the control terminal C of the driving unit 20a receives the enabling signal S1, and the control terminal C of the driving unit 20b receives the enabling signal S2. Among them, the voltage of the node P is VF. Furthermore, each driving unit may further include a third transistor, a fourth transistor, and a driving transistor. For example, the driving unit 20a may further include a third transistor T1a, a fourth transistor T2a, and a driving transistor Td1, and the driving unit 20b may further include a third transistor T1b, a fourth transistor T2b, and a driving transistor Td2. The circuit architectures of the driving unit 20a and the driving unit 20b are the same. Therefore, the following description will be based on the circuit architecture of the driving unit 20a, and the circuit architecture of the driving unit 20b can be analogized accordingly. The third transistor T1a may be a PMOS transistor, and the first end of the third transistor T1a may be the source of the PMOS transistor and is coupled to the first system voltage terminal PVDD; the second end of the third transistor T1a may be the drain of the PMOS transistor; and the control terminal of the third transistor T1a may be the gate of the PMOS transistor and is used to receive the enabling signal S1. The fourth transistor T2a may be an NMOS transistor, and the first end of the fourth transistor T2a is coupled to the input terminal A; the second end of the fourth transistor T2a is coupled to the second end of the third transistor T1a; and the control terminal of the fourth transistor T2a may be the gate of the NMOS transistor and is used to receive the enabling signal S1. The driving transistor Td1 may be a PMOS transistor, and the first end of the driving transistor Td1 may be the source of the PMOS transistor and is coupled to the first system voltage terminal PVDD; the second end of the driving transistor Td1 may be the drain of the PMOS transistor and is coupled to the output terminal B; and the control terminal of the driving transistor Td1 may be the gate of the PMOS transistor and is coupled to the second end of the third transistor T1a. When both the pulse signal VP and the enabling signal S1 are at a high potential, the second transistor Tsw conducts, causing the voltage Vcm of the first control terminal C1 to be at a low potential, the third transistor T1a to be cut off, and the fourth transistor T2a to conduct. The voltage Vcm of the first control terminal C1 can be transmitted to the control terminal of the driving transistor Td1 through the conducting fourth transistor T2a, and the voltage VG1 of the control terminal of the driving transistor Td1 is equal to the voltage Vcm; thereby causing the driving transistor Td1 to conduct, and causing the driving unit 20a to output current to the electronic unit D1.When the enable signal S1 is at a low potential, the third transistor T1a is turned on, while the fourth transistor T2a is turned off. The voltage of the first system voltage terminal PVDD can be transmitted to the control terminal of the driving transistor Td1 through the turned-on third transistor T1a, such that the voltage VG1 at the control terminal of the driving transistor Td1 is equal to the voltage of the first system voltage terminal PVDD; thereby causing the driving transistor Td1 to be turned off and causing the driving unit 20a to stop outputting current to the electronic unit D1. In addition, Figure 1 VG2 therein is the voltage at the control terminal of the driving transistor Td2.

[0030] In an embodiment, the electronic device 10A may further include a current source 15, coupled between the second terminal of the second transistor Tsw and the second system voltage terminal PVSS, for providing a reference current Iref. When the enable signal S1 is at a high potential, the current source 15 and the driving unit 20a form a current mirror, and the ratio of the magnitude of the current output by the driving unit 20a to the electronic unit D1 to the reference current Iref is equal to the ratio of the channel width-length ratio of the driving transistor Td1 to the channel width-length ratio of the second transistor Tsw. Similarly, when the enable signal S2 is at a high potential, the current source 15 and the driving unit 20b form a current mirror, and the ratio of the magnitude of the current output by the driving unit 20b to the electronic unit D1 to the reference current Iref is equal to the ratio of the channel width-length ratio of the driving transistor Td2 to the channel width-length ratio of the second transistor Tsw. Among them, the driving transistors Td1 and Td2 may have different channel width-length ratios, and by combining with the potential control of the enable signals S1 and S2, the current Id flowing through the electronic unit D1 can be switched between different current magnitudes.

[0031] The pulse signal VP has a pulse width, and the current Id passing through the electronic unit D1 can be modulated according to the pulse width of the pulse signal VP. Please refer to Figure 1 and Figure 2 . Figure 2 For Figure 1Timing diagram of the signals and current Id of the electronic device 10A shown. The pulse signal VP has pulses P1, P2, P3, and P4 during time periods t1, t2, t3, and t4, respectively. Among them, the pulses P1, P2, P3, and P4 have pulse widths W1, W2, W3, and W4, respectively. During time periods t1 and t2, the driving transistor Td1 of the driving unit 20a is turned on, while the driving transistor Td2 of the driving unit 20b is turned off. In addition, during time periods t3 and t4, the driving transistor Td1 of the driving unit 20a is turned off, while the driving transistor Td2 of the driving unit 20b is turned on. In this embodiment, during time periods t1 and t2, the current Id is equal to I1; while during time periods t3 and t4, the current Id is equal to I2. Since the channel length-width ratio of the driving transistor Td1 is smaller than that of the driving transistor Td2, I1 is smaller than I2. In addition, the time lengths of time periods t1, t2, t3, and t4 are respectively equal to the pulse widths W1, W2, W3, and W4. Therefore, by making the pulse signal VP have different pulse widths, the time length of the current Id passing through the electronic unit D1 can be adjusted, and thus the light-emitting duration of the electronic unit D1 can be controlled. In addition, by controlling the potentials of the enable signals S1 and S2, the on states of the driving transistors Td1 and Td2 can be controlled, and thus the magnitude of the current Id passing through the electronic unit D1 can be controlled. When the current Id is larger, the light-emitting intensity of the electronic unit D1 is stronger.

[0032] Please refer to Figure 3 , Figure 3 is a circuit diagram of the electronic device 10B according to another embodiment of the present invention. The electronic device 10B includes a first transistor Tcm, a second transistor Tsw, a plurality of driving units 30a and 30b, and an electronic unit D1. Although this embodiment takes the electronic device 10B including two driving units 30a and 30b as an example, in other embodiments of the present invention, the electronic device 10B may include three or more driving units. The driving units 30a and 30b are connected in parallel with each other, and each of the driving units 30a and 30b includes an input terminal A, an output terminal B, a control terminal C, a data terminal D, and a memory unit 40a or 40b. Among them, the input terminal A is coupled to the first control terminal C1, the output terminal B is coupled to the node P, the data terminal D is used to receive the data signal Vdata, and the memory units 40a and 40b are used to store the voltage of the data signal Vdata. In addition, the control terminal C receives the enable signal. Among them, the control terminal C of the driving unit 30a receives the enable signal S1, and the control terminal C of the driving unit 30b receives the enable signal S2. Furthermore, each driving unit may further include a third transistor, a fourth transistor, and a driving transistor. For example: the driving unit 30a may further include a third transistor T1a, a fourth transistor T2a, and a driving transistor Td1, and the driving unit 30b may further include a third transistor T1b, a fourth transistor T2b, and a driving transistor Td2.

[0033] The circuit architectures of the driving unit 30a and the driving unit 30b are the same, and the circuit architectures of the memory unit 40a and the memory unit 40b are the same. Therefore, the following description will be based on the circuit architectures of the driving unit 30a and the memory unit 40a, and the circuit architectures of the driving unit 30b and the memory unit 40b can be analogized therefrom. The third transistor T1a can be a PMOS transistor, and the first end of the third transistor T1a can be the source of the PMOS transistor and is coupled to the first system voltage terminal PVDD; the second end of the third transistor T1a can be the drain of the PMOS transistor; and the control end of the third transistor T1a can be the gate of the PMOS transistor and is used to receive the voltage VE1. The fourth transistor T2a can be an NMOS transistor, and the first end of the fourth transistor T2a is coupled to the input terminal A; the second end of the fourth transistor T2a is coupled to the second end of the third transistor T1a; and the control end of the fourth transistor T2a can be the gate of the NMOS transistor and is used to receive the voltage VE1. The driving transistor Td1 can be a PMOS transistor, and the first end of the driving transistor Td1 can be the source of the PMOS transistor and is coupled to the first system voltage terminal PVDD; the second end of the driving transistor Td1 can be the drain of the PMOS transistor and is coupled to the output terminal B; and the control end of the driving transistor Td1 can be the gate of the PMOS transistor and is coupled to the second end of the third transistor T1a. The memory unit 40a can include a storage capacitor Cst and a data transistor T3a. The storage capacitor Cst is coupled between the first system voltage terminal PVDD and the gate of the third transistor T1a. The first end of the data transistor T3a is coupled to the data terminal D, the second end of the data transistor T3a is coupled to the storage capacitor Cst, and the control end of the data transistor T3a is used to receive the enable signal S1.

[0034] When both the pulse signal VP and the enable signal S1 are at a high potential, the second transistor Tsw conducts, causing the voltage Vcm at the first control terminal C1 to be at a low potential. The data transistor T3a conducts, and the data signal Vdata is transmitted through the conducting data transistor T3a to the gate of the third transistor T1a, causing the third transistor T1a to turn off and the fourth transistor T2a to conduct. In this way, the voltage Vcm at the first control terminal C1 can be transmitted to the control terminal of the driving transistor Td1 through the conducting fourth transistor T2a, making the voltage VG1 at the control terminal of the driving transistor Td1 equal to the voltage Vcm. Consequently, the driving transistor Td1 conducts, and the driving unit 30a outputs current to the electronic unit D1. When the enable signal S1 is at a low potential, the data transistor T3a turns off. Since the storage capacitor Cst stores the voltage of the data signal Vdata, the third transistor T1a and the fourth transistor T2a remain in their original states. In other words, when the enable signal S1 switches from a high potential to a low potential, if the third transistor T1a and the fourth transistor T2a are respectively in the conducting state and the off state, the third transistor T1a and the fourth transistor T2a will respectively remain in the conducting state and the off state; if the third transistor T1a and the fourth transistor T2a are respectively in the off state and the conducting state, the third transistor T1a and the fourth transistor T2a will respectively remain in the off state and the conducting state. When the third transistor T1a conducts and the fourth transistor T2a turns off, the voltage of the first system voltage terminal PVDD can be transmitted to the control terminal of the driving transistor Td1 through the conducting third transistor T1a, making the voltage VG1 at the control terminal of the driving transistor Td1 equal to the voltage of the first system voltage terminal PVDD. Consequently, the driving transistor Td1 turns off, and the driving unit 30a stops outputting current to the electronic unit D1. In this embodiment, the pulse signal VP can also have different pulse widths to adjust the time length of the current Id passing through the electronic unit D1, thereby controlling the light-emitting duration of the electronic unit D1. In addition, by controlling the potentials of the enable signals S1 and S2, the conducting states of the driving transistors Td1 and Td2 can be controlled, thereby controlling the magnitude of the current Id passing through the electronic unit D1.

[0035] In one embodiment, the electronic device 10B may further include a current source 15, coupled between the second terminal of the second transistor Tsw and the second system voltage terminal PVSS, for providing a reference current Iref. When the driving transistor Td1 conducts, the current source 15 and the driving unit 30a form a current mirror. Similarly, when the driving transistor Td2 conducts, the current source 15 and the driving unit 30b form a current mirror. Among them, the driving transistors Td1 and Td2 can have different channel length-width ratios. Together with the potential control of the enable signals S1 and S2, the current Id flowing through the electronic unit D1 can be switched between different current magnitudes.

[0036] Please refer to Figure 3 and Figure 4 . Figure 4 The Figure 3 timing diagrams of the signals and current Id of the electronic device 10B shown. The pulse signal VP has pulses P1 and P2 in time periods t1 and t2 respectively. Among them, the pulses P1 and P2 have pulse widths W1 and W2 respectively. In time period t1, the voltages VE1 and VE2 are at high potential and low potential respectively, so that the driving transistor Td1 is turned on and the driving transistor Td2 is turned off. In addition, in time period t2, the voltages VE1 and VE2 are at low potential and high potential respectively, so that the driving transistor Td1 is turned off and the driving transistor Td2 is turned on. In this embodiment, in time period t1, the current Id is equal to I1; and in time period t2, the current Id is equal to I2. Since the channel aspect ratio of the driving transistor Td1 is smaller than that of the driving transistor Td2, I1 is smaller than I2. In addition, the time lengths of time periods t1 and t2 are respectively equal to the pulse widths W1 and W2. Therefore, by making the pulse signal VP have different pulse widths, the time length of the current Id passing through the electronic unit D1 can be adjusted, thereby controlling the light emitting duration of the electronic unit D1. In addition, by controlling the potentials of the enable signals S1 and S2, the on states of the driving transistors Td1 and Td2 can be controlled, thereby controlling the magnitude of the current Id passing through the electronic unit D1.

[0037] The above-mentioned memory unit may include a storage capacitor and a data transistor. In other embodiments, the memory unit of the electronic device may include two data transistors and two inverters. Please refer to Figure 5 , Figure 5 which is the circuit diagram of the memory unit 40c of the electronic device according to another embodiment of the present invention. The memory unit 40c can be used to replace Figure 3 the memory unit 40a and / or the memory unit 40b in Figure 3 The enable signal Sn can be the Figure 3The voltage VE1 or the voltage VE2 therein. The first end of the second data transistor T4 is coupled to the second end of the first data transistor T3, and the control end of the second data transistor T4 is used to receive the enable signal Sn. The input end of the first inverter 42 is coupled to the second end of the first data transistor T3, the output end of the first inverter 42 is coupled to the input end of the second inverter 44, and the output end of the second inverter 44 is coupled to the second end of the second data transistor T4. The first inverter 42 and the second inverter 44 form a latch circuit for storing the data of the data signal Vdata.

[0038] Please refer to Figure 6 。 Figure 6 It is a circuit diagram of the electronic device 10C according to another embodiment of the present invention. The electronic device 10C includes a first transistor Tcm, a second transistor Tsw, a driving transistor Td, and an electronic unit D1. The first transistor Tcm can be a PMOS transistor, which includes a first end E1 and a first control end C1. The first end E1 can be the source of the first transistor Tcm, and the first control end C1 can be the gate of the first transistor Tcm. The second transistor Tsw can be an NMOS transistor, which includes a second control end C2, and the second control end C2 can be the gate of the second transistor Tsw, coupled to the first end E1 and used to receive the pulse signal VP. In addition, the first end of the second transistor Tsw can be the drain of the NMOS transistor and is coupled to the first control end C1; and the second end of the second transistor Tsw can be the source of the NMOS transistor and is coupled to the second system voltage terminal PVSS. The driving transistor Td can be a PMOS transistor, which includes a third control end C3, and the third control end C3 can be the gate of the driving transistor Td and is coupled to the first control end C1.

[0039] When the pulse signal VP is at a high level, the second transistor Tsw is turned on, and the voltage VG of the first control end C1 becomes a low level, thereby turning on the first transistor Tcm and the driving transistor Td. In this case, the current Id flows through the electronic unit D1. Additionally, when the pulse signal VP is at a low level, the second transistor Tsw is turned off, and the voltage VG of the first control end C1 becomes a high level, thereby turning off the first transistor Tcm and the driving transistor Td. In this case, the current Id is equal to zero.

[0040] The electronic device 10C may further include a third transistor T1 and a current source 15. The third transistor T1 can be a PMOS transistor. The first end of the third transistor T1 is coupled to the first system voltage terminal PVDD, the second end of the third transistor T1 is coupled to the first control end C1, and the control end of the third transistor T1 is coupled to the first end E1 of the first transistor Tcm. The current source 15 is coupled between the second end of the second transistor Tsw and the second system voltage terminal PVSS to provide a reference current Iref.

[0041] The magnitude and time of the current Id passing through the electronic unit D1 can be modulated according to the pulse amplitude and pulse width of the pulse signal VP, respectively. Please refer to Figure 6 and Figure 7 . Figure 7 is Figure 6 the timing diagram of the signal of the electronic device 10C and the current Id shown. The pulse signal VP has pulses P1, P2, P3, P4, P5, and P6 during time periods t1, t2, t3, t4, t5, and t6, respectively. Among them, the pulses P1, P2, P3, P4, P5, and P6 have pulse widths W1, W2, W3, W4, W5, and W6, respectively, and the time lengths of the time periods t1, t2, t3, t4, t5, and t6 are equal to the pulse widths W1, W2, W3, W4, W5, and W6, respectively. In addition, when the pulse signal VP has a larger pulse amplitude, the corresponding voltage VG will be higher, and the corresponding current Id will be smaller, as Figure 7 shown. Among them, the current I1 is less than the current I2, the current I2 is less than the current I3, the pulse amplitudes of the pulses P1 and P2 are greater than the pulse amplitudes of the pulses P3 and P4, and the pulse amplitudes of the pulses P3 and P4 are greater than the pulse amplitudes of the pulses P5 and P6.

[0042] Please refer to Figure 8 . Figure 8 is the circuit diagram of the electronic device 10D according to another embodiment of the present invention. The circuit of the electronic device 10D is similar to the circuit of the Figure 6 electronic device 10C, and the difference between the two is that the electronic device 10D includes a plurality of electronic units (such as D1 to Dn) and a plurality of switching transistors Q1 to Qn. As Figure 8As shown, the electronic device 10D also includes a first transistor Tcm, a second transistor Tsw, a third transistor T1, a driving transistor Td, and a current source 15. In addition, the electronic device 10D further includes a plurality of light-emitting units 80a to 80n, and each of the light-emitting units 80a to 80n includes an electronic unit and a switching transistor. For example, the light-emitting unit 80a includes an electronic unit D1 and a switching transistor Q1, and the light-emitting unit 80n includes an electronic unit Dn and a switching transistor Qn. Each switching transistor can be a PMOS transistor, and its gate serves as a control terminal for receiving a corresponding switching signal (for example: EM1 and EMn). Taking the light-emitting unit 80a as an example, when the switching signal EM1 is at a high potential, the switching transistor Q1 is turned off, so that no current passes through the electronic unit D1; when the driving transistor Td is turned on and the switching signal EM1 is at a low potential, the switching transistor Q1 is turned on, so that current can flow from the first system voltage terminal PVDD, sequentially through the driving transistor Td and the transistor Q1, and then through the electronic unit D1. Similarly, when the switching signal EMn is at a high potential, the switching transistor Qn is turned off, so that no current passes through the electronic unit Dn; when the driving transistor Td is turned on and the switching signal EMn is at a low potential, the switching transistor Qn is turned on, so that current can flow from the first system voltage terminal PVDD, sequentially through the driving transistor Td and the transistor Qn, and then through the electronic unit Dn. Among them, the magnitude and time of the current passing through the electronic unit D1 are also modulated according to the pulse amplitude and pulse width of the pulse signal VP, respectively. Similarly, the magnitude and time of the current passing through the electronic unit Dn are also modulated according to the pulse amplitude and the pulse width of the pulse signal VP, respectively. In addition, Figure 8 VF1 and VFn in it respectively represent the voltages at one end of the electronic unit D1 and the electronic unit Dn.

[0043] In the above embodiments of the present invention, the pulse signal VP is modulated by Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) techniques. Therefore, for an LED display, according to the gray scale of each pixel of the display, the corresponding pulse signal VP can be subjected to PAM and / or PWM modulation, so that the magnitude and time of the current flowing through each electronic unit (such as: D1, Dn) can better meet the needs of each electronic unit.

[0044] The above description is only for the embodiments of the present invention and is not intended to limit the present invention. For those of ordinary skill in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An electronic device, characterized in that, The electronic device includes: A first transistor including a first control terminal; A second transistor coupled to the first transistor and including a second control terminal for receiving a pulse signal having a pulse width; A plurality of driving units connected in parallel with each other, each driving unit including an input terminal, an output terminal, and a control terminal, the input terminal being coupled to the first control terminal, the output terminal being coupled to a node, and the control terminal receiving an enabling signal; and An electronic unit coupled to the node; Wherein, the plurality of driving units respectively provide current to the electronic unit according to the received enabling signals, and the current passing through the electronic unit is modulated according to the pulse width of the pulse signal.

2. The electronic device according to claim 1, wherein Each of the driving units further includes: A third transistor including: A first terminal coupled to a first system voltage terminal; A second terminal; and A control terminal for receiving the enabling signal; A fourth transistor including: A first terminal coupled to the input terminal; A second terminal coupled to the second terminal of the third transistor; and A control terminal for receiving the enabling signal; and A driving transistor including: A first terminal coupled to the first system voltage terminal; A second terminal coupled to the output terminal; and A control terminal coupled to the second terminal of the third transistor.

3. The electronic device according to claim 1, wherein Each of the driving units further includes a data terminal and a memory unit, the data terminal being used for receiving a data signal, and the memory unit being used for storing the voltage of the data signal.

4. The electronic device according to claim 3, wherein The memory unit includes: A storage capacitor having a first terminal coupled to the first system voltage terminal; and A data transistor including: A first terminal coupled to the data terminal; A second terminal coupled to the second terminal of the storage capacitor; and A control terminal for receiving the enabling signal.

5. The electronic device according to claim 4, wherein Each of the driving units further includes: A third transistor including: A first terminal coupled to the first system voltage terminal; A second terminal; and A control terminal coupled to the second terminal of the data transistor; A fourth transistor including: A first terminal coupled to the input terminal; A second terminal coupled to the second terminal of the third transistor; and A control terminal coupled to the second terminal of the data transistor; and A driving transistor including: A first terminal coupled to the first system voltage terminal; A second terminal coupled to the output terminal; and A control terminal coupled to the second terminal of the third transistor.

6. The electronic device according to claim 3, characterized in that The memory unit includes: A first data transistor including: A first terminal coupled to the data terminal; A second terminal; and A control terminal for receiving the enabling signal; A second data transistor including: A first terminal coupled to the second terminal of the first data transistor; A second terminal; and A control terminal for receiving the enabling signal; A first inverter having an input terminal coupled to the second terminal of the first data transistor; and A second inverter, an input terminal of the second inverter being coupled to an output terminal of the first inverter, and an output terminal of the second inverter being coupled to the second terminal of the second data transistor.

7. The electronic device according to claim 6, wherein, Each of the driving units further includes: A third transistor including: A first terminal coupled to the first system voltage terminal; A second terminal; and A control terminal coupled to the second terminal of the first data transistor; A fourth transistor including: A first terminal coupled to the input terminal of each driving unit; a second terminal coupled to the second terminal of the third transistor; and a control terminal coupled to the second terminal of the first data transistor; and a driving transistor, comprising: a first terminal coupled to the first system voltage terminal; a second terminal coupled to the output terminal of each driving unit; and a control terminal coupled to the second terminal of the third transistor.

8. The electronic device according to claim 1, characterized in that, The electronic device further includes a current source coupled to the second terminal of the second transistor.

9. An electronic device, characterized in that, The electronic device includes: a first transistor including a first terminal and a first control terminal; a second transistor including a second control terminal coupled to the first terminal and configured to receive a pulse signal having a pulse width and a pulse amplitude; a driving transistor including a third control terminal coupled to the first control terminal; and a first electronic unit coupled to the driving transistor; wherein the magnitude and time of the current through the first electronic unit are modulated according to the pulse amplitude and the pulse width, respectively.

10. The electronic device according to claim 9, wherein The electronic device further includes: a third transistor, comprising: a first terminal coupled to a first system voltage terminal; a second terminal coupled to the first control terminal; and a control terminal coupled to the first terminal of the first transistor; and a current source coupled to the second terminal of the second transistor.

11. The electronic device according to claim 9, wherein The electronic device further includes: a first switching transistor coupled between the driving transistor and the first electronic unit; a second electronic unit; and a second switching transistor coupled between the driving transistor and the second electronic unit; wherein the magnitude and time of the current through the second electronic unit are modulated according to the pulse amplitude and the pulse width, respectively.

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