Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a pixel circuit, a data line, a first fixed potential signal line, a first scanning line, a second scanning line and a light-emitting element, wherein the pixel circuit comprises a driving transistor, a data write-in transistor, a first switch tube, a second switch tube and a first capacitor. A first electrode of the data write-in transistor is electrically connected with a data line and a first electrode of the first switch tube, a second electrode of the first switch tube is electrically connected with the first capacitor and a first electrode of the second switch tube, and the second switch tube and a second electrode of the data write-in transistor are electrically connected with a first electrode or a second electrode of the driving transistor. The data write-in transistor and the grid of the first switch tube are electrically connected with a first scanning line, and the grid of the second switch tube is electrically connected with a second scanning line. In the same display stage, the enable level period of the second scanning signal is behind the enable level period of the first scanning signal. By adopting the pixel circuit, the display uniformity of the display panel can be higher, and the display effect is better.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies, display panels have been increasingly widely used in devices such as mobile phones, computers, in-vehicle display panels, or wearable devices due to advantages such as low driving voltage, high luminous efficiency, fast response speed, light weight, and thinness.

[0003] However, the current display effect of display panels is not ideal and it is difficult to meet the user's demand for high-quality displays. Summary of the Invention

[0004] Based on this, it is necessary to provide a display panel and a display device that can improve the display effect of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including a pixel circuit, a data line, a first fixed-potential signal line, a first scan line, a second scan line, and a light-emitting element. The pixel circuit includes a driving transistor, a data-writing transistor, a first switching transistor, a second switching transistor, and a first capacitor. Among them, a first pole of the data-writing transistor is electrically connected to the data line and a first pole of the first switching transistor; a second pole of the first switching transistor is electrically connected to a first pole of the first capacitor and a first pole of the second switching transistor; a second pole of the second switching transistor and a second pole of the data-writing transistor are electrically connected to a first pole of the driving transistor or to a second pole of the driving transistor; a second pole of the first capacitor is electrically connected to the first fixed-potential signal line; a gate of the data-writing transistor and a gate of the first switching transistor are electrically connected to the first scan line; a gate of the second switching transistor is electrically connected to the second scan line; a first pole of the driving transistor is electrically connected to the first fixed-potential signal line; a second pole of the driving transistor is electrically connected to the light-emitting element;

[0006] In the same display stage, a period of the second scan signal with an enabling level accessed by the second scan line is located after a period of the first scan signal with an enabling level accessed by the first scan line.

[0007] In a second aspect, an embodiment of the present application further provides a display device, and the display device includes the display panel provided in the first aspect.

[0008] In the display panel provided by the embodiment of the present application, in the same display stage, when the first scan signal is at the enabled level period, on the one hand, the data signal transmitted by the data line is written into the driving transistor through the data writing transistor, and on the other hand, it is written into the first capacitor through the first switching transistor. The first capacitor stores the voltage value corresponding to the data signal. When the second scan signal is at the enabled level period, the data signal stored in the first capacitor biases and resets the driving transistor through the second switching transistor, so that the bias state of the driving transistor can be adjusted, and the characteristics of the driving transistor can be improved. Moreover, the bias reset signal for biasing and resetting the driving transistor is the same as the data signal written into the driving transistor, so that the voltage for biasing and resetting the driving transistor is not affected by the data signals of other row pixel circuits, thereby making the driving current input to the light-emitting element more stable. Therefore, the display uniformity of the display panel can be higher, and the display effect can be better. Description of the Drawings

[0009] Figure 1 is a schematic circuit diagram of a pixel circuit in the related art;

[0010] Figure 2 is a schematic diagram of the display state of a display panel in the related art;

[0011] Figure 3 is a schematic circuit diagram of a pixel circuit provided by an embodiment of the present application;

[0012] Figure 4 is a schematic circuit diagram of a pixel circuit provided by another embodiment of the present application;

[0013] Figure 5 is a schematic signal timing diagram of a display panel provided by an embodiment of the present application;

[0014] Figure 6 is a schematic signal timing diagram of a display panel in the related art;

[0015] Figure 7 is a schematic diagram of the display state of a display panel provided by an embodiment of the present application;

[0016] Figure 8 is a schematic structural diagram of a display device provided by an embodiment of the present application. Detailed Embodiments

[0017] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure content of the present application more thorough and comprehensive.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0019] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more intervening elements. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can also be one or more intervening elements.

[0020] In the case of using "comprising", "having", and "including" as described herein, unless explicit limiting terms are used, such as "only", "consisting of", etc., another component can also be added. Unless otherwise mentioned, terms in the singular form can include the plural form and should not be construed as having a quantity of one.

[0021] It should be understood that although terms such as "first" and "second" can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.

[0022] It should also be understood that when interpreting an element, although not explicitly described, the element is interpreted as including an error range, and this error range should be within the acceptable deviation range of a specific value determined by those skilled in the art. For example, "about", "approximate", or "substantially" can mean within one or more standard deviations, which is not limited herein.

[0023] In addition, in the specification, the phrase "schematic diagram of planar distribution" refers to the drawing when observing the target part from above, and the phrase "schematic cross-sectional diagram" refers to the drawing when observing the cross-section intercepted by vertically cutting the target part from the side.

[0024] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the various elements are only drawn by way of example in the drawings and not necessarily to the true scale.

[0025] As described in the background art section, in the related art, there are problems with the display effect of the display screen of the display panel. The inventor's research found that the reason for the above phenomenon is that during the bias reset process of the driving transistor in the pixel circuit, there is a voltage difference between the bias reset signal and the data signal to be displayed currently, resulting in inaccurate driving current input to the light-emitting device, affecting the light-emitting brightness of the light-emitting device, and ultimately causing poor display uniformity and unsatisfactory display effect.

[0026] Specifically, taking the Figure 1 shown pixel circuit as an example, the data signal Data1 is written into the gate of the driving transistor M2 through the transistor M1 and stored in the capacitor C1. The driving transistor M2 generates a driving current according to the data signal Data1 to drive the light-emitting device D1 to emit light. However, since the potential of node A cannot be stably maintained (such as due to factors like leakage current), and the voltage of node B is the applied power supply voltage, the voltage difference between the gate and the source of the driving transistor M2 has a forward bias. Being in the forward bias state for a long time will cause the characteristics of the driving transistor M2 to change, thus easily resulting in problems with unreliable display.

[0027] To adjust this bias state, in the related art, usually the transistor M1 introduces a bias reset signal to node B for bias adjustment to improve the characteristics of the driving transistor M2. However, in actual applications, the introduced bias reset signal is often the data signal (such as DataN) to be displayed by the pixel circuit in the Nth row (such as the 7th row, the 8th row, etc.) below the current pixel circuit. When there is a voltage difference between DataN and the data signal Data1 of the current pixel circuit, the voltage of DataN will affect the driving current transmitted to the light-emitting device D1 through node C, and further affect the light-emitting brightness of the light-emitting device D1.

[0028] Taking Figure 2For example, in the display panel, area 1 displays a gray screen (such as gray32), and area 2 displays a black block (such as gray0). At this time, there will be a phenomenon that the picture in the Radius corner area below the panel becomes abnormally bright, and there will be an abnormally bright transition area 11 between area 1 and area 2, affecting the display uniformity. The inventor's research found that this is because in the pixel circuit corresponding to the transition area 11, the data signal of gray32 is written to the gate of the write driving transistor M2, but the bias reset signal introduced into node B is the data signal of gray0. Since the voltage of the data signal of gray0 is higher than that of the data signal of gray32, this signal will raise the voltages of both node B and node C at the same time. The increase in the voltage of node C causes the anode voltage of the light-emitting device D1 to increase, thereby increasing the driving current input to the light-emitting device D1, resulting in the brightness of the light-emitting device D1 being higher than expected. Therefore, the picture in the transition area 11 becomes abnormally bright, showing a bright band phenomenon. And the R corner area usually undergoes "black insertion" processing to improve the display effect of the R corner. Therefore, similar to the transition area 11, the R corner area below the panel will also show abnormal brightness. Especially at low brightness, the abnormal brightness phenomenon is more obvious, seriously affecting the display effect.

[0029] Based on the above technical problems, the inventors further studied and found that by biasing and resetting the driving transistor with the same data signal as the gate of the writing driving transistor, the R corner and the problem of abnormal brightening in the transition region can be improved, and the display effect can be enhanced. Based on this, the inventors developed the technical solution of the embodiments of the present application. Specifically, the display panel provided by the embodiments of the present application includes a pixel circuit, a data line, a first fixed potential signal line, a first scan line, a second scan line, and a light-emitting element. The pixel circuit includes a driving transistor, a data writing transistor, a first switching transistor, a second switching transistor, and a first capacitor. Among them, the first pole of the data writing transistor is electrically connected to the data line and the first pole of the first switching transistor. The second pole of the data writing transistor is electrically connected to the first pole or the second pole of the driving transistor. The second pole of the first switching transistor is electrically connected to the first pole of the first capacitor and the first pole of the second switching transistor. The second pole of the second switching transistor is electrically connected to the first pole or the second pole of the driving transistor. The second pole of the first capacitor is electrically connected to the first fixed potential signal line. The gates of the data writing transistor and the first switching transistor are electrically connected to the first scan line. The gate of the second switching transistor is electrically connected to the second scan line. The first pole of the driving transistor is connected to the first fixed potential signal line, and the second pole of the driving transistor is electrically connected to the light-emitting element. In the same display stage, the enabling period of the second scan signal applied to the second scan line is after the enabling period of the first scan signal applied to the first scan line. By adopting the above technical solution, by biasing and resetting the driving transistor with the data signal of the writing driving transistor, the voltage of the driving transistor can be made not affected by the data signals of the pixel circuits of other rows, so that the driving current input to the light-emitting element is more stable, and the display uniformity of the display panel is higher and the display effect is better.

[0030] The above is the core idea of the present application. Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0031] Figure 3 It is a schematic circuit diagram of a display panel provided by an embodiment of the present application. Figure 4 It is another schematic circuit diagram of a display panel provided by an embodiment of the present application. As shown in Figure 3 - Figure 4 The display panel provided by the embodiments of the present application includes a pixel circuit 100, a data line for accessing a data signal Vdata, a first fixed potential signal line for accessing a first fixed potential signal PVDD, a first scan line for accessing a first scan signal S1P, a second scan line for accessing a second scan signal S2P, and a light-emitting element D.

[0032] Among them, the pixel circuit 100 includes a driving transistor T1, a data writing transistor T2, a first switching transistor T3, a second switching transistor T4, and a first capacitor Cst1.

[0033] Among them, each transistor can be a thin film transistor (TFT), for example, it can be a low temperature poly-silicon transistor (LTPS) or a low temperature polycrystalline oxide transistor (LTPO). The first pole and the second pole of each transistor need to be determined according to the specific type of the TFT transistor. Exemplarily, the source electrode of each transistor is the first pole, and the drain electrode is the second pole.

[0034] The first pole of the data writing transistor T2 is electrically connected to the data line and the first pole of the first switching transistor T3. The second pole of the first switching transistor T3 is electrically connected to the first pole of the first capacitor Cst1 and the first pole of the second switching transistor T4. The second pole of the first capacitor Cst1 is electrically connected to the first fixed potential signal line. The gates of the data writing transistor T2 and the first switching transistor T3 are electrically connected to the first scanning line, and the gate of the second switching transistor T4 is electrically connected to the second scanning line; the first pole of the driving transistor T1 is used to be electrically connected to the first fixed potential signal line, and the second pole of the driving transistor T1 is electrically connected to the light-emitting element D.

[0035] In the embodiment of the present application, the connection manner between the second pole of the second switching transistor T4 and the data writing transistor T2 and the driving transistor T1 is relatively flexible. As an example, please refer to Figure 3 , the second pole of the second switching transistor T4 and the second pole of the data writing transistor T2 are electrically connected to the first pole of the driving transistor T1.

[0036] In the same display stage, the enabling level time period of the second scanning signal S2P accessed by the second scanning line is located after the enabling level time period of the first scanning signal S1P accessed by the first scanning line.

[0037] The enabling level time period refers to the time interval during which the enabling level exists. During this time period, the controlled transistor remains in the on state and allows current to pass through.

[0038] In actual implementation, each signal including the first scan signal S1P and the second scan signal S2P has a high-level state and a low-level state, and one of the level states is the enable level, and the other level state is the non-enable level, which specifically needs to be determined according to the type of transistor to be controlled (such as N-type or P-type). As an example, the data writing transistor T2, the first switching transistor T3, and the second switching transistor T4 are all P-type transistors, and the enable level of the first scan signal S1P and the second scan signal S2P is the low level. When the first scan signal S1P is at the enable level, the data writing transistor T2 and the first switching transistor T3 are in the conducting state, thereby allowing current to flow between the first pole and the second pole. When the first scan signal S1P is at the non-enable level, the data writing transistor T2 and the first switching transistor T3 change to the off state. When the second scan signal S2P is at the enable level, the second switching transistor T4 is in the conducting state. When the second scan signal S2P is at the non-enable level, the second switching transistor T4 is in the off state. For the convenience of explanation, the following takes the data writing transistor T2, the first switching transistor T3, and the second switching transistor T4 being all P-type transistors as an example for illustration.

[0039] The driving period of the display panel includes a refresh frame and a hold frame. The function of the refresh frame is to update the data of the pixels on the display panel, and the function of the hold frame is to maintain the display state of the pixels between two refreshes so that the image can be stably presented.

[0040] The same display stage refers to the refresh frame of the same driving period or the hold frame of the same driving period. Among them, the refresh frame may include a data writing stage, a bias reset stage, and a light emitting stage. As Figure 5 shown, in the data writing stage t2, the first scan signal S1P is at the enable level. In this stage, the data signal Vdata transmitted by the data line is transmitted to the first pole of the driving transistor T1 through the data writing transistor T2 to write the data signal Vdata transmitted by the data writing transistor T2 into the gate. On the other hand, the data signal Vdata transmitted by the data line is written into the first capacitor Cst1 through the first switching transistor T3, and the first capacitor Cst1 stores the voltage value corresponding to the data signal Vdata.

[0041] In the bias reset stage t4, the second scan signal S2P is at the enable level. The data signal Vdata stored in the first capacitor Cst1 biases and resets the first pole of the driving transistor T1 through the second switching transistor T4, so that the driving transistor T1 is in the on-bias (OBS) state, improving the forward bias between the source and gate potentials of the driving transistor T1 to improve the characteristics of the driving transistor T1.

[0042] During the light-emitting stage, the driving transistor T1 generates a driving current according to the data signal Vdata to drive the light-emitting element D to emit light. The light-emitting element D can be a light-emitting diode, such as an organic light-emitting diode (OLED). The second pole of the driving transistor T1 is connected to the anode of the light-emitting element D, and the cathode of the light-emitting element D is connected to a second fixed-potential signal line for accessing the second fixed-potential signal PVEE.

[0043] In summary, for the display panel provided in the embodiment of the present application, during the refresh frame, when the first scan signal S1P is at the enabled level period, the data signal Vdata transmitted by the data line is written into the driving transistor T1 through the data writing transistor T2 on the one hand, and written into the first capacitor Cst1 through the first switch transistor T3 on the other hand. The first capacitor Cst1 stores the voltage value corresponding to the data signal Vdata. When the second scan signal S2P is at the enabled level period, the data signal Vdata stored in the first capacitor Cst1 biases and resets the driving transistor T1 through the second switch T9, so that the bias state of the driving transistor T1 can be adjusted, and the characteristics of the driving transistor T1 can be improved. Moreover, the data signal Vdata used for the bias reset is the same as the data signal Vdata written into the driving transistor T1, which can make the voltage of the driving transistor T1 not affected by the data signals of other row pixel circuits, and further make the potential of the anode of the light-emitting device D more stable and the driving current transmitted to the light-emitting element D more stable. Therefore, the display uniformity of the display panel can be higher and the display effect can be better.

[0044] It should also be noted that in the related art, the first pole of the driving transistor T1 is also electrically connected to a fixed voltage signal line to introduce a fixed voltage signal to bias and reset the driving transistor T1. However, this method of introducing a fixed voltage through the fixed voltage signal line will increase the load of the display panel, thus increasing power consumption. In the embodiment of the present application, by saving the data signal Vdata written into the driving transistor T1 and using the data signal Vdata to bias and reset the driving transistor T1, it is not necessary to consume a fixed voltage signal, which can reduce the power consumption of the display panel.

[0045] Specifically, when the first scan signal S1P applied to the first scan line is at the enabled level period, the first switch transistor T3 is turned on and the second switch transistor T4 is turned off, and the data signal Vdata applied to the data line is written into the first capacitor Cst1. When the second scan signal S2P applied to the second scan line is at the enabled level period, the first switch transistor T3 is turned off and the second switch transistor T4 is turned on, and the data signal Vdata stored in the first capacitor biases and resets the driving transistor T1.

[0046] As Figure 5As shown, the bias reset stage t4 in the same display stage is located after the data writing stage t2. In the data writing stage t2, the first scan signal S1P is at the enable level, the first switching transistor T3 is turned on, and the second switching transistor T4 is in the off state because the second scan signal S2P is at the non-enable level. In this way, the data signal Vdata accessed by the data line can be stored in the first capacitor Cst1. When the enable level period of the first scan signal S1P ends, the first switching transistor T3 is turned off, cutting off the signal transmission path between the data line and the first capacitor Cst1.

[0047] In the bias reset stage t4, the second scan signal S2P is converted to the enable level, the second switching transistor T4 is turned on, and the data signal Vdata stored in the first capacitor Cst1 is transmitted through the second switching transistor T4 to the first pole of the driving transistor T1 to perform a bias reset on the driving transistor T1.

[0048] In this embodiment, in the data writing stage t2, the data signal Vdata is written into the first capacitor Cst1 and stored by the first capacitor Cst1. In the bias reset stage, the data signal Vdata stored in the first capacitor Cst1 performs a bias reset on the driving transistor T1. Thus, the voltage of the anode of the light-emitting element D can be made more stable through the driving transistor T1, and further, the driving current flowing into the light-emitting device D can be made more stable, thereby improving the display uniformity and the display effect of the panel is better.

[0049] It can be understood that the connection manner of the second pole of the second switching transistor T4 and the second pole of the data writing transistor T2 to the driving transistor T1 is relatively flexible and can be specifically determined according to the type of the driving transistor T1.

[0050] In some embodiments, please refer to Figure 4 , taking the driving transistor T1 as an N-type transistor as an example for illustration, the second pole of the data writing transistor T2 and the second pole of the second switching transistor T4 are electrically connected to the second pole of the driving transistor T1.

[0051] In this embodiment, in the data writing stage, the data signal Vdata is transmitted to the second pole of the driving transistor T1 and then to the gate of the driving transistor T1. In the bias reset stage t4, the data signal Vdata stored in the first capacitor Cst1 can be transmitted to the second pole of the driving transistor T1, effectively adjusting the bias state of the driving transistor T1 and improving the performance of the driving transistor T1. At the same time, the voltage of the node N3 can also be made more stable, so that the driving current flowing into the light-emitting device D is more stable and the light-emitting brightness of the light-emitting element D is more stable.

[0052] In some embodiments, such as Figure 3As shown, the driving transistor T1 is a P-type transistor, and the second pole of the data writing transistor T2, the second pole of the second switching transistor T4 are electrically connected to the first pole of the driving transistor T1.

[0053] In this embodiment, during the data writing stage, the data signal Vdata can be transmitted from the data writing transistor T2 to the first pole of the driving transistor T1, and then transmitted to the gate through the second pole of the driving transistor T1. During the bias reset stage t4, the data signal Vdata stored in the first capacitor Cst1 can effectively be transmitted to the first pole of the driving transistor T1 through the second switching transistor T4, realizing precise adjustment of the bias state of the driving transistor T1, and further making the voltage of the node N3 more stable. For ease of explanation, the following explanations are all given by taking the driving transistor T1 as a P-type transistor as an example.

[0054] In some embodiments, during the refresh frame, the first scan signal S1P is a single pulse signal, and the second scan signal S2P is a single pulse signal.

[0055] It should be noted that in the related art, during the same display stage, the scan signal of the transistor for controlling data writing is usually set to a signal including two pulses. The first pulse is used to write the data signal to the driving transistor, and the second pulse is used to perform bias reset on the driving transistor. Still taking Figure 1 - Figure 2 as an example, Figure 1 the pixel circuit shown is the pixel circuit corresponding to the transition region 11. Please refer to Figure 6 . During the same display stage, the scan signal SP for controlling the transistor M1 includes two effective pulses. Under the action of the first effective pulse, the transistor M1 is turned on to write the data signal of gray32 to the driving transistor M2. Under the action of the second effective pulse, the transistor M1 is turned on to write the data signal of gray0 to the first pole of the driving transistor M2 to perform bias reset on the driving transistor M2. Although this two-pulse timing control method can achieve bias reset, it will also bring problems such as abnormal brightening at the R corner and bright lines.

[0056] In this embodiment, still taking the display of gray (taking the data signal of gray32 as an example), during the refresh frame, the first scan signal S1P is a single pulse signal. When the first scan signal S1P is at the enabling level, the data signal of gray32 is written into the driving transistor T1 through the data writing transistor T2, and written into the first capacitor Cst1 through the first switching transistor T3. When the second scan signal S2P is at the enabling level, the first scan signal S1P is at the non-enabling level. At this time, the first switching transistor T3 is turned off, and the data signal of gray0 cannot be written. Therefore, the voltage of the node N2 or the node N3 written into the node N5, that is, Vdata （gray32）Thus, the potential of the anode of the light-emitting element D will not be affected by the data signals of other row pixel circuits, making the driving current writing of the light-emitting element D stable and preventing the abnormal increase of the driving current. As Figure 7 shown, adopting the solution of the embodiment of the present application can significantly improve the abnormal brightening and abnormal bright line conditions in the R corner area of the display panel, and the display uniformity is high.

[0057] In some embodiments, the pixel circuit further includes a second capacitor Cst2. Wherein, the first pole of the second capacitor Cst2 is electrically connected to the gate of the driving transistor T1, and the second pole of the second capacitor Cst2 is electrically connected to the first fixed potential signal line. The second capacitor Cst2 functions to store the data signal Vdata of the gate of the driving transistor T1, thereby making the gate voltage of the driving transistor T1 more stable, so that the driving current generated in the light-emitting stage is stable, so as to improve the display uniformity.

[0058] In some embodiments, the display panel further includes a third scan line for accessing the third scan signal S2N, and the pixel circuit 100 further includes a threshold compensation transistor T5. The first pole of the threshold compensation transistor T5 is electrically connected to the second pole of the driving transistor T1, the second pole of the threshold compensation transistor T5 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T5 is electrically connected to the third scan line.

[0059] In the refresh frame, the enabling period of the third scan signal S2N accessed by the third scan line overlaps with the enabling period of the first scan signal S1P and does not overlap with the enabling period of the second scan signal S2P.

[0060] It can be understood that the refresh frame further includes a threshold compensation stage t3, which is located before the bias reset stage t4 and overlaps with the data writing stage t2 in timing. Thus, in the data writing stage t2, when the first scan signal S1P is at the enabling level, the data writing transistor T2 is turned on, and when the data signal Vdata is written to the first pole (P-type transistor) or the second pole (N-type transistor) of the driving transistor T1, the third scan signal S2N is also at the enabling level, and the threshold compensation transistor T5 is turned on, and the data signal Vdata is transmitted to the gate of the driving transistor T1 through the threshold compensation transistor T5, realizing data writing and threshold compensation.

[0061] By setting the threshold compensation transistor T5, the threshold voltage of the driving transistor T1 can be compensated in the threshold compensation stage t3, improving the problem of uneven display brightness caused by the threshold voltage drift of the driving transistor T1 and improving the display quality of the display panel.

[0062] In this embodiment, by overlapping the enabling time period of the third scan signal S2N with the enabling time period of the first scan signal S1P, the threshold compensation stage t3 and the data writing stage t2 are partially overlapped in time sequence, enabling the conduction time periods of the threshold compensation transistor T5 and the data writing transistor T2 to overlap, accelerating the processes of threshold compensation and data writing, reducing the total duration of the refresh frame, and improving the display refresh efficiency.

[0063] By making the enabling time period of the third scan signal S2N non-overlap with the enabling time period of the second scan signal S2P, the threshold compensation and the bias reset can be made independent of each other, ensuring that each process can accurately complete its intended function and improving the reliability and stability of the pixel circuit operation.

[0064] In some embodiments, the start time of the enabling time period of the third scan signal S2N is earlier than the start time of the enabling time period of the first scan signal S1P, and the end time is later than the end time of the enabling time period of the first scan signal S1P. Thus, the data writing stage t2 is within the threshold compensation stage t3, ensuring that the threshold compensation transistor T5 is in the conducting state during the data writing stage t2, and the data signal Vdata can be stably transmitted to the gate of the driving transistor T1. Moreover, there is sufficient time to complete the compensation of the threshold voltage, improving the threshold compensation effect.

[0065] In some embodiments, as Figure 5 shown, during the holding frame, the third scan signal S2N maintains a non-enabling level.

[0066] The third scan signal S2N maintaining a non-enabling level can keep the threshold compensation transistor T5 in the off state, prevent charge leakage, and make the gate potential of the driving transistor T1 stable. Furthermore, the stable gate potential can improve the consistency of the driving current generated by the driving transistor T1 and enhance the stability of the holding frame display.

[0067] During the holding frame, the enabling time period of the second scan signal S2P is located after the enabling time period of the first scan signal S1P.

[0068] During the enabling time period of the first scan signal S1P, the data signal transmitted by the data line is transmitted to the first pole of the driving transistor T1 through the data writing transistor T2, starting the bias reset of the driving transistor T1. At the same time, the data signal transmitted by the data line is transmitted to the first capacitor Cst1 through the first switching transistor T3 and stored by the first capacitor Cst1. During the enabling time period of the second scan signal S2P, the second switching transistor T4 conducts, and the data signal stored in the first capacitor Cst1 adjusts the bias of the driving transistor T1. Thus, there is sufficient time to adjust the bias of the driving transistor T1 during the holding frame, which can effectively improve the characteristics of the driving transistor T1.

[0069] In some embodiments, in the hold frame, the voltage of the data signal accessed by the data line is a constant voltage. By applying a constant voltage to adjust the bias state of the driving transistor T1, problems such as unstable display caused by the forward bias state of the driving transistor T1 can be improved, so that the display states of the hold frame and the refresh frame are consistent.

[0070] Furthermore, the voltage of the data signal accessed by the data line in the hold frame is greater than the voltage of the data signal accessed by the data line in the refresh frame.

[0071] Increasing the voltage of the signal for bias reset in the hold frame can further adjust the bias state of the driving transistor T1, which helps to improve the display effect.

[0072] In some embodiments, both the refresh frame and the hold frame include a non-emitting stage and an emitting stage, and the enabling level period of the first scan signal and the enabling level period of the second scan signal overlap with the non-emitting stage.

[0073] Specifically, the refresh frame includes a non-emitting stage and an emitting stage. In these two stages, the enabling level period of the first scan signal S1P and the enabling level period of the second scan signal S2P both overlap with the non-emitting stage and do not overlap with the emitting stage.

[0074] In this embodiment, by separating the emitting stage and the non-emitting stage, the data writing and bias adjustment processes can be prevented from interfering with the normal light-emitting display, and the brightness fluctuation or screen flicker phenomenon caused by the overlapping of operations can be avoided. Moreover, the bias adjustment is performed in the non-emitting stage, so that the driving transistor T1 can maintain a good driving state in the emitting stage.

[0075] It can be understood that the display panel further includes a light-emitting control signal line for accessing the light-emitting control signal EM, and the pixel circuit 100 further includes a first light-emitting control transistor T6 and a second light-emitting control transistor T7. The first pole of the first light-emitting control transistor T6 is electrically connected to the first fixed potential signal line, and the second pole of the first light-emitting control transistor T6 is electrically connected to the first pole of the driving transistor T1. The first pole of the second light-emitting control transistor T7 is electrically connected to the second pole of the driving transistor T1, the second pole of the second light-emitting control transistor T7 is electrically connected to the anode of the light-emitting element D, and the cathode of the light-emitting element D is electrically connected to the second fixed potential signal line. The gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are both electrically connected to the light-emitting control signal line.

[0076] In the refresh frame and the hold frame, the end time of the enabling level period of the second scan signal S2P is earlier than the start time of the enabling level period of the light-emitting control signal EM accessed by the light-emitting control signal line.

[0077] In this embodiment, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are synchronously controlled by a light-emitting control signal EM to control the lighting of the light-emitting element D. In terms of timing, the enabling time period of the second scan signal S2P in the refresh frame and the hold frame is earlier than that of the light-emitting control signal EM, which can make the bias reset operation continue until the start of the light-emitting stage.

[0078] It should be noted that in the refresh frame, the first OBS stage t6 when the driving transistor T1 is in the OBS state includes a bias reset stage t4 and a reset maintenance stage t5. The reset maintenance stage t5 is the time interval between the end time of the enabling level of the second scan signal S2P and the start time of the enabling level of the light-emitting control signal EM. In the hold frame, the second OBS stage t7 when the driving transistor T1 is in the OBS state is the time interval between the start time of the enabling level of the first scan signal S1P and the start time of the enabling level of the light-emitting control signal EM. Thus, the bias adjustment effect can be improved to better improve the abnormal bright line and the abnormal brightening phenomenon at the R corner, and the display effect can be enhanced.

[0079] In some embodiments, the display panel further includes a first initialization signal line for accessing the first initialization signal REF1 and a fourth scan line for accessing the fourth scan signal S1N. The pixel circuit 100 further includes a first initialization transistor T8. The first pole of the first initialization transistor T8 is electrically connected to the first initialization signal line, the second pole of the first initialization transistor T8 is electrically connected to the gate of the driving transistor T1, and the gate of the first initialization transistor T8 is electrically connected to the fourth scan line.

[0080] In the refresh frame, the enabling time period of the fourth scan signal S1N introduced by the fourth scan line is before the enabling time periods of the second scan signal S2P, the first scan signal S1P, and the third scan signal S2N.

[0081] The non-light-emitting stage of the refresh frame further includes an initialization stage t1, which is before the threshold compensation stage t3, the data writing stage t2, and the bias reset stage t4. In the initialization stage t1, the fourth scan signal S1N is at the enabling level, and the first initialization transistor T8 is turned on, providing the first initialization voltage signal Vrefn1 to the gate of the driving transistor T1, the second end of the storage capacitor Cst, and the second pole of the threshold compensation transistor T5, resetting the gate of the driving transistor T1, the second pole of the threshold compensation transistor T5, and the second capacitor Cst2, avoiding the influence of the previous frame of the picture on the next frame of the picture, and thus improving the accuracy of the light-emitting element D to emit light.

[0082] The type of the first initialization transistor T8 can be set according to specific circumstances. As an example, the first initialization transistor T8 is an N-type transistor to reduce the leakage of the second capacitor Cst2, which is beneficial to maintaining the stability of the gate potential of the driving transistor T1 and improving the accuracy of the driving current generated by the driving transistor T1. Further, the threshold compensation transistor T5 can also be an N-type transistor to make the gate potential of the driving transistor T1 more stable.

[0083] In some embodiments, the display panel further includes a second initialization signal line for accessing the second initialization signal REF2. The pixel circuit 100 further includes a second initialization transistor T9. A first pole of the second initialization transistor T9 is electrically connected to the second initialization signal line, a second pole of the second initialization transistor T9 is electrically connected to an anode of the light-emitting element D, and a gate of the second initialization transistor T9 is electrically connected to the first scan line.

[0084] In this embodiment, the second initialization transistor T9 is turned on under the action of the first scan signal S1P, and can reset the anode potential of the anode D of the light-emitting element to the level of the second initialization signal REF2 before the start of the light-emitting stage, effectively eliminating the residual charge of the previous frame and improving the display afterimage problem.

[0085] To better understand the above embodiments, the following will be explained in detail with reference to an optional embodiment. Please refer to Figure 3 , the display panel includes: a pixel circuit 100, a data line for accessing a data signal Vdata, a first fixed potential signal line for accessing a first fixed potential signal PVDD, a second fixed potential signal line for accessing a second fixed potential signal PVEE, a first scan line for accessing a first scan signal S1P, a second scan line for accessing a second scan signal S2P, a third scan line for accessing a third scan signal S2N, a fourth scan line for accessing a fourth scan signal S1N, a light-emitting control signal line for accessing a light-emitting control signal EM, a first initialization signal line for accessing a first initialization signal REF1, a second initialization signal line for accessing a second initialization signal REF2, and a light-emitting element D.

[0086] Among them, the pixel circuit 100 includes a driving transistor T1, a data writing transistor T2, a first switching transistor T3, a second switching transistor T4, a threshold compensation transistor T5, a first light-emitting control transistor T6, a second light-emitting control transistor T7, a first initialization transistor T8, a second initialization transistor T9, a first capacitor Cst1, and a second capacitor Cst2. The driving transistor T1, the data writing transistor T2, the first switching transistor T3, the second switching transistor T4, the first light-emitting control transistor T6, the second light-emitting control transistor T7, and the second initialization transistor T9 are all P-type transistors, and the threshold compensation transistor T5 and the first initialization transistor T8 are N-type transistors. Each transistor can be a TFT transistor, and the source of each transistor is the first pole and the drain is the second pole.

[0087] Figure 5 is the timing diagram of the pixel circuit 100 in this embodiment. Below, in combination with Figure 3 , Figure 5 , the working process of the pixel circuit 100 in this embodiment will be described:

[0088] In the non-light-emitting stage of the refresh frame, the light-emitting control signal EM is at a non-enabling level, and the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned off.

[0089] In the initialization stage t1, the fourth scan signal S1N is at an enabling level, and the first initialization transistor T8 is turned on, transmitting the first initialization signal REF1 to the node N1 to reset the gate of the driving transistor T1, the second pole of the threshold compensation transistor T5, and the second capacitor Cst2.

[0090] In the data writing stage t2 and the threshold compensation stage t3, the third scan signal S2N is at an enabling level, and the threshold compensation transistor T5 is turned on to connect the node N3 and the node N1.

[0091] After the first scan signal S1P is converted from a non-enabling level to an enabling level, the data writing transistor T2 and the first switching transistor T3 are turned on. On the one hand, the data signal Vdata to be displayed transmitted by the data line is transmitted to the node N2 through the data writing transistor T2, and then transmitted to the node N1 via the second pole of the driving transistor T1 and the threshold compensation transistor T5, and is stored by the second capacitor Cst2. On the other hand, the data signal Vdata transmitted by the data line is written into the node N5 through the first switching transistor T3, and the voltage value corresponding to the data signal Vdata is stored by the first capacitor Cst1. During the enabling period of the first scan signal S1P, the second initialization transistor T9 is turned on to reset the anode potential of the anode D of the light-emitting element according to the second initialization signal REF2.

[0092] After the first scan signal S1P is converted from the enable level to the disable level, the threshold compensation transistor T5 continues to conduct, so that there is sufficient time for threshold compensation. After the threshold compensation is completed, the third scan signal S2N is converted to the disable level.

[0093] In the bias reset stage t4, the second scan signal S2P is at the enable level, and the data signal Vdata stored in the first capacitor Cst1 biases and resets the first pole of the driving transistor T1 through the second switching transistor T4.

[0094] In the reset maintenance stage t5, the first pole of the driving transistor T1 maintains the potential of the data signal Vdata and remains in the OBS state continuously.

[0095] In the light-emitting stage, that is, after the light-emitting control signal EM is converted from the disable level to the enable level, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 conduct, the driving transistor T1 generates a driving current, and transmits it to the light-emitting element D, and the light-emitting element D emits light according to the driving current.

[0096] In the hold frame, the second OBS stage t7 when the driving transistor T1 is in the OBS state is the time interval between the start time of the enable level of the first scan signal S1P and the start time of the enable level of the light-emitting control signal EM. In the hold frame, the third scan signal S2N and the fourth scan signal S1N are at the disable level, and there is no need to refresh the data, nor to reset the node N1. Since the hold frame does not require data refreshing, the data signal transmitted on the data line can be a fixed voltage, and the voltage is higher than the data signal transmitted in the refresh frame. By increasing the voltage of the data signal accessed by the data line, the bias adjustment effect can be improved, and the display effect of the hold frame can be improved.

[0097] The above display panel can adjust the bias state of the driving transistor T1 and improve the characteristics of the driving transistor T1. Moreover, the data signal Vdata used for bias reset is the same as the data signal Vdata written to the driving transistor T1, which can make the voltage of the driving transistor T1 not affected by the data signals of other row pixel circuits, and further make the potential of the anode of the light-emitting element D more stable and the driving current transmitted to the light-emitting element D more stable. Thus, the display uniformity of the display panel can be higher and the display effect can be better.

[0098] Based on the same application concept, the embodiment of the present application also provides a display device. Figure 8 For the structural schematic diagram of the display device 20 provided by the embodiment of the present application, as Figure 8 shown, the display device 20 includes a display panel 10, and the display panel 10 can be set with reference to the display panel in any of the above embodiments. Exemplarily, as Figure 8As shown, the display device 20 includes a display panel 10. Therefore, the display device 20 also has the beneficial effects of the display panel in the above embodiments. For the same parts, reference may be made to the explanations of the display panel 10 above, and details will not be repeated hereinafter.

[0099] The display device 20 provided by the embodiments of the present application may be a mobile phone or any electronic product with a display function, including but not limited to the following categories: televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, industrial control devices, medical display screens, touch interaction terminals, etc. The embodiments of the present application do not make special limitations in this regard.

[0100] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0101] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a pixel circuit, a data line, a first fixed potential signal line, a first scan line, a second scan line, and a light-emitting element. The pixel circuit includes a driving transistor, a data writing transistor, a first switching transistor, a second switching transistor, and a first capacitor. Among them, a first pole of the data writing transistor is electrically connected to the data line and a first pole of the first switching transistor; a second pole of the first switching transistor is electrically connected to a first pole of the first capacitor and a first pole of the second switching transistor; a second pole of the second switching transistor and a second pole of the data writing transistor are electrically connected to a first pole of the driving transistor, or a second pole of the second switching transistor and a second pole of the data writing transistor are electrically connected to a second pole of the driving transistor; a second pole of the first capacitor is electrically connected to the first fixed potential signal line; a gate of the data writing transistor and a gate of the first switching transistor are electrically connected to the first scan line; a gate of the second switching transistor is electrically connected to the second scan line; a first pole of the driving transistor is electrically connected to the first fixed potential signal line; a second pole of the driving transistor is electrically connected to the light-emitting element; During the same display period, a period of the enable level of the second scan signal applied to the second scan line is located after a period of the enable level of the first scan signal applied to the first scan line.

2. The display panel according to claim 1, wherein When the first scan signal applied to the first scan line is at the enable level period, the first switching transistor is turned on and the second switching transistor is turned off, and the data signal applied to the data line is written into the first capacitor; When the second scan signal applied to the second scan line is at the enable level period, the first switching transistor is turned off and the second switching transistor is turned on, and the data signal stored in the first capacitor resets the driving transistor.

3. The display panel according to claim 1, characterized in that, A driving period of the display panel includes a refresh frame and a hold frame. During the refresh frame, both the first scan signal and the second scan signal are single-pulse signals.

4. The display panel according to claim 1, wherein, The display panel further includes a third scan line, and the pixel circuit further includes a threshold compensation transistor; a first pole of the threshold compensation transistor is electrically connected to a second pole of the driving transistor; a second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor, and a gate of the threshold compensation transistor is electrically connected to the third scan line; A driving period of the display panel includes a refresh frame and a hold frame. During the refresh frame, a period of the enable level of the third scan signal applied to the third scan line overlaps with a period of the enable level of the first scan signal, and does not overlap with a period of the enable level of the second scan signal.

5. The display panel according to claim 4, wherein During the hold frame, the third scan signal maintains a non-enable level, a period of the enable level of the second scan signal is located after a period of the enable level of the first scan signal, and a voltage of the data signal applied to the data line is a constant voltage.

6. The display panel according to claim 5, wherein A voltage of the data signal applied to the data line during the hold frame is greater than a voltage of the data signal applied to the data line during the refresh frame.

7. The display panel according to claim 1, wherein The driving period of the display panel includes a refresh frame and a holding frame. The refresh frame and the holding frame include a non-emitting stage and an emitting stage. The enabling level period of the first scan signal and the enabling level period of the second scan signal overlap with the non-emitting stage.

8. The display panel according to claim 1, wherein the driving transistor is a P-type transistor, and the second pole of the data writing transistor and the second pole of the second switching transistor are electrically connected to the first pole of the driving transistor.

9. The display panel according to claim 1, wherein the driving transistor is an N-type transistor, and the second pole of the data writing transistor and the second pole of the second switching transistor are electrically connected to the second pole of the driving transistor.

10. A display device, characterized in that, including the display panel according to any one of claims 1-9.

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