Method for optimizing transmission voltage

Abstract

A method of optimizing a transmission voltage includes: determining a sweet point of an initial transmission voltage; monitoring a pulse count of incremental step pulse programming (ISPP); the offset of the lower limit value of the transmission voltage is obtained through the offset of the ISPP pulse number at different loops; monitoring the pulse number of incremental step pulse erasure (ISPE); the offset of the upper limit value of the transmission voltage is obtained through the offset of the ISPE pulse number at different loops; the offset of the upper limit value and the offset of the lower limit value are added and then divided by 2, and the offset of the sweet point of the transmission voltage is obtained; and adding the sweet point of the initial transmission voltage to the offset of the sweet point of the transmission voltage to obtain an optimized transmission voltage value.

Description

Technical Field

[0001] An embodiment of the present invention relates to a method for optimizing transmission voltage. Background Art

[0002] In flash memory, when data is programmed, electrons accumulate in the floating gate, shifting the threshold voltage of the memory cell positively. When data is erased, electrons are released from the floating gate, shifting the threshold voltage of the memory cell negatively. This programming and erasing process is controlled to keep the threshold of the memory cell within the distribution width of "0" and "1." When a memory cell stores multiple bits, further control is required to keep the threshold of the memory cell within the distribution width of "00," "01," "10," and "11."

[0003] In order to control the threshold distribution of the memory cell, the memory cell is erased using the Incremental Step Pulse Erase (ISPE) method. Figure 1A As shown, ISPE applies an erase pulse Vers0 to the P-well (P-Well) of the selected block. If the erase test determines that the erase is unqualified, an erase pulse Vers1 with a voltage one step higher than the erase pulse Vers0 is applied, so that the voltage of the erase pulse is increased until the erase of all memory cells in the block is determined to be qualified.

[0004] The same is true when programming. In order to accurately inject electrons into the memory cell, the incremental step pulse programming (ISPP) method can be used. Figure 1B As shown, the ISPP method applies a programming pulse Vpgm0 to the selected page. If the page is judged to be unqualified after the programming test, a programming pulse Vpgm1 with a voltage one step higher than the programming pulse Vpgm0 is applied to increase the voltage of the programming pulse until the programming of all memory cells in the page is judged to be qualified. Summary of the Invention

[0005] The present invention provides a method for optimizing transmission voltage, which can dynamically adjust the sweet spot of the transmission voltage so that the transmission voltage is continuously located between an upper limit (HB) value and a lower limit (LB) value that converge with the increase in the number of cycles, thereby reducing the number of failed bits and effectively improving yield and reliability.

[0006] The present invention provides a method for optimizing the transmission voltage, which includes: determining the sweet point of the initial transmission voltage; monitoring the number of pulses of the Incremental Step Pulse Programming (ISPP); obtaining the offset of the lower limit value of the transmission voltage through the offset of the number of pulses of the ISPP at different cycles; monitoring the number of pulses of the Incremental Step Pulse Erase (ISPE); obtaining the offset of the upper limit value of the transmission voltage through the offset of the number of pulses of the ISPE at different cycles; adding the offset of the upper limit value and the offset of the lower limit value and then dividing by 2 to obtain the offset of the sweet point of the transmission voltage; and adding the sweet point of the initial transmission voltage and the offset of the sweet point of the transmission voltage to obtain the optimized transmission voltage value.

[0007] In an embodiment of the present invention, obtaining the offset of the lower limit value of the transmission voltage through the offset of the number of pulses of the above-mentioned ISPP at different cycles includes: monitoring the first number of pulses X1 of the ISPP at the first cycle; monitoring the second number of pulses X2 of the ISPP at the second cycle; and substituting the first number of pulses X1 and the second number of pulses X2 into formula (1) to calculate the offset of the lower limit value of the transmission voltage.

[0008] Y1 = -a(X2 - X1) (1)

[0009] Where Y1 is the offset of the lower limit value of the transmission voltage, and a is a constant greater than zero.

[0010] In an embodiment of the present invention, the above-mentioned a is greater than zero and less than 1.

[0011] In an embodiment of the present invention, obtaining the offset of the upper limit value of the transmission voltage through the offset of the number of pulses of the above-mentioned ISPE at different cycles includes: monitoring the third number of pulses X3 of the ISPE at the first cycle; monitoring the fourth number of pulses X4 of the ISPP at the second cycle; and substituting the third number of pulses X3 and the fourth number of pulses X4 into formula (2) to calculate the offset of the upper limit value of the transmission voltage.

[0012] Y2 = -b(X4 - X3) (2)

[0013] Where Y2 is the offset of the upper limit value of the transmission voltage, and b is a constant greater than zero.

[0014] In an embodiment of the present invention, the above-mentioned b is greater than zero and less than 1.

[0015] In an embodiment of the present invention, the number of pulses of the above-mentioned ISPP decreases as the number of cycles increases.

[0016] In an embodiment of the present invention, the lower limit value of the above-mentioned transmission voltage increases as the number of cycles increases.

[0017] In one embodiment of the present invention, the number of pulses of the above-mentioned ISPE increases as the number of cycles increases.

[0018] In one embodiment of the present invention, the upper limit value of the above-mentioned transfer voltage decreases as the number of cycles increases. Brief Description of the Drawings

[0019] Figure 1A A schematic diagram showing the erasing operation of a flash memory using ISPE;

[0020] Figure 1B A schematic diagram showing the programming operation of a flash memory using ISPP;

[0021] Figure 2 A graph showing the relationship between the transfer voltage and the number of failed bits in an embodiment of the present invention;

[0022] Figure 3A A graph showing the relationship between the number of pulses of ISPP, the transfer voltage, and the number of cycles in an embodiment of the present invention;

[0023] Figure 3B A graph showing the relationship between the number of pulses of ISPE, the transfer voltage, and the number of cycles in an embodiment of the present invention;

[0024] Figure 4A A graph showing the relationship between the number of pulses of ISPP and the lower limit value of the transfer voltage in an embodiment of the present invention;

[0025] Figure 4B A graph showing the relationship between the number of pulses of ISPE and the upper limit value of the transfer voltage in an embodiment of the present invention;

[0026] Figure 5 A graph showing the relationship between the number of cycles and the upper limit value and the lower limit value of the transfer voltage in an embodiment of the present invention;

[0027] Figure 6 A flowchart showing the method for optimizing the transfer voltage in an embodiment of the present invention. Detailed Description of the Invention

[0028] The semiconductor element in the embodiment of the present invention is, for example, a NAND flash memory, or a microprocessor, a microcontroller, a logic, an application specific integrated circuit (ASIC), a processor for processing images and sounds, a signal processor for processing wireless signals, etc. that embed such a flash memory. The memory element in the following embodiments is described by taking the NAND flash memory as an example, but the present invention is not limited thereto.

[0029] Figure 2A graph showing the relationship between the transfer voltage and the number of failed bits according to an embodiment of the present invention, where Figure 2 is a normalized data graph.

[0030] In the current programming operation, a programming voltage (Vpgm) is applied to the selected word line, and a transfer voltage (Vpass) is applied to the unselected word lines to meet the programming requirements. However, when the transfer voltage is too low, the high programming voltage applied to the selected word line will still cause programming interference to the adjacent unselected word lines, resulting in an increase in the number of failed bits (fail bit count). On the other hand, if a higher transfer voltage is applied to the unselected word lines, the higher transfer voltage may cause transfer voltage interference (Vpasswdisturb) to the data in the memory cells, resulting in an increase in the number of failed bits. That is, the transfer voltage needs to be limited between an appropriate upper limit (high boundary, HB) and a lower limit (low boundary, LB) to reduce the number of failed bits, thereby improving the yield and reliability, as Figure 2 shown.

[0031] Generally, the tolerance of memory cells can be tested through multiple programming / erasing cycles. The so-called programming / erasing cycle is obtained by repeatedly applying a programming pulse with a certain voltage and an erasing pulse with a certain voltage. As the number of programming / erasing cycles increases, the degradation of Gm (transconductance) caused by charge trapping becomes more significant, making it difficult for current to flow in the memory cells. In this case, as the number of cycles gradually increases, the threshold voltage (Vth) of the memory cells will gradually shift in the positive direction. Since programming the memory cells is to increase the threshold, the increase in the number of cycles makes programming easier, that is, the programming speed becomes faster. If the programming verification voltage in the ISPP is the same, then the verification can be passed at a lower voltage of the programming pulse. Figure 3A A graph showing the relationship between the number of pulses, the transfer voltage, and the number of cycles of the ISPP according to an embodiment of the present invention, where Figure 3A is a normalized data graph. As Figure 3A shown, the number of pulses of the ISPP can decrease as the number of cycles increases; and the lower limit value of the transfer voltage increases as the number of cycles increases. That is, the number of pulses of the ISPP and the lower limit value of the transfer voltage are inversely proportional to the change in the number of cycles. Figure 4A A graph showing the relationship between the number of pulses of the ISPP and the lower limit (LB) value of the transfer voltage according to an embodiment of the present invention, where Figure 4A is a normalized data graph. As Figure 4AAs shown, as the number of cycles increases, the number of pulses of the ISPP decreases and the lower limit value of the transfer voltage increases. Herein, the number of pulses of the ISPP and the lower limit value of the transfer voltage can be expressed by the following formula (A):

[0032] Y = -aX + c (A)

[0033] Where X is the number of pulses of the ISPP, Y is the lower limit value of the transfer voltage, and a and c are constants greater than zero. In some embodiments, a is greater than zero and less than 1, and c can adjust the absolute value of the lower limit value of the transfer voltage according to different product requirements. In alternative embodiments, a is between 0.2 and 0.5. In other embodiments, a is between 0.35 and 0.36.

[0034] On the other hand, since the erasure of the memory cell reduces the threshold value, the increase in the number of cycles makes the erasure difficult, for example, the erasure speed becomes slower. Therefore, the number of pulses of the ISPE will increase as the number of cycles increases. Further, in the ISPE, if the erasure test fails even after applying the maximum number of erasure pulses, this block is managed as a bad block, so the available storage capacity is limited. Figure 3B A graph showing the relationship between the number of pulses of the ISPE, the transfer voltage, and the number of cycles according to an embodiment of the present invention, wherein Figure 3B is a normalized data graph. As Figure 3B shown, the number of pulses of the ISPE can increase as the number of cycles increases; and the upper limit value of the transfer voltage decreases as the number of cycles increases. That is, the number of pulses of the ISPE and the upper limit value of the transfer voltage are inversely proportional to the change in the number of cycles. Figure 4B A graph showing the relationship between the number of pulses of the ISPE and the upper limit (HB) value of the transfer voltage according to an embodiment of the present invention, wherein Figure 4B is a normalized data graph. As Figure 4B shown, as the number of cycles increases, the number of pulses of the ISPE increases and the upper limit value of the transfer voltage decreases.

[0035] Herein, the number of pulses of the ISPE and the upper limit value of the transfer voltage can be expressed by the following formula (B):

[0036] Y = -bX + d (B)

[0037] Where X is the number of pulses of the ISPP, Y is the upper limit value of the transfer voltage, and b is a constant greater than zero. In some embodiments, b is greater than zero and less than 1, and d can adjust the absolute value of the upper limit value of the transfer voltage according to different product requirements. In alternative embodiments, b is between 0.1 and 0.4. In other embodiments, b is between 0.17 and 0.18.

[0038] Figure 5 The relationship between the number of cycles and the upper limit (HB) and lower limit (LB) of the transmission voltage according to the embodiment of the present invention is shown in FIG. Figure 5 is a normalized data graph. Figure 5 As shown in Figure 1, the upper and lower limits of the transmission voltage converge as the number of loops increases. In this case, if the transmission voltage is set to a fixed initial value (Vi), as the number of loops increases, the initial value (Vi) will exceed the upper limit of the transmission voltage, causing the number of failed bits to increase beyond the criteria.

[0039] To address the aforementioned issues, this embodiment dynamically adjusts the sweet spot of the transmission voltage, ensuring that the transmission voltage remains between an upper limit (HB) and a lower limit (LB), which converge with increasing loop counts. This reduces the number of failed bits and effectively improves yield and reliability. The detailed steps of this embodiment's transmission voltage optimization method are described in the following sections.

[0040] Figure 6 FIG. 1 is a flow chart showing a method S100 for optimizing transmission voltage according to an embodiment of the present invention.

[0041] Please refer to Figure 6 First, step S102 is performed to determine the sweet point of the initial pass voltage. In one embodiment, the sweet point of the initial pass voltage is an experimental value obtained by varying the pass voltage and reading each word line before a program / erase cycle (i.e., zero cycling count). In some embodiments, the sweet point of the initial pass voltage may vary depending on the technology node and product.

[0042] Next, step S104 is performed to monitor the number of pulses of the incremental step pulse programming (ISPP). Specifically, Figure 1B As shown, the ISPP operation applies a programming pulse Vpgm0 to a selected page. If the transfer programming test determines that the page has failed, a programming pulse Vpgm1, one step higher than programming pulse Vpgm0, is applied. The voltage of the programming pulse is increased until all memory cells in the page have passed programming. In one embodiment, the number of ISPP pulses after each cycle is monitored and recorded.

[0043] Then, step S106 is performed to determine the offset of the lower limit of the transmission voltage by analyzing the offset of the ISPP pulse count at different loops. Specifically, the first pulse count X1 of the ISPP at the first loop is monitored. The second pulse count X2 of the ISPP at the second loop is monitored. Next, the first pulse count X1 and the second pulse count X2 are substituted into equation (1) to calculate the offset of the lower limit of the transmission voltage.

[0044] Y1=-a(X2-X1) (1)

[0045] Wherein Y1 is the offset of the lower limit value of the transmission voltage, and a is a constant greater than zero.

[0046] In some embodiments, a is greater than zero and less than 1. In alternative embodiments, a is between 0.2 and 0.5. In other embodiments, a is between 0.35 and 0.36.

[0047] Then, step S108 is performed to monitor the number of pulses of the incremental step pulse erase (ISPE). Specifically, Figure 1A As shown, the ISPE operation applies an erase pulse Vers0 to the P-well of a selected block. If the transmission erase test determines that the memory cells fail the erase test, an erase pulse Vers1 with a voltage one step higher than the erase pulse Vers0 is applied. The erase pulse voltage is increased until all memory cells in the block are deemed to pass the erase test. In one embodiment, the number of ISPE pulses after each cycle is monitored and recorded.

[0048] Then, step S110 is performed to determine the shift in the upper limit of the transmission voltage by measuring the shift in the number of ISPE pulses at different loops. Specifically, the third number of ISPE pulses, X3, at the first loop is monitored. The fourth number of ISPP pulses, X4, at the second loop is monitored. Next, the third and fourth number of pulses, X3, and X4, are substituted into equation (2) to calculate the shift in the upper limit of the transmission voltage.

[0049] Y2=-b(X4-X3) (2)

[0050] Wherein Y2 is the offset of the upper limit value of the transmission voltage, and b is a constant greater than zero.

[0051] In some embodiments, b is greater than zero and less than 1. In alternative embodiments, b is between 0.1 and 0.4. In other embodiments, b is between 0.17 and 0.18.

[0052] Next, step S112 is performed to add the upper limit offset Y2 and the lower limit offset Y1 and divide the sum by 2 (ie, (Y2+Y1) / 2) to obtain the sweet point offset of the transmission voltage.

[0053] Then, step S114 is performed to add the offset between the sweet point of the initial transmission voltage and the sweet point of the transmission voltage to obtain an optimized transmission voltage value. In this embodiment, this optimized transmission voltage value can continuously lie between the upper limit (HB) value and the lower limit (LB) value that converge as the number of cycles increases, thereby reducing the number of failed bits and effectively improving the yield and reliability. In one embodiment, compared with a fixed transmission voltage, the error-correcting code (ECC) of the optimized transmission voltage can be improved from 25 to 4 after 20,000 cycles, that is, the embodiments of the present invention can effectively improve the yield and reliability.

Claims

1. A method for optimizing the transmission voltage, comprising: Determining the sweet point of the initial transmission voltage; Monitoring the number of pulses of the incremental step pulse programming; Obtaining the offset of the lower limit value of the transmission voltage by the offset of the number of pulses of the monitored incremental step pulse programming at different loops; Monitoring the number of pulses of the incremental step pulse erasure; Obtaining the offset of the upper limit value of the transmission voltage by the offset of the number of pulses of the monitored incremental step pulse erasure at the different loops; Adding the offset of the upper limit value and dividing the result by 2 to obtain the offset of the sweet point of the transmission voltage; And Adding the sweet point of the initial transmission voltage and the offset of the sweet point of the transmission voltage to obtain the optimized transmission voltage value.

2. The method for optimizing the transmission voltage according to claim 1, wherein obtaining the offset of the lower limit value of the transmission voltage by the offset of the number of pulses of the monitored incremental step pulse programming at the different loops comprises: Monitoring the first number of pulses X1 of the monitored incremental step pulse programming at the first loop; Monitoring the second number of pulses X2 of the monitored incremental step pulse programming at the second loop; And Substituting the first number of pulses X1 and the second number of pulses X2 into formula (1) to calculate the offset of the lower limit value of the transmission voltage, Y1 = -a(X2 - X1) (1) where Y1 is the offset of the lower limit value of the transmission voltage, and a is a constant greater than zero.

3. The method for optimizing the transmission voltage according to claim 2, wherein a is greater than zero and less than 1.

4. The method for optimizing the transmission voltage according to claim 1, wherein obtaining the offset of the upper limit value of the transmission voltage by the offset of the number of pulses of the monitored incremental step pulse erasure at the different loops comprises: Monitoring the third number of pulses X3 of the monitored incremental step pulse erasure at the first loop; Monitoring the fourth number of pulses X4 of the monitored incremental step pulse programming at the second loop; And Substituting the third number of pulses X3 and the fourth number of pulses X4 into formula (2) to calculate the offset of the upper limit value of the transmission voltage, Y2 = -b(X4 - X3) (2) where Y2 is the offset of the upper limit value of the transmission voltage, and b is a constant greater than zero.

5. The method for optimizing the transmission voltage according to claim 4, wherein b is greater than zero and less than 1.

6. The method for optimizing the transmission voltage according to claim 1, wherein the number of pulses of the monitored incremental step pulse programming decreases as the number of loops increases.

7. The method for optimizing the transmission voltage according to claim 1, wherein the lower limit value of the transmission voltage increases as the number of loops increases.

8. The method for optimizing the transmission voltage according to claim 1, wherein the number of pulses of the monitored incremental step pulse erasure increases as the number of loops increases.

9. The method for optimizing the transmission voltage according to claim 1, wherein the upper limit value of the transmission voltage decreases as the number of loops increases.

10. The method for optimizing the transmission voltage according to claim 1, wherein the method is applicable to NAND flash memories.

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