Semiconductor device structure and preparation method thereof

Abstract

The invention provides a semiconductor device structure and a preparation method thereof, and the method comprises the following steps: providing a substrate which sequentially comprises a semiconductor substrate, a gate material layer and a first dielectric layer from bottom to top; performing photoetching and etching processes on the first dielectric layer to form a patterned first dielectric layer; by using the patterned first dielectric layer as a mask, performing an etching process on the gate material layer to form a first trench structure; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer further extends to cover the bottom surface and the side surface of the first groove structure to form a second groove structure; and etching the second dielectric layer along the second groove structure until the semiconductor substrate is exposed to form a contact hole. According to the preparation method of the semiconductor device structure, the alignment deviation risk can be reduced, the accuracy of the key size of the contact hole is improved, and the risks of device structure abnormality and device electrical abnormality are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor device structure and a preparation method thereof. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, the requirements for integrated circuit integration and performance are becoming increasingly higher. To improve integration and reduce costs, the critical dimensions of device structures are constantly shrinking. For example, the critical dimension (CD) of the contact hole (CT) is getting smaller and smaller. However, the process window in the contact hole process flow for small-size processes has become very sensitive and difficult to control with high precision.

[0003] During the current contact hole fabrication process, the polysilicon and gate oxide layers are first photolithographically etched, followed by the dielectric layer. Finally, the dielectric layer is photolithographically etched again to form the contact hole. Both of these photolithography processes require the overlay mark (OVL mark) to be aligned with the zero-layer mark (0M). This creates two misalignments, and the combined effects of these misalignments make it difficult to precisely control the critical dimensions of the contact hole, potentially leading to structural and electrical anomalies in the device. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device structure and a method for preparing the same, so as to reduce the risk of alignment deviation, improve the accuracy of the critical dimensions of the contact holes, and reduce the risk of device structural anomalies and device electrical anomalies.

[0005] In order to achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor device structure, comprising the following steps:

[0006] Providing a substrate, wherein the substrate comprises, from bottom to top, a semiconductor substrate, a gate material layer, and a first dielectric layer;

[0007] performing photolithography and etching processes on the first dielectric layer to form a patterned first dielectric layer;

[0008] performing an etching process on the gate material layer using the patterned first dielectric layer as a mask to form a first trench structure;

[0009] forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer further extends to cover the bottom surface and side surfaces of the first trench structure to form a second trench structure;

[0010] The second dielectric layer is etched along the second trench structure until the semiconductor substrate is exposed to form a contact hole.

[0011] Optionally, in the method for manufacturing the semiconductor device structure, the etching process of the second dielectric layer includes a dry etching process.

[0012] Optionally, in the method for manufacturing the semiconductor device structure, the formation process of the second dielectric layer includes one of a chemical vapor deposition process and a physical vapor deposition process.

[0013] Optionally, in the method for manufacturing the semiconductor device structure, in the step of performing an etching process on the gate material layer, a plurality of gate structures are formed, and the first trench structure is located between adjacent ones of the gate structures.

[0014] Optionally, in the method for manufacturing the semiconductor device structure, the gate material layer includes a gate oxide layer and a polysilicon layer stacked in sequence, the gate oxide layer is located on the semiconductor substrate, and the first trench structure penetrates through the polysilicon layer and extends at least into the gate oxide layer.

[0015] Optionally, in the method for manufacturing the semiconductor device structure, the steps of performing photolithography and etching on the first dielectric layer include:

[0016] Forming a photoresist layer on the first dielectric layer;

[0017] Performing photolithography on the photoresist layer using a photomask to form a patterned photoresist layer;

[0018] Using the patterned photoresist layer as a mask to etch the first dielectric layer to form a patterned first dielectric layer.

[0019] Optionally, in the method for manufacturing the semiconductor device structure, before the step of performing an etching process on the gate material layer, the manufacturing method further includes: removing the patterned photoresist layer.

[0020] Optionally, in the method for manufacturing the semiconductor device structure, the material of the first dielectric layer is the same as the material of the second dielectric layer; the thickness of the second dielectric layer is adjusted according to the critical dimension of the contact hole.

[0021] Optionally, in the method for manufacturing the semiconductor device structure, after the step of forming the contact hole, the manufacturing method further includes: filling a metal material in the contact hole to form a metal electrode.

[0022] To achieve the above and other related objectives, the present invention provides a semiconductor device structure, which is manufactured by using the method for manufacturing the semiconductor device structure described above.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] In the method for preparing the semiconductor device structure provided by the present invention, lithography is only performed on the first dielectric layer, and the gate material layer is directly etched without lithography, that is, no photomask is used during the etching process of the gate material layer, so there is no risk of alignment deviation, which can improve the accuracy of the critical dimension of the contact hole and reduce the risk of abnormal device structure and abnormal device electrical properties.

[0025] Secondly, in the etching process of the first dielectric layer and the gate material layer of the present invention, only one lithography process is adopted, that is, only one photomask is used, which can reduce costs.

[0026] Moreover, the present invention can adjust the critical dimension of the contact hole by forming a second dielectric layer with different thicknesses to meet the changing requirements of the critical dimension of the contact hole during the production process, without increasing the cost of additional photomasks. At the same time, using this process can better control the accuracy of the critical dimension of the contact hole. Description of the Drawings

[0027] Figure 1 It is a schematic diagram of the product after performing step S01 in a method for preparing a semiconductor device structure;

[0028] Figure 2 It is a schematic diagram of the product after performing step S02 in a method for preparing a semiconductor device structure;

[0029] Figure 3 It is a schematic diagram of the product after performing step S03 in a method for preparing a semiconductor device structure;

[0030] Figure 4 It is a schematic diagram of the product after performing step S04 in a method for preparing a semiconductor device structure;

[0031] Figure 5 It is a schematic diagram of the product after performing step S12 in a method for preparing a semiconductor device structure according to an embodiment of the present invention;

[0032] Figure 6 It is a schematic diagram of the product after performing step S13 in a method for preparing a semiconductor device structure according to an embodiment of the present invention;

[0033] Figure 7 It is a schematic diagram of the product after performing step S3 in a method for preparing a semiconductor device structure according to an embodiment of the present invention;

[0034] Figure 8 It is a schematic diagram of the product after performing step S4 in a method for preparing a semiconductor device structure according to an embodiment of the present invention;

[0035] Figure 9It is a schematic diagram of the product after performing step S5 in the preparation method of the semiconductor device structure according to an embodiment of the present invention;

[0036] Figures 1 to 4 In which:

[0037] 01 - Semiconductor substrate, 02 - Gate oxide layer, 03 - Polysilicon layer, 04 - Trench structure, 05 - Dielectric layer, 06 - Contact hole;

[0038] Figures 5 to 9 In which:

[0039] 10 - Semiconductor substrate, 20 - Gate oxide layer, 30 - Polysilicon layer, 40 - First trench structure, 50 - First dielectric layer, 60 - Second dielectric layer, 70 - Second trench structure, 80 - Contact hole. Detailed implementation manners

[0040] Refer to Figures 1 to 4 , a preparation method of a semiconductor device structure includes the following steps:

[0041] Step S01: Provide a substrate, which sequentially includes a semiconductor substrate 01 and a gate material layer from bottom to top;

[0042] Step S02: Perform a photolithography and etching process on the gate material layer to form a trench structure 04;

[0043] Step S03: Form a dielectric layer 05 in the trench structure 04, and the dielectric layer 05 also extends onto the gate material layer;

[0044] Step S04: Perform a photolithography and etching process on the dielectric layer 05 to form a contact hole 06 penetrating through the dielectric layer 05.

[0045] In step S01, the gate material layer includes a sequentially stacked gate oxide layer 02 and a polysilicon layer 03. In step S02, a single photomask is used to perform the photolithography process of the gate material layer, and during the photolithography process, the alignment of the registration mark to the zero-layer mark has a deviation. In step S04, a single photomask is used to perform the photolithography process of the contact hole, and during the photolithography process, the alignment of the registration mark to the zero-layer mark also has a deviation. The superposition of the two deviations (the deviation in step S02 and the deviation in step S04) makes it difficult to control the accuracy of the critical dimension of the contact hole, and there is a great risk of causing device structure abnormalities and device electrical property abnormalities.

[0046] The following further elaborates on the semiconductor device structure and its manufacturing method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0047] Referring to Figures 5 to 9 , the present invention provides a method for manufacturing a semiconductor device structure, which may include the following steps:

[0048] Step S1: Provide a substrate, which sequentially includes a semiconductor substrate 10, a gate material layer, and a first dielectric layer 50 from bottom to top;

[0049] Step S2: Perform a photolithography and etching process on the first dielectric layer 50 to form a patterned first dielectric layer 50;

[0050] Step S3: Use the patterned first dielectric layer 50 as a mask to perform an etching process on the gate material layer to form a first trench structure 40;

[0051] Step S4: Form a second dielectric layer 60 on the first dielectric layer 50, and the second dielectric layer 60 also extends to cover the bottom surface and side surface of the first trench structure 40 to form a second trench structure 70;

[0052] Step S5: Etch the second dielectric layer 60 along the second trench structure 70 until the semiconductor substrate 10 is exposed to form a contact hole 80.

[0053] Referring to Figure 5 and Figure 6 , perform Step S1 to provide a substrate. In this embodiment, the substrate may include a semiconductor substrate 10, a gate material layer, and a first dielectric layer 50 stacked in sequence. The semiconductor substrate 10 is preferably a SiC (silicon carbide) substrate, but is not limited thereto. The gate material layer may include a gate oxide layer 20 and a polysilicon layer 30 stacked in sequence, and the gate oxide layer 20 is located on the semiconductor substrate 10. The material of the gate oxide layer 20 is preferably silicon oxide (SiO2), the material of the polysilicon layer 30 is preferably polysilicon, and the thicknesses of the gate oxide layer 20 and the polysilicon layer 30 can be set according to process requirements. The material of the first dielectric layer 50 is preferably silicon oxide, but is not limited thereto. The thickness of the first dielectric layer 50 can be set according to process requirements and will not be elaborated here.

[0054] In this embodiment, the formation steps of the substrate may include:

[0055] Step S11: Provide a semiconductor substrate 10;

[0056] Step S12: Form a gate material layer on the semiconductor substrate 10;

[0057] Step S13: Form a first dielectric layer 50 on the gate material layer.

[0058] In step S12 and step S13, the formation processes of the gate material layer and the first dielectric layer 50 can be chemical deposition processes or physical deposition processes, but are not limited thereto.

[0059] Refer to Figure 7 , perform step S2, and perform photolithography and etching processes on the first dielectric layer 50. In this embodiment, the steps of performing photolithography and etching processes on the first dielectric layer 50 may include:

[0060] Step S21: Form a photoresist layer on the first dielectric layer 50;

[0061] Step S22: Use a photomask to perform photolithography on the photoresist layer to form a patterned photoresist layer;

[0062] Step S23: Use the patterned photoresist layer as a mask to etch the first dielectric layer 50 to form a patterned first dielectric layer.

[0063] In step S21, the formation process of the photoresist layer on the first dielectric layer 50 is preferably a spin coating process, but is not limited thereto.

[0064] In step S22, using the photomask as a mask, expose and develop the photoresist layer to achieve photolithography of the photoresist layer. The pattern on the photomask can be set according to process requirements.

[0065] In step S23, the etching process for the first dielectric layer 50 is preferably a dry etching process, but is not limited thereto.

[0066] After step S2 and before step S3 in this embodiment, the method for manufacturing the semiconductor device structure may further include: removing the patterned photoresist layer. In this embodiment, the removal process of the patterned photoresist layer is preferably an ashing process, but is not limited thereto.

[0067] Continue to refer to Figure 7, perform step S3 to form the first trench structure 40. In this embodiment, an etching process is performed on the gate material layer using the patterned first dielectric layer 50 as a mask to form the first trench structure 40. By performing the etching process on the gate material layer in this embodiment, a plurality of gate structures and the first trench structure 40 located between the gate structures can be formed, that is, the gate material layer covered by the patterned first dielectric layer 50 is not etched to form the gate structure; while the gate material layer not covered by the patterned first dielectric layer 50 is etched away to form the first trench structure 40. The width of the first trench structure 40 is set according to process requirements. The etching process is preferably dry etching, but is not limited thereto. The material of the first dielectric layer 50 is preferably the same as the material of the gate oxide layer 20. Therefore, the first trench structure 40 penetrates through the polysilicon layer 30 and extends at least into a partial depth of the gate oxide layer 20, that is, the first trench structure 40 can penetrate through the polysilicon layer 30 and extend into a partial depth of the gate oxide layer 20; the first trench structure 40 can also sequentially penetrate through the polysilicon layer 30 and the gate oxide layer 20 to expose the upper surface of the semiconductor substrate 10.

[0068] In this embodiment, an etching process is directly performed on the gate material layer without the need to perform a photolithography process. Therefore, there is no need to use a photomask, and there is no risk of alignment deviation. The accuracy of the critical dimension of the contact hole can be improved, the risk of device structure abnormality and device electrical property abnormality can be reduced, and the cost can also be reduced.

[0069] Refer to Figure 8 , perform step S4 to form the second dielectric layer 60. In this embodiment, the second dielectric layer 60 is located on the first dielectric layer 50 and extends to cover the bottom surface and the side surface of the first trench structure 40 to form the second trench structure 70. The material of the second dielectric layer 60 is preferably the same as the material of the first dielectric layer 50. Further, the material of the second dielectric layer 60 is preferably silicon oxide, but is not limited thereto. The formation process of the second dielectric layer 60 is preferably a chemical deposition process or a physical deposition process, but is not limited thereto.

[0070] In this embodiment, the thickness of the second dielectric layer 60 can be determined according to the design requirements of the contact hole 80, that is, the thickness of the second dielectric layer 60 can be adjusted according to the critical dimension of the contact hole 80. The thicker the second dielectric layer 60 formed above the first dielectric layer 50, the thicker the second dielectric layer 60 formed on the side surface of the first trench structure 40, and the smaller the width of the formed second trench structure 70. Therefore, the width of the second trench structure 70 can be adjusted by adjusting the thickness of the second dielectric layer 60 (that is, the thickness of the second dielectric layer 60 above the first dielectric layer 50), and the width of the second trench structure 70 is the same as the critical dimension of the contact hole 80. Therefore, in this embodiment, the critical dimension of the contact hole 80 can be adjusted by adjusting the thickness of the second dielectric layer 60. That is, the present invention can adjust the critical dimension of the contact hole 80 by depositing the second dielectric layer 60 with different thicknesses, which can meet the change requirements of the critical dimension of the contact hole 80 during the production process, without increasing the additional mask cost, and at the same time, using this process can better control the accuracy of the critical dimension of the contact hole 80.

[0071] Refer to Figure 9 , perform step S5 to form the contact hole 80. In this embodiment, the contact hole 80 is formed by etching the second dielectric layer 60 along the second trench structure 70, and the contact hole 80 exposes the upper surface of the semiconductor substrate 10. The etching process of the second dielectric layer 60 is preferably dry etching, but is not limited thereto. In this embodiment, by controlling the dry etching time, the second dielectric layer 60 under the bottom of the second trench structure 70 can be etched completely to form the contact hole 80. During the dry etching process, a part of the thickness of the second dielectric layer 60 above the first dielectric layer 50 will also be etched. In this embodiment, the width (critical dimension) of the contact hole 80 is the same as the width of the second trench structure 70.

[0072] After step S5 in this embodiment, the method for manufacturing the semiconductor device structure may further include: filling a metal material in the contact hole 80 to form a metal electrode. The metal electrode is in contact with the semiconductor substrate 10. The metal material can be one or a combination of Ni (nickel), Ti (titanium), TiN (titanium nitride), W (tungsten), or Al (aluminum), etc. In this embodiment, the metal material can be filled by electroplating process or deposition process, but is not limited thereto.

[0073] The present invention also provides a semiconductor device structure, which is obtained by using the preparation method of the semiconductor device structure described above, and is specifically obtained by steps S1 to S5. The semiconductor device structure may specifically include: a semiconductor substrate 10, a plurality of gate structures, a first dielectric layer 50, a second dielectric layer 60, and a contact hole 80. The gate structure is located on the semiconductor substrate 10, and the gate structure may include a gate oxide layer 20 and a polysilicon layer 30 stacked in sequence; the first dielectric layer 50 is located on the gate structure; the second dielectric layer 60 covers the side surfaces of the gate structure and the first dielectric layer 50; the contact hole 80 penetrates through the second dielectric layer 60. The semiconductor device structure may further include a metal electrode, and the metal electrode fills the contact hole 80 and is in contact with the semiconductor substrate 10.

[0074] In summary, in the present invention, only the first dielectric layer is lithographed, and the gate material layer is directly etched without lithography, that is, a photomask is not used in the etching process of the gate material layer, so there is no risk of alignment deviation, which can improve the accuracy of the critical dimension of the contact hole and reduce the risk of abnormal device structure and abnormal device electrical properties; moreover, in the present invention, only one lithography process is adopted in the etching processes of the first dielectric layer and the gate material layer, that is, only one photomask is used, which can reduce the cost; in addition, the present invention can flexibly control the critical dimension of the contact hole through the deposition of the second dielectric layer, and for small-sized contact holes, the preparation method of the semiconductor device structure of the present invention has higher accuracy and is easier to control.

[0075] In addition, it can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0076] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, and they may vary. It should also be understood that the terms described herein are only used to describe specific embodiments and not to limit the scope of the present invention. It must be noted that the singular forms "a", "an", and "the" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means reference to one or more steps and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein should be understood to also refer to functional equivalents of such structures. Language that may be construed as approximate should be so understood unless the context clearly dictates otherwise.

Claims

1. A method for preparing a semiconductor device structure, characterized in that Including the following steps: Providing a substrate, which sequentially includes a semiconductor substrate, a gate material layer, and a first dielectric layer from bottom to top; Performing a photolithography and etching process on the first dielectric layer to form a patterned first dielectric layer; Using the patterned first dielectric layer as a mask to perform an etching process on the gate material layer to form a first trench structure; Forming a second dielectric layer on the first dielectric layer, and the second dielectric layer further extends to cover the bottom surface and side surface of the first trench structure to form a second trench structure; Etching the second dielectric layer along the second trench structure until the semiconductor substrate is exposed to form a contact hole.

2. The method for preparing the semiconductor device structure according to claim 1, wherein, The etching process of the second dielectric layer includes a dry etching process.

3. The method for manufacturing a semiconductor device structure according to claim 1, wherein The forming process of the second dielectric layer includes one of a chemical deposition process and a physical deposition process.

4. The manufacturing method of the semiconductor device structure according to claim 1, characterized in that, In the step of performing an etching process on the gate material layer, a plurality of gate structures are formed, and the first trench structure is located between adjacent gate structures.

5. The method for fabricating a semiconductor device structure according to claim 1, wherein, The gate material layer includes a gate oxide layer and a polysilicon layer stacked in sequence. The gate oxide layer is located on the semiconductor substrate, and the first trench structure penetrates through the polysilicon layer and at least extends to a partial depth of the gate oxide layer.

6. The manufacturing method of the semiconductor device structure according to claim 1, characterized in that The step of performing a photolithography and etching process on the first dielectric layer includes: Forming a photoresist layer on the first dielectric layer; Performing photolithography on the photoresist layer using a photomask to form a patterned photoresist layer; Using the patterned photoresist layer as a mask to etch the first dielectric layer to form a patterned first dielectric layer.

7. The manufacturing method of the semiconductor device structure according to claim 6, characterized in that, Before the step of performing an etching process on the gate material layer, the preparation method further includes: removing the patterned photoresist layer.

8. The manufacturing method of the semiconductor device structure according to claim 1, characterized in that, The material of the first dielectric layer is the same as that of the second dielectric layer; the thickness of the second dielectric layer is adjusted according to the critical dimension of the contact hole.

9. The manufacturing method of the semiconductor device structure according to claim 1, characterized in that, After the step of forming the contact hole, the preparation method further includes: filling a metal material in the contact hole to form a metal electrode.

10. A semiconductor device structure, characterized in that, Prepared by using the preparation method of the semiconductor device structure according to any one of claims 1 to 9.

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