Three-dimensional semiconductor structure and manufacturing method thereof

Abstract

The invention provides a manufacturing method of a three-dimensional semiconductor structure. The manufacturing method of the three-dimensional semiconductor structure comprises the following steps: providing a wafer which comprises a front surface and a back surface; the method comprises the following steps: adhering the front surface of a wafer to a support substrate, coating a photoresist layer on the back surface of the wafer, and etching the back surface of the wafer to form a plurality of grooves in the back surface of the wafer. The wafer is diced to form a plurality of semiconductor devices.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a manufacturing method thereof, and particularly to a three-dimensional semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advancements in the materials and designs of integrated circuits have produced several generations of integrated circuits, with each generation having smaller and more complex circuits than the previous one.

[0003] As the number of electronic components on a single wafer has increased rapidly, three-dimensional integrated circuit layouts or stacked wafer designs have been used for certain semiconductor components to overcome the feature size and density limitations associated with two-dimensional layouts. Generally, in the design of three-dimensional integrated circuits, two or more semiconductor wafers are bonded together, and electrical connections are formed between the wafers. When manufacturing chip-to-chip electrical connections, a three-dimensional semiconductor structure is formed due to the stacked semiconductor devices. However, when the three-dimensional semiconductor structure operates, heat accumulation increases. How to increase the heat dissipation capacity of the three-dimensional semiconductor structure will help improve the operating efficiency and service life of the three-dimensional semiconductor structure. Summary of the Invention

[0004] An object of the present invention is to provide a three-dimensional semiconductor structure that can increase the heat dissipation capacity of the three-dimensional semiconductor structure, thereby effectively improving the operating efficiency and service life of the three-dimensional semiconductor structure.

[0005] According to an embodiment of the present disclosure, a manufacturing method of a three-dimensional semiconductor structure includes the following steps: providing a wafer, where the wafer includes a front side and a back side; adhering the front side of the wafer to a support substrate; coating a photoresist layer on the back side of the wafer; and etching the back side of the wafer to form a plurality of grooves on the back side of the wafer. The wafer is cut to form a plurality of semiconductor devices.

[0006] In some embodiments, each semiconductor device includes a plurality of cooling grooves formed by the grooves.

[0007] In some embodiments, the cooling grooves preferably horizontally penetrate the corresponding semiconductor device.

[0008] In some embodiments, the manufacturing method of the three-dimensional semiconductor structure further includes soldering a first semiconductor device of the semiconductor devices on an interposer, and the cooling grooves face the interposer.

[0009] In some embodiments, a method for manufacturing a three-dimensional semiconductor structure further includes welding a second semiconductor device on top of a first semiconductor device, and the cooling grooves of the second semiconductor device face the first semiconductor device.

[0010] In some embodiments, the interposer includes a front side and a back side, and the first semiconductor device is welded on top of the front side of the interposer.

[0011] In some embodiments, the front side of the interposer includes a plurality of grooves facing the first semiconductor device.

[0012] In some embodiments, the grooves on the front side of the interposer preferably horizontally penetrate the interposer.

[0013] In some embodiments, the back side of the interposer includes a plurality of grooves.

[0014] In some embodiments, the grooves on the back side of the interposer preferably horizontally penetrate the interposer.

[0015] According to another aspect of the present invention, a three-dimensional semiconductor structure is disclosed, which includes a first semiconductor device and a plurality of grooves. The first semiconductor device includes a front side and a back side, and the grooves are formed on the back side of the first semiconductor device to form a plurality of cooling grooves.

[0016] In some embodiments, the cooling grooves on the back side of the first semiconductor device preferably horizontally penetrate the first semiconductor device.

[0017] In some embodiments, the three-dimensional semiconductor structure further includes an interposer, the first semiconductor device is welded on top of the interposer, and the cooling grooves face the interposer.

[0018] In some embodiments, the three-dimensional semiconductor structure further includes a second semiconductor device, which is welded on top of the first semiconductor device, and the cooling grooves of the second semiconductor device face the first semiconductor device.

[0019] In some embodiments, the interposer includes a front side and a back side, and the first semiconductor device is welded on top of the front side of the interposer.

[0020] In some embodiments, the front side of the interposer includes a plurality of grooves facing the first semiconductor device.

[0021] In some embodiments, the grooves on the front side of the interposer preferably horizontally penetrate the interposer.

[0022] In some embodiments, the back side of the interposer includes a plurality of grooves.

[0023] In some embodiments, the grooves on the back side of the interposer preferably horizontally penetrate the interposer.

[0024] In some embodiments, the first semiconductor device includes a first dielectric layer, a first semiconductor layer, a second dielectric layer, a plurality of metal wires, a plurality of first microbumps, and a plurality of second microbumps. The first semiconductor layer is formed on the first dielectric layer, the second dielectric layer is formed on the first semiconductor layer, the metal wires are formed in the first dielectric layer, the first semiconductor layer, and the second dielectric layer, the first microbumps are formed on the surface of the first dielectric layer and are electrically connected to the metal wires, and the second microbumps are formed on the surface of the second dielectric layer and are electrically connected to the metal wires.

[0025] Therefore, the three-dimensional semiconductor structure can form cooling grooves in the semiconductor device through the grooves to increase the porosity in the wafer and allow the air flow to circulate, further increasing the heat dissipation efficiency when the semiconductor device operates. In addition, cooling grooves can also be formed on the front and / or back of the interposer to further increase the heat dissipation efficiency of the semiconductor device and the interposer during operation.

[0026] It should be understood that the foregoing general description and the following detailed description are merely exemplary and are intended to provide further explanation of the present disclosure. Description of the Drawings

[0027] To make the above and other objects, features, advantages, and embodiments of the present disclosure more apparent and understandable, the descriptions of the accompanying drawings are as follows:

[0028] Figures 1 to 7 Cross-sectional views at different stages of a method for manufacturing a three-dimensional semiconductor structure according to some embodiments of the present disclosure.

[0029] Figure 8 Cross-sectional view of a three-dimensional semiconductor structure according to some other embodiments of the present disclosure.

[0030] Figure 9 Flow chart of a three-dimensional semiconductor structure according to some embodiments of the present disclosure. Detailed Embodiments

[0031] The following will disclose multiple embodiments of the present disclosure with reference to the drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not used to limit the present disclosure. That is, in some embodiments of the present disclosure, these practical details are not necessary and thus are not used to limit the present disclosure. In addition, for the purpose of simplifying the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings. In addition, for the convenience of the reader, the dimensions of the elements in the drawings are not drawn in actual proportion.

[0032] Figures 1 to 7 Cross-sectional views at different stages of a method for manufacturing a three-dimensional semiconductor structure according to some embodiments of the present disclosure,Figure 8 FIG. 0 is a cross-sectional view of a three-dimensional semiconductor structure according to other embodiments of the present disclosure, and Figure 9 FIG. 1 is a schematic flow chart showing a method of manufacturing a three-dimensional semiconductor structure.

[0033] Referring to Figures 1 to 7 and Figure 9 , a method 1000 of manufacturing a three-dimensional semiconductor structure includes step 1010 of forming a plurality of microbumps on the back surface 201 of a wafer 200. Referring to Figure 1 and Figure 9 , which includes providing a wafer 200 having a front surface 203 and a back surface 201, and then adhering the front surface 203 of the wafer 200 to a support substrate 100 using an adhesive layer 210. Then, a plurality of second microbumps 290 are formed on the back surface 201 of the wafer 200.

[0034] The wafer 200 includes a first dielectric layer 220, a first semiconductor layer 230, a second dielectric layer 240, a plurality of metal wires 202, a plurality of first microbumps 250, and a plurality of second microbumps 290. The first semiconductor layer 230 is formed on the first dielectric layer 220, the second dielectric layer 240 is formed on the first semiconductor layer 230, and the metal wires 202 are formed in the first dielectric layer 220, the first semiconductor layer 230, and the second dielectric layer 240. In addition, the first microbumps 250 are formed on the surface of the first dielectric layer 220, such as the front surface 203 of the wafer 200, the first microbumps 250 are electrically connected to the metal wires 202, and the second microbumps 290 are formed on the surface of the second dielectric layer 240, such as the back surface 201 of the wafer 200, and the second microbumps 290 are electrically connected to the metal wires 202. In addition, a plurality of semiconductor elements 300 are formed on the first semiconductor layer 230 and are located in the first dielectric layer 220.

[0035] In some embodiments, the metal wires 202 include a first metal pad 260, a first conductive via 270 is connected to the first metal pad 260, and the first microbumps 250 are formed on the first metal pad 260. In addition, the metal wires 202 further include a second conductive via 280, and the second microbumps 290 are formed on the second conductive via 280 exposed in the second dielectric layer 240 to electrically connect the metal wires 202 and the first microbumps 250.

[0036] In some embodiments, the first dielectric layer 220 and the second dielectric layer 240 may comprise or be formed of at least one of dielectric materials, such as dielectric materials. Semiconductor carbides (such as silicon carbide (SiC)), semiconductor oxides (such as silicon dioxide (SiO2)), semiconductor nitrides (such as silicon nitride (SiN)), and semiconductor carbon oxides (such as silicon oxycarbide (SiOC)), although the present invention is not limited thereto.

[0037] In some embodiments, the metal wire 202, such as each of the first metal pad 260, the first conductive via 270, and / or the second conductive via 280, may be made of copper (Cu) and copper alloys. Copper (Cu) and copper alloys are used to replace aluminum (Al) and aluminum alloys in interconnect metallization. Copper is relatively inexpensive, easy to process, and has a lower resistivity than aluminum. In addition, compared to tungsten (W), copper has improved electrical properties, making copper an ideal metal for use as conductive plugs and conductive wirings. As used herein, copper is intended to cover high-purity elemental copper as well as copper-based alloys, such as copper alloys containing small amounts of tin, zinc, manganese, titanium, magnesium, and germanium, although the present invention is not limited thereto.

[0038] Then, in step 1020, referring to Figure 2 and Figure 9 , a photoresist layer 310 is coated on the back surface 201 of the wafer 200.

[0039] In step 1030, referring to Figure 3 and Figure 9 , a photomask 500 is provided to perform exposure and patterning of the photoresist layer 310.

[0040] In step 1040, referring to Figure 4 and Figure 9 , a plurality of grooves 320 are etched on the back surface 201 of the wafer 200 using dry etching, wherein the grooves 320 are formed as cooling grooves to increase the porosity in the wafer 200 and allow air flow to increase the heat dissipation efficiency.

[0041] In step 1050, referring to Figure 5 and Figure 9 , the photoresist layer 310 is removed and cleaned to expose the grooves 320 on the wafer 200, wherein the grooves 320 are cooling grooves to increase the porosity of the wafer 200 and allow air flow to increase the heat dissipation efficiency.

[0042] In some embodiments, the cooling grooves formed by the grooves 320 are preferably formed horizontally on the back surface 201 of the wafer 200.

[0043] In some embodiments, the groove 320 preferably etches through the second dielectric layer 240, more preferably etches into the first semiconductor layer 230, and the groove depth 501 of the groove 320 is preferably greater than the thickness of the second dielectric layer 240, more preferably greater than half of the sum of the thickness of the second dielectric layer 240 and the first semiconductor layer 230, i.e., 502. For example, the groove depth 501 of the groove 320 is approximately equal to 2 / 3 of the sum of the thickness of the second dielectric layer 240 and the first semiconductor layer 230, i.e., 502.

[0044] Step 1060, referring also to Figure 6 and Figure 9 , strip the wafer 200 and place it on the dicing frame 600 to dice the wafer 200 to form a plurality of semiconductor devices 700.

[0045] In some embodiments, the cooling groove formed by the groove 320 preferably horizontally penetrates through the semiconductor device 700.

[0046] Step 1070, referring also to Figure 7 and Figure 9 , the manufacturing method 1000 of this three-dimensional semiconductor structure further includes welding the first semiconductor device 701 of the semiconductor device 700 onto the interposer 800, and the groove 320 faces the interposer 800.

[0047] In addition, in some embodiments, the manufacturing method 1000 of the three-dimensional semiconductor structure further includes welding the second semiconductor device 702 onto the first semiconductor device 701, and the cooling groove of the second semiconductor device 702 faces the first semiconductor device 701.

[0048] In some embodiments, the interposer 800 includes a third dielectric layer 810, a second semiconductor layer 820, a fourth dielectric layer 830, a plurality of third microbumps 840, a plurality of fourth microbumps 890, and a plurality of metal wires 860.

[0049] The second semiconductor layer 820 is formed on the third dielectric layer 810, and the fourth dielectric layer 830 is formed on the second semiconductor layer 820.

[0050] In some embodiments, the third microbumps 840 are formed on the back surface 802 of the interposer 800, i.e., the surface of the third dielectric layer 810, and the fourth microbumps 890 are formed on the front surface 801 of the interposer 800, i.e., the surface of the fourth dielectric layer 830. In addition, the third microbumps 840 are electrically connected to the metal wires 860, and the fourth microbumps 890 are also electrically connected to the metal wires 860.

[0051] In some embodiments, the metal wire 860 further includes a fourth conductive via 850, a third conductive via 870, and a second metal pad 880. The third micro-bump 840 is connected to the fourth conductive via 850, and the fourth micro-bump 890 is connected to the second metal pad 880.

[0052] The second micro-bump 290 of the first semiconductor device 701 is soldered to the fourth micro-bump 890 of the interposer 800 to electrically connect the first semiconductor device 701 and the interposer 800.

[0053] In some embodiments, the three-dimensional semiconductor structure 10 includes a plurality of stacked semiconductor devices 700, such as including a first semiconductor device 701 and a second semiconductor device 702. The second semiconductor device 702 is stacked on top of the first semiconductor device 701, and the first semiconductor device 701 is fixed on top of the interposer 800 so that the first semiconductor device 701 and the second semiconductor device 702 are electrically connected to the interposer 800.

[0054] In some embodiments, the first semiconductor layer 230 and / or the second semiconductor layer 820 includes an elemental semiconductor (e.g., germanium or silicon), a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or a combination thereof.

[0055] Therefore, the three-dimensional semiconductor structure 10 disclosed in the present invention can form cooling grooves through the grooves 320 to increase the porosity in the wafer 200 and allow air flow to further increase the heat dissipation efficiency when the semiconductor device 700 is operating.

[0056] In addition, referring Figure 8 , as shown in the figure, in some embodiments, the three-dimensional semiconductor structure 20 also includes a plurality of stacked semiconductor devices 700, such as including a first semiconductor device 701 and a second semiconductor device 702. The second semiconductor device 702 is stacked on top of the first semiconductor device 701, and the first semiconductor device 701 is fixed on top of the interposer 900 so that the first semiconductor device 701 and the second semiconductor device 702 are electrically connected to the interposer 900.

[0057] In some embodiments, the interposer 900 includes a fifth dielectric layer 910, a third semiconductor layer 920, a sixth dielectric layer 930, a plurality of fifth micro-bumps 940, a plurality of sixth micro-bumps 990, and a plurality of metal wires 960.

[0058] The third semiconductor layer 920 is formed on the fifth dielectric layer 910, and the sixth dielectric layer 930 is formed on the third semiconductor layer 920.

[0059] In some embodiments, the fifth micro-bump 940 is formed on the back surface 902 of the interposer 900, i.e., the surface of the fifth dielectric layer 910, and the sixth micro-bump 990 is formed on the front surface 901 of the interposer 900, i.e., the surface of the sixth dielectric layer 930. In addition, the fifth micro-bump 940 is electrically connected to the metal wire 960, and the sixth micro-bump 990 is also electrically connected to the metal wire 960.

[0060] In some embodiments, the metal wire 960 further includes a sixth conductive via 950, a fifth conductive via 970, and a third metal pad 980. The fifth micro-bump 940 is connected to the sixth conductive via 950, and the sixth micro-bump 990 is connected to the third metal pad 980.

[0061] The second micro-bump 290 of the first semiconductor device 701 is soldered to the sixth micro-bump 990 of the interposer 900 to conduct the first semiconductor device 701 and the interposer 900.

[0062] In some embodiments, the interposer 900 includes a front surface 901 and a back surface 902, and the first semiconductor device 701 is soldered on the front surface 901 of the interposer 800. The front surface 901 of the interposer 900 further includes a plurality of grooves 410 to form cooling grooves facing the first semiconductor device 701.

[0063] In some embodiments, the grooves 410 of the interposer 900 preferably horizontally penetrate the interposer 900.

[0064] In some embodiments, the back surface 902 of the interposer 900 also includes a plurality of grooves 420 to form cooling grooves facing away from the first semiconductor device 701.

[0065] In some embodiments, the grooves 420 of the interposer 900 preferably horizontally penetrate the interposer 900.

[0066] In some embodiments, the grooves 420 of the interposer 900 are perpendicular to the grooves 410 of the interposer 900.

[0067] In some embodiments, the grooves 420 of the interposer 900 are parallel to the grooves 410 of the interposer 900.

[0068] Therefore, the three-dimensional semiconductor structure 20 disclosed in the present invention can form cooling grooves in the semiconductor device 700 through the grooves 320 to increase the porosity in the wafer 200 and allow air flow to circulate, further increasing the heat dissipation efficiency when the semiconductor device 700 operates. In addition, cooling grooves can also be formed on the front surface 901 and / or the back surface 902 of the interposer 900 to further increase the heat dissipation efficiency of the semiconductor device 700 and the interposer 900 during operation.

[0069] In some embodiments, the groove 420 preferably etches through the fifth dielectric layer 910, more preferably etches into the third semiconductor layer 920, and the groove depth 503 of the groove 420 is preferably greater than the thickness of the fifth dielectric layer 910, more preferably greater than half of the sum of the thickness of the fifth dielectric layer 910 and the thickness 504 of the third semiconductor layer 920. For example, the groove depth 503 of the groove 420 is approximately equal to 2 / 3 of the sum of the thickness of the fifth dielectric layer 910 and the thickness 504 of the third semiconductor layer 920.

[0070] In some embodiments, the groove 410 preferably etches a portion of the sixth dielectric layer 930, and the groove depth 505 of the groove 410 is preferably greater than half of the thickness 506 of the sixth dielectric layer 930. For example, the groove depth 505 of the groove 410 is approximately equal to 2 / 3 of the thickness 506 of the sixth dielectric layer 930.

[0071] In some embodiments, the metal wire is made of copper (Cu) and copper alloy. Copper (Cu) and copper alloy are used to replace aluminum (Al) and aluminum alloy in the interconnect metallization. Copper is relatively inexpensive, easy to process, and has a lower resistivity than aluminum. In addition, compared with tungsten (W), copper has improved electrical properties, making copper an ideal metal for use as conductive plugs and conductive wirings. As used herein, copper is intended to cover high-purity elemental copper as well as copper-based alloys, such as copper alloys containing small amounts of tin, zinc, manganese, titanium, magnesium, and germanium, but the present invention is not limited thereto.

[0072] In some embodiments, the dielectric layer can be formed of or by at least one of dielectric materials, such as dielectric materials. Semiconductor carbides (such as silicon carbide (SiC)), semiconductor oxides (such as silicon dioxide (SiO2)), semiconductor nitrides (such as silicon nitride (SiN)), and semiconductor carbon oxides (such as silicon oxycarbide (SiOC)), but the present invention is not limited thereto.

[0073] Therefore, the three-dimensional semiconductor structure disclosed in the present invention can form cooling grooves in the semiconductor device through the grooves to increase the porosity in the wafer and allow air flow to circulate, further increasing the heat dissipation efficiency when the semiconductor device operates. In addition, cooling grooves can also be formed on the front surface and / or the back surface of the interposer to further increase the heat dissipation efficiency of the semiconductor device and the interposer during operation.

[0074] Although the embodiments have been disclosed in detail above, other embodiments are possible and are not intended to limit the disclosure. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments of the disclosure.

[0075] Those skilled in the art can make various changes or substitutions without departing from the spirit and scope of the disclosure. Therefore, all such changes or substitutions should be covered by the scope of protection of the appended claims of the disclosure.

[0076]

Symbol Description

[0077] 10: Three-dimensional semiconductor structure

[0078] 20: Three-dimensional semiconductor structure

[0079] 100: Support substrate

[0080] 200: Wafer

[0081] 201: Back side

[0082] 202: Metal wire

[0083] 203: Front side

[0084] 210: Adhesive layer

[0085] 220: First dielectric layer

[0086] 230: First semiconductor layer

[0087] 240: Second dielectric layer

[0088] 250: First micro-bump

[0089] 260: First metal pad

[0090] 270: First conductive via

[0091] 280: Second conductive via

[0092] 290: Second micro-bump

[0093] 300: Semiconductor element

[0094] 310: Photoresist layer

[0095] 320: Groove

[0096] 410: Groove

[0097] 420: Groove

[0098] 500: Photomask

[0099] 501: Groove depth

[0100] 502: Thickness

[0101] 503: Groove depth

[0102] 504: Thickness

[0103] 505: Groove depth

[0104] 506: Thickness

[0105] 600: Cutting frame

[0106] 700: Semiconductor device

[0107] 701: First semiconductor device

[0108] 702: Second semiconductor device

[0109] 800: Interposer

[0110] 801: Front side

[0111] 802: Back side

[0112] 810: Third dielectric layer

[0113] 820: Second semiconductor layer

[0114] 830: Fourth dielectric layer

[0115] 840: Third microbump

[0116] 850: Fourth conductive via

[0117] 860: Metal wire

[0118] 870: Third conductive via

[0119] 880: Second metal pad

[0120] 890: Fourth microbump

[0121] 900: Interposer

[0122] 901: Front side

[0123] 902: Back side

[0124] 910: Fifth dielectric layer

[0125] 920: Third semiconductor layer

[0126] 930: Sixth dielectric layer

[0127] 940: Fifth microbump

[0128] 950: The sixth conductive via hole

[0129] 960: Metal wire

[0130] 970: The fifth conductive via hole

[0131] 980: The third metal pad

[0132] 990: The sixth micro bump

[0133] 1000: Method for manufacturing a three-dimensional semiconductor structure

[0134] Steps: 1010 to 1070.

Claims

1. A manufacturing method of a three-dimensional semiconductor structure, characterized in that, Comprising: Providing a wafer, wherein the wafer comprises a front side and a back side; Adhering the front side of the wafer to a support substrate; Coating a photoresist layer on the back side of the wafer; Etching the back side of the wafer to form a plurality of grooves on the back side of the wafer; And Dicing the wafer to form a plurality of semiconductor devices.

2. The method of manufacturing a three-dimensional semiconductor structure according to claim 1, wherein each of the plurality of semiconductor devices comprises a plurality of cooling grooves formed by the plurality of grooves.

3. The method of manufacturing a three-dimensional semiconductor structure according to claim 2, wherein the plurality of cooling grooves horizontally penetrate the corresponding semiconductor device.

4. The manufacturing method of the three-dimensional semiconductor structure according to claim 3, wherein, Further comprising: Welding a first semiconductor device of the plurality of semiconductor devices on top of an interposer, and the plurality of cooling grooves face the interposer.

5. The manufacturing method of the three-dimensional semiconductor structure according to claim 4, wherein, Further comprising: Welding a second semiconductor device on top of the first semiconductor device, and the cooling grooves of the second semiconductor device face the first semiconductor device.

6. The method of manufacturing a three-dimensional semiconductor structure according to claim 4, wherein the interposer comprises a front side and a back side, and the first semiconductor device is welded on top of the front side of the interposer.

7. The method of manufacturing a three-dimensional semiconductor structure according to claim 6, wherein the front side of the interposer comprises a plurality of grooves facing the first semiconductor device.

8. The method of manufacturing a three-dimensional semiconductor structure according to claim 7, wherein the plurality of grooves of the interposer horizontally penetrate the interposer.

9. The method of manufacturing a three-dimensional semiconductor structure according to claim 6, wherein the back side of the interposer comprises a plurality of grooves.

10. The method of manufacturing a three-dimensional semiconductor structure according to claim 9, wherein the plurality of grooves of the interposer horizontally penetrate the interposer.

11. A three-dimensional semiconductor structure, characterized in that, Comprising: A first semiconductor device, comprising a front side and a back side; and A plurality of grooves formed on the back side of the first semiconductor device to form a plurality of cooling grooves.

12. The three-dimensional semiconductor structure according to claim 11, wherein the plurality of cooling grooves horizontally penetrate the first semiconductor device.

13. The three-dimensional semiconductor structure according to claim 11, wherein, Further comprising: An interposer, wherein the first semiconductor device is welded on top of the interposer, and the plurality of cooling grooves face the interposer.

14. The three-dimensional semiconductor structure according to claim 13, wherein, Further comprising: A second semiconductor device, welded on top of the first semiconductor device, and the cooling grooves of the second semiconductor device face the first semiconductor device.

15. The three-dimensional semiconductor structure according to claim 13, wherein the interposer comprises a front side and a back side, and the first semiconductor device is welded on top of the front side of the interposer.

16. The three-dimensional semiconductor structure according to claim 15, wherein the front side of the interposer comprises a plurality of grooves facing the first semiconductor device.

17. The three-dimensional semiconductor structure according to claim 16, wherein the plurality of grooves of the interposer horizontally penetrate the interposer.

18. The three-dimensional semiconductor structure according to claim 15, wherein the back side of the interposer comprises a plurality of grooves.

19. The three-dimensional semiconductor structure according to claim 18, wherein the plurality of grooves of the interposer horizontally penetrate the interposer.

20. The three-dimensional semiconductor structure according to claim 11, wherein the first semiconductor device comprises: a first dielectric layer; a first semiconductor layer formed on the first dielectric layer; a second dielectric layer formed on the first semiconductor layer; a plurality of metal wires formed in the first dielectric layer, the first semiconductor layer, and the second dielectric layer; a plurality of first micro-bumps formed on the surface of the first dielectric layer and electrically connected to the plurality of metal wires; and a plurality of second micro-bumps formed on the surface of the second dielectric layer and electrically connected to the plurality of metal wires.

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