Semiconductor device, vibration device, and method for manufacturing

Abstract

A semiconductor device includes: a semiconductor substrate having a first surface and a second surface which are in a front-back relationship with each other, and in which a through-hole penetrating the first surface and the second surface is formed; a semiconductor circuit disposed on the second surface side of the semiconductor substrate and including a conductive layer exposed in the through hole; and a first wiring which is disposed on the inner peripheral surface of the through-hole, and which has a film thickness at the central portion of the through-hole that is thicker than the film thickness at the edge portion of the through-hole.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a vibration device, and a method for manufacturing a semiconductor device. Background Art

[0002] For example, the semiconductor device described in Patent Document 1 includes: a semiconductor substrate having an upper surface and a lower surface that are in a front-back relationship, and having a through hole penetrating through these two surfaces; a first conductive layer disposed on the lower surface of the semiconductor substrate and exposed in the through hole; an insulating layer disposed on the inner wall of the through hole; an organic insulating layer disposed on the insulating layer; and a wiring disposed on the organic insulating layer and electrically connected to the first conductive layer through a second opening portion provided in the organic insulating layer. Further, the wiring extends from inside the through hole to the upper surface of the semiconductor substrate.

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2018-113466

[0004] However, in such a structure, it is difficult to ensure the thickness of the wiring in the through hole, and disconnection of the wiring in the through hole is likely to occur. Summary of the Invention

[0005] The semiconductor device of the present invention includes:

[0006] a semiconductor substrate having a first surface and a second surface that are in a front-back relationship, and having a through hole penetrating through the first surface and the second surface;

[0007] a semiconductor circuit disposed on the second surface side of the semiconductor substrate and having a conductive layer exposed in the through hole; and

[0008] a first wiring disposed on the inner peripheral surface of the through hole and having a film thickness at the central portion of the through hole thicker than that at the edge portion.

[0009] The vibration device of the present invention includes:

[0010] the above-described semiconductor device; and

[0011] a vibration element bonded to the semiconductor device and electrically connected to the semiconductor circuit.

[0012] The method for manufacturing a semiconductor device of the present invention includes:

[0013] a preparation step of preparing a base material having a semiconductor substrate and a semiconductor circuit, the semiconductor substrate having a first surface and a second surface that are in a front-back relationship, and having a through hole penetrating through the first surface and the second surface, the semiconductor circuit being disposed on the second surface side of the semiconductor substrate and having a conductive layer exposed in the through hole;

[0014] First wiring formation process: A first wiring is formed in the through hole by electroplating treatment. The first wiring is electrically connected to the conductive layer, and the film thickness at the central part of the through hole is thicker than that at the edge part. Description of the drawings

[0015] Figure 1 It is a cross-sectional view showing a vibration device according to the first embodiment.

[0016] Figure 2 It is an enlarged cross-sectional view of a through hole formed in a semiconductor substrate.

[0017] Figure 3 It is an enlarged cross-sectional view of a through hole formed in a semiconductor substrate.

[0018] Figure 4 It is an enlarged cross-sectional view of a through hole formed in a semiconductor substrate.

[0019] Figure 5 It is a top view showing the upper surface of a semiconductor device.

[0020] Figure 6 It is a cross-sectional view of a semiconductor device.

[0021] Figure 7 It is a top view showing a vibration element.

[0022] Figure 8 It is a cross-sectional view for explaining a method of forming a bonding member.

[0023] Figure 9 It is a cross-sectional view for explaining problems in electroplating treatment.

[0024] Figure 10 It is a flowchart showing a manufacturing process of a vibration device.

[0025] Figure 11 It is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0026] Figure 12 It is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0027] Figure 13 It is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0028] Figure 14 It is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0029] Figure 15 It is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0030] Figure 16 It is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0031] Figure 17 is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0032] Figure 18 is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0033] Figure 19 is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0034] Figure 20 is a cross-sectional view for explaining a manufacturing method of a vibration device.

[0035] Figure 21 is a cross-sectional view showing a vibration device according to a second embodiment.

[0036] Figure 22 is a cross-sectional view showing a state where the vibration device shown in Figure 21 is mounted on a mounting substrate.

[0037] Explanation of Reference Numerals

[0038] 1: Vibration device; 100: Mounting substrate; 2: Semiconductor device; 3: Vibration element; 31: Vibration substrate; 321: Excitation electrode; 322: Excitation electrode; 323: Terminal; 324: Terminal; 325: Wiring; 326: Wiring; 4: Cover; 40: Bonding member; 41: Recess; 5: Semiconductor substrate; 5a: Upper surface; 5b: Lower surface; 5c: Demarcation part; 51: Through-hole; 52: Through-hole; 60: Insulating film; 611: First organic resin film; 612: First organic resin film; 621: Second organic resin film; 622: Second organic resin film; 7: Semiconductor circuit; 70: Oscillation circuit; 700: Element; 71: Laminate; 72: Wiring layer; 721: Electrode pad; 722: Electrode pad; 73: Insulating layer; 74: Passivation film; 75: Terminal layer; 751: External terminal; 752: Internal terminal; 753: Internal terminal; 8A: Wiring; 8B: Wiring; 811: First wiring; 811a: Recess; 812: First wiring; 812a: Recess; 821: Second wiring; 821a: Internal terminal; 821b: Wiring layer; 821c: Coating layer; 822: Second wiring; 822a: Internal terminal; 822b: Wiring layer; 822c: Coating layer; B1: Bonding member; B2: Bonding member; D: Depth; G: Gap; L: Electroplating solution; M: Mask; P: Package; Q: Abnormal part; S: Accommodation space; S1: Preparation process; S2: First wiring formation process; S3: Second wiring formation process; S4: Bonding member formation process; S5: Vibration element bonding process; S6: Cover bonding process; T1: Film thickness; T2: Film thickness. Detailed Embodiments

[0039] Next, a semiconductor device, a vibration device, and a method for manufacturing a semiconductor device according to the present invention will be described in detail according to the embodiments shown in the drawings.

[0040] First Embodiment

[0041] Figure 1 FIG. is a cross-sectional view of a vibration device according to the first embodiment. Figures 2 to 4 FIGS. are enlarged cross-sectional views of through holes formed in a semiconductor substrate, respectively. Figure 5 FIG. is a top view of the upper surface of a semiconductor device. Figure 6 FIG. is a cross-sectional view of a semiconductor device. Figure 7 FIG. is a top view of a vibration element. Figure 8 FIG. is a cross-sectional view for explaining a method of forming a bonding member. Figure 9 FIG. is a cross-sectional view for explaining problems in electroplating treatment. Figure 10 FIG. is a flowchart showing a manufacturing process of a vibration device. Figures 11 to 20 FIGS. are cross-sectional views for explaining a method of manufacturing a vibration device, respectively. For the sake of convenience in explanation, in each drawing, three mutually orthogonal axes are shown as the X-axis, Y-axis, and Z-axis. Also, the side toward which the arrow in the Z-axis direction points is also referred to as "upper", and the opposite side is also referred to as "lower". Also, the top view from the Z-axis direction is simply referred to as "top view".

[0042] As Figure 1 shown, the vibration device 1 includes a semiconductor device 2, a vibration element 3 disposed on the upper surface of the semiconductor device 2, and a lid 4 that covers the vibration element 3 and is joined to the upper surface of the semiconductor device 2. In such a vibration device 1, a package P is formed by the semiconductor device 2 and the lid 4, and the vibration element 3 is housed in a housing space S of the package P.

[0043] Semiconductor Device 2

[0044] As Figure 1 shown, the semiconductor device 2 includes a semiconductor substrate 5. The semiconductor substrate 5 is a silicon substrate. However, there is no particular limitation on the semiconductor substrate 5, and a substrate made of a semiconductor material other than silicon such as Ge, GaP, GaAs, InP, etc. may also be used. Further, the semiconductor substrate 5 has an upper surface 5a as a first surface and a lower surface 5b as a second surface, which are in a front-back relationship. Also, a pair of through holes 51, 52 penetrating the upper surface 5a and the lower surface 5b are formed in the semiconductor substrate 5. The through holes 51, 52 can be formed by, for example, RIE (Reactive Ion Etching). Thereby, through holes 51, 52 having a high aspect ratio can be formed. However, there is no particular limitation on the method of forming the through holes 51, 52.

[0045] Moreover, the semiconductor device 2 has insulating films 60 formed on the upper surface 5a and the lower surface 5b of the semiconductor substrate 5. The insulating film 60 formed on the upper surface 5a enters into the through holes 51 and 52 and is also formed at the upper end portions of the through holes 51 and 52. The insulating film 60 is made of, for example, silicon dioxide (SiO2). The insulating film 60 can be formed by, for example, sputtering. However, the constituent material and the forming method of the insulating film 60 are not particularly limited.

[0046] Moreover, the semiconductor device 2 has a semiconductor circuit 7 formed on the lower surface 5b side of the semiconductor substrate 5 and electrically connected to the vibration element 3. The semiconductor circuit 7 includes an oscillation circuit 70 that oscillates the vibration element 3 and generates the frequency of a reference signal such as a clock signal. Thus, the vibration device 1 becomes an oscillator, and high versatility and demand can be expected.

[0047] The semiconductor circuit 7 has a plurality of elements 700 formed on the lower surface 5b of the semiconductor substrate 5 and a stacked body 71 stacked on the lower surface 5b of the semiconductor substrate 5. The stacked body 71 has a wiring layer 72 formed on the lower surface 5b of the semiconductor substrate 5, an insulating layer 73 formed on the lower surface of the wiring layer 72, a passivation film 74 formed on the lower surface of the insulating layer 73, and a terminal layer 75 formed on the lower surface of the passivation film 74. Moreover, the plurality of elements 700 are electrically connected to each other through the wirings included in the wiring layer 72 and the through electrodes penetrating between the layers to constitute the oscillation circuit 70. The elements 700 are, for example, transistors, resistors, capacitor elements, etc.

[0048] In this way, by forming the semiconductor circuit 7 on the semiconductor substrate 5, the space of the semiconductor substrate 5 can be effectively utilized. Moreover, since the semiconductor circuit 7 can be integrally formed with the vibration device 1, miniaturization of the entire device can also be achieved. In particular, by forming the semiconductor circuit 7 on the lower surface 5b side, compared with the case where the semiconductor circuit 7 is formed on the upper surface 5a side, there is no bonding region with the lid 4, and the formable region of the semiconductor circuit 7 is correspondingly widened. Therefore, the degree of freedom in designing the semiconductor circuit 7 is increased.

[0049] In addition, in the present embodiment, the stacked body 71 includes one wiring layer 72, but is not limited thereto, and a plurality of wiring layers 72 may be stacked with the insulating layer 73 interposed therebetween. That is, the wiring layer 72 and the insulating layer 73 may be alternately stacked multiple times between the semiconductor substrate 5 and the passivation film 74. Thereby, the degree of freedom in routing the wirings is improved, and circuit design becomes easy.

[0050] Further, the wiring layer 72 has electrode pads 721, which are conductive layers and overlap with the through-holes 51 and are exposed within the through-holes 51, and electrode pads 722, which are conductive layers and overlap with the through-holes 52 and are exposed within the through-holes 52. Further, the terminal layer 75 has a plurality of external terminals 751 for connecting the semiconductor circuit 7 to an external device. Each external terminal 751 penetrates the insulating layer 73 and the passivation film 74 and is electrically connected to the wiring layer 72.

[0051] In addition, as Figures 1 to 3 shown, the semiconductor device 2 has first organic resin films 611 and 612 disposed within the through-holes 51 and 52. The first organic resin films 611 and 612 each have insulating properties. Further, the first organic resin film 611 is disposed on the inner peripheral surface of the through-hole 51 and covers the inner peripheral surface of the through-hole 51. Similarly, the first organic resin film 612 is disposed on the inner peripheral surface of the through-hole 52 and covers the inner peripheral surface of the through-hole 52. Thus, by covering the inner peripheral surfaces of the through-holes 51 and 52 with the first organic resin films 611 and 612, the first wirings 811 and 812 and the semiconductor substrate 5 described later can be more reliably insulated.

[0052] Further, the first organic resin films 611 and 612 extend from the upper openings of the through-holes 51 and 52 to the upper surface 5a and cover the boundary portion 5c between the through-holes 51 and 52 and the upper surface 5a. Further, the surfaces of the portions of the first organic resin films 611 and 612 covering the boundary portion 5c are arc-shaped. In addition, within the through-holes 51 and 52, the inner peripheral surfaces of the first organic resin films 611 and 612 are formed in a conical shape with the inner diameter gradually decreasing from the upper side to the lower side.

[0053] There is no particular limitation on the constituent material of such first organic resin films 611 and 612, and for example, polyimide resin, epoxy resin, etc. can be used.

[0054] As Figures 1 to 3 shown, the semiconductor device 2 further has first wirings 811 and 812, which are disposed within the through-holes 51 and 52 and are electrically connected to the electrode pads 721 and 722. The first wiring 811 is disposed on the inner peripheral surface of the first organic resin film 611 within the through-hole 51 and is electrically connected to the electrode pad 721 through the lower opening of the through-hole 51. The first wiring 811 is disposed within the inner peripheral surface of the through-hole 51. Further, within the through-hole 51, the first organic resin film 611 is disposed between the inner peripheral surface of the through-hole 51 and the first wiring 811. Similarly, the first wiring 812 is disposed on the inner peripheral surface of the first organic resin film 612 within the through-hole 52 and is electrically connected to the electrode pad 722 through the lower opening of the through-hole 52. The first wiring 812 is disposed within the inner peripheral surface of the through-hole 52. Further, within the through-hole 52, the first organic resin film 612 is disposed between the inner peripheral surface of the through-hole 52 and the first wiring 812.

[0055] Moreover, the first wirings 811 and 812 are configured to be filled in the through-holes 51 and 52 and cover the bottoms of the through-holes 51 and 52. Also, within the through-holes 51 and 52, the film thickness T2 of the first wirings 811 and 812 at the central portions of the through-holes 51 and 52 is thicker than the film thickness T1 at the edge portions. That is, T2 > T1. By configuring the first wirings 811 and 812 in this manner, first wirings 811 and 812 with a sufficient thickness can be formed within the through-holes 51 and 52, and disconnection of the first wirings 811 and 812 within the through-holes 51 and 52 can be effectively suppressed.

[0056] Moreover, recessed portions 811a and 812a that recess into the through-holes 51 and 52 are formed on the upper surfaces of the first wirings 811 and 812. Therefore, the film thickness T2 of the first wirings 811 and 812 at the central portions of the through-holes 51 and 52 is thinner than the depth D of the through-holes 51 and 52. That is, T2 < D. Thereby, it is possible to prevent the through-holes 51 and 52 from being completely filled by the first wirings 811 and 812. For example, when, as Figure 4 shown, T2 ≥ D, resulting in the through-holes 51 and 52 being completely filled by the first wirings 811 and 812, the thermal stress applied to the semiconductor substrate 5 due to the thermal expansion of the first wirings 811 and 812 within the through-holes 51 and 52 increases excessively, and depending on the strength of the semiconductor substrate 5, the semiconductor substrate 5 may be damaged. Therefore, in the present embodiment, by forming the recessed portions 811a and 812a and setting T2 < D, the thermal stress applied to the semiconductor substrate 5 is suppressed to a small level. Thereby, breakage of the semiconductor substrate 5 is effectively suppressed, and the vibration device 1 with high reliability is achieved.

[0057] The film thickness T2 is not particularly limited. For example, it is preferably 50% or more and 90% or less of the depth D, more preferably 60% or more and 80% or less. That is, preferably 0.5D ≤ T2 ≤ 0.9D, more preferably 0.6D ≤ T2 ≤ 0.8D. By configuring it in this manner, first wirings 811 and 812 with a sufficient thickness can be formed within the through-holes 51 and 52, and the thermal stress applied to the semiconductor substrate 5 due to the thermal expansion of the first wirings 811 and 812 within the through-holes 51 and 52 can be suppressed to a sufficiently small level.

[0058] The recessed portions 811a and 812a are shallower than the through-holes 51 and 52, and the inclination is gentler than the inner peripheral surfaces of the through-holes 51 and 52. Therefore, the reachable area for sputtering when forming the second wirings 821 and 822 described later can be ensured, and the second wirings 821 and 822 can be formed with good precision.

[0059] Further, the first wirings 811 and 812 extend out from the upper openings of the through-holes 51 and 52 to the upper surface 5a and extend all the way to the outside of the first organic resin films 611 and 612. Additionally, as described above, the portions of the first organic resin films 611 and 612 covering the boundary portion 5c have arcs, so it is easy to form the first wirings 811 and 812 on the boundary portion 5c, and it is possible to effectively suppress defective formation, damage, disconnection, etc. of the first wirings 811 and 812 at this portion. Also, the first wirings 811 and 812 cover the through-holes 51 and 52. Moreover, the portions of the first wirings 811 and 812 extending out to the upper surface 5a surround the through-holes 51 and 52 in a top view.

[0060] The first wirings 811 and 812 are electroplated wirings formed by electrolytic plating treatment. In this way, by forming the first wirings 811 and 812 through electrolytic plating treatment, it is easy to form relatively thick first wirings 811 and 812, and it is possible to effectively suppress the disconnection of the first wirings 811 and 812 in the through-holes 51 and 52. Also, high interlayer adhesion can be achieved. However, as the plating treatment, it is not limited to electrolytic plating treatment, and the first wirings 811 and 812 can also be formed by electroless plating treatment.

[0061] Here, in the electrolytic plating treatment, a seed layer for promoting the growth of plating is formed in the through-holes 51 and 52 and on the upper surface 5a by sputtering. Therefore, in the present embodiment, as described above, the inner peripheral surfaces of the first organic resin films 611 and 612 are made conical to ensure the reachable area of sputtering when forming the seed layer. As a result, the seed layer can be formed with a desired thickness in the entire area, and thus the first wirings 811 and 812 can be formed with good precision.

[0062] There is no particular limitation on the constituent material of such first wirings 811 and 812. For example, copper (Cu) can be used. Additionally, the constituent material being copper (Cu) means using copper (Cu) as the main material, and as long as copper (Cu) is used as the main material, other materials can also be added. Also, there is no particular limitation on the structure of the seed layer. For example, it can be a laminate of a base layer made of a titanium / tungsten alloy (TiW) and a surface layer made of copper (Cu).

[0063] As Figures 1 to 3 shown, the semiconductor device 2 also has second wirings 821 and 822 disposed on the upper surface 5a of the semiconductor substrate 5. The second wiring 821 overlaps with the first wiring 811 from above, thereby being electrically connected to the first wiring 811. Also, the first wiring 811 and the second wiring 821 form a wiring 8A. Similarly, the second wiring 822 overlaps with the first wiring 812 from above, thereby being electrically connected to the first wiring 812. Also, the first wiring 812 and the second wiring 822 form a wiring 8B.

[0064] Also, as Figure 5 shown, the second wirings 821 and 822 have internal terminals 821a and 822a disposed at one end thereof for joining the vibration element 3.

[0065] Also, the second wirings 821 and 822 are also disposed on the through-holes 51 and 52 and cover the first wirings 811 and 812. Thus, the exhaust gas generated from the first wirings 811 and 812 can be sealed in the through-holes 51 and 52 by the second wirings 821 and 822. Therefore, the environmental change in the storage space S, particularly the pressure increase, caused by the exhaust gas can be suppressed. Therefore, the vibration characteristics of the vibration element 3 are stable, and the vibration device 1 with high reliability is obtained. Particularly in the present embodiment, since the second wirings 821 and 822 cover the entire first wirings 811 and 812, the above effects are more obvious. In addition, since the first wirings 811 and 812 as electroplated wirings contain a large amount of moisture and are likely to generate exhaust gas, the above effects are also more obvious in this regard.

[0066] The second wirings 821 and 822 are sputtering wirings formed by sputtering. And the surface roughness of the second wirings 821 and 822 is smaller than that of the first wirings 811 and 812, and the thickness is thinner. By forming the second wirings 821 and 822 by sputtering, the generation of exhaust gas from the second wirings 821 and 822 can be suppressed. Therefore, the environmental change in the storage space S, particularly the pressure increase, can be suppressed. And the second wirings 821 and 822 become a fine film, and the exhaust gas generated from the first wirings 811 and 812 can be more reliably sealed in the through-holes 51 and 52. In addition, as described above, a part of the through-holes 51 and 52 is buried by the first wirings 811 and 812, and concave portions 811a and 812a shallower and gentler than the through-holes 51 and 52 are formed on the surface thereof. Therefore, the reachable area of sputtering can be ensured, and the second wirings 821 and 822 can be formed with good precision. Therefore, the second wirings 821 and 822 can more reliably cover the entire area of the first wirings 811 and 812.

[0067] As Figure 2 and Figure 3As shown, the second wirings 821 and 822 are composed of a laminate of wiring layers 821b and 822b, and coating layers 821c and 822c that cover the wiring layers 821b and 822b. Further, the wiring layers 821b and 822b are composed of a laminate of a base layer made of a titanium / tungsten alloy (TiW) and a wiring layer made of copper (Cu), but not shown. Further, the coating layers 821c and 822c are composed of a laminate of a base layer made of titanium (Ti) and a surface layer made of gold (Au), but not shown. In this way, by covering the outermost layer of the second wirings 821 and 822 with a surface layer made of gold (Au), deterioration of electrical characteristics due to oxidation of the second wirings 821 and 822 can be effectively suppressed.

[0068] As Figure 6 shown, the semiconductor device 2 further includes second organic resin films 621 and 622 disposed on the upper surface 5a of the semiconductor substrate 5. The second organic resin films 621 and 622 each have insulation properties. The second organic resin film 621 is interposed between the upper surface 5a and the internal terminal 821a of the second wiring 821. In other words, the internal terminal 821a is formed on the second organic resin film 621 and covers the second organic resin film 621. Similarly, the second organic resin film 622 is interposed between the upper surface 5a and the internal terminal 822a of the second wiring 822. In other words, the internal terminal 822a is formed on the second organic resin film 622 and covers the second organic resin film 622.

[0069] As a constituent material of such second organic resin films 621 and 622, there is no particular limitation, and for example, polyimide resin, epoxy resin, etc. can be used in the same manner as the aforementioned first organic resin films 611 and 612.

[0070] Cover body 4

[0071] As Figure 1 shown, the cover body 4 has a bottomed recess 41 that is open on its lower surface and houses the vibration element 3 inside. Further, the cover body 4 is joined to the upper surface of the semiconductor device 2, that is, the upper surface 5a of the semiconductor substrate 5, by a joining member 40 on its lower surface. Thereby, a storage space S for housing the vibration element 3 is formed between the cover body 4 and the semiconductor device 2. The storage space S is airtight and is formed in a reduced pressure state, preferably a state closer to a vacuum state. Thereby, viscous resistance is reduced and the oscillation characteristics of the vibration element 3 are improved. However, the atmosphere of the storage space S is not particularly limited.

[0072] The lid 4 is a silicon substrate similar to the semiconductor substrate 5. Thus, the linear expansion coefficients of the semiconductor substrate 5 and the lid 4 are the same, suppressing the generation of thermal stress due to thermal expansion, and becoming the vibration device 1 having good vibration characteristics. Also, since the vibration device 1 can be formed by semiconductor processes, the vibration device 1 can be manufactured with good precision and its miniaturization can be achieved. However, the lid 4 is not particularly limited. For example, a substrate made of a semiconductor material other than silicon such as Ge, GaP, GaAs, InP, etc. may also be used.

[0073] Vibration element 3

[0074] As Figure 7 shown, the vibration element 3 has a vibration substrate 31 and electrodes disposed on the surface of the vibration substrate 31. The vibration substrate 31 has a thickness-shear vibration mode and is formed of an AT-cut crystal substrate in the present embodiment. Since the AT-cut crystal substrate has three-dimensional frequency-temperature characteristics, the vibration element 3 having good temperature characteristics is obtained. Also, the electrodes have an exciting electrode 321 disposed on the upper surface of the vibration substrate 31 and an exciting electrode 322 disposed opposite to the exciting electrode 321 on the lower surface. Also, the electrodes have a pair of terminals 323, 324 disposed on the lower surface of the vibration substrate 31, a wiring 325 electrically connecting the terminal 323 and the exciting electrode 321, and a wiring 326 electrically connecting the terminal 324 and the exciting electrode 322.

[0075] In addition, the structure of the vibration element 3 is not limited to the above structure. For example, the vibration element 3 may be formed in a mesa shape in which the vibration region sandwiched between the exciting electrodes 321, 322 protrudes from its periphery. Conversely, it may also be formed in an inverse mesa shape in which the vibration region is recessed from its periphery. Also, bevel processing for grinding the periphery of the vibration substrate 31 and convex surface processing for making the upper and lower surfaces into convex curved surfaces may be performed.

[0076] Also, as the vibration element 3, it is not limited to a vibration element that vibrates in a thickness-shear vibration mode. For example, it may also be a vibration element in which a plurality of vibration arms bend and vibrate in the in-plane direction. That is, the vibration substrate 31 is not limited to a vibration substrate formed of an AT-cut crystal substrate, and may also be formed of a crystal substrate other than an AT-cut crystal substrate, such as an X-cut crystal substrate, a Y-cut crystal substrate, a Z-cut crystal substrate, a BT-cut crystal substrate, an SC-cut crystal substrate, an ST-cut crystal substrate, etc. Also, in the present embodiment, the vibration substrate 31 is made of crystal, but it is not limited thereto. For example, it may also be made of a piezoelectric single crystal such as lithium niobate, lithium tantalate, lithium tetraborate, lanthanum gallium silicate, potassium niobate, gallium phosphate, etc., or may also be made of a piezoelectric single crystal other than these. In addition, the vibration element 3 is not limited to a piezoelectric drive type vibration element, and may also be an electrostatic drive type vibration element that uses electrostatic force.

[0077] Such a vibration element 3, as shown in Figure 6 , is joined to the internal terminals 821a and 822a by conductive joining members B1 and B2. Also, the joining member B1 electrically connects the internal terminal 821a and the terminal 323, and the joining member B2 electrically connects the internal terminal 822a and the terminal 324. Thus, the vibration element 3 and the semiconductor circuit 7 are electrically connected by the joining members B1 and B2 and the wirings 8A and 8B.

[0078] Such joining members B1 and B2 are microbumps formed by electrolytic plating treatment. Thus, by forming the joining members B1 and B2 by electrolytic plating treatment, it is possible to form the minute joining members B1 and B2. Therefore, miniaturization of the vibration device 1 can be achieved. However, the plating treatment is not limited to electrolytic plating treatment, and the joining members B1 and B2 may be formed by electroless plating treatment. Also, the constituent material of the joining members B1 and B2 is not particularly limited, and gold (Au) is used in the present embodiment. Thereby, deterioration of electrical characteristics due to oxidation is suppressed, and the joining members B1 and B2 having good conductivity are obtained.

[0079] The joining members B1 and B2 are formed, for example, by forming a mask M having openings at the formation sites of the joining members B1 and B2 as shown in Figure 8 , and then applying a voltage in a state where the semiconductor device 2 is immersed in the plating solution L. Here, as shown in Figure 9 , when the surface roughness of the wiring layers 821b and 822b of the second wirings 821 and 822 is large, the coating layers 821c and 822c cannot be uniformly formed on their surfaces, and abnormal sites Q such as sites where the film thickness is thin and through holes may be formed in the coating layers 821c and 822c. Thus, if abnormal sites Q are formed in the coating layers 821c and 822c, when the semiconductor device 2 is immersed in the plating solution L, the wiring layers 821b and 822b will dissolve in the plating solution L through the abnormal sites Q, and copper (Cu) which is the constituent material of the wiring layers 821b and 822b will be mixed into the joining members B1 and B2. Thus, if copper (Cu) is mixed into the joining members B1 and B2, the purity of gold (Au) is lowered, and thereby the joining strength between the joining members B1 and B2 and the vibration element 3 is reduced. As a result, the mechanical strength of the vibration device 1 is reduced. For example, in the case where the wiring layers 821b and 822b are formed by plating treatment, such a problem is likely to occur.

[0080] On the contrary, by forming the wiring layers 821b and 822b by sputtering as in the present embodiment, the surface roughness of the wiring layers 821b and 822b can be made smaller than that of the first wirings 811 and 812 which are electroplated wirings. Therefore, the surface roughness of the wiring layers 821b and 822b can be suppressed small enough so that abnormal portions Q are difficult to form in the covering layers 821c and 822c. Therefore, the above problems can be effectively suppressed. That is, according to the vibration device 1 of the present embodiment, the mixing of copper (Cu) into the bonding members B1 and B2 can be suppressed, and the reduction in the bonding strength between the bonding members B1 and B2 and the vibration element 3 can be effectively suppressed. Therefore, the reduction in the mechanical strength of the vibration device 1 can be suppressed.

[0081] The structure of the vibration device 1 has been described above. In such a vibration device 1, the wirings 8A and 8B that electrically connect the vibration element 3 and the semiconductor circuit 7 are composed of the first wirings 811 and 812 and the second wirings 821 and 822 formed separately. Therefore, in the first wirings 811 and 812, by making the film thickness in the through holes 51 and 52 thick enough as electroplated wirings, the disconnection in the through holes 51 and 52 can be suppressed, and the bonding property with the vibration element 3 as sputtered wirings in the second wirings 821 and 822 can be made good. Therefore, according to the vibration device 1, the disconnection of the wirings 8A and 8B in the through holes 51 and 52 and the poor bonding between the vibration element 3 and the wirings 8A and 8B can be effectively suppressed, and high reliability can be exhibited.

[0082] Next, a manufacturing method of the vibration device 1 will be described. The manufacturing method of the vibration device 1 is as Figure 10 shown, and includes: a preparation step S1 of preparing a base material of the semiconductor device 2; a first wiring formation step S2 of forming the first wirings 811 and 812 by electroplating; a second wiring formation step S3 of forming the second wirings 821 and 822 by sputtering; a bonding member formation step S4 of forming the bonding members B1 and B2 by electroplating; a vibration element bonding step S5 of bonding the vibration element 3 and the semiconductor device 2 by the bonding members B1 and B2; and a cover body bonding step S6 of bonding the cover body 4 and the semiconductor device 2.

[0083] Preparation step S1

[0084] First, as Figure 11 shown, a semiconductor substrate 5 is prepared, and a semiconductor circuit 7 is formed on the lower surface 5b side. Thus, a base material of the semiconductor device 2 is obtained. Then, if necessary, the semiconductor substrate 5 is ground and polished from the upper surface 5a side, and the semiconductor substrate 5 is thinned to a predetermined thickness. Then, as Figure 12As shown, through holes 51 and 52 reaching electrode pads 721 and 722 are formed in semiconductor substrate 5. The through holes 51 and 52 can be formed, for example, by RIE (Reactive Ion Etching). Then, for example, an insulating film 60 is formed by sputtering from the upper surface 5a side of semiconductor substrate 5, and unnecessary portions of the insulating film 60 are removed by etching, as Figure 13 shown, to expose electrode pads 721 and 722 within through holes 51 and 52.

[0085] First wiring formation step S2

[0086] Then, an organic resin is coated on the inner peripheral surfaces and the upper surface 5a of through holes 51 and 52. After heating and curing (drying) the coated organic resin and patterning it, as Figure 14 shown, first organic resin films 611 and 612 are formed. Also, during coating, the organic resin flows downward due to its own weight, so the inner peripheral surfaces of the formed first organic resin films 611 and 612 become conical. Then, an organic resin is coated on the upper surface 5a. After heating and curing (drying) the coated organic resin and patterning it, as Figure 15 shown, second organic resin films 621 and 622 are formed. However, the second organic resin film 622 is not shown in Figure 15 . Also, not limited thereto, the first organic resin films 611 and 612 may be formed after forming the second organic resin films 621 and 622, or these organic resin films may be formed simultaneously.

[0087] Then, as Figure 16 shown, first wirings 811 and 812 are formed on the inner peripheral surfaces and the upper surface 5a of through holes 51 and 52 by electrolytic plating treatment from above the first organic resin films 611 and 612. At this time, by forming relatively thick first wirings 811 and 812, disconnection of the first wirings 811 and 812 within through holes 51 and 52 can be effectively suppressed. Also, although not shown, the process of forming the first wirings 811 and 812, for example, includes: a process of forming a seed layer on the surface of semiconductor substrate 5 by sputtering, a process of forming a mask having openings corresponding to the first wirings 811 and 812 on the seed layer, a process of growing electroplating within the openings of the mask to form the first wirings 811 and 812, and a process of etching and removing unnecessary portions of the seed layer after removing the mask. As described above, since the inner peripheral surfaces of the first organic resin films 611 and 612 are conical, the reachable area of sputtering is ensured, and the seed layer can be formed with good precision.

[0088] Second wiring formation step S3

[0089] Then, as Figure 17As shown, from above the first wirings 811 and 812, the second wirings 821 and 822 are formed on the upper surface 5a by sputtering, and the first wirings 811 and 812 are covered with the second wirings 821 and 822. Thereby, the exhaust gas generated from the first wirings 811 and 812 can be sealed in the through holes 51 and 52. In addition, since a part of the through holes 51 and 52 is buried by the first wirings 811 and 812, the reachable area of sputtering can be ensured in this process, and the second wirings 821 and 822 can be formed with good precision.

[0090] In addition, although not shown, the process of forming the second wirings 821 and 822 includes: a patterning process after forming a base layer of the wiring layers 821b and 822b by sputtering, a patterning process after forming the wiring layers 821b and 822b of the second wirings 821 and 822 by sputtering, a patterning process after forming a base layer of the coating layers 821c and 822c by sputtering, and a patterning process after forming a surface layer of the coating layers 821c and 822c by sputtering.

[0091] Bonding component forming process S4

[0092] Then, as Figure 18 shown, by electrolytic plating treatment, bonding components B1 and B2 are formed on the internal terminals 821a and 822a of the second wirings 821 and 822. However, the bonding component B2 etc. are not shown in Figure 18 . The forming method of the bonding components B1 and B2 is as described above. As described above, the wiring layers 821b and 822b of the second wirings 821 and 822 are formed by sputtering, so the surface roughness of the wiring layers 821b and 822b can be made small enough. Therefore, abnormal parts Q are difficult to form on the coating layers 821c and 822c on the wiring layers 821b and 822b, and it is possible to effectively suppress the dissolution of the wiring layers 821b and 822b in the plating solution L. Therefore, it is difficult for the material of the second wirings 821 and 822, that is, copper (Cu), to be mixed in the bonding components B1 and B2, and the bonding components B1 and B2 composed of high-purity gold (Au) can be formed.

[0093] Vibration element bonding process S5

[0094] Then, as Figure 19 shown, by pressing and fitting the vibration element 3 onto the bonding components B1 and B2, the vibration element 3 is bonded to the internal terminals 821a and 822a. At this time, the second organic resin films 621 and 622 formed directly below the internal terminals 821a and 822a function as stress relief layers for relieving the stress generated during pressing. Therefore, the stress applied to the semiconductor device 2 in this process can be reduced, and the breakage of the semiconductor device 2 can be effectively suppressed.

[0095] Cover body joining step S6

[0096] Then, as Figure 20 shown, the cover body 4 is joined to the upper surface 5a of the semiconductor substrate 5 in a reduced-pressure state.

[0097] Through the above steps, the vibration device 1 is obtained. According to such a manufacturing method of the vibration device 1, it is possible to enclose the exhaust gas generated from the first wirings 811 and 812 in the through holes 51 and 52 by the second wirings 821 and 822. Therefore, it is possible to suppress environmental changes in the accommodation space S, particularly an increase in pressure, caused by the exhaust gas. Therefore, the vibration characteristics of the vibration element 3 are stable, and the vibration device 1 with high reliability is obtained.

[0098] The vibration device 1 has been described above. As described above, such a vibration device 1 has: a semiconductor substrate 5 having an upper surface 5a as a first surface and a lower surface 5b as a second surface that are in a reverse relationship with each other, and through holes 51 and 52 penetrating the upper surface 5a and the lower surface 5b; a semiconductor circuit 7 disposed on the lower surface 5b side of the semiconductor substrate 5 and having electrode pads 721 and 722 as conductive layers exposed in the through holes 51 and 52; and first wirings 811 and 812 disposed on the inner peripheral surfaces of the through holes 51 and 52, and having a film thickness T2 at the central portion of the through holes 51 and 52 that is thicker than the film thickness T1 at the edge portion. According to such a structure, it is possible to form the first wirings 811 and 812 with a sufficient thickness in the through holes 51 and 52, and effectively suppress disconnection of the first wirings 811 and 812 in the through holes 51 and 52.

[0099] Also, as described above, recessed portions 811a and 812a that are recessed into the through holes 51 and 52 are formed on the surfaces of the first wirings 811 and 812. Thereby, it is possible to prevent the through holes 51 and 52 from being completely filled with the first wirings 811 and 812, and suppress the thermal stress applied to the semiconductor substrate 5 to a small value. Therefore, breakage of the semiconductor substrate 5 is effectively suppressed, and a semiconductor device 2 with high reliability is obtained.

[0100] Also, as described above, the film thickness T2 of the first wirings 811 and 812 at the central portion of the through holes 51 and 52 is 50% or more and 90% or less of the depth D of the through holes 51 and 52. By adopting such a structure, it is possible to ensure that the film thickness of the first wirings 811 and 812 in the through holes 51 and 52 is thick enough, and suppress the thermal stress applied to the semiconductor substrate 5 due to thermal expansion of the first wirings 811 and 812 in the through holes 51 and 52 to a small enough value.

[0101] Also, as described above, the second wirings 821 and 822 are disposed on the upper surface 5a and are electrically connected to the first wirings 811 and 812. With such a structure, it is possible to easily lead out the wirings to the upper surface 5a.

[0102] Also, as described above, the first wirings 811 and 812 extend to the upper surface 5a, and the second wirings 821 and 822 are in contact with the first wirings 811 and 812 on the upper surface 5a. With such a structure, it is possible to easily connect the first wirings 811 and 812 and the second wirings 821 and 822.

[0103] Also, as described above, the second wirings 821 and 822 cover the first wirings 811 and 812. With such a structure, it is possible to enclose the exhaust gas generated from the first wirings 811 and 812 in the through holes 51 and 52 by the second wirings 821 and 822.

[0104] Also, as described above, the first wirings 811 and 812 are electroplated wirings, and the second wirings 821 and 822 are sputtered wirings. With such a structure, it is easy to form the relatively thick first wirings 811 and 812. Also, the surface roughness of the second wirings 821 and 822 can be reduced.

[0105] Also, as described above, the first organic resin films 611 and 612 are provided between the inner peripheral surfaces of the through holes 51 and 52 and the first wirings 811 and 812. With such a structure, the first wirings 811 and 812 and the semiconductor substrate 5 can be more reliably insulated.

[0106] Also, as described above, the vibration device 1 includes the semiconductor device 2 and the vibration element 3 that is joined to the semiconductor device 2 and is electrically connected to the semiconductor circuit 7. With such a vibration device 1, the effects of the semiconductor device 2 described above can be achieved, and the vibration device 1 with high reliability can be obtained.

[0107] Also, as described above, the semiconductor circuit 7 includes the oscillation circuit 70 that oscillates the vibration element 3. With such a structure, the vibration device 1 becomes an oscillator, and high versatility and demand can be expected.

[0108] Also, as described above, the method for manufacturing the semiconductor device 2 includes: a preparation step S1 of preparing a base material having a semiconductor substrate 5 and a semiconductor circuit 7. The semiconductor substrate 5 has an upper surface 5a as a first surface and a lower surface 5b as a second surface that are in a front-back relationship, and through holes 51 and 52 penetrating the upper surface 5a and the lower surface 5b are formed. The semiconductor circuit 7 is disposed on the lower surface 5b side of the semiconductor substrate 5 and includes electrode pads 721 and 722 as conductive layers exposed in the through holes 51 and 52. A first wiring formation step S2 of forming first wirings 811 and 812 in the through holes 51 and 52 by electroplating treatment. The first wirings are electrically connected to the electrode pads 721 and 722, and the film thickness T2 at the central portion of the through holes 51 and 52 is thicker than the film thickness T1 at the edge portion. According to such a manufacturing method, first wirings 811 and 812 having a sufficient thickness can be formed in the through holes 51 and 52, and disconnection of the first wirings 811 and 812 in the through holes 51 and 52 can be effectively suppressed.

[0109] Second Embodiment

[0110] Figure 21 is a cross-sectional view showing a vibration device according to the second embodiment. Figure 22 is a view showing Figure 21 a cross-sectional view of a state where the shown vibration device is mounted on a mounting substrate.

[0111] The vibration device 1 according to the present embodiment is the same as the vibration device 1 of the foregoing first embodiment except for the different structure of the semiconductor device 2. In the following description, regarding the vibration device 1 of the present embodiment, the description will be centered on the differences from the foregoing first embodiment, and the description of the same matters will be omitted. Also, in the respective drawings of the present embodiment, the same reference numerals are assigned to the same structures as those of the foregoing embodiments.

[0112] As Figure 21As shown, in the semiconductor device 2 of the present embodiment, the up and down are opposite to those of the first embodiment, and a semiconductor circuit 7 is formed on the upper surface 5a side of the semiconductor substrate 5. Specifically, the semiconductor substrate 5 has a lower surface 5b as a first surface and an upper surface 5a as a second surface that are in a positive and negative relationship. Moreover, the semiconductor circuit 7 is formed on the upper surface 5a side of the semiconductor substrate 5, except for the bonding region with the lid 4. The semiconductor circuit 7 has a plurality of elements 700 such as transistors formed on the upper surface 5a of the semiconductor substrate 5, and a laminate 71 laminated on the upper surface 5a of the semiconductor substrate 5. The laminate 71 has a wiring layer 72 formed on the upper surface 5a of the semiconductor substrate 5, an insulating layer 73 formed on the upper surface of the wiring layer 72, a passivation film 74 formed on the upper surface of the insulating layer 73, and a terminal layer 75 formed on the upper surface of the passivation film 74. Thus, by forming the semiconductor circuit 7 on the upper surface 5a side of the semiconductor substrate 5, the semiconductor circuit 7 is housed in the package P and protected.

[0113] Moreover, the terminal layer 75 has two internal terminals 752 and 753 for electrically connecting the semiconductor circuit 7 and the vibration element 3. The internal terminals 752 and 753 penetrate through the insulating layer 73 and the passivation film 74 and are electrically connected to the wiring layer 72. Moreover, the internal terminals 752 and 753 are electrically connected to the terminals 323 and 324 of the vibration element 3 through the bonding members B1 and B2. Thereby, the vibration element 3 and the semiconductor circuit 7 are electrically connected through the bonding members B1 and B2 and the internal terminals 752 and 753. Moreover, the electrode pads 721 and 722 are pads for outputting signals such as oscillation signals from the semiconductor circuit 7 to the outside, pads for input signals for supplying a power supply voltage and a ground potential from the outside to the semiconductor circuit 7, and the like.

[0114] Moreover, the first wirings 811 and 812 are disposed and filled in the through-holes 51 and 52, and through the first wirings 811 and 812, the wiring is led out from the semiconductor circuit 7 to the outside. In addition, since the structures of the first wirings 811 and 812 are the same as those in the aforementioned first embodiment, the description thereof is omitted.

[0115] The vibration device 1 structured as described above is installed on the mounting substrate 100 by, for example, Figure 22 as shown, solder reflow or the like. At this time, the portions of the first wirings 811 and 812 protruding from the lower surface 5b function as terminals. Moreover, by forming the relatively thick first wirings 811 and 812 in the through-holes 51 and 52, the gap G between the mounting substrate 100 and the through-holes 51 and 52 is reduced, and accordingly, the voids can be reduced. Therefore, the connection reliability between the vibration device 1 and the mounting substrate 100 is improved.

[0116] According to the second embodiment described above, the same effects as those of the aforementioned first embodiment can also be achieved.

[0117] As described above, the semiconductor device, the vibration device, and the method of manufacturing the semiconductor device of the present invention have been described according to the illustrated embodiments. However, the present invention is not limited thereto, and the structures and processes of each part can be replaced with any structures and processes having the same functions. In addition, any other structures and processes can be added to the present invention. Moreover, the present invention can also be formed by combining two or more embodiments.

[0118] In addition, in the foregoing embodiments, an example in which the vibration device 1 is applied to an oscillator has been described. However, the application examples of the vibration device 1 are not particularly limited. For example, it can be applied to inertial sensors such as acceleration sensors and angular velocity sensors. Moreover, it can also be applied to any other devices.

Claims

1. A semiconductor device, characterized in that, having: a semiconductor substrate having a first surface and a second surface which are in a front-back relationship with each other, and having a through hole penetrating the first surface and the second surface; a semiconductor circuit disposed on the second surface side of the semiconductor substrate and having a conductive layer exposed in the through hole; and a first wiring disposed on the inner peripheral surface of the through hole and having a film thickness at the central portion of the through hole thicker than that at the edge portion.

2. The semiconductor device according to claim 1, wherein a recess recessed into the through hole is formed on the surface of the first wiring.

3. The semiconductor device according to claim 2, wherein the film thickness of the first wiring at the central portion of the through hole is 50% or more and 90% or less of the depth of the through hole.

4. The semiconductor device according to claim 1, wherein the semiconductor device has a second wiring disposed on the first surface and electrically connected to the first wiring.

5. The semiconductor device according to claim 4, wherein the first wiring extends to the first surface, and the second wiring contacts the first wiring on the first surface.

6. The semiconductor device according to claim 4, wherein the second wiring covers the first wiring.

7. The semiconductor device according to claim 4, wherein the first wiring is an electroplated wiring, and the second wiring is a sputtered wiring.

8. The semiconductor device according to claim 1, wherein the semiconductor device has a first organic resin film interposed between the inner peripheral surface of the through hole and the first wiring.

9. A vibration device, characterized in that, having: the semiconductor device according to any one of claims 1 to 8; and a vibration element bonded to the semiconductor device and electrically connected to the semiconductor circuit.

10. The vibration device according to claim 9, wherein the semiconductor circuit has an oscillation circuit for oscillating the vibration element.

11. A method of manufacturing a semiconductor device, characterized in that, comprising: a preparation step of preparing a base material having a semiconductor substrate and a semiconductor circuit, the semiconductor substrate having a first surface and a second surface which are in a front-back relationship with each other, and having a through hole penetrating the first surface and the second surface, the semiconductor circuit being disposed on the second surface side of the semiconductor substrate and having a conductive layer exposed in the through hole; and a first wiring formation step of forming a first wiring in the through hole by electroplating treatment, the first wiring being electrically connected to the conductive layer and having a film thickness at the central portion of the through hole thicker than that at the edge portion.

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