Test structure of wafer, test wafer and method for manufacturing test wafer

Abstract

The application relates to a test structure of a wafer, a test wafer and a preparation method of the test wafer. The test structure comprises a test part on a first side of the wafer and two test ports at two ends of the test part. The test part comprises at least one feature line and at least two test lines, each of the test lines is connected at the head and the tail through the feature line, the width of the feature line is different from the width of the test line, each of the test ports is used for being connected with a time domain reflection device, and is used for receiving a test signal emitted by the time domain reflection device and receiving a reflection signal formed after the test signal is reflected through the feature line, and the test signal and the reflection signal are used for determining an electrical parameter of the feature line together. Through the test structure, whether the wafer is fractured and failed can be determined.

Description

Technical Field

[0001] This application relates to the field of wafer thinning technology, and in particular to a wafer testing structure, a test wafer, and a method for preparing the test wafer. Background Technology

[0002] Wafer thinning is a key step in the back-end process of semiconductor manufacturing. Through precise grinding technology, the back side of the wafer is gradually thinned to achieve the predetermined thickness specifications. This not only reduces the chip thickness and package size, but also improves the chip's heat dissipation and overall performance.

[0003] However, because the thinning process significantly reduces the wafer thickness, thereby increasing its brittleness, the wafer may break or fail during the thinning process if the process parameters are mismatched. Summary of the Invention

[0004] Therefore, it is necessary to provide a test structure, a test wafer, and a method for preparing the test wafer to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a wafer testing structure, comprising: a testing section located on a first side of the wafer, and two testing ports located at both ends of the testing section; wherein,

[0006] The test section includes at least one feature line and at least two test lines, and each of the test lines is connected end to end through the feature line; the width of the feature line is different from the width of the test line.

[0007] Each of the test ports is used to connect to a time-domain reflectometry device and to receive test signals emitted by the time-domain reflectometry device, and to receive the reflected signal formed after the test signals are reflected by the feature line; wherein, the test signals and the reflected signals are used together to determine the electrical parameters of the feature line.

[0008] In one embodiment, the test structure includes:

[0009] An adhesion layer is located on a first side of the wafer, which is opposite to a second side of the wafer, which is the side of the wafer to be thinned.

[0010] A conductive layer is located on the side of the adhesion layer away from the wafer.

[0011] In one embodiment, the test section includes at least two sub-test sections connected in sequence. Each sub-test section includes at least one feature line and at least two test lines. Any two adjacent sub-test sections are connected by the test lines. The distance between the feature lines of different sub-test sections and the center of the wafer is different.

[0012] The first end of the first sub-test unit is connected to one of the test ports, and the second end of the last sub-test unit is connected to another test port.

[0013] In one embodiment, the at least two sub-test sections include a first sub-test ring and a second sub-test ring arranged concentrically, the center of the first sub-test ring and the center of the second sub-test ring being the center of the wafer; wherein the distance between the first sub-test ring and the wafer is between two-fifths and three-fifths of the wafer radius; and the distance between the second sub-test ring and the wafer is between seven-tenths and nine-tenths of the wafer radius.

[0014] Secondly, this application provides a test wafer, the test wafer comprising a wafer and a test structure of the wafer in any of the above embodiments.

[0015] Thirdly, this application provides a method for preparing a test wafer, the method comprising:

[0016] Provide wafers;

[0017] An adhesion layer is formed on a first side of the wafer using a photomask; wherein the photomask includes a test section pattern and two test port patterns located at both ends of the test section, the first side and the second side of the wafer are opposite sides, and the second side is the side of the wafer to be thinned;

[0018] A conductive layer is formed on the side of the adhesion layer away from the wafer using a photomask to form a test structure; wherein, the test structure includes a test section and two test ports located at both ends of the test section, the test section includes at least one feature line and at least two test lines, and each of the test lines is connected end to end through the feature line; the width of the feature line is different from the width of the test line;

[0019] Each of the test ports is used to connect to a time-domain reflectometry device and to receive test signals emitted by the time-domain reflectometry device, and to receive the reflected signal formed after the test signals are reflected by the feature line; wherein, the test signals and the reflected signals are used together to determine the electrical parameters of the feature line.

[0020] Fourthly, this application provides a wafer thinning test method, applied to the test wafer as described in the above embodiments, the method comprising:

[0021] Obtain the initial electrical parameters of the test structure on the test wafer;

[0022] Obtain the test electrical parameters of the test structure after thinning the second side of the test wafer;

[0023] The thinning test result of the test wafer is determined based on the initial electrical parameters and the test electrical parameters.

[0024] In one embodiment, the thinning process includes a mechanical thinning process, and the test electrical parameters include mechanical test electrical parameters; wherein, obtaining the test electrical parameters of the test structure after thinning the second side of the test wafer includes:

[0025] A first protective layer is formed on the side of the test structure away from the test wafer;

[0026] The second side of the test wafer is mechanically thinned.

[0027] Remove the first protective layer and obtain the mechanical test electrical parameters after mechanically thinning the test wafer.

[0028] In one embodiment, the thinning process includes a chemical polishing process, and the test electrical parameters include chemical test electrical parameters; wherein, obtaining the test electrical parameters of the test structure after thinning the second side of the test wafer includes:

[0029] A second protective layer is formed on the side of the test structure away from the test wafer;

[0030] The second side of the test wafer is chemically polished.

[0031] Remove the second protective layer and obtain the chemical test electrical parameters after chemical polishing of the test wafer.

[0032] In one embodiment, the test structure includes a first sub-test ring and a second sub-test ring; the method further includes:

[0033] If the thinning process results in the failure of the first sub-test ring, the first operating parameter of the thinning process is adjusted.

[0034] If the thinning process results in the failure of the second sub-test ring, the second operating parameter of the thinning process is adjusted.

[0035] The first operating parameter is different from the second operating parameter.

[0036] The aforementioned wafer test structure, test wafer, test wafer fabrication method, and wafer thinning test method include a test section located on the first side of the wafer and two test ports located at both ends of the test section. The test section includes at least one feature line and at least two test lines, with each test line connected end-to-end through the feature line. The width of the feature line is different from the width of the test line, and consequently, the impedance of the feature line is different from the impedance of the test line. A time-domain reflectometry device can send a test signal to the test structure through the test ports. Due to the different impedances of the feature line and the test line, the test signal will be reflected when passing through the feature line, generating a reflected signal. In application, test signals can be sent to the test structure on the wafer before and after wafer thinning. By comparing whether the reflected signals of the feature lines obtained before and after wafer thinning change, it can be determined whether the wafer has broken or failed. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the test structure of a wafer in one embodiment;

[0039] Figure 2 This is a schematic cross-sectional view of a test wafer in one embodiment;

[0040] Figure 3 This is a schematic diagram of the test structure of the wafer in another embodiment;

[0041] Figure 4 This is a schematic flowchart of a test wafer fabrication method in one embodiment;

[0042] Figure 5 This is a flowchart illustrating a wafer thinning test method in one embodiment;

[0043] Figure 6 This is a flowchart illustrating step S502 in one embodiment;

[0044] Figure 7 This is a flowchart illustrating step S502 in another embodiment;

[0045] Figure 8 This is a flowchart illustrating a wafer thinning test method in another embodiment;

[0046] Figure 9This is a waveform diagram of the reflected signal when the test structure is intact in one embodiment;

[0047] Figure 10 This is a waveform diagram of the reflected signal when the first feature line breaks near its location in one embodiment;

[0048] Figure 11 This is a waveform diagram of the reflected signal when the fourth feature line breaks near its location in one embodiment. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0054] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0055] As described in the background section, wafer thinning is a crucial step in the back-end processes of semiconductor manufacturing. Through precise grinding techniques, the back side of the wafer is gradually thinned to achieve a predetermined thickness. This not only reduces chip thickness and package size but also improves heat dissipation and overall performance. In the post-Moore's Law era, further shrinking of transistor size has become increasingly difficult due to limitations in photolithography and material physics. Wafer thinning technology has become increasingly important due to the urgent need for advanced packaging technologies. According to Moore's Law, the number of transistors on an integrated circuit doubles every 18 months. The size of transistors on chips is getting smaller and smaller, and their price is also decreasing. However, in recent years, limitations in photolithography and material physics have made further shrinking of transistor size extremely difficult, and Moore's Law is facing expiration. High-density advanced chip packaging technology is considered an important means to break through Moore's Law and further improve chip performance. In the semiconductor manufacturing process, wafer thinning is an essential step in achieving advanced packaging and high-performance devices. However, to ensure wafer quality and reliability, defect detection must be performed during the thinning process to identify defects that may affect subsequent processes and the performance of the final product. Thinning processes significantly reduce wafer thickness, thereby increasing its brittleness. During thinning, mismatched process parameters can lead to wafer breakage or failure. Technicians can identify defects early, preventing further processing of problematic wafers and reducing material waste and production costs.

[0056] One method for defect detection on wafers involves polarizing light using a polarizer and then incident it at an angle onto the wafer. A CCD camera captures the scattered light, and the polarization intensity and polarization direction (the ratio of these two polarization components) are determined based on the resulting P-polarized and S-polarized light component images. The polarization intensity and direction are also determined by comparing images obtained under two conditions: one with no stress applied to the wafer and the other with static stress (tensile stress) applied to the light-illuminated side of the wafer. These images are then compared to predetermined thresholds for defect detection and classification. While this method allows for quality management of wafer defects, it requires scanning every location on the wafer with polarized light, resulting in excessive time consumption and inefficiency. The technology is complex, with high equipment and maintenance costs, and requires accompanying software for data analysis, further increasing its complexity and dependence. Furthermore, this method has certain requirements regarding wafer surface flatness or material uniformity, and its applicability needs further verification.

[0057] Another method for defect detection on wafers in related technologies involves obtaining a target image using Graphical Data System (GDS) information of a specific layout in the semiconductor wafer. The target image includes a first outline with a first pattern corresponding to the specific layout. Based on the first outline, image-based alignment is performed to acquire a raw image from the semiconductor wafer. The semiconductor wafer is then analyzed by measuring the raw image to provide diagnostic results. This method requires equipment such as electron microscopes, is technically complex, has high equipment and maintenance costs, and requires supporting database data analysis, resulting in high labor costs and technical complexity.

[0058] Based on the above-mentioned technical problems, in an exemplary embodiment, please refer to... Figure 1 This application provides a wafer test structure 20, including: a test section located on a first side of the wafer 10, and two test ports 21 located at both ends of the test section; wherein, the test section includes at least one feature line 22 and at least two test lines 23, and each test line 23 is connected end to end through the feature line 22; the width of the feature line 22 is different from the width of the test line 23; each test port 21 is used to connect to a time-domain reflectometry device, and is used to receive the test signal emitted by the time-domain reflectometry device, and to receive the reflected signal formed after the test signal is reflected by the feature line 22; wherein, the test signal and the reflected signal are used together to determine the electrical parameters of the feature line 22.

[0059] It is understood that the test structure 20 provided in this application can be formed on the first surface of the wafer 10. Before thinning the second side of the wafer, the transmitting probe and receiving probe of the time-domain reflectometry device can be connected to the two test ports 21 of the test structure 20, respectively. The transmitting probe sends a test signal to the test structure 20, and the receiving probe receives the reflected signal after the test signal passes through the test section. In this application, the feature line and the test line are made of the same material, but the width of the feature line 22 is different from the width of the test line 23. For example, as shown... Figure 1 As shown, the width of feature line 22 is smaller than the width of test line 23. Therefore, the impedance of feature line 22 is greater than that of test line 23. Consequently, the waveform of the reflected signal through feature line 22 exhibits a peak. When the test section includes multiple feature lines 22, the transmission time of their reflected waves varies due to the positional differences of feature lines 22, thus realizing the mapping relationship between different peaks on the test structure 20 and feature lines 22. In one example, the linewidth of test line 23 can be between 50µm and 1000µm, the linewidth of feature line 22 can be 0.2 to 0.4 times the linewidth of test line 23, the shape of test port 21 can be circular, the diameter of test port 21 can be 1.2 to 1.5 times the linewidth of test line 23, and the spacing between two test ports 21 can be between 400µm and 1000µm.

[0060] In applications, during the thinning process of the second side of wafer 10, inappropriate thinning process parameters may lead to wafer breakage and failure. Therefore, after the thinning process of the second side of wafer 10 is completed, the transmit / receive probe and ground probe of the time-domain reflectometry device can be connected again to the corresponding two test ports 21 in the test structure 20. The transmit / receive probe sends a test signal to the test structure 20 again and receives the reflected signal after the test section passes through the test section. It can be understood that if wafer 10 breaks during the thinning process, the test section on the first side of wafer 10 will also break, which is manifested as a steep peak with increased impedance in the reflected signal. By comparing the waveforms of the reflected signals before and after the thinning of wafer 10, it can be determined whether wafer 10 has broken during the thinning process.

[0061] The aforementioned wafer test structure includes a test section located on the first side of the wafer and two test ports located at both ends of the test section. The test section includes at least one feature line and at least two test lines, with each test line connected end-to-end through the feature line. The width of the feature line is different from the width of the test line, and consequently, the impedance of the feature line is different from the impedance of the test line. A time-domain reflectometry device can send test signals to the test structure through the test ports. Due to the different impedances of the feature line and the test line, the test signal will be reflected when passing through the feature line, generating a reflected signal. In application, test signals can be sent to the test structure on the wafer before and after wafer thinning. By comparing whether the reflected signals of the feature lines obtained before and after wafer thinning change, it can be determined whether the wafer has broken or failed.

[0062] In one exemplary embodiment, please refer to Figure 2 The test structure 20 includes an adhesion layer 201 and a conductive layer 202. The adhesion layer 201 is located on a first side of the wafer 10, and the first side and the second side of the wafer 10 are opposite sides, with the second side being the side of the wafer to be thinned. The conductive layer 202 is located on the side of the adhesion layer 201 away from the wafer 10.

[0063] In the application, when preparing the test wafer, a pre-prepared mask can be used. The mask includes a test section pattern and two test port patterns located at both ends of the test section. First, a wafer 10 is provided. Then, one or more adhesion layers 201 composed of chromium (Cr) and titanium (Ti) can be uniformly deposited on the first side of the wafer 10 using the pre-prepared mask. The deposition method includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable deposition techniques. In one example, the thickness of the adhesion layer 201 can be between 30 nm and 1000 nm to provide the required adhesion, conductivity, and / or corrosion resistance for the test structure 20. Next, a conductive layer 202 can be uniformly deposited on the side of the adhesion layer 201 away from the wafer 10 using a mask, through physical vapor deposition, electroplating, electroless plating or other suitable deposition techniques, to form the test structure 20. The material of the conductive layer 202 includes, but is not limited to, one or more of Au, silver (Ag), and copper (Cu). The thickness of the conductive layer 202 can be between 50µm and 2000µm to provide the required conductivity and solderability.

[0064] In one exemplary embodiment, please refer to Figure 3The test section includes at least two sub-test sections connected in sequence. Each sub-test section includes at least one feature line 22 and at least two test lines 23. Any two adjacent sub-test sections are connected by test lines 23. The distance between the feature lines of different sub-test sections and the center of the wafer is different. The first end of the first sub-test section is connected to a test port, and the second end of the last sub-test section is connected to another test port.

[0065] In one example, each sub-test section can be a concentric ring with a notch. The center of each sub-test section and the center of the wafer 10 are projected onto the same plane as the wafer. Different sub-test sections are connected sequentially by test lines 23. The innermost sub-test section, which is the one with the smallest distance from the center of the wafer 10, is connected to a test port 21. The outermost sub-test section, which is the one with the largest distance from the center of the wafer 10, is connected to another test port 21.

[0066] In one exemplary embodiment, please continue to refer to Figure 3 The at least two sub-test sections include a first sub-test ring and a second sub-test ring arranged concentrically, with the center of the first sub-test ring and the center of the second sub-test ring being the center of the wafer; wherein, the distance between the first sub-test ring and the wafer is between two-fifths and three-fifths of the wafer radius; and the distance between the second sub-test ring and the wafer is between seven-tenths and nine-tenths of the wafer radius.

[0067] Exemplarily, both the first and second sub-test rings include three feature lines 22 and four test lines 23, respectively, and are connected via the test lines 23. The first sub-test ring has a first feature line 22-1, a second feature line 22-2, and a third feature line 22-3, while the second sub-test ring has a fourth feature line 22-4, a fifth feature line 22-5, and a sixth feature line 22-6. The test port 21 connected to the first sub-test ring is used to connect to the transmit / receive probe of the time-domain reflectometry device, and the test port 21 connected to the second sub-test ring is used to connect to the ground probe of the time-domain reflectometry device; alternatively, the test port 21 connected to the first sub-test ring is used to connect to the ground probe of the time-domain reflectometry device, and the test port 21 connected to the second sub-test ring is used to connect to the transmit / receive probe of the time-domain reflectometry device.

[0068] In one exemplary embodiment, this application provides a test wafer, which includes a wafer and a test structure for the wafer in any of the above embodiments. Also, please refer to... Figure 4 This application also provides a method for preparing a test wafer, the method comprising steps S401 to S403.

[0069] S401: Provides wafers.

[0070] S402: An adhesion layer is formed on the first side of the wafer using a photomask.

[0071] The mask includes a test section pattern and two test port patterns located at both ends of the test section. The test section pattern further includes at least one feature line pattern and at least two test line patterns. The first side and the second side of wafer 10 are opposite sides, with the second side being the side of the wafer to be thinned. The adhesion layer 201 includes, but is not limited to, chromium (Cr) and titanium (Ti), and its thickness can be between 30 nm and 1000 nm to provide the required adhesion, conductivity, and corrosion resistance for the test structure 20.

[0072] S403: A conductive layer is formed on the side of the adhesion layer away from the wafer using a photomask to form a test structure.

[0073] Since the mask includes a test section pattern and two test port patterns located at both ends of the test section, the fabricated test structure has a test section corresponding to the pattern on the mask and two test ports 21 located at both ends of the test section. The test section includes at least one feature line 22 and at least two test lines 23, with each test line 23 connected end-to-end through the feature line 22. The width of the feature line 22 is different from the width of the test line 23. Each test port 21 is used to connect to a time-domain reflectometry device and to receive the test signal emitted by the time-domain reflectometry device, as well as the reflected signal formed after the test signal is reflected by the feature line. The test signal and the reflected signal are used together to determine the electrical parameters of the feature line. The conductive layer 202 is made of one or more of Au, silver (Ag), and copper (Cu), and the thickness of the conductive layer 202 can be between 50µm and 2000µm to provide the required conductivity and solderability.

[0074] In one exemplary embodiment, please refer to Figure 5 This application provides a wafer thinning test method, applied to the test wafer as described in the above embodiments, the wafer thinning test method including steps S501 to S503.

[0075] S501: Obtain the initial electrical parameters of the test structure on the test wafer.

[0076] In one example, see Figure 3The test section includes a first sub-test ring and a second sub-test ring that are connected sequentially and concentrically arranged. The first sub-test ring has a first feature line 22-1, a second feature line 22-2, and a third feature line 22-3. The second sub-test ring has a fourth feature line 22-4, a fifth feature line 22-5, and a sixth feature line 22-6. The test port 21 connected to the first sub-test ring is used to connect to the transmit / receive probe of the time domain reflectometer, and the test port 21 connected to the second sub-test ring is used to connect to the ground probe of the time domain reflectometer. This example and the following examples all use... Figure 3 The test structure shown is used as an example for illustration. Before wafer thinning begins, the transmit / receive probes of the time domain reflectometer are connected to test port 21, which is connected to the first sub-test ring, and the ground probes of the time domain reflectometer are connected to test port 21, which is connected to the second sub-test ring, thereby forming a test loop.

[0077] Next, the time-domain reflectometry device is turned on, and the transmit / receive probe sends a test signal to the test structure 20. At the same time, the transmit / receive probe receives the reflected signal of the test structure. Since the feature line 22 is narrower than the test line 23, its impedance is larger, which causes the waveform reflected by the feature line 22 to show a peak. Since the positions of each feature line 22 are different, the transmission time of the reflected wave of each feature line 22 is also different, thus realizing the mapping relationship between different peaks on the reflected signal and the feature line 22.

[0078] S502: Obtain the test electrical parameters of the test structure after thinning the second side of the test wafer.

[0079] After acquiring the reflection signal before wafer thinning, the reflection signal can be saved. Simultaneously, the connection between the test structure 20 and the time-domain reflectometry (TD-RS) device is disconnected, and thinning processing is performed on the second side of the test wafer. After the thinning process is completed, the transmit / receive probes of the TD-RS device can be reconnected to the test port 21 connected to the first sub-test ring, and the ground probes of the TD-RS device can be reconnected to the test port 21 connected to the second sub-test ring, forming a test loop. Then, the TD-RS device is turned on, and the transmit / receive probes send the same test signal to the test structure 20, while simultaneously receiving the reflection signal from the test structure through the transmit / receive probes.

[0080] S503: Determine the thinning test results of the test wafer based on the initial electrical parameters and the test electrical parameters.

[0081] It is understandable that if the wafer breaks during the wafer thinning process, the test structure attached to the wafer will also be open-circuited, which will be manifested as a steep peak of increased impedance in the waveform of the reflected signal. Therefore, by comparing the waveforms of the reflected signal before and after wafer thinning, it can be determined whether the wafer broke during the thinning process.

[0082] In one exemplary embodiment, the thinning process includes a mechanical thinning process, and the electrical parameter testing includes mechanical testing of electrical parameters. See also... Figure 6 Step S502, obtaining the test electrical parameters of the test structure after thinning the second side of the test wafer, including steps S601 to S603.

[0083] S601: A first protective layer is formed on the side of the test structure away from the test wafer.

[0084] Before thinning the test wafer, a first protective layer can be formed on the side of the test structure away from the test wafer to prevent the test structure 20 from breaking due to reasons other than wafer breakage during the mechanical thinning process. In one example, the material of the first protective layer can be polyimide, polyethylene, acrylic polymers, polyester polymers, epoxy resins, polyurethanes, etc.

[0085] S602: Perform mechanical thinning on the second side of the test wafer.

[0086] In this embodiment, the sandpaper used in the mechanical thinning process can be between 600 and 4000 grit, and the grinding feed rate can be between 0.05 mm / min and 1 mm / min per pass. The polishing particles used can be diamond, alumina, silicon carbide particles, etc., and the particle size can be between 0.5 μm and 5 μm. The relative movement between the sandpaper and the wafer during the mechanical thinning process is completed by an automatic or semi-automatic grinding machine, wherein the grinding pressure ranges from 0.2 MPa to 10 MPa and the grinding speed is 200 rpm to 3000 rpm to ensure that the wafer reaches the predetermined final thickness.

[0087] S603: Remove the first protective layer and obtain the mechanical test electrical parameters after mechanical thinning of the test wafer.

[0088] After the mechanical thinning process is completed, the first protective layer on the surface of the test structure can be removed. The transmitting / receiving probes of the time-domain reflectometry device can then be reconnected to the test port 21 connected to the first sub-test ring, and the grounding probes of the time-domain reflectometry device can be connected to the test port 21 connected to the second sub-test ring, forming a test loop. Next, the time-domain reflectometry device is turned on, and the transmitting / receiving probes send the same test signal to the test structure 20. Simultaneously, the reflected signal from the test structure, i.e., the mechanical test electrical parameters, is received through the transmitting / receiving probes.

[0089] In one exemplary embodiment, the thinning process includes chemical polishing, and the electrical parameters being tested include chemical electrical parameters. (See [link to relevant documentation]). Figure 7Step S502, obtaining the test electrical parameters of the test structure after thinning the second side of the test wafer, including steps S701 to S703.

[0090] S701: A second protective layer is formed on the side of the test structure away from the test wafer.

[0091] Before thinning the test wafer, a second protective layer can be formed on the side of the test structure away from the test wafer to prevent the test structure 20 from breaking due to reasons other than wafer breakage during the chemical polishing process. In one example, the material of the second protective layer can be polyimide, polyethylene, acrylic polymers, polyester polymers, epoxy resins, polyurethanes, etc.

[0092] S702: Perform chemical polishing on the second side of the test wafer.

[0093] Specifically, chemical polishing is a type of chemical mechanical polishing. The abrasive particles in the chemical mechanical polishing slurry used in chemical mechanical polishing are silicon dioxide, alumina, cerium oxide, etc., with a particle size distribution between 20 nm and 100 nm, used to provide mechanical polishing. The solvent in the chemical mechanical polishing slurry is water or organic solvents such as ethanol, acetone, and ethyl acetate, and the pH value of the slurry is between 9 and 12. The chemical mechanical polishing process includes setting the rotation speed of the polishing machine, with the carrier disk rotating at 30 rpm to 3000 rpm and the polishing head rotating at 30 rpm to 200 rpm, to generate relative motion and achieve uniform polishing. The chemical mechanical polishing process also includes setting the polishing pressure, i.e., the pressure applied to the wafer by the polishing head is 5 kPa to 5000 kPa, to control the polishing rate and the uniformity of the wafer surface. The polishing time can be between 5 min and 60 min, depending on the polishing requirements and the wafer material.

[0094] S703: Remove the second protective layer and obtain the chemical test electrical parameters after chemical polishing of the test wafer.

[0095] After chemical polishing, the second protective layer on the surface of the test structure can be removed. The transmit / receive probes of the time-domain reflectometry (TDDR) device can then be reconnected to test port 21, which is connected to the first sub-test ring, and the ground probes of the TDDR device can be connected to test port 21, which is connected to the second sub-test ring, forming a test loop. Next, the TDDR device is activated, and the transmit / receive probes send the same test signal to the test structure 20. Simultaneously, the reflected signal from the test structure, i.e., the chemical test electrical parameters, is received through the transmit / receive probes.

[0096] In one exemplary embodiment, please refer to Figure 8The test structure includes a first sub-test ring and a second sub-test ring; the wafer thinning test method also includes steps S801 and S802.

[0097] S801: If the first sub-test ring fails as a result of the thinning process, adjust the first working parameter of the thinning process.

[0098] As described in the above embodiments, the reflected signal includes reflected waves from each feature line. Due to the different positions of each feature line 22, the transmission time of the reflected waves from each feature line 22 is also different, with the transmission time of the reflected waves from feature lines 22 closer to the transmitting / receiving probe being shorter. If the test structure fails, the shape of the reflected wave from the feature line after the failure point on the test structure will be different from the shape of the reflected wave from the corresponding feature line before wafer thinning. For example, if the test structure between the third feature line 22-3 and the fourth feature line 22-4 breaks, the shapes of the reflected waves from the fourth feature line 22-4, the fifth feature line 22-5, and the sixth feature line 22-6 will be different from the shapes of the reflected waves from the fourth feature line 22-4, the fifth feature line 22-5, and the sixth feature line 22-6 before wafer thinning. Therefore, the specific failure location of the wafer can be determined by comparing the waveforms of the reflected signals before and after wafer thinning.

[0099] If the first sub-test ring fails after the wafer undergoes mechanical thinning, the first working parameters such as the grinding pressure of the grinding machine, the mesh size of the grinding paper, and the grinding feed rate can be adjusted; if the first sub-test ring fails after the wafer undergoes chemical polishing, the first working parameters such as the polishing pressure of the polishing machine can be adjusted.

[0100] S802: If the second sub-test ring fails as a result of the thinning process, adjust the second working parameter of the thinning process.

[0101] If the second sub-test ring fails after the wafer undergoes mechanical thinning, the second working parameters such as the grinding speed of the grinding machine, the type of polishing particles, and the particle diameter can be adjusted. If the second sub-test ring fails after the wafer undergoes chemical polishing, the second working parameters such as the abrasive type and abrasive size of the chemical mechanical polishing slurry, the polishing speed of the polishing machine, and the polishing time can be adjusted.

[0102] It should be understood that, although Figures 4-8 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 4-8At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0103] In a detailed embodiment, please refer to Figure 3 The test unit includes a first sub-test ring and a second sub-test ring that are connected in sequence and concentrically arranged. The first sub-test ring has a first feature line 22-1, a second feature line 22-2 and a third feature line 22-3. The second sub-test ring has a fourth feature line 22-4, a fifth feature line 22-5 and a sixth feature line 22-6. The test port 21 connected to the first sub-test ring is used to connect to the transmit / receive probe of the time domain reflectometer, and the test port 21 connected to the second sub-test ring is used to connect to the ground probe of the time domain reflectometer. This will be explained as an example.

[0104] First, using a pre-prepared mask, a 120 nm thick chromium (Cr) adhesion layer was uniformly deposited on the first side of the wafer using chemical vapor deposition. Subsequently, a 300 µm thick conductive layer of gold (Au) was uniformly deposited on top of the adhesion layer using electroplating to provide the required conductivity and solderability. The final test structure has the following shape. Figure 3 As shown, the test linewidth is 180µm, the wafer diameter is 20mm, the diameter of the first sub-test ring is 0.5 times the wafer diameter, and the diameter of the second sub-test ring is 0.8 times the wafer diameter; there are three feature lines on the first and second sub-test rings respectively, and the linewidth of the feature lines is 100µm.

[0105] Next, connect the transmit / receive probes of the time-domain reflectometry device to test port 21 connected to the first sub-test ring, and connect the ground probes of the time-domain reflectometry device to test port 21 connected to the second sub-test ring, and then obtain the following... Figure 9 The waveform of the reflected signal shown serves as a control group for subsequent tests. The waveform of the reflected signal clearly reflects the condition of each characteristic line; by observing the waveform of each characteristic line, information about each characteristic line can be obtained. Figure 9 In the diagram, a1 is the reflected wave of the first characteristic line 22-1, b1 is the reflected wave of the second characteristic line 22-2, c1 is the reflected wave of the third characteristic line 22-3, d1 is the reflected wave of the fourth characteristic line 22-4, e1 is the reflected wave of the fifth characteristic line 22-5, and f1 is the reflected wave of the sixth characteristic line 22-6.

[0106] Subsequently, a first protective layer of polyimide was used to protect the test structure. Then, mechanical polishing was performed sequentially using 1200-grit and 2000-grit sandpaper, controlling the chip polishing depth to be 0.05 mm per pass. The polishing particles were diamond particles with a particle size of 2 μm. The polishing pressure was adjusted to 1 MPa and the polishing speed to 200 rpm. After mechanical thinning, the first protective layer was removed, and the thinned wafer was inspected again. The transmit / receive probes of the time-domain reflectometry device were connected to test port 21 connected to the first sub-test ring, and the ground probes of the time-domain reflectometry device were connected to test port 21 connected to the second sub-test ring. The result was as follows: Figure 10 The waveform of the reflected signal shown is in Figure 10 In the diagram, a2 represents the reflected wave from the first characteristic line 22-1, b2 represents the reflected wave from the second characteristic line 22-2, c2 represents the reflected wave from the third characteristic line 22-3, d2 represents the reflected wave from the fourth characteristic line 22-4, e2 represents the reflected wave from the fifth characteristic line 22-5, and f2 represents the reflected wave from the sixth characteristic line 22-6. Through comparison... Figure 9 and Figure 10 It can be seen that the main failure point is located near the first characteristic line 22-1, indicating that the possible cause of failure is excessive pressure applied during mechanical polishing or excessively large polishing particle diameter. The same batch of identical wafers was used to re-fabricate the test structure, and the above steps were repeated. The mechanical polishing pressure was adjusted to 0.5 MPa, and the polishing particle diameter was 1 μm. The waveform of the reflected signal after wafer thinning was tested again, and no obvious abnormalities were found.

[0107] The chemical mechanical polishing (CMP) process continues. A second protective layer of polyimide organic film is used to protect the test structure on the first side of the wafer, followed by CMP treatment. The polishing slurry uses silicon dioxide abrasive with a particle size distribution between 20 nm and 100 nm. The solvent is acetone, and the pH of the CMP slurry is adjusted to around 10. The rotation speed of the polishing machine's carrier disk is set to 2000 rpm, and the polishing head rotation speed is set to 100 rpm to generate relative motion and achieve uniform polishing. The pressure applied by the polishing head to the wafer is 3000 kPa, and the polishing time is set to 30 min. After the CMP process is completed, the second protective layer is removed. Then, the transmit / receive probes of the time-domain reflectometry (TDDR) device are connected to test port 21, which is connected to the first sub-test ring, and the ground probes of the TDDR device are connected to test port 21, which is connected to the second sub-test ring. The result is then as follows: Figure 11 The waveform of the reflected signal shown is in Figure 11 In the diagram, a3 is the reflected wave from the first characteristic line 22-1, b3 is the reflected wave from the second characteristic line 22-2, c3 is the reflected wave from the third characteristic line 22-3, d3 is the reflected wave from the fourth characteristic line 22-4, e3 is the reflected wave from the fifth characteristic line 22-5, and f3 is the reflected wave from the sixth characteristic line 22-6. (Comparison) Figure 9 and Figure 11 It can be seen that the main failure point is located near the fourth characteristic line 22-4, indicating that the possible cause of failure is excessive chemical mechanical polishing speed or excessive polishing time. The same batch of identical wafers was used to re-fabricate the test structure, and the above steps were repeated, setting the carrier disk speed to 1000 rpm, the polishing head speed to 100 rpm, and the polishing time to 20 minutes. The waveform of the reflected signal after wafer thinning was tested again, and no obvious abnormalities were found. This achieved iterative improvement of the wafer thinning process parameters, increasing the yield of wafer thinning.

[0108] This application discloses a wafer thinning test method that can detect the location of defects generated during the wafer thinning process and take timely corrective measures by adjusting the operating parameters of the grinding or polishing machine, thereby assessing the reliability of the semiconductor manufacturing process. During the testing process, reflected signals can be detected online, and when a fault occurs, its location and failure mode can be determined promptly. Compared to traditional electronic material verification and failure analysis, this method significantly reduces experimental time, identifies risk points in wafer devices, and supports the reliability design of electronic components. This invention has application needs for product development units, third-party evaluation agencies, and product application units, and can generate significant economic value.

[0109] In one exemplary embodiment, this application also provides a wafer thinning test apparatus, which includes: a first acquisition module, a second acquisition module, and a first determination module. Wherein,

[0110] The first acquisition module is used to acquire the initial electrical parameters of the test structure on the test wafer.

[0111] The second acquisition module is used to acquire the test electrical parameters of the test structure after the second side of the test wafer has been thinned.

[0112] The first determining module is used to determine the thinning test results of the test wafer based on the initial electrical parameters and the test electrical parameters.

[0113] In an exemplary embodiment, the thinning process includes mechanical thinning, and the electrical parameter testing includes mechanical electrical parameter testing; wherein, the second acquisition module includes: a first protection submodule, a first thinning submodule, and a first testing submodule.

[0114] The first protection submodule is used to form a first protective layer on the side of the test structure away from the test wafer.

[0115] The first thinning submodule is used to perform mechanical thinning on the second side of the test wafer.

[0116] The first test submodule removes the first protective layer and obtains the mechanical test electrical parameters of the test wafer after mechanical thinning.

[0117] In one exemplary embodiment, the thinning process includes chemical polishing, and the electrical parameter testing includes chemical electrical parameter testing; wherein, the second acquisition module includes a second protection submodule, a first polishing submodule, and a second testing submodule.

[0118] The second protection submodule is used to form a second protective layer on the side of the test structure away from the test wafer.

[0119] The first polishing submodule is used to perform chemical polishing on the second side of the test wafer.

[0120] The second test submodule is used to remove the second protective layer and obtain the chemical test electrical parameters after the test wafer has undergone chemical polishing.

[0121] In one exemplary embodiment, the test structure includes a first sub-test ring and a second sub-test ring; the wafer thinning test apparatus further includes a first control module and a second control module.

[0122] The first control module is used to adjust the first working parameters of the thinning process when the first sub-test ring fails as a result of the thinning process.

[0123] The second control module is used to adjust the second working parameters of the thinning process when the result of the thinning process is that the second sub-test ring fails.

[0124] The first working parameter is different from the second working parameter.

[0125] Specific limitations regarding the wafer thinning test apparatus can be found in the limitations of the wafer thinning test method described above, and will not be repeated here. Each module in the aforementioned wafer thinning test apparatus can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module. It should be noted that the module division in this embodiment is illustrative and only represents a logical functional division; other division methods may be used in actual implementation.

[0126] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the wafer thinning test method in any of the above embodiments.

[0127] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0128] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A wafer testing structure, characterized in that, include: A test section located on the first side of the wafer, and two test ports located at both ends of the test section; wherein, The test section includes at least one feature line and at least two test lines, and each of the test lines is connected end to end through the feature line; the width of the feature line is different from the width of the test line. Each of the test ports is used to connect to a time-domain reflectometry device and to receive test signals emitted by the time-domain reflectometry device, and to receive the reflected signal formed after the test signals are reflected by the feature line; wherein, the test signals and the reflected signals are used together to determine the electrical parameters of the feature line.

2. The wafer testing structure according to claim 1, characterized in that, The test structure includes: An adhesion layer is located on a first side of the wafer, which is opposite to a second side of the wafer, which is the side of the wafer to be thinned. A conductive layer is located on the side of the adhesion layer away from the wafer.

3. The wafer testing structure according to claim 1, characterized in that, The test section includes at least two sub-test sections connected in sequence. Each sub-test section includes at least one feature line and at least two test lines. Any two adjacent sub-test sections are connected by the test lines. The distance between the feature lines of different sub-test sections and the center of the wafer is different. The first end of the first sub-test unit is connected to one of the test ports, and the second end of the last sub-test unit is connected to another test port.

4. The wafer testing structure according to claim 3, characterized in that, The at least two sub-test sections include a first sub-test ring and a second sub-test ring arranged concentrically, the center of the first sub-test ring and the center of the second sub-test ring being the center of the wafer; wherein, the distance between the first sub-test ring and the wafer is between two-fifths and three-fifths of the wafer radius; and the distance between the second sub-test ring and the wafer is between seven-tenths and nine-tenths of the wafer radius.

5. A test wafer, characterized in that, The test wafer includes a wafer and a test structure for the wafer as described in any one of claims 1-4.

6. A method for preparing a test wafer, characterized in that, The method includes: Provide wafers; An adhesion layer is formed on a first side of the wafer using a photomask; wherein the photomask includes a test section pattern and two test port patterns located at both ends of the test section, the first side and the second side of the wafer are opposite sides, and the second side is the side of the wafer to be thinned; A conductive layer is formed on the side of the adhesion layer away from the wafer using a photomask to form a test structure; The test structure includes a test section and two test ports located at both ends of the test section. The test section includes at least one feature line and at least two test lines, with each test line connected end-to-end through the feature line. The width of the feature line is different from the width of the test lines. Each test port is used to connect to a time-domain reflectometry device and to receive test signals emitted by the time-domain reflectometry device, as well as to receive reflected signals formed after the test signals are reflected by the feature lines. The test signals and the reflected signals are used together to determine the electrical parameters of the feature lines.

7. A wafer thinning test method, characterized in that, Applied to the test wafer as described in claim 5, the method includes: Obtain the initial electrical parameters of the test structure on the test wafer; Obtain the test electrical parameters of the test structure after thinning the second side of the test wafer; The thinning test result of the test wafer is determined based on the initial electrical parameters and the test electrical parameters.

8. The wafer thinning test method according to claim 7, characterized in that, The thinning process includes mechanical thinning, and the test electrical parameters include mechanical test electrical parameters; wherein, obtaining the test electrical parameters of the test structure after thinning the second side of the test wafer includes: A first protective layer is formed on the side of the test structure away from the test wafer; The second side of the test wafer is mechanically thinned. Remove the first protective layer and obtain the mechanical test electrical parameters after mechanically thinning the test wafer.

9. The wafer thinning test method according to claim 7, characterized in that, The thinning process includes chemical polishing, and the electrical parameters being tested include chemical electrical parameters; wherein, obtaining the electrical parameters of the test structure after thinning the second side of the test wafer includes: A second protective layer is formed on the side of the test structure away from the test wafer; The second side of the test wafer is chemically polished; Remove the second protective layer and obtain the chemical test electrical parameters after chemical polishing of the test wafer.

10. The wafer thinning test method according to any one of claims 7 to 9, characterized in that, The test structure includes a first sub-test ring and a second test ring; the method further includes: If the thinning process results in the failure of the first sub-test ring, the first operating parameter of the thinning process is adjusted. If the thinning process results in the failure of the second sub-test ring, the second operating parameter of the thinning process is adjusted. The first operating parameter is different from the second operating parameter.

Images