Vertical cavity surface emitting laser, laser array and light emitting device

Abstract

The invention relates to a vertical-cavity surface-emitting laser, a laser array and a light-emitting device. The vertical-cavity surface-emitting laser comprises an N-type substrate, an upper distributed Bragg reflector, and an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, a second tunnel junction, a P-type metal contact layer and a cathode electrode which are sequentially stacked along the direction vertical to the substrate, the first tunnel junction is used for reversing an N-type carrier in the N-type buffer layer into a P-type carrier; the second tunnel junction is used for reversing carriers in the upper distributed Bragg reflector into carriers of an opposite conduction type; wherein the surface, deviating from the N-type buffer layer, of the N-type substrate comprises an anode electrode. At least the driving frequency and speed of the VCSEL can be improved, and the size of the driving system is reduced.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to a U.S. patent application filed with the U.S. Patent Office on January 29, 2024, with serial number 63 / 626,171 and titled "A VCSEL structure containing two tunnel junctions", the entire content of which is incorporated herein by reference. Technical field

[0003] This application relates to the field of semiconductor lasers, and particularly to a vertical - cavity surface - emitting laser, a laser array, and a light - emitting device. Background technique

[0004] VCSEL (Vertical - Cavity Surface - Emitting Laser) is a type of semiconductor laser, and its basic structure mainly consists of an active layer and DBR (Distributed Bragg Reflector - DBR) mirrors with optical feedback function.

[0005] In related VCSELs, the cathode for applying a low - potential voltage is generally set on the back of the substrate, and the anode for applying a high - potential voltage is generally set above the front of the substrate, making it difficult to adopt a common - anode driving method, restricting the reduction of the volume of the driving system, and making it difficult to use N - type transistors with faster response speeds, resulting in limitations of VCSELs in high - frequency and high - speed driving application fields. Summary of the invention

[0006] Based on this, in view of the technical problems in the above - mentioned background technique, it is necessary to provide a vertical - cavity surface - emitting laser, a laser array, and a light - emitting device, which can at least use N - type transistors with faster response speeds, improve the driving frequency and speed of VCSELs while reducing the volume of the driving system.

[0007] To achieve the above-mentioned and other objectives, according to various embodiments of the present disclosure, a first aspect of the present disclosure provides a vertical cavity surface emitting laser, comprising an N-type substrate, an upper distributed Bragg reflector, and an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, a second tunnel junction, a P-type metal contact layer, and a cathode electrode stacked in sequence along a direction perpendicular to the substrate; the first tunnel junction is used to invert carriers in the N-type buffer layer into carriers of the opposite conductivity type; the second tunnel junction is used to invert carriers in the upper distributed Bragg reflector into carriers of the opposite conductivity type; the upper distributed Bragg reflector is located between the active layer and the P-type metal contact layer, and the upper distributed Bragg reflector is associated with the second tunnel junction; wherein the surface of the N-type substrate facing away from the N-type buffer layer comprises an anode electrode.

[0008] In the vertical cavity surface emitting laser in the above embodiment, an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, an N second tunnel junction, a P-type metal contact layer and a cathode electrode are stacked in sequence along a direction away from the top surface of the substrate; the first tunnel junction is used to invert N-type carriers in the N-type buffer layer into P-type carriers, and the second tunnel junction is used to invert carriers in the upper distributed Bragg reflector into carriers of the opposite conductivity type, so that an anode electrode can be provided on the back side of the substrate and a cathode electrode can be provided above the front side of the substrate, thereby realizing the use of an N-type transistor with a faster response speed to drive the light-emitting structure of the vertical cavity surface emitting laser, and facilitating the use of a common anode driving method, thereby reducing the volume of the driving system while increasing the driving frequency and speed of the VCSEL.

[0009] In one embodiment, the active layer includes a target stacked structure comprising a P-type semiconductor layer, a quantum well layer, and an N-type semiconductor layer stacked in sequence perpendicular to the substrate; the P-type semiconductor layer is adjacent to a P-type distributed Bragg reflector; and the quantum well layer includes at least one quantum well. The optical thicknesses of the active layer, the P-type distributed Bragg reflector, and the upper distributed Bragg reflector collectively define the resonant wavelength of the VCSEL, which can be designed to fall within the emission wavelength range of the active layer to achieve laser emission.

[0010] In one embodiment, the central cross-section of the quantum well region of the quantum well layer is located within the antinode interval of the standing wave electric field of the vertical cavity surface emitting laser; the position of the antinode is z, and the antinode interval is [z-λ / 8, z+λ / 8], where λ is the wavelength of the standing wave, so as to minimize energy loss in the internal film layer and improve the light output efficiency and quality of the VCSEL.

[0011] In one embodiment, the active layer includes a plurality of target stacked structures stacked in sequence along a direction perpendicular to the substrate; adjacent target stacked structures are connected via an interlayer tunnel junction; in adjacent target stacked structures, the N-type semiconductor layer of one target stacked structure is adjacent to the P-type semiconductor layer of another target stacked structure. By combining the optical thickness of the P-type distributed Bragg reflector and the optical thickness of the upper distributed Bragg reflector, the optical thickness of the active layer is set to set the resonant cavity wavelength of the VCSEL.

[0012] In one embodiment, the central cross-section of the interlayer tunnel junction is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; the central cross-section is parallel to the substrate; the position of the node is p, and the node interval is [p - λ / 8, p + λ / 8], where λ is the wavelength of the standing wave, so as to minimize the energy loss of the internal film layer and improve the light output efficiency and quality of the VCSEL.

[0013] In one embodiment, the upper distributed Bragg reflector includes a P-type distributed Bragg reflector layer located between the second tunnel junction and the P-type metal contact layer.

[0014] In one embodiment, the upper distributed Bragg reflector includes an N-type distributed Bragg reflector layer located between the active layer and the second tunnel junction.

[0015] In one embodiment, the upper distributed Bragg reflector includes a sub-N-type distributed Bragg reflector layer and a sub-P-type distributed Bragg reflector layer. The sub-N-type distributed Bragg reflector layer is located between the active layer and the second tunnel junction; the sub-P-type distributed Bragg reflector layer is located between the second tunnel junction and the P-type metal contact layer.

[0016] In one embodiment, the central cross-section of the first tunnel junction is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; the position of the node is p, and the node interval is [p - λ / 8, p + λ / 8], where λ is the wavelength of the standing wave, so as to minimize the energy loss of the internal film layer and improve the light output efficiency and quality of the VCSEL.

[0017] According to various embodiments of the present disclosure, a second aspect of the present disclosure provides a laser array, including a plurality of vertical cavity surface emitting lasers (VCSELs) arranged in rows and columns as described in any one of the foregoing embodiments; wherein, the VCSELs located in the same row are all connected to corresponding row selection lines; the VCSELs located in the same column are all connected to corresponding column selection lines; the VCSELs in different rows are respectively connected to different row selection lines; the VCSELs in different columns are respectively connected to different column selection lines; by selecting a row selection line and a column selection line, the VCSEL connected to both the selected row selection line and the selected column selection line is selected, realizing a common anode driving method, and using an N-type transistor with a faster response speed to drive the light emitting structure of the VCSEL, reducing the volume of the driving system while increasing the driving frequency and speed of the VCSEL. By setting that the VCSELs located in the same row are all connected to corresponding row selection lines, the VCSELs located in the same column are all connected to corresponding column selection lines, the VCSELs in different rows are respectively connected to different row selection lines, and the VCSELs in different columns are respectively connected to different column selection lines, when a certain VCSEL fails, the faulty laser can be quickly located, improving the operation efficiency of the device.

[0018] In one embodiment, a plurality of vertically cavity surface emitting lasers arranged in rows and columns share a common anode electrode; wherein, among the plurality of vertically cavity surface emitting lasers sharing a common anode electrode, the cathode electrodes of any adjacent vertically cavity surface emitting lasers are insulated from each other. In the case of simplifying the anode driving, it is convenient to realize the independent driving of the cathodes of different VCSELs, meeting the driving control requirements of the customized light emission scheme of the laser array.

[0019] In one embodiment, an isolation structure is included between adjacent vertically cavity surface emitting lasers, and the isolation structure extends along the direction perpendicular to the substrate to the top surface of the P-type distributed Bragg reflector. On the premise of simplifying the structure and manufacturing process steps of the laser array, the mutual influence between adjacent VCSELs is avoided.

[0020] According to various embodiments of the present disclosure, a third aspect of the present disclosure provides a light emitting device, including:

[0021] a vertical cavity surface emitting laser as described in any one of the foregoing embodiments; or

[0022] a laser array as described in any one of the foregoing embodiments. Description of the Drawings

[0023] To better describe and illustrate the embodiments and / or examples of the applications disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the currently described embodiments and / or examples, and the best mode currently understood of these applications.

[0024] Figure 1a It is shown as a schematic longitudinal sectional view of a vertical cavity surface emitting laser provided in an embodiment of the present disclosure;

[0025] Figure 1b It is shown as a schematic longitudinal sectional view of a vertical cavity surface emitting laser provided in another embodiment of the present disclosure;

[0026] Figure 1c It is shown as a schematic longitudinal sectional view of a vertical cavity surface emitting laser provided in yet another embodiment of the present disclosure;

[0027] Figure 2 It is shown as a schematic top view of a laser array provided in an embodiment of the present disclosure;

[0028] Figure 3 It is shown as a schematic longitudinal sectional view of a laser array provided in another embodiment of the present disclosure, wherein Figure 3 It may be a schematic longitudinal sectional view obtained along the Figure 2 AA' direction shown in;

[0029] Figure 4 It is shown as a schematic flow chart of a method for fabricating a vertical cavity surface emitting laser provided in an embodiment of the present disclosure.

[0030] Explanation of reference numerals:

[0031] 11. N-type substrate; 12. N-type buffer layer; 13. First tunnel junction; 14. P-type distributed Bragg reflector; 15 / 15a / 15b. Active layer; 16 / 16a / 16b. N-type distributed Bragg reflector layer; 16m. P-type distributed Bragg reflector layer; 161. Sub N-type distributed Bragg reflector layer; 162. Sub P-type distributed Bragg reflector layer; 17 / 17a / 17b. Second tunnel junction; 18 / 18a / 18b. P-type metal contact layer; 19 / 19a / 19b. Cathode electrode; 100a. First vertical cavity surface emitting laser; 100b. Second vertical cavity surface emitting laser; 100c. Third vertical cavity surface emitting laser; 100d. Fourth vertical cavity surface emitting laser; 100e. Fifth vertical cavity surface emitting laser; 100f. Sixth vertical cavity surface emitting laser. Detailed implementation manners

[0032] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure will be thorough and complete.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein in the specification of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of the present disclosure.

[0035] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0037] The embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure. Thus, variations from the shown shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

[0038] In the embodiments of the present disclosure, the multi-layer structure may be formed layer by layer or integrally formed; wherein, adjacent two-layer structures may be in contact or isolated from each other.

[0039] In the embodiments of the present disclosure, the vertical substrate may be the upper surface of the vertical substrate, and the parallel substrate may be the upper surface of the parallel substrate.

[0040] Please refer to Figures 1a to 3 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present disclosure. Although only the components related to the present disclosure are shown in the illustrations and are not drawn according to the number, shape and size of the components in actual implementation, the types, numbers and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0041] The basic structure of a VCSEL mainly includes an active layer and DBR (Distributed Bragg Reflector, DBR) mirrors with optical feedback functions. The active layer is sandwiched between the two side DBRs, jointly forming a Fabry-Perot resonator. The excitation source generates optical gain through the gain medium of the active layer by spontaneous emission. The light waves in the resonator are reflected between the top and bottom DBRs to form a stable standing wave, which is continuously amplified after stimulated emission and finally forms a laser.

[0042] Generally, the upper mirror and the lower mirror of a VCSEL are doped with P-type and N-type materials respectively, thereby forming a diode junction.

[0043] In the case of MOSFETs, the performance characteristics of N-channel transistors are generally better than those of P-channel transistors. For example, due to the higher mobility of electrons over holes, N-channel transistors have a relatively high response speed and low resistance. For bipolar junction transistors, the performance characteristics of NPN transistors are generally better than those of PNP transistors. Therefore, when driving a VCSEL or a VCSEL array, using N-channel transistors or NPN transistors helps improve the performance of the device.

[0044] Please refer to Figures 1a - 1c , in some embodiments, a vertical cavity surface emitting laser is provided, including an N-type substrate 11, an upper distributed Bragg reflector (not shown), and an N-type buffer layer 12, a first tunnel junction 13, a P-type distributed Bragg reflector 14, an active layer 15, a second tunnel junction 17, a P-type metal contact layer 18, and a cathode electrode 19 stacked in sequence along the direction perpendicular to the substrate (e.g., the oz direction); the first tunnel junction 13 is used to invert N-type carriers in the N-type buffer layer 12 into P-type carriers; the second tunnel junction 17 is used to invert carriers in the upper distributed Bragg reflector into carriers of the opposite conductivity type; the upper distributed Bragg reflector is located between the active layer 15 and the P-type metal contact layer 18, and the upper distributed Bragg reflector is associated with the second tunnel junction 17; wherein, the surface of the N-type substrate 11 facing away from the N-type buffer layer 12 includes an anode electrode (not shown).

[0045] As an example, please continue to refer to Figure 1a , the upper distributed Bragg reflector includes an N-type distributed Bragg reflector layer 16, and the N-type distributed Bragg reflector layer 16 is located between the active layer 15 and the second tunnel junction 17. The second tunnel junction 17 can be used to invert N-type carriers in the N-type distributed Bragg reflector layer 16 into P-type carriers.

[0046] As an example, please continue to refer to Figure 1b , the upper distributed Bragg reflector includes a P-type distributed Bragg reflector layer 16m, and the P-type distributed Bragg reflector layer 16m is located between the second tunnel junction 17 and the P-type metal contact layer 18. The second tunnel junction 17 can be used to invert P-type carriers in the P-type distributed Bragg reflector layer 16m into N-type carriers to match the conductivity type of the active layer 15.

[0047] As an example, please continue to refer to Figure 1c, the upper distributed Bragg reflector includes a sub-N-type distributed Bragg reflector layer 161 and a sub-P-type distributed Bragg reflector layer 162. The sub-N-type distributed Bragg reflector layer 161 is located between the active layer 15 and the second tunnel junction 17; the sub-P-type distributed Bragg reflector layer 162 is located between the second tunnel junction 17 and the P-type metal contact layer 18. The second tunnel junction 17 can be used to reverse the N-type carriers in the sub-N-type distributed Bragg reflector layer 161 into P-type carriers.

[0048] As an example, please continue to refer to Figure 1a , in the direction away from the top surface of the substrate, an N-type buffer layer 12, a first tunnel junction 13, a P-type distributed Bragg reflector 14, an active layer 15, an N-type distributed Bragg reflector 16, a second tunnel junction 17, a P-type metal contact layer 18, and a cathode electrode 19 are sequentially stacked; the first tunnel junction 13 is used to reverse the N-type carriers in the N-type buffer layer 12 into P-type carriers, and then the second tunnel junction 17 is used to reverse the N-type carriers in the N-type distributed Bragg reflector 16 into P-type carriers, so that an anode electrode can be arranged on the back surface of the substrate, and a cathode electrode 19 can be arranged above the front surface of the substrate, realizing a light-emitting structure for driving a vertical cavity surface emitting laser using an N-type transistor with a faster response speed, and facilitating the adoption of a common anode driving method to reduce the volume of the driving system while increasing the driving frequency and speed of the VCSEL.

[0049] As an example, please continue to refer to Figures 1a - 1c , the N-type substrate 11 can be composed of a semiconductor material, an insulating material, a semi-insulating material, or any combination thereof. The N-type substrate 11 can be a single-layer structure or a multi-layer structure. For example, the N-type substrate 11 can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. The type of the substrate should not limit the protection scope of the present disclosure. The N-type substrate 11 can include one or more of elements such as word lines, bit lines, and transistors, which are omitted herein because they have little relation to the inventive point of the present solution.

[0050] As an example, please continue to refer to Figures 1a - 1c , generally, one or more of elements such as word lines, bit lines, and transistors need to be fabricated in the N-type substrate 11. To reduce the lattice mismatch between the first tunnel junction 13 and the N-type substrate 11, or to prevent possible defects in the N-type substrate 11 from having an adverse effect on the first tunnel junction 13, an N-type buffer layer 12 is arranged between the N-type substrate 11 and the first tunnel junction 13 to effectively improve the yield and reliability of fabricating semiconductor devices.

[0051] As an example, please continue to refer to Figures 1a - 1c, the active layer 15 includes a target stack structure; the target stack structure includes a P-type semiconductor layer (not shown), a quantum well layer (not shown), and an N-type semiconductor layer (not shown) stacked in sequence along the direction perpendicular to the substrate (e.g., the oz direction); the P-type semiconductor layer is adjacent to the P-type distributed Bragg reflector 14; the quantum well layer includes at least one quantum well. The optical thickness of the active layer 15, the optical thickness of the P-type distributed Bragg reflector 14, and the optical thickness of the upper distributed Bragg reflector together define the resonant cavity wavelength of the VCSEL, which can be designed within the emission wavelength range of the active layer 15 to achieve laser emission.

[0052] As an example, the central cross-section of the quantum well region of the quantum well layer is located within the antinode interval of the standing wave electric field of the vertical cavity surface emitting laser; the position of the antinode is z, and the antinode interval is [z - λ / 8, z + λ / 8], where λ is the wavelength of the standing wave, so as to minimize the energy loss of the internal film layer and improve the light extraction efficiency and quality of the VCSEL.

[0053] As an example, the active layer includes a plurality of target stack structures stacked in sequence along the direction perpendicular to the substrate; adjacent target stack structures are connected via an interlayer tunnel junction; in adjacent target stack structures, the N-type semiconductor layer of one target stack structure is adjacent to the P-type semiconductor layer of another target stack structure. By combining the optical thickness of the P-type distributed Bragg reflector and the optical thickness of the upper distributed Bragg reflector, and setting the optical thickness of the active layer, the resonant cavity wavelength of the VCSEL is set.

[0054] As an example, the central cross-section of the interlayer tunnel junction is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; the central cross-section is parallel to the substrate; the position of the node is p, and the node interval is [p - λ / 8, p + λ / 8], where λ is the wavelength of the standing wave, so as to minimize the energy loss of the internal film layer and improve the light extraction efficiency and quality of the VCSEL.

[0055] As an example, please continue to refer to Figures 1a - 1c , the central cross-section (perpendicular to the oz direction) of the first tunnel junction 13 is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; the position of the node is p, and the node interval is [p - λ / 8, p + λ / 8], where λ is the wavelength of the standing wave, so as to minimize the energy loss of the internal film layer and improve the light extraction efficiency and quality of the VCSEL.

[0056] In some embodiments, please continue to refer to Figures 1a - 1c, the P-type distributed Bragg reflector 14 may include a stacked multi-layer first reflector layer (not shown), the first reflector layer includes first sub-reflector layers (not shown) and second sub-reflector layers (not shown) with different refractive indexes. In the P-type distributed Bragg reflector 14, the first sub-reflector layer is adjacent to the N-type substrate 11; the first sub-reflector layer and the second sub-reflector layer of adjacent first reflector layers are adjacent; the first sub-reflector layer includes indium gallium phosphide, and the lattice constant of the compound in the second sub-reflector layer is greater than that of indium gallium phosphide.

[0057] In some embodiments, please continue to refer to Figures 1a - 1c , the first sub-reflector layer includes indium gallium phosphide, and the lattice constant of the compound in the second sub-reflector layer is greater than that of indium gallium phosphide, which can cancel out the stress in the first reflector layer in the P-type distributed Bragg reflector 14 and reduce the warpage degree. In currently related vertical cavity surface emitting lasers, by using an epitaxial layer mirror in which two materials with different refractive indexes are alternately grown according to an optical thickness of a quarter wavelength, a very high reflectivity (>99%) can be obtained, which can meet the special requirements of the device structure for the mirror. However, due to the lattice difference between the substrate and the epitaxial layer, stress accumulates in each thin epitaxial layer, and at the same time, due to the overall thickness of the epitaxial layer mirror being too thick, the warpage degree of the epitaxial wafer becomes larger, thereby affecting the yield of the semiconductor chip. In the vertical cavity surface emitting laser according to the embodiments of the present disclosure, by providing a stacked multi-layer first reflector layer in the P-type distributed Bragg reflector 14, the first reflector layer includes indium gallium phosphide first sub-reflector layers and second sub-reflector layers with different refractive indexes. In the P-type distributed Bragg reflector 14, the first sub-reflector layer is adjacent to the N-type substrate 11, the first sub-reflector layer and the second sub-reflector layer of adjacent first reflector layers are adjacent, and the lattice constant of the compound in the second sub-reflector layer is set to be greater than that of indium gallium phosphide, which can cancel out the stress between the sub-reflector layers in the P-type distributed Bragg reflector 14, reduce the warpage degree, and improve the yield of the semiconductor chip.

[0058] In some embodiments, please continue to refer to Figures 1a - 1c , the upper distributed Bragg reflector includes a stacked multi-layer second reflector layer (not shown), the second reflector layer includes third sub-reflector layers (not shown) and fourth sub-reflector layers (not shown) with different refractive indexes. The third sub-reflector layer and the fourth sub-reflector layer of adjacent second reflector layers are adjacent; both the third sub-reflector layer and the fourth sub-reflector layer include aluminum gallium arsenide, and the aluminum contents of the third sub-reflector layer and the fourth sub-reflector layer are different.

[0059] Exemplarily, the third sub-reflector layer and the fourth sub-reflector layer include Al x Ga 1-x As, Al x Ga 1-xThe As material is formed by the uniform recombination of AlAs and GaAs, and has the advantages of high carrier mobility, adjustable Al composition, and very small lattice mismatch with GaAs. Among them, Al in the third sub-reflection layer x Ga 1-x As, where x < 0.1; Al in the fourth sub-reflection layer x Ga 1-x As, where x > 0.9. The third sub-reflection layer with a high refractive index and the fourth sub-reflection layer with a low refractive index grow alternately. By increasing the number of periods, a high reflectivity can be obtained, meeting the special requirements of the VCSEL structure for the mirror.

[0060] In some embodiments, the first sub-reflection layer includes In y Ga 1-y P; where y ∈ [0, 0.48], for example, 0, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, or 0.48, etc.

[0061] In some embodiments, the second sub-reflection layer includes aluminum arsenide or aluminum gallium arsenide.

[0062] As an example, the first sub-reflection layer can be In 0.48 Ga 0.52 P, the substrate can be GaAs. The lattice constant of In 0.48 Ga 0.52 P is smaller than that of the GaAs substrate, and the first sub-reflection layer is under tensile stress. The second sub-reflection layer includes Al x Ga 1-x As, usually x > 0.9. The lattice constant of the second sub-reflection layer is larger than that of In 0.48 Ga 0.52 P, and the second sub-reflection layer is under compressive stress. In this way, the tensile stress and compressive stress cancel each other out within each DBR period (i.e., the first reflection layer), reducing the warpage of the epitaxial wafer.

[0063] Specifically, for a VCSEL with a wavelength of 940 nm, the refractive index difference between high- and low-Al-composition AlGaAs is about 0.465, and the refractive index difference between In 0.48 Ga 0.52 P and AlGaAs is about 0.246. Using InGaP as the DBR material, in order to obtain sufficient reflectivity, a low warpage can be maintained when the DBR thickness is relatively thick.

[0064] In some embodiments, a laser array is provided, including a plurality of vertical-cavity surface-emitting lasers (VCSELs) arranged in rows and columns as described in any one of the foregoing embodiments; wherein, the VCSELs located in the same row are all connected to corresponding row selection lines; the VCSELs located in the same column are all connected to corresponding column selection lines; the VCSELs in different rows are respectively connected to different row selection lines; the VCSELs in different columns are respectively connected to different column selection lines; by selecting a row selection line and a column selection line, the VCSELs connected to both the selected row selection line and the selected column selection line are selected, realizing a common-anode driving method, and using N-type transistors with faster response speeds to drive the light-emitting structures of the VCSELs, reducing the volume of the driving system while increasing the driving frequency and speed of the VCSELs. By setting that the VCSELs located in the same row are all connected to corresponding row selection lines, the VCSELs located in the same column are all connected to corresponding column selection lines, the VCSELs in different rows are respectively connected to different row selection lines, and the VCSELs in different columns are respectively connected to different column selection lines, when a certain VCSEL fails, the faulty laser can be quickly located, improving the operating efficiency of the device.

[0065] As an example, please refer to Figures 2 - 3 , the first vertical-cavity surface-emitting laser 100a, the second vertical-cavity surface-emitting laser 100b, the third vertical-cavity surface-emitting laser 100c, the fourth vertical-cavity surface-emitting laser 100d, the fifth vertical-cavity surface-emitting laser 100e, and the sixth vertical-cavity surface-emitting laser 100f arranged in rows and columns share a common anode electrode; among the first vertical-cavity surface-emitting laser 100a, the second vertical-cavity surface-emitting laser 100b, the third vertical-cavity surface-emitting laser 100c, the fourth vertical-cavity surface-emitting laser 100d, the fifth vertical-cavity surface-emitting laser 100e, and the sixth vertical-cavity surface-emitting laser 100f, the cathode electrodes of any adjacent vertical-cavity surface-emitting lasers are insulated from each other. In the case of simplifying the anode driving, it is convenient to realize the independent cathode driving of different VCSELs, meeting the driving control requirements of the customized light-emitting scheme of the laser array.

[0066] As an example, an isolation structure is included between adjacent vertical-cavity surface-emitting lasers, and the isolation structure extends along the direction perpendicular to the substrate (such as the oz direction) to the top surface of the P-type distributed Bragg reflector, avoiding the mutual influence between adjacent VCSELs on the premise of simplifying the structure and manufacturing process steps of the laser array.

[0067] As an example, please continue to refer to Figure 3, the isolation structure can be an isolation trench. An isolation trench is provided between the first vertical cavity surface emitting laser 100a and the second vertical cavity surface emitting laser 100b, and the isolation trench extends in the direction perpendicular to the substrate (e.g., the oz direction) to the top surface of the P-type distributed Bragg reflector 14; the active layer 15a, N-type distributed Bragg reflector 16a, second tunnel junction 17a, P-type metal contact layer 18a, and cathode electrode 19a of the first vertical cavity surface emitting laser 100a are isolated and insulated from the active layer 15b, N-type distributed Bragg reflector 16b, second tunnel junction 17b, P-type metal contact layer 18b, and cathode electrode 19b of the second vertical cavity surface emitting laser 100b via the isolation trench; the first vertical cavity surface emitting laser 100a and the second vertical cavity surface emitting laser 100b share the N-type substrate 11, N-type buffer layer 12, first tunnel junction 13, and P-type distributed Bragg reflector 14.

[0068] In some embodiments, a light-emitting device is provided, including the vertical cavity surface emitting laser as described in any one of the foregoing embodiments.

[0069] In some embodiments, a light-emitting device is provided, including the laser array as described in any one of the foregoing embodiments.

[0070] As an example, please refer to Figure 4 , a method for fabricating a vertical cavity surface emitting laser is provided, including:

[0071] Step S602: Provide an N-type substrate, the back surface of the N-type substrate includes an anode electrode;

[0072] Step S604: Form an upper distributed Bragg reflector on the front surface of the N-type substrate, and sequentially stack an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, a second tunnel junction, a P-type metal contact layer, and a cathode electrode along the direction perpendicular to the substrate; the first tunnel junction is used to invert N-type carriers in the N-type buffer layer into P-type carriers; the second tunnel junction is used to invert carriers in the upper distributed Bragg reflector into carriers of the opposite conductivity type.

[0073] As an example, please continue to refer to Figure 1a, an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, an N-type distributed Bragg reflector, a second tunnel junction, a P-type metal contact layer, and a cathode electrode are sequentially stacked in a direction away from the top surface of the substrate; the first tunnel junction is used to invert N-type carriers in the N-type buffer layer into P-type carriers, and then the second tunnel junction is used to invert N-type carriers in the N-type distributed Bragg reflector into P-type carriers, so that an anode electrode can be disposed on the back surface of the substrate and a cathode electrode can be disposed above the front surface of the substrate, realizing a light-emitting structure for driving a vertical cavity surface-emitting laser using an N-type transistor with a faster response speed, and facilitating the adoption of a common anode driving method to reduce the volume of the driving system while increasing the driving frequency and speed of the VCSEL.

[0074] It should be understood that although Figure 4 the steps in the flowchart of Figure 4 are shown sequentially in the order indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover,

[0075] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present disclosure.

[0076] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0077] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0078] The above-described embodiments only represent several implementation manners of the present disclosure. Their descriptions are relatively specific and detailed, but they should not be construed as limitations to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent should be subject to the appended claims.

Claims

1. A vertical cavity surface emitting laser, characterized in that, It includes an N-type substrate, an upper distributed Bragg reflector, and an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, a second tunnel junction, a P-type metal contact layer, and a cathode electrode that are sequentially stacked along a direction perpendicular to the substrate; The first tunnel junction is used to invert the carriers in the N-type buffer layer into carriers of the opposite conductivity type; The second tunnel junction is used to invert the carriers in the upper distributed Bragg reflector into carriers of the opposite conductivity type; The upper distributed Bragg reflector is located between the active layer and the P-type metal contact layer, and the upper distributed Bragg reflector is associated with the second tunnel junction; Wherein, the surface of the N-type substrate facing away from the N-type buffer layer includes an anode electrode.

2. The vertical cavity surface emitting laser according to claim 1, characterized in that The active layer includes a target stacked structure; The target stacked structure includes a P-type semiconductor layer, a quantum well layer, and an N-type semiconductor layer that are sequentially stacked along a direction perpendicular to the substrate; the P-type semiconductor layer is adjacent to the P-type distributed Bragg reflector; The quantum well layer includes at least one quantum well; or The central cross-section of the first tunnel junction is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; The position of the node is p, and the node interval is [p - λ / 8, p + λ / 8], where λ is the wavelength of the standing wave.

3. The vertical cavity surface emitting laser according to claim 2, characterized in that, The central cross-section of the quantum well region of the quantum well layer is located within the antinode interval of the standing wave electric field of the vertical cavity surface emitting laser; The position of the antinode is z, and the antinode interval is [z - λ / 8, z + λ / 8]; or The active layer includes a plurality of the target stacked structures that are sequentially stacked along a direction perpendicular to the substrate; Adjacent target stacked structures are connected via an interlayer tunnel junction; Among adjacent target stacked structures, the N-type semiconductor layer of one target stacked structure is adjacent to the P-type semiconductor layer of another target stacked structure.

4. The vertical cavity surface emitting laser according to claim 3, characterized in that, The central cross-section of the interlayer tunnel junction is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; the central cross-section is parallel to the substrate; The position of the node is p, and the node interval is [p - λ / 8, p + λ / 8].

5. The vertical cavity surface emitting laser according to claim 1, wherein The upper distributed Bragg reflector includes: A P-type distributed Bragg reflector layer located between the second tunnel junction and the P-type metal contact layer; or An N-type distributed Bragg reflector layer located between the active layer and the second tunnel junction.

6. The vertical cavity surface emitting laser according to claim 1, characterized in that, The upper distributed Bragg reflector includes: A sub-N-type distributed Bragg reflector layer located between the active layer and the second tunnel junction; and A sub-P-type distributed Bragg reflector layer located between the second tunnel junction and the P-type metal contact layer.

7. A laser array, characterized in that, It includes a plurality of vertical cavity surface emitting lasers arranged in rows and columns as described in any one of claims 1-6; Wherein, the vertical cavity surface emitting lasers in the same row are all connected to the corresponding row selection line; The vertical cavity surface emitting lasers in the same column are all connected to the corresponding column selection line; The vertical cavity surface emitting lasers in different rows are respectively connected to different row selection lines; The vertical cavity surface emitting lasers in different columns are respectively connected to different column selection lines; Select a vertical cavity surface emitting laser that is connected to both the selected row selection line and the selected column selection line by selecting a row selection line and a column selection line.

8. The laser array according to claim 7, wherein, A plurality of the vertical cavity surface emitting lasers arranged in rows and columns share a common anode electrode; Among the plurality of the vertical cavity surface emitting lasers sharing the common anode electrode, the cathode electrodes of any adjacent vertical cavity surface emitting lasers are insulated from each other.

9. The laser array according to claim 8, characterized in that, An isolation structure is included between adjacent vertical cavity surface emitting lasers, and the isolation structure extends in a direction perpendicular to the substrate to the top surface of the P-type distributed Bragg reflector.

10. A light-emitting device, characterized in that, Comprising: The vertical cavity surface emitting laser according to any one of claims 1-6; Or The laser array according to any one of claims 7-9.

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