Switched mode power supply (SMPS)

Abstract

The invention relates to a switched mode power supply (SMPS). A switched mode power supply includes: a first switch coupling a first node receiving a supply voltage to a second node supplying an output voltage; and a second switch coupling a third node receiving the reference voltage to the second node. The comparator is used for comparing the output voltage with the comparison voltage. When the switched mode power supply is operating in the pulse skipping mode, the comparator generates an output signal indicating that the output voltage is higher than the comparison voltage during a portion of the on phase of the first switch. Once the output voltage is below the comparison voltage, the switched mode power supply transitions from the pulse skip mode to the continuous conduction mode.

Description

[0001] Priority Claim

[0002] This application claims the benefit of priority of French Patent Application No. 2400814, filed on January 29, 2024, the content of which is hereby incorporated by reference in its entirety to the fullest extent permitted by law. Technical Field

[0003] The present disclosure generally relates to electronic systems and, more particularly, to circuits for powering these systems. More specifically, the present disclosure relates to switch-mode power supplies and their different operating modes. Background Art

[0004] There are several types of power supply circuits that enable the delivery of a current / voltage pair to an electronic circuit, device, or system, or more generally to a load. Linear power supplies and switch-mode power supplies are examples of power supply circuits.

[0005] A switch-mode power supply (SMPS) is a power supply circuit configured to supply a DC voltage (usually from another DC voltage). A switch-mode power supply is typically a DC / DC converter, but some switch-mode power supplies may include a rectification stage that enables them to take an AC voltage (e.g., the mains supply) as an input.

[0006] It may be desirable to be able to at least partially improve certain aspects of known switch-mode power supplies.

[0007] There is a need for switch-mode power supplies with higher performance.

[0008] There is a need for switch-mode power supplies that consume less energy.

[0009] There is a need to overcome all or some of the disadvantages of known switch-mode power supplies. Summary of the Invention

[0010] According to a first aspect, an embodiment provides a switch-mode power supply that exhibits less output voltage oscillation during the transition from pulse-skipping mode (PSK) to continuous conduction mode (CCM).

[0011] An embodiment provides a switch-mode power supply including a comparator that compares the output voltage of the switch-mode power supply with a reference voltage, such that the conduction time of a switch of the switch-mode power supply that outputs at the output reference voltage (e.g., ground voltage) is forced to be 1 for at least 20% of the time.

[0012] One embodiment provides a switched - mode power supply including a first switch configured to couple a first node receiving a first power voltage to a second node configured to supply a second output voltage; and a comparator configured to compare the second output voltage with a third comparison voltage; wherein when the switched - mode power supply is operating in pulse - skipping mode, the comparator is configured to indicate that the second output voltage is higher than the third comparison voltage during a portion of the on - time of the first switch.

[0013] Another embodiment provides a method of implementing a switched - mode power supply including a first switch that couples a first node receiving a power voltage to a second node supplying a second output voltage; a comparator adapted to compare the second output voltage with a third comparison voltage; wherein when the switched - mode power supply is operating in pulse - skipping mode, the comparator is configured to indicate that the second output voltage is higher than the third comparison voltage during a portion of the on - time of the first switch.

[0014] According to one embodiment, the portion of the on - time starts to extend from a first (intermediate) time after a second initial time of the on - time until a third final time of the on - time.

[0015] According to one embodiment, the duration of the portion is greater than or equal to 20% of the duration of the on - time.

[0016] According to one embodiment, the first switch is a PMOS - type transistor.

[0017] According to one embodiment, the comparator includes a circuit for adapting its output signal.

[0018] According to one embodiment, the circuit for adapting its output signal is an OR logic gate.

[0019] According to one embodiment, the switched - mode power supply further includes a circuit for controlling the first switch, the circuit being adapted to receive the output from the comparator.

[0020] According to one embodiment, the circuit for control is a state machine.

[0021] According to one embodiment, the switched - mode power supply further includes a second switch that couples a third node receiving a fourth reference voltage to the second output node.

[0022] According to one embodiment, the second switch is an NMOS - type transistor.

[0023] According to one embodiment, the switched - mode power supply further includes a coil coupling the first switch to the second output node.

[0024] According to one embodiment, the switch-mode power supply further includes a zero-current detection circuit configured to detect whether the current flowing through the coil is zero.

[0025] According to one embodiment, when the second output voltage is higher than the third comparison voltage and the current flowing through the coil is zero, the switch-mode power supply switches from the continuous conduction mode (CCM) to the pulse skip mode (PSK).

[0026] According to one embodiment, when the second output voltage is lower than the third comparison voltage and the current flowing through the coil is zero, the switch-mode power supply switches from the pulse skip mode to the DC conduction mode.

[0027] According to a second aspect, one embodiment provides a switch-mode power supply that consumes less energy during the transition from the pulse skip mode (PSK) to the continuous conduction mode (CCM).

[0028] One embodiment provides a switch-mode power supply that includes a comparator such as the comparator described above, and during the conduction stage of the NMOS transistor of the switch-mode power supply, the transition from the pulse skip mode to the continuous conduction mode is performed.

[0029] One embodiment provides a switch-mode power supply including a first switch that couples a first node receiving a first power supply voltage to a second node supplying a second output voltage; a second switch that couples a third node receiving a fourth reference voltage to the second output node; and a comparator configured to compare the second output voltage with a third comparison voltage, wherein when the switch-mode power supply is operating in the pulse skip mode, the comparator is configured to indicate that during a portion of the conduction stage of the first switch, the second output voltage is higher than the third comparison voltage, and wherein once the second output voltage is lower than the third comparison voltage, the switch-mode power supply switches from the pulse skip mode to the continuous conduction mode.

[0030] Another embodiment provides a method for implementing a switched-mode power supply, the switched-mode power supply including a first switch that couples a first node receiving a first power voltage to a second node supplying a second output voltage; a second switch that couples a third node receiving a fourth reference voltage to the second output node; and a comparator configured to compare the second output voltage with a third comparison voltage, wherein when the switched-mode power supply is operating in pulse-skipping mode, the comparator is configured to indicate that the second output voltage is higher than the third comparison voltage during a portion of the on-phase of the first switch, and wherein once the second output voltage falls below the third comparison voltage, the switched-mode power supply transitions from pulse-skipping mode to continuous-conduction mode.

[0031] According to one embodiment, the portion of the on-phase begins to extend from a first (intermediate) time after a second initial time of the on-phase until a third final time of the on-phase.

[0032] According to one embodiment, the duration of the portion is greater than or equal to 20% of the duration of the on-phase.

[0033] According to one embodiment, the first switch is a PMOS-type transistor.

[0034] According to one embodiment, the second switch is an NMOS-type transistor.

[0035] According to one embodiment, the switched-mode power supply further includes a circuit for controlling the first switch, the circuit being adapted to receive the output from the comparator.

[0036] According to one embodiment, the control circuit is a state machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other features and advantages, and other features and advantages, are described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which

[0038] Figure 1 an embodiment of a switched-mode power supply is shown;

[0039] Figure 2 shows Figure 1 an application example of an embodiment of;

[0040] Figure 3 shows a diagram illustrating Figure 1 a first aspect of the operation of an embodiment of;

[0041] Figure 4 shows a diagram illustrating Figure 1 a first implementation mode of an embodiment of;

[0042] Figure 5 shows Figure 4 an actual implementation example of the first line-of-sight mode of

[0043] Figure 6 shows illustrates Figure 1 a timing diagram of the second implementation mode of the illustrated embodiment of

[0044] Figure 7 shows Figure 6 an actual implementation example of the second implementation mode of

[0045] Figure 8 shows illustrates Figure 1 the operation of the second aspect of the illustrated embodiment of; and

[0046] Figure 9 shows illustrates regarding Figure 8 the operations described in the figure of Detailed Description

[0047] In the various figures, the same features are designated by the same reference numerals. In particular, structural features and / or functional features common to the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0048] For clarity, only the steps and elements that contribute to an understanding of the described embodiments are shown and described in detail.

[0049] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate elements other than conductors; and when referring to two elements coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

[0050] In the following description, whenever an absolute position qualifier (such as "front", "rear", "top", "bottom", "left", "right", etc.) or a relative position qualifier (such as "top", "bottom", "upper", "lower", etc.) or a direction qualifier (such as "horizontal", "vertical", etc.) is mentioned, the orientation of the drawing is referred to unless otherwise specified.

[0051] Unless otherwise specified, the expressions "about", "substantially", "essentially", and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0052] The embodiments described below relate to improvements to known switched-mode power supplies. A switched-mode power supply is a circuit that enables the supply of a DC power voltage, typically by taking another DC voltage or an AC voltage as input. The switched-mode power supply involved herein is a DC / DC converter, that is, a converter that converts a DC voltage into an AC voltage. Figure 1 A switched-mode power supply according to an embodiment is shown, Figure 2 and an example application of such a switched-mode power supply is detailed.

[0053] Switched-mode power supplies typically include multiple operating modes, depending specifically on the size of the load connected to the output of the switched-mode power supply, hereinafter referred to as the output load. The first operating mode is the continuous conduction mode (CCM) for high output loads. The second operating mode is the pulse skip mode (PSK) or the pulse frequency modulation mode (PFM) for low output loads.

[0054] According to a first aspect, the embodiments described below relate to the case where a medium output load (that is, a load that is neither high nor low) is connected to the output of a switched-mode power supply. In such a configuration, the switched-mode power supply may perform a series of conversions between the CCM mode and the PSK mode, and the output voltage of the switched-mode power supply may oscillate. To overcome this problem, the method described below provides a modified comparator that is configured to determine the size of the output load. Figures 3 to 7 These embodiments are detailed.

[0055] According to a second aspect, the embodiments described below disclose a way to save energy during the transition from the PSK mode to the CCM mode. Figure 8 and Figure 9 These embodiments are shown in detail.

[0056] Figure 1 is an electrical diagram of an embodiment of the switched-mode power supply 100.

[0057] The switched-mode power supply 100 includes two switches T101 and T102 connected in series between two nodes, where one node receives the DC power voltage VDD and the other node receives a reference voltage VSS, for example, a ground voltage. The first conducting terminal of the switch T101 is connected (preferably, connected) to the node supplying the power voltage VDD, and the second conducting terminal of the switch T101 is connected (preferably, connected) to the first terminal of the switch T102. The second conducting terminal of the switch T102 is connected (preferably, connected) to the node supplying the reference voltage VSS.

[0058] The switches T101 and T102 are, for example, transistors, more specifically, metal oxide semiconductor field effect transistors, or MOSFET transistors, or MOS transistors. More specifically, the transistor T101 is a P-channel MOS transistor, or a P-type MOS transistor, or a PMOS transistor, and the transistor T102 is an N-channel MOS transistor, or an N-type MOS transistor, or an NMOS transistor. Those skilled in the art can easily think of other types of switches. Specifically, other types of transistors, such as bipolar transistors, can be used herein. Further, the reverse control switches T101 and T102 are shown here, but those skilled in the art are capable of forming the switched-mode power supply 100 with switches controlled in a similar manner.

[0059] The switched-mode power supply 100 further includes a control circuit FSM101 (FSM), which is configured to control the switches T101 and T102. According to one example, the control circuit FSM101 is an automaton, such as a state machine or a finite state machine (FSM). The control circuit receives, as inputs, a plurality of signals (described below) from other circuits forming the switched-mode power supply 100, and delivers, as outputs, a control signal CMDP intended to control the switch T101 and a control signal CMDN intended to control the switch T102. The control circuit FSM101 manages the operating modes of the switched-mode power supply 100, that is, the CCM mode and the PSK mode. To this end, the control circuit FSM101 may also supply a signal MODE, which indicates the current operating mode of the switched-mode power supply 100.

[0060] The switched-mode power supply further includes a coil B101 and an output capacitor C101. The coil B101 is connected to the junction node of the switches T101 and T102 and the output node OUT100 of the switched-mode power supply 100. Thus, the first conducting terminal of the coil B101 is connected (preferably, joined) to the junction node of the switches T101 and T102, and the second conducting terminal of the coil B101 is connected (preferably, joined) to the node OUT100. The node OUT100 supplies a feedback voltage VFB, which is an image of the output voltage of the switched-mode power supply 100. The capacitor C101 may be located outside the switched-mode power supply 100 and is connected between the output node OUT100 and the ground. Thus, the first conducting terminal of the capacitor C101 is connected (preferably, joined) to the node OUT100, and the second conducting terminal of the capacitor C101 is connected (preferably, joined) to a node receiving a reference voltage VSS or to a node connected to another reference voltage different from the reference voltage VSS.

[0061] The switched-mode power supply further includes a pulse-width modulation loop 101 (PWM loop), and the pulse-width modulation loop 101 includes an inverter amplifier Comp101 and a comparator Comp102 assembled in cascade. The inverter amplifier Comp101 receives a comparison voltage Vref at the non-inverting input and receives a feedback voltage VFB from the switched-mode power supply 100 at the inverting input. The inverter amplifier Comp101 outputs an error voltage Verr. The inverter amplifier Comp101 amplifies the voltage difference between the voltages it receives as inputs. The comparator Comp102 receives the error voltage Verr at the non-inverting input and receives a ramp voltage Vramp at the inverting input. The ramp voltage Vramp is generated by a ramp generator circuit of the switched-mode power supply 100, and the ramp generator circuit is not shown herein. The comparator Comp102 outputs a pulse-width modulation voltage PWM, and the PWM is supplied to the control circuit FSM101.

[0062] The switched-mode power supply further includes a comparison circuit 102, and the comparison circuit 102 enables determination of the operating state of the switched-mode power supply 100. The comparison circuit 102 includes a zero-current detection circuit ZCD101 (ZCD), a circuit FB101 (FB) for comparing the feedback voltage VFB and the comparison voltage Vref, and a circuit Comp103 for comparing the ramp voltage Vramp and the comparison voltage Vref.

[0063] The zero-current detection circuit ZCD101 (ZCD) is configured to detect whether the current flowing through the coil B101 changes sign. The circuit ZCD101 is a comparator. To this end, the circuit ZCD101 receives a reference voltage VSS at the non-inverting input and receives a voltage VLX supplied by the junction node of the switches T101 and T102 at the inverting input. The circuit ZCD101 outputs a signal END_NMOS, and the signal END_NMOS indicates the end of the conduction phase of the switch T102.

[0064] The circuit FB101 (FB) compares the feedback voltage VFB and is configured to estimate the magnitude of the output load of the switched-mode power supply 100. To this end, the circuit FB101 receives the feedback voltage VFB at the non-inverting input and receives the comparison voltage Vref at the inverting input. The circuit FB101 outputs a signal START_PMOS, and the signal START_PMOS indicates the start of the conduction phase of the switch T101.

[0065] The circuit Comp103 compares the ramp voltage Vramp, receives the comparison voltage Vref at the non-inverting input, and receives the ramp voltage Vamp at the inverting input. The circuit Comp103 outputs the signal END_PMOS, which indicates the end of the conduction phase of the switch T102. The circuit Comp103 defines the duration of the conduction phase of the switch T101.

[0066] In combination Figures 3 to 9 with the embodiments described in

[0067] Figure 2 An example of the application of a switching mode power supply of the type of switching mode power supply 100 described with respect to Figure 1 is shown very schematically and in block form.

[0068] Figure 2 More specifically, the microcontroller 200 (MCU) and its power supply unit 201 (PMU) are illustrated. According to one embodiment, the power supply unit 201 includes a reference signal generation circuit 2011 (Ref), Figure 1 a switching mode power supply 2012 (SMPS) of the type of switching mode power supply 100 described in

[0069] one or more voltage converter circuits 2013 (LDO), one or more state machines 2014 (FSM), one or more oscillation circuits 2015 (OSC), and one or more regulation circuits 2016 (LPREG), for example, a low power regulation circuit.

[0070] Figure 3 is a state diagram 300 illustrating the operation of the switching mode power supply 100 described with respect to 1 according to the first aspect.

[0071] As previously described, the switching mode power supply 100 includes multiple operating modes depending on the magnitude of its output load. More specifically, the switching mode power supply 100 includes two operating modes: a continuous conduction mode (CCM) for high output loads and a pulse skip mode (PSK) for low output loads.

[0072] When the switching mode power supply 100 is in the PSK mode, it charges its coil B101 using voltage peaks, the duration between which depends on the voltage requested by the output load. The lower the load, the longer the duration between the peaks.

[0073] When the switching mode power supply 100 is in the CCM mode, it continuously charges its coil B101 by sending an oscillating voltage to the coil B101.

[0074] Whether in the PSK mode or in the CCM mode, the control switches T101 and T102 are controlled to obtain the voltage for powering the coil B101.

[0075] To switch from one mode to another, it is essential to estimate the size of the output load. For this purpose, the output voltage supplied to the output load (represented by the feedback voltage VFB) is compared with the comparison voltage Vref. The result of this comparison indicates the operating mode in which the switching mode power supply should be.

[0076] More specifically, when the feedback voltage VFB is lower than the comparison voltage Vref, it is assumed that the switching mode power supply 100 operates in the CCM mode; and when the feedback voltage VFB is higher than the comparison voltage Vref, it is assumed that the switching mode power supply 100 operates in the PSK mode. This comparison is achieved by the comparator FB101 described with respect to Figure 1 and is also described in detail with respect to Figures 4 to 6 .

[0077] However, to effectively initiate the transition between one mode and another and avoid continuous changes when the load varies around the mean value, it is essential to take into account a second criterion. Therefore, to switch from one state to another, the comparison result of the feedback voltage VFB and the comparison voltage Vref when the current IB101 flowing through the coil B101 becomes zero must be taken into account. Therefore, the current IB101 is monitored by the zero current detection circuit ZCD101 described with respect to Figure 1 .

[0078] Therefore, to switch from the CCM mode to the PSK mode, two conditions (referred to as Cond1) must be met: the feedback voltage VFB is greater than the comparison voltage Vref, and the current IB101 flowing through the coil B101 becomes zero.

[0079] To switch from the PSK mode to the CCM mode, two conditions (referred to as Cond2) must be met: the feedback voltage VFB is lower than the comparison voltage Vref, and the current IB101 flowing through the coil B101 becomes zero.

[0080] As previously described, to monitor the effectiveness of these conditions, the comparator FB101 and the detection circuit ZCD101 are implemented. However, according to an embodiment, to compensate for the possible delay of the comparator FB101, the result of the comparator FB101 is not taken into account during the entire conduction phase of the switch T101. A more detailed explanation of this is given with respect to Figures 4 to 7 .

[0081] Figure 4 shows the timing diagram of the first implementation mode of the switching mode power supply illustrated in the PSK mode. Figure 1

[0082] Figure 4 It includes the following timing diagrams: Timing diagram 401 showing the theoretical time variation of the current IB101 flowing through coil B101, timing diagram 402 showing the time variation of the signal CMDP for controlling switch T101, timing diagram 403 showing the time variation of the control signal CMDN of switch T102, and showing the time variation of Figure 1 the voltage VCLAMP inside the comparator FB101 described above in timing diagram 404, and the time variation of the output signal START_PMOS of the comparator FB101 described above in timing diagram 405. Figure 1

[0083] As previously described, in the PSK mode, the current IB101 flowing through coil B101 periodically appears as pulses, and the duration between the pulses specifically depends on the value of the feedback voltage VFB. More specifically, coil B101 is charged when switch T101 is turned on (that is, during the conduction phase of switch T101), and is discharged when switch T102 is turned on (that is, during the conduction phase of switch T102).

[0084] The conduction phase of switch T101 is implemented as follows. Once the feedback voltage VFB is lower than the comparison voltage Vref, a falling edge appears in the signal START_PMOS, which causes a falling edge in the control signal CMDP, and switch T101 is turned on. When the voltage Vramp ( Figure 4 not shown in the figure) is higher than the comparison voltage Vref, the conduction phase of switch T101 ends, which causes a state change in the signal END_PMOS, that is, a rising edge or a falling edge. The state change of the signal END_PMOS causes a rising edge in the control signal CMDP, which indicates the end of the conduction phase of switch T101.

[0085] The conduction phase of switch T102 is implemented as follows. The conduction phase of switch T102 starts when the conduction phase of switch T101 ends (that is, when the ramp voltage Vramp is greater than the comparison voltage Vref). When the current IB101 flowing through coil B101 becomes zero, the conduction phase of switch T102 ends, which causes a state change in the signal END_NMOS ( Figure 4 not shown in the figure), and further causes a falling edge in the control signal CMDN.

[0086] ​​As previously mentioned, the transition from the PSK mode to the CCM mode requires the implementation of comparator FB101 and detection circuit ZCD101. The inventors observed during the testing phase that comparator FB101 may exhibit a delay, which in itself causes a delay when transitioning from the PSK mode to the CCM mode. To overcome this problem, the inventors decided not to take into account the result of comparator FB101 during the entire duration of the conduction phase of switch T101. More specifically, the operation of comparator FB101 is modified to be further controlled by voltage VCLAMP, which defines a duration D400 during which, regardless of the value of feedback voltage VFB, the output of comparator FB101 indicates that the feedback voltage VFB is higher than the comparison voltage Vref. In other words, the operation of comparator FB101 is modified such that during a portion of the conduction phase of switch T101, regardless of the value of feedback voltage VFB, the output of comparator FB101 indicates that the feedback voltage VFB is higher than the comparison voltage Vref. Regarding Figure 5 A more detailed description of this modified comparator FB101 will be given.

[0087] According to the first embodiment, duration D400 is defined to be in the range of 20% to 100% of the duration of the conduction phase of switch T101. Further, this duration D400 is placed at the end of the conduction phase of switch T101, that is, it starts after the start of the conduction phase of switch T101 and continues until the end of the conduction phase of switch T101. In other words, the portion of the conduction phase starts from a first (intermediate) time after a second initial time of the conduction phase and continues until a third final time of the conduction phase.

[0088] Figure 5 An example of a comparator 500 configured to be used as comparator FB101 in the switch - mode power supply 100 described above is shown. Figure 1 in the switch - mode power supply 100 described above.

[0089] Comparator 500 includes a comparator stage 501 (Comp) that is configured to take voltage VFB and Vref as inputs. More specifically, stage 501 receives the comparison voltage Vref on the non - inverting input and the feedback voltage VFB on the inverting input. Stage 501 outputs a result signal. This stage 501 will not be described in detail herein as it is within the capabilities of those skilled in the art.

[0090] Comparator 500 further includes a circuit 502 configured to adapt the output signal START_PMOS of the comparator 500. The circuit 502 receives the power supply voltage VDD and the signals Mode and CMDP. The circuit 502 includes a control circuit 503(CMD) configured to generate a voltage VCLAMP that enables the definition of a duration D400; and a switch 504. The switch 504 receives the power supply voltage VDD at its first conductive terminal and has a second conductive terminal coupled (preferably, connected) to the output of the comparator 501. The switch 504 receives the voltage VCLAMP at its control terminal.

[0091] According to one example, comparator 500 further includes two inverter circuits Inv501 and Inv502. The input of the inverter circuit Inv501 is coupled (preferably, connected) to node A, and the output of the inverter circuit Inv501 is coupled (preferably, connected) to the input of the inverter circuit Inv502. The output of the inverter circuit Inv502 supplies the output signal START_PMOS of the comparator 500.

[0092] Figure 6 Shows a timing diagram of a second preferred implementation mode of the switched-mode power supply in PSK mode. Figure 1

[0093] Figure 6 Shows the following timing diagrams: a timing diagram 601 illustrating the theoretical time variation of the current IB101 flowing through the coil B101, a timing diagram 602 illustrating the time variation of the signal CMDP for controlling the switch T101, a timing diagram 603 illustrating the time variation of the signal CMDN for controlling the switch T102, and a timing diagram 604 illustrating the time variation of the voltage VCLAMP inside the comparator FB101 described with respect to Figure 1 and a timing diagram 605 illustrating the time variation of the output signal START_PMOS of the comparator FB101 described with respect to Figure 1

[0094] This second implementation mode is similar to the first implementation mode described with respect to Figure 4 Elements common to these two implementation modes will not be described in detail. Only the differences between these implementation modes will be highlighted.

[0095] As previously mentioned, to avoid delay problems in the comparator FB101, the voltage VCLAMP is used to modify its operation, and a duration D600 is introduced during the conduction phase of the switch T101. The duration D600 is longer than that with respect to Figure 4The described duration D400 is long. The duration D600 is equal to the maximum duration D400, that is, equal to the duration of the conduction phase of switch T101, which duration has been subtracted by the time of the pulse enabling the opening of said conduction phase. Regarding Figure 7 The comparator FB101 modified to obtain the duration D600 is also described in detail.

[0096] Figure 7 An example of an embodiment of a comparator 700 configured to be used as the comparator FB101 in the switched - mode power supply 100 described regarding Figure 1 is shown.

[0097] Comparator 700 is similar to comparator 500 described regarding Figure 5 No further detailed description is given for the elements common to comparators 500 and 700. Only the differences between comparators 500 and 700 are highlighted.

[0098] Comparator 700 includes a comparator stage 501 (Comp), a circuit 702 for adapting the output signal START_PMOS, and inverter circuits Inv501 and Inv502.

[0099] Circuit 702 receives the supply voltage VDD and the signals Mode and CMDP. Circuit 702 includes an OR - type logic gate OR701 and a switch 504 instead of the control circuit 503 (CMD). The first input terminal of gate OR701 receives the signal Mode, and the second input terminal of gate OR701 receives the control signal CMDP. The output terminal of logic gate OR701 supplies the voltage VCLAMP. Switch 504 receives the supply voltage VDD on its first conductive terminal and has a second conductive terminal that is coupled (preferably, connected) to the output of comparator stage 501. Switch 504 receives the voltage VCLAMP on its control terminal.

[0100] Figure 8 is a state diagram 800 illustrating the operation of the switched - mode power supply 100 according to a second aspect regarding Figure 1 described.

[0101] As previously described, the switched - mode power supply 100 includes two operating modes, namely, the CCM mode and the PSK mode. Figure 8 The state diagram 800 of

[0102] is related to the transition from the PSK mode to the CCM mode. Figure 5 or Figure 7 is achieved by using one of the comparator circuits 500 or 700 or the other comparator circuit of Figure 1After the switching mode power supply 100, the inventors have found a new way to achieve an energy-saving transition between the PSK mode and the CCM mode.

[0103] The implementation mode of the transition between the PSK mode and the CCM mode described below performs this transition only during the conduction phase of the switch T102. This is because the comparators 500 or 700 are used.

[0104] When the switching mode power supply 100 operates according to this implementation mode, the switching mode power supply switches from the PSK mode to the CCM mode only during the conduction phase of the switch T102 and when the feedback voltage VFB becomes lower than the comparison voltage Vref. The zero-crossing point of the current flowing through the coil B101 is no longer taken into account. In fact, when using Figures 4 to 6 the implementation mode, the output of the comparator FB101 is not taken into account during the conduction phase of the switch T101 because the latter has been modified. Verifying the state of the current IB101 is only to avoid erroneously detecting the transition during the conduction phase of the switch T101. Specifically, the output of the circuit ZCD101 is used only during the conduction phase of the switch T102 to avoid false detection due to the slowness of the circuit FB101 because the circuit FB101 has to wait for the current in the coil to deplete.

[0105] Otherwise, the transition phase from the PSK mode to the CCM mode includes the following series of states: state 801 (PSKPMOS_ON), in which the switching mode power supply 100 is in the PSK mode and during the conduction phase of the switch T101; state 802 (PSKNMOS_ON), in which the switching mode power supply 100 is in the PSK mode and during the conduction phase of the switch T102; state 803 (CCMPMOS_ON), in which the switching mode power supply 100 enters the CCM mode through the conduction phase of the switch T101.

[0106] The transition between state 801 and state 802 is performed in the manner described with respect to Figure 4 (denoted as condition Cond801, that is, by using the comparison of the voltage Vramp and the comparison voltage Vref).

[0107] The transition between state 802 and state 803 is performed by monitoring a single condition Cond802 (the comparison result of the feedback voltage VFB and the comparison voltage Vref).

[0108] An advantage of this embodiment is that it also enables a fast transition from the PSK mode to the CCM mode when the feedback voltage VFB suddenly drops. In fact, since only this parameter is taken into account, it also takes into account no delay.

[0109] Figure 9including curves that illustrate the advantages of the implementation described with respect to Figure 8 the implementation described.

[0110] Figure 9 The following curves are shown: a curve Iref showing the average value that the current IB101 flowing through coil B101 is to reach, a curve IB101-1 showing the variation of the current IB101 flowing through coil B101 in the case where the Figure 8 implementation mode is not implemented, a curve IB101-2 showing the variation of the current IB101 flowing through coil B101 in the case where the Figure 8 implementation mode is implemented, a curve START_PMOS showing the variation of the current IB101 flowing through coil B101 in the case where the Figure 8 implementation mode is implemented, a curve START_PMOS representing the variation of the signal START_PMOS, a curve VFB1 showing the variation of the feedback voltage VFB in the case where the Figure 8 implementation mode is not implemented, and a curve VFB2 showing the variation of the feedback voltage VFB in the case where the Figure 8 implementation mode is implemented.

[0111] Figure 9 The curves of Figure 8 more specifically illustrate the transition from the PSK mode to the CCM mode and compare the Figure 3 implementation mode with the operations described with respect to Figure 3 Accordingly, two switching mode power supplies 901 and 902 are considered here. Power supply 901 operates in the mode described with respect to Figure 8 and power supply 902 uses the Figure 9 implementation mode. More specifically, switching mode power supplies 901 and 902 operate in the PSK mode in the left hand portion of Figure 9 and in the CCM mode in the right hand portion of Figure 9 The transition occurs in the central portion of

[0112] It should be noted that using the Figure 8 implementation mode enables the mode to be changed before the coil B101 of power supply 902 is fully discharged. Thus, the mode can be changed without having to recharge the coil, which is typically achieved by a boost circuit. Accordingly, Figure 8 the implementation mode of

[0113] can accelerate the transition from the PSK mode to the CCM mode while saving energy.

[0114] Based on the functional indications given above, those skilled in the art are capable of actually applying the described embodiments and variations.

Claims

1. A switching mode power supply, comprising: A first switch that couples a first node configured to receive a supply voltage to a second node that supplies an output voltage; A second switch that couples a third node configured to receive a reference voltage to the second node; And A comparator configured to compare the output voltage with a comparison voltage; Wherein when the switching mode power supply is operating in pulse skip mode, the comparator is configured to indicate that the output voltage is higher than the comparison voltage during a portion of the on-phase of the first switch; And A control circuit configured to convert the switching mode power supply from the pulse skip mode to continuous conduction mode in response to the comparator indicating that the output voltage is lower than the comparison voltage.

2. The power supply according to claim 1, wherein the portion of the on-phase extends from a first time after a second time and until a third time, wherein the second time is an initial time of the on-phase, and wherein the third time is a last time of the on-phase.

3. The power supply according to claim 1, wherein a duration of the portion of the on-phase is greater than or equal to 20% of a duration of the on-phase from the initial time to the final time.

4. The power supply according to claim 1, wherein the first switch is a PMOS type transistor.

5. The power supply according to claim 1, wherein the second switch is an NMOS type transistor.

6. The power supply according to claim 1, wherein the control circuit receives an output from the comparator and is configured to control the first switch.

7. The power supply according to claim 6, wherein the control circuit is a state machine.

8. A switching mode power supply, comprising: A first switch that couples a first node that receives a supply voltage to a second node that supplies an output voltage; A second switch that couples a third node that receives a first reference voltage to the second node; And A comparator configured to compare a feedback voltage derived from the output voltage with a second reference voltage and generate a control signal that transitions to a first logic state that indicates a start of an on-phase of the first switch; Wherein the comparator circuit further includes a clamping circuit configured to clamp the control signal in a second logic state opposite the first logic state in response to a combination of a current operating mode of the switching mode power supply and a switching control signal for controlling the first switch.

9. The power supply according to claim 8, wherein the clamping circuit includes: A transistor coupled to the supply voltage; And A logic circuit configured to logically combine a mode signal indicating the current operating mode of the switching mode power supply and the switching control signal; Wherein an output of the logic circuit controls switching of the transistor.

10. The power supply according to claim 9, wherein the logic circuit is a logical OR gate.

11. The power supply according to claim 8, wherein the clamping circuit is configured to clamp the control signal at the second logic state in response to a change in the logic state of a mode signal indicating the current operating mode of the switched-mode power supply when the switch control signal is controlling the first switch to close.

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