An eight-phase output phase interpolator

Abstract

The present invention discloses an eight-phase output phase interpolator, which belongs to the field of analog integrated circuit design technology, and includes: a frequency divider, an input buffer, a CMOS-to-CML circuit, a digital decoder, a first phase interpolation core, a second phase interpolation core, a limiter, a phase blender and a CML-to-CMOS circuit. The present invention adopts a phase interpolation structure, and two phase interpolation cores, an odd-path and an even-path, respectively interpolate the four-phase orthogonal CML signals. The two output signals differ by 45°, and the phase deviation introduced in its linear interpolation structure presents a characteristic of opposite directions between the two paths. By fusing the two output signals through the phase blender, the nonlinear error in the single-path structure is effectively offset, the linearity of the overall interpolation output is improved, the INL of the interpolator is significantly reduced, and the phase resolution and accuracy of the multi-phase clock system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit design, and in particular relates to an eight-phase output phase interpolator. Background Art

[0002] The development of high-speed communication systems has placed higher demands on clock generation and recovery modules with high precision, high speed, and low power consumption. In applications such as clock data recovery, multiphase clock generation, and high-speed data sampling, phase interpolators are key circuit modules for achieving high-resolution phase control. Their performance directly impacts the system's time resolution, jitter characteristics, and power consumption. Traditional phase interpolators typically employ weighted current or voltage interpolation structures, controlling the signal path through different logic control codes to interpolate between adjacent multiphase clocks.

[0003] However, traditional eight-phase output phase interpolators usually use linear interpolation, with large integral nonlinearity (INL) and poor interpolation effect. Traditional eight-phase output phase interpolators are interpolation paths adapted to different quadrants, and interpolation units are often enabled on demand in a switchable form. This control method causes most interpolation units to be idle when not working in the current quadrant, and not participate in effective interpolation, resulting in a waste of chip area and current resources, and reducing the utilization efficiency of the overall structure. In addition, traditional eight-phase output phase interpolators usually achieve phase control of different quadrants through external quadrant selectors. This part of the circuit requires additional multi-way switching network and control logic, which not only significantly increases the structural complexity and clock path length of the system, but also easily introduces phase jitter and boundary switching errors, affecting the stability and interpolation accuracy of the system. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an eight-phase output phase interpolator. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides an eight-phase output phase interpolator, comprising:

[0006] A frequency divider, an input buffer, a CMOS-to-CML circuit, a digital decoder, a first phase interpolation core, a second phase interpolation core, a limiter, a phase blender, and a CML-to-CMOS circuit; wherein,

[0007] The frequency divider is used to divide the frequency of the two-phase input signal and output a four-phase input signal;

[0008] The input buffer is used to isolate the frequency divider and the CMOS-to-CML circuit, and to perform shaping and matching on the four-phase input signal output by the frequency divider, and output the matched four-phase input signal;

[0009] The CMOS-to-CML circuit is used to convert the matched four-phase input signal into a four-phase orthogonal CML signal;

[0010] The digital decoder is used to decode the external input CODE code and output the odd-path logic control code and the even-path logic control code;

[0011] The first phase interpolation core is used to perform phase interpolation on the four-phase orthogonal CML signal under the control of the odd-path logic control code, and output an odd-path four-phase orthogonal interpolation signal;

[0012] The second phase interpolation core is used to perform phase interpolation on the four-phase orthogonal CML signal under the control of the even-path logic control code, and output an even-path four-phase orthogonal interpolation signal;

[0013] The limiter is used to perform limiting processing on the odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal, and output an eight-phase interpolation signal;

[0014] The phase fuser is configured to perform phase fusion on the eight-phase interpolation signal and output an eight-phase fused signal;

[0015] The CML-to-CMOS circuit is used to convert the eight-phase fusion signal into a CMOS-level clock signal and output the converted signal.

[0016] Beneficial effects of the present invention:

[0017] 1. This invention utilizes a phase interpolation structure, with two phase interpolation cores, odd and even, interpolating the four-phase orthogonal CML signals separately. The two output signals differ by 45°, and the phase deviation introduced by the linear interpolation structure exhibits opposite directions between the two paths. By fusing the two output signals through a phase blender, the nonlinear error in the single-path structure is effectively offset, improving the linearity of the overall interpolation output, significantly reducing the interpolator's INL, and enhancing the phase resolution and accuracy of the multiphase clock system.

[0018] 2. Each interpolation unit proposed in this invention selects a different quadrant output path based on a logic control code switch, internalizing the quadrant inversion function and eliminating the need for additional quadrant switching circuits. This reduces the system's structural complexity, clock path length, and area.

[0019] 3. Each interpolation unit proposed in this invention is always in operation. Compared with an eight-phase output phase interpolator consisting of four phase interpolators, only half the number of interpolation units is required, saving layout area, making the circuit module more compact, and improving the interpolator's integration into high-speed chips. It is suitable for large-scale integrated communication systems and SoC platforms.

[0020] 4. The input load of the phase interpolation core proposed in the present invention is the same under any external input CODE code, and the input signal does not change with the change of the number of interpolation units, thereby ensuring the stability of the working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the principle of an eight-phase output phase interpolator provided by an embodiment of the present invention;

[0022] Figure 2 A schematic structural diagram of a phase interpolation core in an eight-phase output phase interpolator provided by an embodiment of the present invention;

[0023] Figure 3 A schematic structural diagram of an interpolation unit in a phase interpolation core provided by an embodiment of the present invention;

[0024] Figure 4 Schematic diagram of outputs of the first phase interpolation core and the second phase interpolation core provided by an embodiment of the present invention;

[0025] Figure 5 A schematic diagram illustrating the principle of a first fusion situation during phase fusion provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram illustrating the principle of the second fusion situation during phase fusion provided by an embodiment of the present invention;

[0027] Figure 7 A simulation diagram of the output signal INL of the phase interpolation core and the output signal INL of the phase blender provided in an embodiment of the present invention;

[0028] Figure 8 This is a simulation result diagram of an eight-phase clock signal ultimately output by an eight-phase output phase interpolator provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0030] The embodiment of the present invention provides an eight-phase output phase interpolator, such as Figure 1 As shown, this may include:

[0031] A frequency divider, an input buffer, a CMOS-to-CML circuit, a digital decoder, a first phase interpolation core, a second phase interpolation core, a limiter, a phase blender, and a CML-to-CMOS circuit; wherein,

[0032] A frequency divider, used to divide the frequency of a two-phase input signal and output a four-phase input signal;

[0033] The input buffer is used to isolate the frequency divider and the CMOS-to-CML circuit, and to shape and match the four-phase input signal output by the frequency divider and output the matched four-phase input signal;

[0034] A CMOS-to-CML circuit for converting matched four-phase input signals into four-phase quadrature CML signals;

[0035] Digital decoder, used to decode the external input CODE code and output odd-path logic control code and even-path logic control code;

[0036] The first phase interpolation core is used to perform phase interpolation on the four-phase orthogonal CML signal under the control of the odd-path logic control code, and output an odd-path four-phase orthogonal interpolation signal;

[0037] The second phase interpolation core is used to perform phase interpolation on the four-phase orthogonal CML signal under the control of the even-path logic control code, and output an even-path four-phase orthogonal interpolation signal;

[0038] A limiter is used to perform limiting processing on the odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal, and output an eight-phase interpolation signal;

[0039] A phase fuser, used to perform phase fusion on the eight-phase interpolation signal and output an eight-phase fused signal;

[0040] The CML-to-CMOS circuit is used to convert the eight-phase fusion signal into a CMOS-level clock signal and output it.

[0041] The eight-phase output phase interpolator proposed in this embodiment of the present invention utilizes a phase interpolation structure. Two phase interpolation cores, one for the odd path and the other for the even path, interpolate the four-phase orthogonal CML signals separately. The two output signals differ by 45°, and the phase deviation introduced by the linear interpolation structure exhibits opposite directions between the two paths. By fusing the two output signals through a phase blender, the nonlinear errors inherent in the single-path structure are effectively offset, improving the linearity of the overall interpolated output, significantly reducing the interpolator's INL, and enhancing the phase resolution and accuracy of the multiphase clock system.

[0042] To facilitate understanding, each module of the eight-phase output phase interpolator proposed in the embodiment of the present invention is introduced separately below.

[0043] The frequency divider divides the two-phase input signal and outputs a four-phase input signal.

[0044] The frequency divider converts the high frequency bi-phase input signal: CLK P , CLK N Frequency divided into four-phase input signal: CLK IP, CLK IN , CLK QP , CLK QN .

[0045] The input buffer isolates the frequency divider and the CMOS-to-CML circuit, shapes and matches the four-phase input signals output by the frequency divider, and enhances the driving capability of the subsequent CMOS-to-CML circuit.

[0046] The CMOS-to-CML circuit converts the CMOS-level clock signal into a current-mode logic (CML) differential signal and outputs a four-phase orthogonal CML signal: CLK I,P , CLK I,N , CLK Q,P and CLK Q,N , to meet the input requirements of the phase interpolator.

[0047] The digital decoder decodes the externally input N-bit CODE code, generates an odd-path logic control code and an even-path logic control code, and controls the first phase interpolation core and the second phase interpolation core respectively.

[0048] The difference between the odd path logic control code and the even path logic control code is 2 N-3 , so that the phase difference between the output odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal is 45°; where N represents the number of bits of the CODE code.

[0049] The first phase interpolation core and the second phase interpolation core have the same structure, such as Figure 2 As shown, both include: a first resistor R NODD , the second resistor R PODD , the third resistor R NEVEN , the fourth resistor R PEVEN , a first interpolation array and a second interpolation array; wherein,

[0050] The first resistor R NODD The first end of is connected to the power supply voltage, the second end is connected to the first output end of the first interpolation array, and the second end serves as the first output end of the corresponding phase interpolation core;

[0051] The second resistor R PODD A first end of the phase interpolation core is connected to the power supply voltage, a second end of the phase interpolation core is connected to the second output end of the first interpolation array, and the second end serves as the second output end of the corresponding phase interpolation core;

[0052] The third resistor R NEVEN The first end is connected to the power supply voltage, the second end is connected to the third output end of the second interpolation array, and the second end serves as the third output end of the corresponding phase interpolation core;

[0053] The fourth resistor R PEVEN The first end is connected to the power supply voltage, the second end is connected to the fourth output end of the second interpolation array, and the second end serves as the fourth output end of the corresponding phase interpolation core;

[0054] The differential input terminal of the first interpolation array serves as the first signal input terminal of the corresponding phase interpolation core, the control terminal serves as the first control code input terminal of the corresponding phase interpolation core, the bias terminal is connected to the bias voltage VB, the first output terminal is connected to the first output terminal of the second interpolation array, the second output terminal is connected to the second output terminal of the second interpolation array, the third output terminal is connected to the third output terminal of the second interpolation array, and the fourth output terminal is connected to the fourth output terminal of the second interpolation array;

[0055] The differential input terminal of the second interpolation array serves as the second signal input terminal of the corresponding phase interpolation core, the control terminal serves as the second control code input terminal of the corresponding phase interpolation core, and the bias terminal is connected to the bias voltage VB.

[0056] The first interpolation array and the second interpolation array have the same structure, and both include a plurality of parallel interpolation units.

[0057] The first interpolation array and the second interpolation array both include 2 N-2 Parallel interpolation units; where N represents the number of bits of the external input CODE code.

[0058] Specifically, the first interpolation array 2 N-2 Interpolation units constitute I path, and 2 in the second interpolation array N-2 The interpolation units constitute the Q path. Figure 2 As can be seen from the figure, the input signals of the first phase interpolation core and the second phase interpolation core are four-phase orthogonal CML signals: CLK I,P , CLK I,N , CLK Q,P and CLK Q,N , I Road 2 N-2 The logic control signal received by the control terminal of each interpolation unit is LOGIC I , Q Road 2 N-2 The logic control signal received by the control terminal of each interpolation unit is LOGIC Q , thereby controlling the connection to the first resistor R NODD , the second resistor R PODD , the third resistor R NEVEN and the fourth resistor R PEVEN The number of interpolation units is set to realize current weighted interpolation; the bias terminal is connected to the bias voltage VB to control the current flowing through the MOS tube corresponding to the bias terminal. The output four-phase orthogonal interpolation signals are: VOP ODD 、VON ODD 、VOPEVEN 、VON EVEN It can be understood that for the first phase interpolation core, LOGIC I LOGIC is the weighted coefficient of the odd-path logic control code acting on the I path. Q is the weighted coefficient of the odd-path logic control code acting on the Q path; for the second phase interpolation core, LOGIC I LOGIC is the weighted coefficient of the even-path logic control code acting on the I path. Q It is the weighting coefficient of the even-path logic control code acting on the Q path.

[0059] Interpolation units, such as Figure 3 As shown, this may include:

[0060] MOS transistor MN1, MOS transistor MN2, MOS transistor MN3, first single-pole four-throw switch S1 and second single-pole four-throw switch S2; wherein,

[0061] The gate terminals of the MOS transistor MN1 and the MOS transistor MN2 serve as differential input terminals of the corresponding interpolation arrays;

[0062] The source end of the MOS transistor MN1 is connected to the source end of the MOS transistor MN2, and the drain end is connected to the input end of the first single-pole four-throw switch S1;

[0063] The drain terminal of the MOS transistor MN2 is connected to the input terminal of the second single-pole four-throw switch S2;

[0064] The source terminal of the MOS transistor MN3 is grounded, the gate terminal serves as the bias terminal of the corresponding interpolation array, and the drain terminal is connected to the source terminal of the MOS transistor MN1;

[0065] The control end of the first single-pole four-throw switch S1 serves as the control end of the corresponding interpolation array, and the output end thereof is respectively connected to the first output end ODD_IN, the second output end ODD_IP, the third output end EVEN_IN, and the fourth output end EVEN_IP of the corresponding interpolation array;

[0066] The control end of the second SP4T switch S2 is connected to the control end of the first SP4T switch S1 , and the output ends are respectively connected to the first output end ODD_IN, the second output end ODD_IP, the third output end EVEN_IN and the fourth output end EVEN_IP of the corresponding interpolation array.

[0067] It can be understood that, for the sake of convenience, the logic signal LOGIC connected to the control terminal of the first single-pole four-throw switch S1 indicates that the logic control signal is LOGIC I OR logic control signal is LOGIC Q ,CLK P and CLK NRepresents the differential input signal. For the interpolation unit in the first interpolation array, LOGIC refers to the logic control signal LOGIC I ,CLK P Refers to CLK I,P ,CLK N Refers to CLK I,N For the interpolation unit in the second interpolation array, LOGIC refers to the logic control signal LOGIC Q ,CLK P Refers to CLK Q,P ,CLK N Refers to CLK Q,N , which indicates that the control end of the interpolation array is used to receive a binary logic control code to control the connection mode of the interpolation unit so that the current output is connected to different resistance paths to complete the interpolation.

[0068] The differential input of the interpolation array is connected to the four-phase orthogonal CML signal: CLK I,P , CLK I,N , CLK Q,P and CLK Q,N .

[0069] The interpolation unit can realize the inversion of different quadrants under the control of the logic control code. The output end of the first single-pole four-throw switch S1 of an interpolation unit of the I path is connected to the first resistor R NODD The output end of the second single-pole four-throw switch S2 is connected to the second resistor R PODD When the interpolation unit is the first resistor R NODD and the second resistor R PODD Provides a positive current of I and does not affect the third resistor R NEVEN and the fourth resistor R PEVEN Function: The output end of the first single-pole four-throw switch S1 of an interpolation unit of the I path is selected to connect the second resistor R PODD The output end of the second single-pole four-throw switch S2 is connected to the first resistor R NODD When the interpolation unit is the first resistor R NODD and the second resistor R PODD The circuit provides a reverse I-channel unit current and does not affect the third resistor R NEVEN and the fourth resistor R PEVEN Function: The output end of the first single-pole four-throw switch S1 of an interpolation unit of the I path is selected to connect the third resistor R NEVEN The output end of the second single-pole four-throw switch S2 is connected to the fourth resistor R PEVEN When the interpolation unit is the third resistor R NEVEN and the fourth resistor R PEVENProvides a positive current I path, and does not affect the first resistor R NODD and the second resistor R PODD Function: The output end of the first single-pole four-throw switch S1 of an interpolation unit of the I path is selected to connect the fourth resistor R PEVEN The output end of the second single-pole four-throw switch S2 is connected to the third resistor R NEVEN When the interpolation unit is the third resistor R NEVEN and the fourth resistor R PEVEN Provides a reverse I-way unit current and does not affect the first resistor R NODD and the second resistor R PODD effect;

[0070] The output end of the first single-pole four-throw switch S1 of an interpolation unit of the Q circuit is selectively connected to the first resistor R NODD The output end of the second single-pole four-throw switch S2 is connected to the second resistor R PODD When the interpolation unit is the first resistor R NODD and the second resistor R PODD Provides a positive Q-channel unit current and does not affect the third resistor R NEVEN and the fourth resistor R PEVEN Function: The output end of the first single-pole four-throw switch S1 of an interpolation unit of the Q circuit is selected to connect the second resistor R PODD The output end of the second single-pole four-throw switch S2 is connected to the first resistor R NODD When the interpolation unit is the first resistor R NODD and the second resistor R PODD Provides a reverse Q-path unit current and does not affect the third resistor R NEVEN and the fourth resistor R PEVEN Function: The output end of the first single-pole four-throw switch S1 of an interpolation unit of the Q circuit is selected to connect the third resistor R NEVEN The output end of the second single-pole four-throw switch S2 is connected to the fourth resistor R PEVEN When the interpolation unit is the third resistor R NEVEN and the fourth resistor R PEVEN Provides a positive Q-channel unit current and does not affect the first resistor R NODD and the second resistor R PODD Function: The output end of the first single-pole four-throw switch S1 of an interpolation unit of the Q path is selected to connect the fourth resistor R PEVEN The output end of the second single-pole four-throw switch S2 is connected to the third resistor R NEVEN When the interpolation unit is the third resistor R NEVEN and the fourth resistor R PEVEN Provides a reverse Q-path unit current and does not affect the first resistor R NODDand the second resistor R PODD Function; Among them, the Q-channel unit current is the current output by an interpolation unit in the Q-channel, and the I-channel unit current is the current output by an interpolation unit in the I-channel.

[0071] The first SP4T switch S1 and the second SP4T switch S2 have the same structure, both consisting of four transistors connected in parallel. The gate voltage of the transistor is controlled to control the start of the transistor, thereby realizing the function of the SP4T switch.

[0072] Output diagram of the first phase interpolation core and the second phase interpolation core, as shown in Figure 4 As shown, VOP ODD (First Phase Interpolation Core), VOP EVEN (first phase interpolation core), VON ODD (first phase interpolation core) and VON EVEN (First phase interpolation core) represents the four-phase orthogonal interpolation signal output by the first phase interpolation core, VOP ODD (Second Phase Interpolation Core), VOP EVEN (Second phase interpolation core), VON ODD (second phase interpolation core) and VON EVEN (Second phase interpolation core) represents the four-phase orthogonal interpolation signal output by the second phase interpolation core, Figure 4 As can be seen, VOP ODD and VON ODD is a differential signal with opposite phases, VOP EVEN and VON EVEN is a differential signal with opposite phases, so Figure 4 Only the coordinates of one signal in the differential signal are given. N-2 The parallel interpolation units constitute I path, 2 N-2 The parallel interpolation units form the Q path. If the Q path has 2 N-2 -15 interpolation units S1 output terminal selection connection R NODD , the output of S2 is connected to R PODD When these interpolation units are the first resistor R NODD and the second resistor R PODD Provides 2 N-2 -15 forward Q-channel unit currents. I-channel has 15 interpolation units. The output of S1 is connected to R NODD , the output of S2 is connected to R PODD When these interpolation units are the first resistor R NODD and the second resistor R PODD Provides 15 positive I-way unit currents; at the same time, the output of S1 of the remaining 15 units of Q-way is connected to RPEVEN , the output of S2 is connected to R NEVEN When these interpolation units are the third resistor R NEVEN and the fourth resistor R PEVEN Provides 15 reverse Q-channel unit currents. The remaining 2 I-channels N-2 -15 units of S1 output terminal selection connection R NEVEN , the output of S2 is connected to R PEVEN When these interpolation units are the third resistor R NEVEN and the fourth resistor R PEVEN Provides 15 units of forward I current. Figure 4 As shown, the first resistor R NODD and the second resistor R PODD 2 N-2 -15 positive Q-channel unit currents and 15 positive I-channel unit currents are superimposed and converted into differential signals VOP after passing through pull-up resistors ODD and VON ODD ; The third resistor R NEVEN and the fourth resistor R PEVEN 15 reverse Q-channel unit currents and 2 N-2 -15 positive I-channel unit currents are superimposed and converted into differential signals VOP after passing through pull-up resistors EVEN and VON EVEN .Depend on Figure 4 It can be obtained that the phase difference between the phase differential signal VOP and the differential signal VON is 90°, so the phase interpolation core can output four-phase orthogonal interpolation signals of 0°, 90°, 180°, and 270°; among them, the Q-channel unit current is the current output by an interpolation unit in the Q-channel, and the I-channel unit current is the current output by an interpolation unit in the I-channel.

[0073] It can be understood that the odd-path logic control code and the even-path logic control code inputted by the digital decoder to the first phase interpolation core and the second phase interpolation core are different. N-2 The control code is input to the first phase interpolation core I path 2 N-2 The phase difference of the control code is 2 N-3 ; Input to the Q path of the second phase interpolation core 2 N-2 The control code is 2 times different from the control code input to the Q path of the first phase interpolation core. N-3 , so that the first phase interpolation core can output four-phase orthogonal interpolation signals of 0°, 90°, 180°, and 270°, and the second phase interpolation core can output four-phase orthogonal interpolation signals of 45°, 135°, 225°, and 315°.

[0074] The output signal of the eight-phase output phase interpolator proposed in the present invention can be expressed as:

[0075] ;

[0076] in, and Indicates the weighted coefficient acting on the I or Q path respectively. represents the angular frequency, represents the amplitude of the output signal, Indicates the phase of the output signal.

[0077] In order to make the output signal have a constant swing, the ideal control code should be the decimal digital code corresponding to the external input N-BitCODE code. , which changes as a trigonometric function:

[0078] ;

[0079] ;

[0080] Wherein, N represents the number of bits of the CODE code.

[0081] The digital decoder proposed in the embodiment of the present invention performs linear control in the following manner:

[0082] Quadrant 1: ;

[0083] Quadrant 4: ;

[0084] Quadrant 3: ;

[0085] Quadrant 4: .

[0086] Each interpolation unit proposed in the embodiment of the present invention selects a different quadrant output path through a switch according to a logic control signal, thereby internalizing the quadrant inversion function and eliminating the need for an additional quadrant switching circuit, thereby reducing the system's structural complexity and clock path length, and reducing the area; each interpolation unit is always in a working state. Compared with an eight-phase phase interpolator composed of four phase interpolators, only half the interpolation units are required, saving layout area, making the circuit module more compact, and improving the integrability of the interpolator in high-speed chips, making it suitable for large-scale integrated communication systems and SoC platforms; the input load of each bit interpolation core is the same under any external input CODE code, and the input signal does not change with changes in the number of interpolation units, thereby ensuring the stability of the working state.

[0087] The limiter performs limiting processing on the odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal, and outputs an eight-phase interpolation signal, including:

[0088] The limiter converts the odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal into square wave signals with the same swing amplitude;

[0089] The square wave signals with the same swing amplitude are converted into CML signals with the same swing amplitude through filters, and the CML signals with the same swing amplitude are output as eight-phase interpolation signals.

[0090] The limiter can include a CMOS-to-CML circuit and a filtering circuit. The phase interpolation core is linear interpolation, and the four-phase orthogonal interpolation signal output by the linear interpolation structure has different swings under different CODE codes. The limiter first converts the input odd-path four-phase orthogonal interpolation signal and even-path four-phase orthogonal interpolation signal into square wave signals with the same swing through the CMOS-to-CML circuit. Then, the filtering circuit converts the square wave signals with the same swing into CML signals with the same swing. These are output as eight-phase interpolation signals, providing input signals with consistent swing and slope for the subsequent phase blender.

[0091] The phase blender performs phase blending on the eight-phase interpolation signal and outputs an eight-phase blended signal. Figure 5 and Figure 6 As shown in the figure, the phase blender performs phase blending on two CML signals with a phase difference of 45°. Assume that the two CML signals are as follows:

[0092] ;

[0093] ;

[0094] For two CML signals and Perform superposition to obtain the superimposed signal :

[0095] ;

[0096] in, Indicates signal The amplitude of represents the angular frequency, Indicates time, Indicates signal The phase, Indicates signal The amplitude of Indicates signal phase.

[0097] Using trigonometric identity transformation to deduce, we can get:

[0098] ;

[0099] in, , Represents the superimposed signal The amplitude of , Represents the superimposed signal phase.

[0100] Now give the specific conditions:

[0101] First fusion situation: If CML signal and Same frequency, same amplitude, and , we can get the superposition for:

[0102] ;

[0103] ;

[0104] According to the formula, after splicing The phase is in the middle and the amplitude is amplified, such as Figure 5 shown.

[0105] Second fusion situation: If CML signal and Same frequency, 、 as well as , we can get the superposition for:

[0106] ;

[0107] ;

[0108] According to the formula, after superposition The phase is closer to the one with larger amplitude, and the amplitude is amplified, such as Figure 6 shown.

[0109] As can be seen above, inconsistent amplitudes (swings) between the two signals can cause the fused phase to deviate from the expected position, leading to clock errors. To ensure phase fusion accuracy, the amplitudes of the signals involved must be strictly consistent, making a limiter essential. The limiter limits the input odd-path and even-path four-phase orthogonal interpolation signals. The core of phase interpolation is linear interpolation, and the output of the four-phase orthogonal interpolation signal from the linear interpolation structure has different swings under different CODEs. The limiter first converts the input odd-path and even-path four-phase orthogonal interpolation signals into square wave signals with the same swing through a CML-to-CMOS circuit. Then, a filter converts the square wave signals with the same swing into CML signals with the same swing. The output eight-phase interpolation signals have consistent swing and slope, providing the subsequent phase fusion stage with input signals with consistent swing and slope. The eight-phase clock signals ultimately output by the eight-phase output phase interpolator are: CKOUT_0, CKOUT_45, CKOUT_90, CKOUT_135, CKOUT_180, CKOUT_225, CKOUT_270, and CKOUT_315.

[0110] The simulation diagram of the output signal INL of the phase interpolation core and the output signal INL of the phase blender provided in the embodiment of the present invention is as follows: Figure 7 As shown, Figure 7 The horizontal axis represents the decimal digital code (PI CODE) corresponding to the external input N-bit CODE, and the vertical axis represents integral nonlinearity. Taking the 7-bit phase interpolator in the figure as an example, the dashed curve represents the INL output of the first phase interpolation core; the dot-dashed curve represents the INL output of the second phase interpolation core; and the solid curve represents the final output INL of the phase blender. The INL output of a single phase interpolation core (the first or second phase interpolation core) exhibits significant periodic fluctuations, with significant nonlinear offsets in certain sections, indicating that the traditional linear structure has poor interpolation accuracy at certain phase points. After the phase blender fuses the interpolation results of the two phase interpolator cores, the final output INL curve is significantly smoother, the overall nonlinear error is significantly reduced, the maximum INL is lowered, and superior linearity is demonstrated. This fusion mechanism effectively suppresses the periodic error accumulation effect of a single path, achieving a more accurate and consistent eight-phase signal output.

[0111] The simulation result diagram of the eight-phase clock signal finally output by the eight-phase output phase interpolator provided by the embodiment of the present invention is as follows: Figure 8 As shown, Figure 8The horizontal axis represents the operating time of the eight-phase output phase interpolator in nanoseconds, while the vertical axis represents the output signal of the eight-phase output phase interpolator in millivolts. Under the condition of CODE = 0, the phase interpolator outputs eight sets of equally spaced clocks with phases of 45°, namely, 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°. Each output signal has a consistent period and exhibits good cycle stability. There is a fixed phase offset between adjacent clocks, with a delay corresponding to approximately 1 / 8 of the clock period, indicating that the final interpolation effect is good, achieving an eight-phase clock output.

[0112] An embodiment of the present invention provides an eight-phase output phase interpolator that adopts a dual-path phase interpolation structure. Two phase interpolation cores, one for the odd path and the other for the even path, interpolate four-phase orthogonal CML signals separately. The two output signals differ by 45°, and the phase deviation introduced in its linear interpolation structure exhibits a characteristic of opposite directions between the two paths. By fusing the two output signals through a phase blender, the nonlinear error in the single-channel structure is effectively offset, the linearity of the overall interpolation output is improved, the INL of the interpolator is significantly reduced, and the phase resolution and accuracy of the multi-phase clock system are improved; each interpolation unit selects a different quadrant output path according to the logic control code switch, internalizing the quadrant inversion function and eliminating the need for additional quadrant switching circuits, thereby reducing circuit complexity and area; each interpolation unit is always in a working state. Compared with an eight-phase phase interpolator composed of four phase interpolators, only half the interpolation units are required, saving layout area, making the circuit module more compact, and improving the interpolator's integrability in high-speed chips, making it suitable for large-scale integrated communication systems and SoC platforms; the input load of the phase interpolation core is the same under any external input CODE code, and the input signal does not change with changes in the number of interpolation units, ensuring the stability of the working state.

[0113] It should be noted that, in the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0114] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. An eight-phase output phase interpolator, characterized in that: include: A frequency divider, an input buffer, a CMOS-to-CML circuit, a digital decoder, a first phase interpolation core, a second phase interpolation core, a limiter, a phase blender, and a CML-to-CMOS circuit; wherein, The frequency divider is used to divide the frequency of the two-phase input signal and output a four-phase input signal; The input buffer is used to isolate the frequency divider and the CMOS-to-CML circuit, and to perform shaping and matching on the four-phase input signal output by the frequency divider, and output the matched four-phase input signal; The CMOS-to-CML circuit is used to convert the matched four-phase input signal into a four-phase orthogonal CML signal; The digital decoder is used to decode the external input CODE code and output the odd-path logic control code and the even-path logic control code; The first phase interpolation core is used to perform phase interpolation on the four-phase orthogonal CML signal under the control of the odd-path logic control code, and output an odd-path four-phase orthogonal interpolation signal; The second phase interpolation core is used to perform phase interpolation on the four-phase orthogonal CML signal under the control of the even-path logic control code and output an even-path four-phase orthogonal interpolation signal; the first phase interpolation core and the second phase interpolation core have the same structure and both include: a first resistor R NODD , the second resistor R PODD , the third resistor R NEVEN , the fourth resistor R PEVEN , a first interpolation array and a second interpolation array; wherein, The first resistor R NODD The first end of is connected to the power supply voltage, the second end is connected to the first output end of the first interpolation array, and the second end serves as the first output end of the corresponding phase interpolation core; The second resistor R PODD A first end of the phase interpolation core is connected to the power supply voltage, a second end of the phase interpolation core is connected to the second output end of the first interpolation array, and the second end serves as the second output end of the corresponding phase interpolation core; The third resistor R NEVEN The first end is connected to the power supply voltage, the second end is connected to the third output end of the second interpolation array, and the second end serves as the third output end of the corresponding phase interpolation core; The fourth resistor R PEVEN The first end is connected to the power supply voltage, the second end is connected to the fourth output end of the second interpolation array, and the second end serves as the fourth output end of the corresponding phase interpolation core; The differential input terminal of the first interpolation array serves as the first signal input terminal of the corresponding phase interpolation core, the control terminal serves as the first control code input terminal of the corresponding phase interpolation core, the bias terminal is connected to the bias voltage VB, the first output terminal is connected to the first output terminal of the second interpolation array, the second output terminal is connected to the second output terminal of the second interpolation array, the third output terminal is connected to the third output terminal of the second interpolation array, and the fourth output terminal is connected to the fourth output terminal of the second interpolation array; The differential input terminal of the second interpolation array serves as the second signal input terminal of the corresponding phase interpolation core, the control terminal serves as the second control code input terminal of the corresponding phase interpolation core, and the bias terminal is connected to the bias voltage VB; The limiter is used to perform limiting processing on the odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal, and output an eight-phase interpolation signal; The phase fuser is configured to perform phase fusion on the eight-phase interpolation signal and output an eight-phase fused signal; The CML-to-CMOS circuit is used to convert the eight-phase fusion signal into a CMOS-level clock signal and output the converted signal.

2. The eight-phase output phase interpolator according to claim 1, characterized in that: The difference between the odd path logic control code and the even path logic control code is 2 N-3 ; Where N represents the number of bits of the external input CODE code.

3. The eight-phase output phase interpolator according to claim 1, characterized in that: The first interpolation array and the second interpolation array have the same structure, and both include a plurality of parallel interpolation units.

4. The eight-phase output phase interpolator according to claim 3, characterized in that: The first interpolation array and the second interpolation array both include 2 N-2 Parallel interpolation units; where N represents the number of bits of the external input CODE code.

5. The eight-phase output phase interpolator according to claim 3, characterized in that: Each of the interpolation units includes: MOS transistor MN1, MOS transistor MN2, MOS transistor MN3, first single-pole four-throw switch S1 and second single-pole four-throw switch S2; wherein, The gate terminals of the MOS transistor MN1 and the MOS transistor MN2 serve as differential input terminals of the corresponding interpolation arrays; The source end of the MOS transistor MN1 is connected to the source end of the MOS transistor MN2, and the drain end is connected to the input end of the first single-pole four-throw switch S1; The drain end of the MOS transistor MN2 is connected to the input end of the second single-pole four-throw switch S2; The source terminal of the MOS transistor MN3 is grounded, the gate terminal serves as the bias terminal of the corresponding interpolation array, and the drain terminal is connected to the source terminal of the MOS transistor MN1; The control end of the first single-pole four-throw switch S1 serves as the control end of the corresponding interpolation array, and the output end thereof is respectively connected to the first output end, the second output end, the third output end and the fourth output end of the corresponding interpolation array; The control end of the second SP4T switch S2 is connected to the control end of the first SP4T switch S1 , and the output ends thereof are respectively connected to the first output end, the second output end, the third output end and the fourth output end of the corresponding interpolation array.

6. The eight-phase output phase interpolator according to claim 5, characterized in that: The first SP4T switch S1 and the second SP4T switch S2 have the same structure, and are both composed of four transistors connected in parallel.

7. The eight-phase output phase interpolator according to claim 1, characterized in that: The limiter performs limiting processing on the odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal to output an eight-phase interpolation signal, including: The limiter converts the odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal into square wave signals with the same swing amplitude; The square wave signals with the same swing amplitude are converted into CML signals with the same swing amplitude through a filter, and the CML signals with the same swing amplitude are output as eight-phase interpolation signals.

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