Trigger circuit and operation circuit
By designing trigger circuits and protection circuits in integrated circuits, adjusting the input and output pad voltages and disabling the core circuits during electrostatic discharge events or system disable energy, the problem of the integrated circuit being susceptible to electrostatic discharge damage is solved, and effective protection of the core circuits is achieved.
Patent Information
- Application Number
- CN202410116547.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-29
- Publication Date
- 2025-07-29
AI Technical Summary
Integrated circuits are susceptible to electrostatic discharge, especially under thin gate oxide layers, which makes it difficult for the prior art to effectively protect the core circuit.
A trigger circuit is designed, including adjustment circuits and protection circuits, by adjusting the input and output pad voltages and disabling the core circuits during electrostatic discharge events or system disabling energy. The protection circuit controls the node level according to the output voltage to prevent the electrostatic discharge current from entering the core circuit.
Effectively prevent electrostatic discharge current from damaging the core circuit, protect the integrated circuit from static damage, and meet the requirements of high-voltage electrostatic discharge.
Smart Images
Figure CN120389742A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a trigger circuit, and more particularly to a trigger circuit for shutting down important components when an electrostatic discharge event occurs. Background Art
[0002] Component damage caused by electrostatic discharge has become one of the most important reliability problems for integrated circuit products. Especially as the size continues to shrink, the gate oxide layer of metal oxide semiconductors becomes thinner and thinner, and integrated circuits are more vulnerable to damage due to electrostatic discharge. In general industrial standards, the input / output pins (I / O pins) of integrated circuit products must be able to pass the human body model electrostatic discharge test of more than 2000 volts and the machine model electrostatic discharge test of more than 200 volts. Summary of the Invention
[0003] An embodiment of the present invention provides a trigger circuit, coupled to an input / output pad and a core circuit, and including an adjustment circuit and a protection circuit. The adjustment circuit adjusts the voltage of the input / output pad to generate an output voltage. The protection circuit is coupled between the adjustment circuit and the core circuit and receives a system start signal. When the system start signal is disabled or an electrostatic discharge event occurs at the input / output pad, the protection circuit disables the core circuit according to the output voltage. When the system start signal is enabled, the protection circuit stops disabling the core circuit.
[0004] The present invention further provides an operating circuit, including a core circuit and a trigger circuit. The core circuit is used to set the voltage level of an input / output pad. The trigger circuit is coupled to the input / output pad and includes an adjustment circuit and a protection circuit. The adjustment circuit adjusts the voltage of the input / output pad to generate an output voltage. The protection circuit is coupled between the adjustment circuit and the core circuit and receives a system start signal. When the system start signal is disabled or an electrostatic discharge event occurs at the input / output pad, the protection circuit disables the core circuit according to the output voltage. When the system start signal is enabled, the protection circuit stops disabling the core circuit.
[0005] The present invention can solve the problems of component and integrated circuit damage caused by electrostatic discharge. Brief Description of the Drawings
[0006] Figure 1A It is a schematic diagram of the operating circuit of the present invention.
[0007] Figure 1B It is another schematic diagram of the operating circuit of the present invention.
[0008] Figure 2 It is a schematic diagram of the trigger circuit of the present invention.
[0009] Figure 3 Schematic diagram of the operation of the trigger circuit of the present invention.
[0010] Figure 4 Another schematic diagram of the operation of the trigger circuit of the present invention.
[0011] 100A, 100B: Operating circuit
[0012] 110: Core circuit
[0013] 120A, 120B: Trigger circuit
[0014] ND: Node
[0015] PD_1 to PD_3: Input / output pads
[0016] NDRV: Driving transistor
[0017] VSS, VDDL, VDDH: Operating voltages
[0018] SYS_EN: System start signal
[0019] 130: Electrostatic discharge protection circuit
[0020] 140: Specific circuit
[0021] DIN: Input signal
[0022] 111: High-end controller
[0023] 210: Adjustment circuit
[0024] 220: Protection circuit
[0025] 230: Level setting circuit
[0026] SO: Output voltage
[0027] Q1 to Q8: Transistors
[0028] NGC, GC: Signals
[0029] PB: Set voltage Specific embodiments
[0030] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. Among them, the configuration of each element in the embodiments is for the purpose of illustration and is not intended to limit the present invention. In addition, some of the reference numerals in the drawings of the embodiments are repeated. For the sake of simplicity of description, this does not mean the relevance between different embodiments.
[0031] Figure 1ASchematic diagram of the operation circuit of the present invention. As Figure 1A shown, the operation circuit 100A includes a core circuit 110 and a trigger circuit 120A. The core circuit 110 is coupled between the node ND and an input / output pad PD_1. In this embodiment, the core circuit 110 sets the voltage level of the input / output pad PD_1 according to the voltage level of the node ND. For example, when the voltage level of the node ND is equal to a first level, the core circuit 110 sets the voltage level of the input / output pad PD_1 to be equal to a second level. The first level may be greater than or less than the second level.
[0032] The present invention does not limit the architecture of the core circuit 110. In a possible embodiment, the core circuit 110 includes a driving transistor NDRV. The driving transistor NDRV sets the voltage level of the input / output pad PD_1 according to the voltage level of the node ND. For example, when the voltage level of the node ND is a high level, the driving transistor NDRV is turned on. Therefore, the voltage level of the input / output pad PD_1 is approximately equal to the operating voltage VSS, such as 0V. When the voltage level of the node ND is a low level, the driving transistor NDRV is not turned on. Therefore, the voltage level of the input / output pad PD_1 is not equal to the operating voltage VSS.
[0033] In this embodiment, the driving transistor NDRV is an N-type transistor, but it is not intended to limit the present invention. In other embodiments, the driving transistor NDRV is a P-type transistor. As Figure 1A shown, the gate of the driving transistor NDRV is coupled to the node ND. The drain of the driving transistor NDRV is coupled to the input / output pad PD_1. The source of the driving transistor NDRV receives an operating voltage VSS (or a first operating voltage).
[0034] In some embodiments, the driving transistor NDRV is a low gate high drain transistor. In this example, the voltage that the drain of the driving transistor NDRV can withstand is greater than the voltage that the gate can withstand. For example, the maximum voltage that the gate of the driving transistor NDRV can withstand is 6V, and the maximum voltage that the drain can withstand may be greater than 20V.
[0035] The trigger circuit 120A is coupled to the input / output pad PD_1 and the core circuit 110, and receives a system start signal SYS_EN. When the system start signal SYS_EN is disabled, the trigger circuit 120A disables the core circuit 110, causing the core circuit 110 to stop setting the voltage level of the input / output pad PD_1. When the system start signal SYS_EN is enabled, the trigger circuit 120A stops disabling the core circuit 110. Accordingly, the core circuit 110 sets the voltage level of the input / output pad PD_1 according to the voltage level of the node ND. In a possible embodiment, when an electrostatic discharge event occurs at the input / output pad PD_1, the trigger circuit 120A disables the core circuit 110 to prevent an electrostatic discharge current from entering and damaging the core circuit 110 through the input / output pad PD_1.
[0036] In other embodiments, the operation circuit 100A further includes an electrostatic discharge protection circuit 130. The electrostatic discharge protection circuit 130 is coupled to the input / output pad PD_1. When an electrostatic discharge event occurs at the input / output pad PD_1, the electrostatic discharge protection circuit 130 releases an electrostatic discharge current to prevent the electrostatic discharge current from entering the core circuit 110. In a possible embodiment, the electrostatic discharge protection circuit 130 is further coupled to an input / output pad PD_2. In this case, when an electrostatic discharge event occurs at the input / output pad PD_1 and the input / output pad PD_2 is coupled to ground, the electrostatic discharge protection circuit 130 provides a discharge path. An electrostatic discharge current flows from the input / output pad PD_1, through the electrostatic discharge protection circuit 130, and is released to the input / output pad PD_2.
[0037] In some embodiments, the operation circuit 100A further includes a specific circuit 140. The specific circuit 140 receives the system start signal SYS_EN and an input signal DIN. When the system start signal SYS_EN is enabled, the specific circuit 140 sets the voltage level of the node ND according to the input signal DIN. For example, when the input signal DIN is at a third level, the voltage level of the node ND may be equal to a fourth level. When the input signal DIN is at a fifth level, the voltage level of the node ND may be equal to a sixth level. The third level is relative to the fifth level. The fourth level is relative to the sixth level. Additionally, the third level may be greater than or lower than the fourth level. The fifth level may be greater than or lower than the sixth level. However, when the system start signal SYS_EN is disabled, the specific circuit 140 stops setting the voltage level of the node ND. At this time, the voltage level of the node ND may be 0V.
[0038] Figure 1B Schematic diagram of the operation circuit of the present invention. Figure 1B Similar Figure 1A , except that Figure 1BThe operation circuit 100B further includes a trigger circuit 120B. The trigger circuit 120B is coupled to the input / output pad PD_3 and the core circuit 110, and receives the system start signal SYS_EN.
[0039] When the system start signal SYS_EN is disabled, the trigger circuit 120B disables the core circuit 110, so that the core circuit 110 stops setting the voltage level of the input / output pad PD_1. When the system start signal SYS_EN is enabled, the trigger circuit 120B stops disabling the core circuit 110. Therefore, the core circuit 110 sets the voltage level of the input / output pad PD_1 according to the voltage level of the node ND. In a possible embodiment, when an electrostatic discharge event occurs at the input / output pad PD_3, the trigger circuit 120B disables the core circuit 110 to prevent an electrostatic discharge current from entering and damaging the core circuit 110 through the input / output pad PD_3.
[0040] The present invention does not limit the uses of the input / output pads PD_1 and PD_3. In a possible embodiment, the input / output pad PD_1 or PD_3 serves as an output terminal for outputting a signal. In another possible embodiment, the input / output pad PD_1 or PD_3 serves as an input terminal for receiving an operating voltage. The use of the input / output pad PD_1 may be the same as or different from that of the input / output pad PD_3. For example, the input / output pad PD_1 is an output terminal for outputting a signal, while the input / output pad PD_3 serves as an input terminal for receiving a signal or a power supply.
[0041] The present invention does not limit the number of trigger circuits. In other embodiments, the operation circuit 100B has more trigger circuits. Different trigger circuits are coupled to different input / output pads to prevent electrostatic current from entering the core circuit 110 through different input / output pads. In this example, each trigger circuit receives the system start signal SYS_EN and is coupled to the node ND.
[0042] In some embodiments, the core circuit 110 includes a high side controller 111 and a driving transistor NDRV. The high side controller 111 is coupled between the input / output pad PD_3 and the driving transistor NDRV. In a possible embodiment, the high side controller 111 sets the voltage level of the input / output pad PD_1 to be equal to the voltage level of the input / output pad PD_3. In some embodiments, the input / output pad PD_3 receives an operating voltage VDDH. The operating voltage VDDH is greater than the operating voltage VSS.
[0043] The present invention does not limit the circuit architecture of the high-end controller 111. Any circuit that can set the input / output pad PD_1 to a high level can be used as the high-end controller 111. In this embodiment, the driving transistor NDRV serves as a low-end controller to set the input / output pad PD_1 to a low level.
[0044] Figure 2 FIG. is a schematic diagram of the trigger circuit of the present invention. Since the trigger circuits 120A and 120B have the same architecture, Figure 2 only the architecture of the trigger circuit 120A is shown. As Figure 2 shown, the trigger circuit 120A includes an adjustment circuit 210 and a protection circuit 220. The adjustment circuit 210 is coupled to the input / output pad PD_1 and adjusts the voltage of the input / output pad PD_1 to generate an output voltage SO. The protection circuit 220 is coupled between the adjustment circuit 210 and the core circuit 110 and receives the system start signal SYS_EN.
[0045] In other embodiments, Figure 1B the trigger circuit 120B of has another adjustment circuit (or second adjustment circuit) and another protection circuit (or second protection circuit). In this example, the second adjustment circuit is coupled to the input / output pad PD_3 and adjusts the voltage of the input / output pad PD_3 to generate another output voltage (or second output voltage). The second protection circuit is coupled between the second adjustment circuit and the core circuit 110 and receives the system start signal SYS_EN.
[0046] Since the operation of the trigger circuit 120B is the same as that of the trigger circuit 120A, the operation of the trigger circuit 120A will be described by taking the trigger circuit 120A as an example. When the system start signal SYS_EN is disabled or an electrostatic discharge event occurs at the input / output pad PD_1, the protection circuit 220 sets the voltage level of the node ND according to the output voltage SO to disable the core circuit 110. When the system start signal SYS_EN is enabled, the protection circuit 220 stops setting the voltage level of the node ND to suspend the disabling of the core circuit 110.
[0047] In a possible embodiment, the adjustment circuit 210 includes transistors Q1 to Q3. The gate and drain of transistor Q1 are coupled together, and its source receives the operating voltage VSS. The gate of transistor Q2 is coupled to the gate of transistor Q1. The drain of transistor Q2 is coupled to the input / output pad PD_1. In a possible embodiment, transistor Q2 is a low-gate-high-drain transistor. In this example, the drain of transistor Q2 can withstand a relatively large voltage (such as above 10V). Therefore, when an electrostatic discharge event occurs at the input / output pad PD_1, transistor Q2 will not be damaged by the electrostatic discharge current. The gate of transistor Q3 is coupled to the source of transistor Q2. The drain of transistor Q3 is coupled to the drain of transistor Q1. The source of transistor Q3 receives an operating voltage VDDL (or called the second operating voltage). In some embodiments, transistors Q1 and Q2 are N-type transistors, and transistor Q3 is a P-type transistor.
[0048] In other embodiments, the drain of transistor Q2 may be coupled to the input / output pad PD_3. In this example, in the normal mode (i.e., when the system start signal SYS_EN is enabled), the voltage level of the input / output pad PD_3 is greater than the operating voltage VDDL, and the operating voltage VDDL is greater than the operating voltage VSS. For example, the voltage level of the input / output pad PD_3 may be 12V, the operating voltage VDDL may be 6V, and the operating voltage VSS is about 0V.
[0049] The protection circuit 220 includes transistors Q4 to Q6. The gate of transistor Q4 receives the operating voltage VSS. The source of transistor Q4 is coupled to the source of transistor Q2. The gate of transistor Q5 receives the system start signal SYS_EN. The drain of transistor Q5 is coupled to the drain of transistor Q4. The source of transistor Q5 receives the operating voltage VSS. The gate of transistor Q6 is coupled to the drain of transistor Q5. The drain of transistor Q6 is coupled to the core circuit 110. The source of transistor Q6 receives the operating voltage VSS. In some embodiments, transistor Q4 is a P-type transistor, and transistors Q5 and Q6 are N-type transistors.
[0050] In other embodiments, the trigger circuit 120A further includes a level setting circuit 230. The level setting circuit 230 provides a setting voltage PB to the bases of transistors Q3 and Q4. In this example, since the setting voltage PB is equal to the source voltage of transistor Q3, the parasitic diode (not shown) between the source and base of transistor Q3 will not be turned on, avoiding the generation of leakage current. In addition, the setting voltage PB is greater than the drain voltage of transistor Q3. Therefore, the parasitic diode between the drain and base of transistor Q3 will not be turned on either. Furthermore, since the setting voltage PB is greater than the source and drain voltages of transistor Q4, the parasitic diodes between the source and base and between the drain and base of transistor Q4 will not be turned on.
[0051] The present invention does not limit the architecture of the level setting circuit 230. In a possible embodiment, the level setting circuit 230 includes transistors Q7 and Q8. The gate of transistor Q7 is coupled to the drain of transistor Q1. The drain of transistor Q7 is coupled to the bases of transistors Q3 and Q4. The source of transistor Q7 receives the operating voltage VDDL. The gate of transistor Q8 receives the operating voltage VDDL. The drain of transistor Q8 is coupled to the bases of transistors Q3 and Q4. The source of transistor Q8 is coupled to the gate of transistor Q7. In some embodiments, both transistors Q7 and Q8 are P-type transistors.
[0052] Figure 3 FIG. is a schematic diagram of the operation of the trigger circuit 120A of the present invention. When the operation circuit 100A is powered on, the input / output pad PD_3 receives an operating voltage VDDH, such as 12V. At this time, the operating voltage VDDL is about 6V. During ON_1 and ON_2, the system start signal SYS_EN is enabled. Therefore, the trigger circuit 120A operates in a normal on mode. In this embodiment, when the system start signal SYS_EN is enabled, the voltage level of the system start signal SYS_EN is a high level, such as 6V.
[0053] Please refer to Figure 2 , in the normal on mode, since the system start signal SYS_EN is enabled, transistor Q5 is turned on. Therefore, the voltage level of signal GC approaches the operating voltage VSS, such as 0V. Since transistor Q6 is not turned on, the protection circuit 220 pauses the voltage level of the control node ND. At this time, the voltage level of node ND is controlled by a specific circuit (such as 140).
[0054] In the normal on mode, since transistor Q1 acts as a pull high element and has a diode connect architecture, the level of signal NGC is approximately the operating voltage VSS plus the threshold voltage of transistor Q1. In a possible embodiment, the level of signal NGC is approximately 0.7V to 1V. Therefore, transistor Q2 is slightly turned on, and the output voltage SO is about 0.3V (the gate voltage 1V of transistor Q2 minus the threshold voltage 0.7V of transistor Q2). Transistor Q3 is turned on, causing transistor Q2 to continue to conduct. At this time, the output voltage SO may rise to 2V. However, since transistor Q5 is turned on and signal GC is about 0V, transistor Q4 is not easily turned on. Therefore, the voltage level of signal GC remains 0V.
[0055] During OFF_1 and OFF_2, the system startup signal SYS_EN is disabled. In a possible embodiment, when the system startup signal SYS_EN is disabled, the level of the system startup signal SYS_EN may be a low level, such as 0V. Additionally, during OFF_1 and OFF_2, the trigger circuit 120A operates in a normal off mode. In the normal off mode, the system startup signal SYS_EN is disabled, so the transistor Q5 is not conducting.
[0056] Since the level of the signal NGC is approximately 0.7V to 1V. At this time, the transistor Q2 conducts slightly. Therefore, the output voltage SO is approximately 0.3V, turning on the transistor Q3, causing the transistor Q2 to continue to conduct. In this example, the transistors Q2 and Q3 form a negative feedback circuit. The output voltage SO may rise to 2V. Since the transistor Q5 is not conducting, the transistor Q4 conducts. The voltage level of the signal GC rises. In a possible embodiment, the voltage level of the signal GC is approximately equal to 4.45V. Since the voltage level of the signal GC is greater than the threshold voltage of the transistor Q6, the transistor Q6 conducts, causing the level of the node ND to be approximately equal to the operating voltage VSS.
[0057] In a possible embodiment, the maximum value of the output voltage SO is approximately equal to the operating voltage VDDL minus the threshold voltage of the transistor Q2. In other embodiments, the voltage level of the signal GC is related to the size of the transistor (such as the channel size). Therefore, by using different transistor sizes (such as channel sizes), the signal GC can have different voltage levels.
[0058] Figure 4 This is another operation schematic diagram of the trigger circuit 120A of the present invention. When the operation circuit 100A is not powered on, the operating voltage VDDL is a floating level. The voltage level VDDH of the input / output pad PD_3 is also a floating level. In a possible embodiment, a circuit (not shown) generates the system startup signal SYS_EN based on the operating voltage VDDL. In this example, since the operating voltage VDDL is a floating level, this circuit cannot generate the system startup signal SYS_EN. Therefore, the level of the system startup signal SYS_EN may be approximately 0V or a lower floating level. At this time, the transistor Q5 is not conducting.
[0059] At time point 400, an electrostatic discharge event occurs at the input / output pad PD_1. Therefore, the trigger circuit 120A enters a protection mode. Please refer to Figure 2, in the protection mode, the level of signal NGC is approximately 0.7V to 1V. Therefore, transistor Q2 conducts slightly. At this time, the output voltage SO is approximately 0.3V, so transistor Q3 conducts, causing transistor Q2 to continue conducting. The output voltage SO may rise to 2V. Since transistor Q5 is not conducting, transistor Q4 conducts. Therefore, the voltage level of signal GC rises. At this time, the voltage level of signal GC may be approximately 2.48V. Since the voltage level of signal GC is greater than the threshold voltage of transistor Q6, transistor Q6 conducts, making the level of node ND approximately equal to the operating voltage VSS.
[0060] Please refer to Figure 1A , when the level of node ND is approximately equal to the operating voltage VSS, the core circuit 110 is turned off. Therefore, the electrostatic discharge current does not enter the core circuit 110 from the input / output pad PD_1. In some embodiments, when an electrostatic discharge event occurs at the input / output pad PD_1 or PD_3, the gate voltage of the driving transistor NDRV in the core circuit 110 is approximately equal to the operating voltage VSS. Therefore, the driving transistor NDRV does not conduct. Since the electrostatic discharge current does not enter the driving transistor NDRV, the driving transistor NDRV can be protected. Additionally, when the electrostatic discharge current is released, the voltage level of signal GC gradually decreases, such as from 2.48V to 1V.
[0061] In the normal on mode and normal off mode, the operating voltage VDDL is approximately equal to 6V, and the signal NGC is approximately equal to 0.7 to 1V. Therefore, transistor Q7 of the core circuit 220 conducts, making the set voltage PB approximately equal to the operating voltage VDDL. Since the base voltages of transistors Q3 and Q4 are approximately equal to the operating voltage VDDL, the parasitic diodes of transistors Q3 and Q4 do not conduct, avoiding leakage current.
[0062] In other embodiments, when an electrostatic discharge event occurs at the input / output pad PD_3, a protection circuit (not shown) in the trigger circuit 120B sets the voltage level of node ND to a low level, such as 0V. Therefore, the driving transistor NDRV in the core circuit 110 does not conduct, preventing the electrostatic discharge current from flowing through the driving transistor NDRV.
[0063] It should be understood that when an element is referred to as being "coupled" to another element, it can be directly coupled or connected to the other element, or there can be other elements in between. Conversely, when an element is "connected" to another element, there are no other elements in between. Additionally, "enable" shall mean changing the state of a Boolean signal. The Boolean signal can be enabled to be high or have a higher voltage, and the Boolean signal can be enabled to be low or have a lower voltage at the discretion of the circuit designer. Similarly, "disable" shall mean changing the state of the Boolean signal to a voltage level opposite to the enabled state.
[0064] Unless otherwise defined, all terms herein (including technical and scientific terms) shall have the ordinary meaning as understood by those of ordinary skill in the technical field to which this invention pertains. In addition, unless explicitly stated, the definitions of terms in the general dictionary shall be interpreted as being consistent with their meanings in the articles of the relevant technical field, and shall not be interpreted in an ideal or overly formal sense. Although terms such as "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. In the claims, terms such as "first", "second", etc. are used as labels and are not intended to impose numerical requirements on their objects.
[0065] Although the present invention has been disclosed above in preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention can be implemented by physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.
Claims
1. A trigger circuit, characterized in that, Couple an input / output pad and a core circuit, and include: An adjustment circuit that adjusts the voltage of the input / output pad to generate an output voltage; and A protection circuit coupled between the adjustment circuit and the core circuit and receiving a system startup signal, wherein: When the system startup signal is disabled or an electrostatic discharge event occurs at the input / output pad, the protection circuit disables the core circuit according to the output voltage; When the system startup signal is enabled, the protection circuit stops disabling the core circuit.
2. The trigger circuit according to claim 1, wherein The adjustment circuit includes: A first transistor having a first gate, a first drain, and a first source, the first gate being coupled to the first drain, and the first source receiving a first operating voltage; A second transistor having a second gate, a second drain, and a second source, the second gate being coupled to the first gate, and the second drain being coupled to the input / output pad; A third transistor having a third gate, a third drain, and a third source, the third gate being coupled to the second source, and the third drain being coupled to the first drain.
3. The trigger circuit according to claim 2, wherein Both the first transistor and the second transistor are N-type transistors, and the third transistor is a P-type transistor.
4. The trigger circuit according to claim 2, characterized in that The protection circuit includes: A fourth transistor having a fourth gate, a fourth drain, and a fourth source, the fourth gate receiving the first operating voltage, and the fourth source being coupled to the second source; A fifth transistor having a fifth gate, a fifth drain, and a fifth source, the fifth gate receiving the system startup signal, the fifth drain being coupled to the fourth drain, and the fifth source receiving the first operating voltage; and A sixth transistor having a sixth gate, a sixth drain, and a sixth source, the sixth gate being coupled to the fifth drain, the sixth drain being coupled to the core circuit, and the sixth source receiving the first operating voltage.
5. The trigger circuit according to claim 4, wherein The fourth transistor is a P-type transistor, and both the fifth and sixth transistors are N-type transistors.
6. The trigger circuit according to claim 4, characterized in that, Further include: A level setting circuit that provides a setting voltage to the bases of the third and fourth transistors, wherein: The third source receives a second operating voltage; The setting voltage is greater than the voltages of the third and fourth drains.
7. The trigger circuit according to claim 6, wherein The level setting circuit includes: A seventh transistor having a seventh gate, a seventh drain, and a seventh source, the seventh gate being coupled to the first drain, the seventh drain being coupled to the bases of the third and fourth transistors, and the seventh source receiving the second operating voltage; and An eighth transistor having an eighth gate, an eighth drain, and an eighth source, the eighth gate receiving the second operating voltage, the eighth drain being coupled to the bases of the third and fourth transistors, and the eighth source being coupled to the seventh gate.
8. The trigger circuit according to claim 7, wherein Both the seventh transistor and the eighth transistor are P-type transistors.
9. The trigger circuit according to claim 7, wherein The first operating voltage is less than the second operating voltage.
10. The trigger circuit according to claim 7, characterized in that, When the system startup signal is disabled or the electrostatic discharge event occurs at the input / output pad, the sixth transistor provides the first operating voltage to the core circuit; When the system startup signal is enabled, the fifth transistor provides the first operating voltage to the sixth transistor to turn off the sixth transistor.
11. An operating circuit, characterized in that, Include: A core circuit for setting a voltage level of a first input / output pad; and A first trigger circuit coupled to the first input / output pad and including: A first adjustment circuit for adjusting the voltage of the first input / output pad to generate a first output voltage; and A first protection circuit coupled between the first adjustment circuit and the core circuit and receiving a system startup signal, wherein: When the system startup signal is disabled or an electrostatic discharge event occurs at the first input / output pad, the first protection circuit disables the core circuit according to the first output voltage; When the system startup signal is enabled, the first protection circuit stops disabling the core circuit.
12. The operating circuit according to claim 11, characterized in that, The core circuit includes a driving transistor, the gate of the driving transistor is coupled to a node, the drain of the driving transistor is coupled to the first input / output pad, and the source of the driving transistor receives a first operating voltage, When the voltage of the node is equal to a second operating voltage, the driving transistor transmits the first operating voltage to the first input / output pad, When the voltage of the node is equal to the first operating voltage, the driving transistor stops transmitting the first operating voltage to the first input / output pad.
13. The operating circuit according to claim 12, wherein Further included: A specific circuit receiving the system startup signal and an input signal, wherein: When the system startup signal is enabled, the specific circuit sets the voltage level of the node according to the input signal, When the system startup signal is disabled, the specific circuit stops setting the voltage level of the node.
14. The operating circuit according to claim 13, characterized in that, Further included: An electrostatic discharge protection circuit coupled to the first input / output pad, wherein when the electrostatic discharge event occurs at the first input / output pad, it releases an electrostatic discharge current to prevent the electrostatic discharge current from entering the core circuit.
15. The operating circuit according to claim 11, wherein The adjustment circuit includes: A first transistor having a first gate, a first drain, and a first source, the first gate is coupled to the first drain, and the first source receives the first operating voltage; A second transistor having a second gate, a second drain, and a second source, the second gate is coupled to the first gate, and the second drain is coupled to the first input / output pad; A third transistor having a third gate, a third drain, and a third source, the third gate is coupled to the second source, and the third drain is coupled to the first drain.
16. The operation circuit according to claim 15, characterized in that, The protection circuit includes: A fourth transistor having a fourth gate, a fourth drain, and a fourth source, the fourth gate receives the first operating voltage, and the fourth source is coupled to the second source; A fifth transistor having a fifth gate, a fifth drain, and a fifth source, the fifth gate receives the system startup signal, the fifth drain is coupled to the fourth drain, and the fifth source receives the first operating voltage; and A sixth transistor having a sixth gate, a sixth drain, and a sixth source, the sixth gate is coupled to the fifth drain, the sixth drain is coupled to the first level setting circuit, and the sixth source receives the first operating voltage.
17. The operating circuit according to claim 16, characterized in that, Further included: A seventh transistor, having a seventh gate, a seventh drain, and a seventh source, the seventh gate being coupled to the first drain, the seventh drain being coupled to the bases of the third and fourth transistors, and the seventh source receiving the second operating voltage; and An eighth transistor, having an eighth gate, an eighth drain, and an eighth source, the eighth gate receiving the second operating voltage, the eighth drain being coupled to the bases of the third and fourth transistors, and the eighth source being coupled to the seventh gate.
18. The operating circuit according to claim 17, wherein The first transistor, the second transistor, the fifth transistor, and the sixth transistor are all N-type transistors, and the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are all P-type transistors.
19. The operating circuit according to claim 17, characterized in that, Further comprising: A second trigger circuit, coupled to a second input / output pad, and comprising: A second adjustment circuit, adjusting the voltage of the second input / output pad to generate a second output voltage; and A second protection circuit, coupled between the second adjustment circuit and the core circuit, and receiving the system start signal, wherein: When the system start signal is disabled or an electrostatic discharge event occurs at the second input / output pad, the second protection circuit disables the core circuit according to the second output voltage; When the system start signal is enabled, the second protection circuit stops disabling the core circuit.
20. The operating circuit according to claim 19, wherein When the system start signal is enabled, the second input / output pad receives a third operating voltage, the third operating voltage being greater than the first and second operating voltages, and the second operating voltage being greater than the first operating voltage.