High-precision multi-channel synchronous acquisition method for magnetic inertia-constraint device

Abstract

The invention discloses a high-precision multichannel synchronous acquisition method for a magnetic inertia-constraint device, and the method comprises the steps: firstly, employing a high-performance FPGA chip and a high-precision ADC chip, combining an analog signal front-end conditioning module, designing a data acquisition board card through employing a dual-cascade phase-locked loop clock, and employing a fixed error compensation mechanism, thereby achieving the high-precision synchronous acquisition of a magnetic inertia-constraint device; and correction design is carried out on the phase inconsistency of the analog channel, so that the in-board channel acquisition synchronization precision is ensured. Aiming at the problem of inter-board channel acquisition synchronization, a control mainboard is designed, inter-board channel acquisition synchronization correction is carried out based on a clock cache cascade architecture, and accurate synchronous acquisition and high-speed transmission of signals are realized in combination with a network port and a switch. Compared with a traditional method, the method provided by the invention not only meets various performance index requirements of signal acquisition in the magnetic inertia-constraint device, but also reduces the deployment cost of an acquisition system.

Description

[0001] The invention relates to the field of data acquisition, and specifically to a high-precision multi-channel synchronous acquisition method for a magneto-inertial confinement device. Background Art

[0002] In the modern energy field, nuclear fusion is considered one of the most promising clean energy sources in the future. The research and development of nuclear fusion energy systems need to overcome many technical challenges, one of which is the monitoring and acquisition of various related signals in magneto-inertial confinement devices. A magneto-inertial confinement device is a new nuclear fusion implementation scheme that combines magnetic confinement and inertial confinement technologies. Its core function is to achieve efficient compression and stable confinement of plasma through the synergistic action of magnetic fields and inertial forces, thereby triggering a controllable nuclear fusion reaction. Signal acquisition is the core link for realizing plasma control, device safe operation, performance optimization, and scientific research, and poses extremely high requirements for the high-precision signal acquisition ability of the device.

[0003] The signal acquisition methods of traditional magneto-inertial confinement devices have significant limitations in terms of the number of channels, acquisition accuracy, and data transmission capabilities. Specifically, such methods mainly rely on a multi-machine architecture constructed by oscilloscopes to achieve signal acquisition. However, in the complex environment of magneto-inertial confinement devices, the system's demand for the number of acquisition channels can reach the order of hundreds. At this time, problems such as limited acquisition channel numbers and insufficient timing synchronization accuracy in the multi-machine architecture are significantly amplified, making it difficult to meet the strict requirements of the device for high-density, high-precision, and low-latency signal acquisition.

[0004] In order to meet the requirements of various performance indicators for signal acquisition in magneto-inertial confinement devices while reducing the deployment cost of the acquisition system, the present invention proposes a high-precision multi-channel synchronous acquisition method for magneto-inertial confinement devices. The method of the present invention is implemented based on the architecture of "several four-channel acquisition cards (signal conditioning channels + ADC + FPGA) + control motherboard + switch + PC". Summary of the Invention

[0006] In view of this, the present invention proposes a signal acquisition method that takes into account the number of acquisition channels, acquisition synchronization accuracy, and development and deployment costs. The present invention first designs a data acquisition board by integrating high-performance FPGA and ADC chips, and adopting a dual-stage phase-locked loop (PLL) clock synchronization circuit combined with an analog front-end conditioning module. At the same time, based on a fixed phase error compensation algorithm, digital correction is performed on the inter-channel delay deviation to ensure the in-board channel synchronization accuracy. For the multi-board cascaded application scenario, a control motherboard is designed, and inter-board channel acquisition synchronization correction is performed based on a clock buffer cascaded architecture to achieve inter-board channel acquisition synchronization. At the same time, the precise time protocol and a 10 Gigabit Ethernet switch are used to form a network to build a high-transmission-rate distributed synchronous acquisition network, realizing precise synchronous acquisition and high-speed transmission of signals.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] A high-precision multi-channel synchronous acquisition method for a magnetic inertia-confinement device, specifically including the following steps:

[0009] Step 1: Design an analog signal conditioning module using high-precision resistors, capacitors, BUF802, OPA140, LMH5401, and LMH6401 to achieve the adjustment of signal amplitude gain and bias level.

[0010] Step 2: Combine the temperature-compensated crystal oscillator DSA321SCL and the LMK04821 clock chip, and design a clock module using a double-cascaded phase-locked loop structure to achieve sampling clock synchronization.

[0011] Step 3: Use AD9680, KINTEX-7 series FPGA chips, DDR3 cache, PHY chips, and RJ45 interfaces to design the acquisition, processing, and transmission modules of the data acquisition card.

[0012] Step 4: Obtain the sampling data of each channel, perform operations using the sine fitting method to obtain the error between the sampling data of the in-board channels, and perform corresponding delay compensation on each channel according to the error parameters.

[0013] Step 5: Use NB3L553DG, CDCLVC1106PWR clock buffer chips, and LH32M0S3 single-chip microcomputer, and design a control main board based on the clock buffer cascade architecture to achieve high-precision synchronization of different acquisition boards.

[0014] Step 6: Use an S5735S Ethernet switch to communicate with the PC side, and develop a host computer software based on the Qt framework for data waveform display, file storage, and board control.

[0015] Compared with the traditional method, the advantages of the method of the present invention are as follows:

[0016] First, design an analog signal front-end conditioning module using high-precision resistors, capacitors, and related operational amplifier chips to achieve the adjustment of signal amplitude gain and bias level, ensuring the quantization accuracy of the ADC. Use a double-cascaded phase-locked loop clock synchronization circuit to achieve sampling clock synchronization, and perform digital correction on the inter-channel delay deviation based on the fixed phase error compensation algorithm. At the same time, combine FPGA and DDR3 to design a data acquisition card, which can achieve high-synchronization data acquisition of in-board channels. Design a control main board through the clock buffer cascade architecture to provide synchronous pulses and a homologous reference clock to achieve high-precision multi-acquisition board synchronization, thereby achieving inter-board channel synchronization. The host computer software developed based on the Qt framework has a good visualization interface and data management function. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings, where:

[0018] Figure 1 It is a framework diagram of a high-precision multi-channel synchronous acquisition method for a magnetic inertia-constraint device of the present invention;

[0020] Figure 2 It is an architecture diagram of the data acquisition system used in the present invention; Specific embodiments

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in combination with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0022] The present invention discloses a high-precision multi-channel synchronous acquisition method that takes into account the number of acquisition channels, acquisition synchronization accuracy, and development and deployment costs. Refer to Figure 1 , Figure 2 As shown, the present invention first designs a data acquisition board by integrating a high-performance FPGA and an ADC chip, and adopting a dual-stage phase-locked loop (PLL) clock synchronization circuit combined with an analog front-end conditioning module. At the same time, based on a fixed phase error compensation algorithm, digital correction is performed on the inter-channel delay deviation to ensure the in-board channel synchronization accuracy. For the multi-board cascaded application scenario, a control main board is designed, and inter-board channel acquisition synchronization correction is performed based on a clock buffer cascaded architecture to achieve inter-board channel acquisition synchronization. At the same time, an accurate time protocol and a 10 Gigabit Ethernet switch are used to form a network to build a high-transmission-rate distributed synchronous acquisition network, realizing precise signal synchronous acquisition and high-speed transmission.

[0023] The specific implementation steps of the present invention are as follows:

[0024] Step 1: Design an analog signal conditioning module using high-precision resistors, capacitors, BUF802, OPA140, LMH5401, and LMH6401 to achieve the adjustment of signal amplitude gain and bias level.

[0025] Among them, the design of the analog signal conditioning module specifically includes: a passive attenuation network, an impedance transformation circuit, a DC bias adjustment circuit, and a controllable gain amplifier circuit (including a single-ended to differential conversion unit and a programmable gain amplifier).

[0026] Considering the relationship between amplifier gain and noise, the signal passive attenuation circuit adopts a voltage division network with a 5-fold attenuation, and uses a fixed capacitor and a tunable capacitor to change the value of the tunable capacitor to achieve the effect of complete compensation for parasitic capacitance.

[0027] Select the amplifier chip BUF802 and make it work in the composite loop mode (CL Mode) to cooperate with the precision operational amplifier (OPA140) to construct a dual-path signal processing system, improving the DC precision and frequency response flatness of the system.

[0028] Select the digital-to-analog converter chip DAC8560 and control the output of the DAC to adjust the bias voltage.

[0029] Select the amplifier chips LMH5401 and LMH6401 to achieve single-ended to differential conversion and controllable amplitude gain of the signal.

[0030] Step 2: Combine the temperature-compensated crystal oscillator DSA321SCL and the LMK04821 clock chip, and design the clock module using a double-cascaded phase-locked loop structure to achieve sampling clock synchronization.

[0031] Among them, the design of the sampling clock synchronization module specifically includes:

[0032] Select the DSA321SCL temperature-compensated crystal oscillator (TCXO) as the system's main clock reference source, and use the LMK04821 clock generator chip, configured in the double-cascaded phase-locked loop mode.

[0033] Using the 10MHz signal output by DSA321SCL as a reference, generate a 100MHz intermediate clock through integer division and PLL1, receive the output signal of PLL1, and combine with the on-chip low-noise VCO to generate multiple channels of synchronous sampling clocks.

[0034] Step 3: Use the AD9680, KINTEX-7 series FPGA chip, DDR3 cache, PHY chip, and RJ45 interface to design the acquisition, processing, and transmission modules of the data acquisition card.

[0035] Among them, the design of the acquisition, processing, and transmission modules of the data acquisition card specifically includes:

[0036] Adopt the AD9680 14-bit dual-channel ADC to digitize the signal and interconnect with the FPGA through the JESD204B Subclass 1 protocol.

[0037] Use the XC7K325T model FPGA chip, deploy 8 groups of JESD204B IP cores, and each channel occupies 4 GTX transceivers to achieve 16-channel parallel reception of ADC data.

[0038] External MT41J256M16HA DDR3 chip, configured with a 64-bit bus, uses the internal Ping-Pong cache structure of the chip to alternately write to DDR3 Bank0 / Bank1 to achieve zero-waiting time switching.

[0039] Combined with the KSZ9031RNXIC gigabit PHY chip and RJ45 interface to build a network link to achieve communication with the PC side.

[0040] Step 4: Obtain the sampling data of each channel, perform operations using the sine fitting method to obtain the error between the sampling data of the channels within the board, and perform corresponding delay compensation on each channel according to the error parameters.

[0041] Among them, the delay correction design based on the fixed phase error compensation algorithm specifically includes:

[0042] First, after obtaining the sampling data of each channel, it is necessary to estimate the phase error between channels. The ideal sampling signal is:

[0043] s(t) = Asin(2πft + φ0) + ε(t) (1)

[0044] Where A is the amplitude, f is the signal frequency, φ0 is the initial phase, and ε(t) is the noise term.

[0045] For the discrete sampling sequence s i [n] of the i-th channel, use the least squares sine fitting to estimate its phase φ i :

[0046]

[0047] By solving the eigenvalues of the Hessian matrix, obtain the phase estimation values {φ1, φ2,..., φ M} of each channel, and calculate the phase difference relative to the main channel:

[0048] Δφ i = φ i - φ ref (i = 1, 2,..., M) (3)

[0049] Convert the phase difference to a time difference:

[0050]

[0051] According to the system clock resolution δt, calculate the number of digital delay units:

[0052]

[0053] Where N delay,i is the number of dynamic insertion delay units in the FPGA.

[0054] Step Five: Design a control motherboard using the active crystal oscillator SIT8008BI, NB3L553DG, CDCLVC1106PWR clock buffer chip, and LH32M0S3 single-chip microcomputer, and based on the clock buffer cascade architecture to achieve high-precision synchronization of different acquisition boards.

[0055] Use the SIT8008BI active crystal oscillator as the global reference source for the control motherboard to provide a pure clock reference for the cascade architecture, and generate internal pulse signals through the LH32M0S3 single-chip microcomputer.

[0056] Use the CDCLVC1106PWR to receive the 10MHz signal, pulse signal, and external trigger signal of the SIT8008BI respectively to form the first-level clock buffer module, and compensate for the PCB trace difference through the internal adjustable delay line to ensure the synchronization of multiple fan-out signals.

[0057] Use the NB3L553DG to receive the multiple fan-out signals of the CDCLVC1106 first-level clock buffer module respectively to form the second-level clock buffer module, break through the driving limit of the traditional single-level buffer, and support multi-board cascading.

[0058] Step Six: Use the S5735S Ethernet switch to communicate with the PC side, and develop upper computer software based on the Qt framework for data waveform display, file storage, and board control.

[0059] Use the S5735S-24P4X-A gigabit Ethernet switch to deploy QoS policies to ensure data priority transmission, enable the LLDP protocol to achieve automatic topology discovery, and configure static MAC address binding to prevent ARP attacks. At the same time, the data stream uses the IEEE1588PTP protocol to achieve nanosecond-level time synchronization.

[0060] Based on the QT framework, use layout managers QVBoxLayout, QHBoxLayout, and QGridLayout to organize controls, ensure the adaptive function of the interface at different resolutions, and integrate data visualization, high-speed storage, and precise control.

Claims

1. A high-precision multi-channel synchronous acquisition method for a magnetic inertial confinement device, characterized in that: First, a data acquisition board is designed by integrating a high-performance FPGA and an ADC chip, and adopting a dual-stage phase-locked loop (PLL) clock synchronization circuit combined with an analog front-end conditioning module. At the same time, the inter-channel delay deviation is digitally corrected based on a fixed phase error compensation algorithm to ensure the synchronization accuracy of the channels within the board. For the multi-board cascaded application scenario, a control main board is designed, and the inter-board channel acquisition synchronization is corrected based on the clock buffer cascaded architecture to achieve the inter-board channel acquisition synchronization. At the same time, the Precision Time Protocol and a 10 Gigabit Ethernet switch are used for networking to build a high-transmission-rate distributed synchronization acquisition network, realizing the precise synchronization acquisition and high-speed transmission of signals.

2. A high-precision multi-channel synchronous acquisition method for a magnetic inertia-confinement device according to claim 1, comprising the following steps: Step 1: Design an analog signal conditioning module using high-precision resistors, capacitors, BUF802, OPA140, LMH5401, and LMH6401 to achieve the adjustment of signal amplitude gain and bias level. Among them, the design of the analog signal conditioning module specifically includes: a passive attenuation network, an impedance transformation circuit, a DC bias adjustment circuit, and a controllable gain amplifier circuit (including a single-ended to differential conversion unit, a programmable gain amplifier). The specific steps are as follows: 1) Considering the relationship between amplifier gain and noise, the signal passive attenuation circuit adopts a voltage division network with a 5-fold attenuation, and uses a fixed capacitor and a variable capacitor. By changing the value of the variable capacitor, the effect of complete compensation for parasitic capacitance can be achieved. 2) Select the amplifier chip BUF802 and make it operate in the composite loop mode (CL Mode) to cooperate with the precision operational amplifier (OPA140) to construct a two-path signal processing system, improving the DC accuracy and frequency response flatness of the system. 3) Select the digital-to-analog converter chip DAC8560 and control the output of the DAC to adjust the bias voltage. 4) Select the amplifier chips LMH5401 and LMH6401 to achieve single-ended to differential conversion and controllable amplitude gain of the signal. Step 2: Combine the temperature-compensated crystal oscillator DSA321SCL and the LMK04821 clock chip, and design a clock module using a double-cascaded phase-locked loop structure to achieve sampling clock synchronization. Among them, the design steps of the sampling clock synchronization module are as follows: 1) Select the DSA321SCL temperature-compensated crystal oscillator (TCXO) as the system main clock reference source, and use the LMK04821 clock generator chip, configured in the double-stage interlocked phase-locked loop mode. 2) Taking the 10 MHz signal output by the DSA321SCL as a reference, generate a 100 MHz intermediate clock through integer division and PLL1, receive the output signal of PLL1, and combine with the on-chip low-noise VCO to generate multiple channels of synchronous sampling clocks. Step 3: Use AD9680, KINTEX-7 series FPGA chips, DDR3 cache, PHY chips, and RJ45 interfaces to design the acquisition, processing, and transmission modules of the data acquisition card. The specific steps are as follows: 1) The AD9680 14-bit dual-channel ADC is adopted to digitize the signals and interconnect with the FPGA through the JESD204B Subclass 1 protocol. 2) The FPGA chip of XC7K325T model is used to deploy 8 groups of JESD204B IP cores. Each channel occupies 4 GTX transceivers to realize 16-channel parallel reception of ADC data. The external MT41J256M16HA DDR3 chip is configured as a 64-bit bus and uses the internal Ping-Pong cache structure of the chip to alternately write to DDR3 Bank0 / Bank1 to achieve zero-waiting time switching. A network link is constructed by combining the KSZ9031RNXIC gigabit PHY chip and the RJ45 interface to realize communication with the PC side. Step 4: Obtain the sampling data of each channel, perform operations using the sine fitting method to obtain the error between the sampling data of the channels on the board, and perform corresponding delay compensation on each channel according to the error parameters. Among them, the specific steps of the delay correction design based on the fixed phase error compensation algorithm are as follows: 1) First, after obtaining the sampling data of each channel, it is necessary to estimate the phase error between channels. The ideal sampling signal is: s(t) = Asin(2πft + φ0) + ε(t) (1) where A is the amplitude, f is the signal frequency, φ0 is the initial phase, and ε(t) is the noise term. 2) For the discrete sampling sequence s i [n] of the i-th channel, use the least squares sine fitting to estimate its phase φ i : 3) By solving the eigenvalues of the Hessian matrix, the phase estimates {φ1, φ2,..., φ M} of each channel are obtained, and the phase difference relative to the main channel is calculated: Δφ i = φ i - φ ref (i = 1, 2,..., M) (3) 4) Convert the phase difference to a time difference: 5) Calculate the number of digital delay units according to the system clock resolution δt: Where N delay,i is the number of dynamically inserted delay units in the FPGA. Step 5: Use the active crystal oscillator SIT8008BI, NB3L553DG, CDCLVC1106PWR clock buffer chip, and LH32M0S3 single-chip microcomputer, and design the control main board based on the clock buffer cascade architecture to achieve high-precision synchronization of different acquisition boards. The specific steps are as follows: 1) Use the SIT8008BI active crystal oscillator as the global reference source of the control main board to provide a pure clock reference for the cascade architecture, and generate internal pulse signals through the LH32M0S3 single-chip microcomputer. 2) Use the CDCLVC1106PWR to receive the 10MHz signal, pulse signal, and external trigger signal of the SIT8008BI respectively to form the first-level clock buffer module, and compensate for the PCB trace difference through the internal adjustable delay line to ensure the synchronization of the multi-path fan-out signals. 3) Use the NB3L553DG to receive the multi-path fan-out signals of the CDCLVC1106 first-level clock buffer module respectively to form the second-level clock buffer module, break through the driving limit of the traditional single-level buffer, and support multi-board cascading. Step 6: Use the S5735S Ethernet switch to communicate with the PC side, and develop the upper computer software based on the Qt framework for data waveform display, file storage, and board control. The specific steps are as follows: 1) Use the S5735S-24P4X-A Gigabit Ethernet switch, deploy QoS policies to ensure the priority transmission of data, enable the LLDP protocol to achieve automatic topology discovery, and configure static MAC address binding to prevent ARP attacks. At the same time, the data stream uses the IEEE1588PTP protocol to achieve nanosecond-level time synchronization. 2) Based on the QT framework, use layout managers QVBoxLayout, QHBoxLayout, and QGridLayout to organize controls, ensure that the interface has adaptive functions at different resolutions, and integrate data visualization, high-speed storage, and precise control.

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