Equipment management method, device and system based on bus technology

Abstract

The embodiment of the invention provides an equipment management method, device and system based on a bus technology, a bus controller does not need to initiate, bus equipment can actively send own equipment information to the bus controller after being powered on, and the bus controller sends the equipment information of the bus equipment to the bus controller after receiving the equipment information of the bus equipment. The address space of the bus is allocated to the bus equipment according to the equipment information of the bus equipment, so that the time delay of finding the bus equipment by the bus controller is reduced, and the efficiency of managing a bus network by the bus controller is improved.

Description

[0001] This application claims the priority of a Chinese patent application titled "A Management Method for Bus Devices and a Bus Controller" with an application number of 202410117987.9 and filed with the National Intellectual Property Administration on January 26, 2024. The entire content of which is incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular, to a device management method, device, and system based on bus technology. Background Art

[0003] Compared with traditional Ethernet, bus networks have advantages such as lower latency and larger bandwidth. With the rapid development of information technology, data and computing-intensive application scenarios such as public clouds, artificial intelligence (AI), and autonomous driving computing are becoming more and more popular, and the entire computing system will become more and more complex. Thus, the requirements for the interconnecting bus are bound to become higher and higher, and it becomes increasingly important to reduce the latency of the bus network and improve the management efficiency of the bus network. Summary of the Invention

[0004] In the existing management mechanism of bus networks, the bus controller discovers and registers bus devices through enumeration scanning. As the scale of the bus network continues to increase, the number of bus devices that the bus controller needs to scan continues to increase, which not only causes the latency of the bus controller discovering bus devices to continuously increase, but also causes the load of the bus controller to continuously increase, increasing the probability of the bus controller malfunctioning and reducing the reliability of the bus network.

[0005] In view of this, this application provides a device management method, device, and system based on bus technology. After the bus device is powered on, it can actively send its device information to the bus controller without waiting to receive an enumeration message sent by the bus controller. After receiving the device information of the bus device, the bus controller allocates the address space of the bus for the bus device according to the device information of the bus device. In this way, it is not only beneficial to reduce the latency of the bus controller discovering bus devices and improve the efficiency of the bus controller managing the bus network, but also beneficial to reduce the load of the bus controller, reduce the probability of the bus controller malfunctioning, and thus improve the reliability of the bus network.

[0006] In a first aspect, the present application provides a device management method based on bus technology. This method is executed by a bus controller in a bus network, and the bus network includes multiple bus devices interconnected by a bus. The bus controller can be a bus device, or a partial component of a bus device (such as a processor, a chip, or a chip system, etc.), or a logical module or software that implements all or part of the functions of a bus device. In this method, the bus controller receives device announcement information, and the device announcement information includes device information of a first bus device, where the device information of the first bus device is actively sent by the first bus device to the bus controller after power-on. Then, the bus controller allocates an address space of the bus for the first bus device according to the device information of the first bus device, and then sends configuration information to the first bus device, and the configuration information includes address information for describing the address space.

[0007] Since the bus controller can allocate an address space for the first bus device according to the device information actively sent by the first bus device after power-on, in this way, it is not only beneficial to reduce the time delay for the bus controller to discover the bus device and improve the efficiency of the bus controller in managing the bus network, but also beneficial to reduce the load of the bus controller and lower the probability of the bus controller malfunctioning, thereby enhancing the reliability of the bus network.

[0008] Optionally, the first bus device actively sends its own device information to the bus controller after power-on, and it is not limited that the first bus device must not have received information from the bus controller before sending its own device information to the bus controller. Instead, it means that the first bus device sending its own device information to the bus controller does not depend on receiving information from the bus controller (such as an enumeration message). Even if the first bus device has not received any information from the bus controller after power-on, the first bus device can still send its own device information to the bus controller.

[0009] In a possible implementation manner of the first aspect, the device information of the first bus device is forwarded from the first bus device and then through one or more bus devices in the bus network to the bus controller. Or rather, the first bus device is not directly connected to the bus controller. The bus controller can allocate an address space for the non-directly connected first bus device according to the device information actively sent by it, which is beneficial to reducing the time delay for the bus controller to discover the first bus device through one or more bus devices and improving the efficiency of the bus controller in managing a large-scale bus network (such as a bus network across computing devices).

[0010] In a possible implementation manner of the first aspect, multiple bus devices are arranged in at least two computer devices.

[0011] In a possible implementation of the first aspect, the device announcement information further includes path information. The path information is used to indicate the information that the device information of the first bus device is forwarded through one or more bus devices. The bus controller can also determine the forwarding path of the device announcement information between the first bus device and the bus controller according to the path information. The bus controller's determination of the forwarding route between the first bus device and itself is conducive to improving its management of the bus network. Moreover, based on the device information actively sent by the first bus device after power-on, the bus controller can determine the forwarding path between the first bus device and itself, which is conducive to reducing the delay for the bus controller to determine the topological position of the first bus device in the bus network. In this way, it is not only conducive to improving the efficiency of the bus controller in managing the bus network, but also conducive to reducing the load of the bus controller and reducing the probability of the bus controller failing, thereby enhancing the reliability of the bus network.

[0012] This application does not limit the implementation manner that enables the device announcement information to further include path information. Optionally, after receiving the device information of the first bus device, the bus device with forwarding function encapsulates the device information of the first bus device and the information for forwarding it together and then forwards it.

[0013] This application does not limit that all bus devices with forwarding function encapsulate the device information of the first bus device and the information for forwarding it together and then forward it after receiving the device information of the first bus device. Optionally, the bus device connecting the first bus device in the bus network can encapsulate the device information of the first bus device and the information for forwarding it together and then forward it after receiving the device information of the first bus device.

[0014] In a possible implementation of the first aspect, when the device information of the first bus device is forwarded to the bus controller through multiple bus devices in the bus network, there can be multiple forwarding paths between the bus controller and the first bus device. The bus controller can respectively receive multiple device announcement information each including the device information of the first bus device. The device information of the first bus device in these multiple device announcement information is forwarded to the bus controller through different forwarding paths among these multiple forwarding paths. Moreover, as introduced above, the device announcement information further includes path information, and this path information is used to indicate the information that the device information of the first bus device in this device announcement information is forwarded through one or more bus devices. After that, the bus controller can determine the corresponding multiple forwarding paths according to the path information in each device announcement information among the multiple device announcement information.

[0015] This application does not limit the implementation manner in which the device information of the first bus device in the multiple device announcement messages reaches the bus controller via multiple forwarding paths. Optionally, a bus device with forwarding function in the bus network (such as a bus switch) can forward the device information of the first bus device by broadcasting after receiving it. Or, a bus device with forwarding function in the bus network (such as a bus switch) can forward the device information of the first bus device to the peer bus device with forwarding function and the bus controller after receiving it, and for the peer bus device without forwarding function and not being the bus controller, the device information of the first bus device may not be forwarded to it, which is beneficial to improving the security of the device information of the first bus device.

[0016] This application does not limit that all bus devices with forwarding function in the bus network forward the received device information of the first bus device by broadcasting. Optionally, after receiving the device information of the first bus device, the bus device connected to the first bus device in the bus network forwards it by broadcasting.

[0017] Optionally, a single forwarding path sequentially passes through one or more bus devices, and different forwarding paths pass through different bus devices or different ports of bus devices or different numbers of bus devices.

[0018] In a possible implementation manner of the first aspect, when the bus controller sends configuration information to the first bus device, it may include: the bus controller determines a target forwarding path according to the multiple forwarding paths between the first bus device and itself determined above, and sends the configuration information to the first bus device through the target forwarding path. Compared with the bus controller sending configuration information to the first bus device through multiple forwarding paths respectively, it is beneficial to save the transmission resources of the bus.

[0019] Optionally, the bus controller sending configuration information to the first bus device through the target forwarding path may mean sending the configuration information through the ports on the target forwarding path among its multiple ports, or the configuration information carries the information of the target forwarding path to instruct other bus devices except the first bus device to forward the configuration information according to the target forwarding path after receiving the configuration information.

[0020] In a possible implementation of the first aspect, the bus controller may further send device information of the bus controller to at least one bus device connected to the bus controller. The device information of the bus controller is used to instruct at least one bus device to record information about the port for connecting to the bus controller. In this way, by sending its own device information, the bus controller helps at least one bus device connected to it record the port through which they are connected to the bus controller, thus facilitating the improvement of the success rate of other bus devices in sending information to the bus controller and enhancing the management efficiency of the bus controller for the bus network.

[0021] In a possible implementation of the first aspect, the bus controller may also receive device information of a second bus device in the bus network, and the device information of the second bus device is forwarded by at least one bus device according to the recorded information about the port for connecting to the bus controller. Similar to the previous case, the device information of the second bus device may be actively sent by the second bus device to the bus controller after power-on. After receiving the device information of the second bus device, at least one bus device forwards the device information according to the recorded information about the port for connecting to the bus controller, which helps improve the success rate of the bus controller in receiving the device of the second bus device. Moreover, it helps prevent at least one bus device from broadcasting the device information of the second bus device to each of its ports respectively. In this way, on the one hand, it helps reduce the load of at least one bus device, save the transmission resources of the bus, and on the other hand, it helps improve the security of the second bus device.

[0022] In a possible implementation of the first aspect, the bus controller may also receive status notification information of a first bus device. The status notification information of the first bus device is used to indicate that the first bus device will exit the bus network or is still connected to the bus network, and the status notification information of the first bus device is forwarded by at least one bus device according to the recorded information about the port for connecting to the bus controller. Then, the bus controller can determine the connection status of the first bus device in the bus network based on the status notification information of the first bus device. In this way, it helps improve the success rate of the bus controller in receiving the status notification information, enhances the management efficiency of the bus controller for the bus network, and also helps prevent at least one bus device from broadcasting the status notification information to each of its ports respectively, reducing the load of at least one bus device and saving the transmission resources of the bus.

[0023] Optionally, the connection status of the first bus device in the bus network may be that the first bus device will exit the bus network, has exited the bus network, or is still connected to the bus network.

[0024] In a possible implementation of the first aspect, the device types of the bus devices that forward the device information of the first bus device in the bus network include bus switches. Optionally, the device types of the bus devices that forward the device information of the first bus device in the bus network may also include other types. For example, they may also include bus terminals that support mapping their own storage spaces to the address space of the bus.

[0025] In a possible implementation of the first aspect, the device information of the first bus device includes the identifier of the first bus device, and the identifier of the first bus device includes at least one of the device type of the first bus device, the manufacturer identifier of the first bus device, and the device identifier of the first bus device.

[0026] In a possible implementation of the first aspect, the device information of the first bus device includes the size of the address space required by the first bus device. In this way, it is beneficial for the bus controller to allocate an address space for the first bus device according to the size of the address space required by the first bus device, which helps to improve the accuracy of the bus controller in allocating the address space for the first bus device. This not only helps to avoid configuration errors caused by the address space allocated by the bus controller for the first bus device being larger than the maximum available storage space of the first bus device, but also helps to avoid wasting the storage resources of the first bus device due to the address space allocated by the bus controller for the first bus device being much smaller than the available storage space of the first bus device.

[0027] In the method provided in the first aspect, the first bus device can be any bus device in the bus network, or any bus device that supports mapping its own storage space to the address space of the bus. The first bus device can send its device information through a message, and the bus controller can receive the device announcement information through a message. The message sent by the first bus device and the message received by the bus controller may be different. For example, the message sent by the first bus device may not include path information, while the message received by the bus controller may include, in addition to the device information of the first bus device, path information. Optionally, the device information of the first bus device and the path information in the device announcement information may also be encapsulated in different messages. The device announcement information received by the bus controller may include, in addition to the device information of the first bus device, the device information of other bus devices, and the device information of different bus devices may be encapsulated in the same or different messages.

[0028] Second aspect, the present application provides a device management method based on bus technology. This method is applied to a bus network, which includes multiple bus devices interconnected by a bus, and a bus controller runs in the bus network. The bus controller can be understood by referring to the bus controller described in the first aspect. In this method, after power-on, the first bus device in the bus network actively sends the device information of the first bus device; the bus controller receives the device announcement information, which includes the device information of the first bus device; the bus controller allocates an address space of the bus for the first bus device according to the device information of the first bus device, and sends configuration information to the first bus device, where the configuration information includes address information used to describe the address space; the first bus device receives the configuration information, and maps all or part of its storage space to the address space described by the address information according to the indication of the configuration information.

[0029] In the method provided in the second aspect, the possible steps executed by the bus controller, the first bus device, and other bus devices in the bus network can be understood by referring to the steps executed by the corresponding devices in the first aspect, and will not be elaborated here.

[0030] For example, in a possible implementation manner of the first aspect, the device information of the first bus device is forwarded from the first bus device and then relayed by one or more bus devices in the bus network to the bus controller.

[0031] For example, in a possible implementation manner of the second aspect, the bus device connecting the first bus device in the bus network can, after receiving the device information of the first bus device, forward the device information of the first bus device and the path information of the bus device itself for relaying the device information of the first bus device. The path information of the bus device for relaying the device information of the first bus device is used to indicate the information that the device information of the first bus device is relayed by this bus device. Optionally, the bus device encapsulates the device information of the first bus device and the path information of the bus device itself for relaying the device information of the first bus device in the same message and then forwards it.

[0032] For example, in a possible implementation manner of the second aspect, after receiving the device information of the first bus device, the bus device connecting the first bus device in the bus network forwards it in a broadcast manner.

[0033] For example, in a possible implementation manner of the second aspect, the method further includes: the bus controller sends its own device information to at least one bus device connected to itself; the at least one bus device records the information of the port used to connect the bus controller according to the indication of the device information of the bus controller.

[0034] For example, in a possible implementation of the second aspect, the method further includes: after power-on, the second bus device in the bus network actively sends its device information to the bus controller; the at least one bus device forwards the device information of the second bus device to the bus controller according to the information of the ports of the bus controller; the bus controller receives the device information of the second bus device.

[0035] For example, in a possible implementation of the second aspect, the method further includes: the first bus device sends its status notification information to the bus controller, and the status notification information is used to indicate that the first bus device will exit the bus network or is still connected to the bus network; the at least one bus device forwards the status notification information to the bus controller according to the information of the ports of the bus controller; the bus controller receives the status notification information and determines the connection status of the first bus device in the bus network according to the status notification information.

[0036] A third aspect of the present application provides a bus controller, which is deployed in a bus network. The bus network includes a plurality of bus devices connected by a bus. The bus controller can be a bus device, or a part of the components of the bus device (such as a processor, a chip, or a chip system, etc.), or a logical module or software that implements all or part of the functions of the bus device.

[0037] The bus controller may include a transceiver module and a processing module. Among them, the transceiver module can be used to receive device notification information, and the device notification information includes the device information of the first bus device, and the device information of the first bus device is actively sent to the bus controller by the first bus device after power-on. The processing module is used to allocate the address space of the bus for the first bus device according to the device information of the first bus device. The transceiver module is also used to send configuration information to the first bus device, and the configuration information includes address information for describing the address space.

[0038] In a possible implementation of the third aspect, the device information of the first bus device is forwarded from the first bus device and then forwarded to the bus controller through one or more bus devices in the bus network.

[0039] In a possible implementation of the third aspect, the device notification information further includes path information, and the path information is used to indicate the information of the device information of the first bus device being forwarded through one or more bus devices. The processing module is also used to determine the forwarding path of the device notification information between the first bus device and the bus controller according to the path information.

[0040] In a possible implementation of the third aspect, when the device information of the first bus device is forwarded to the bus controller via multiple bus devices in the bus network, the transceiver module is specifically configured to receive multiple device advertisement messages respectively, and the device information of the first bus device in the multiple device advertisement messages is via different forwarding paths. The processing module is configured to determine corresponding multiple forwarding paths according to the path information in each device advertisement message in the multiple device advertisement messages.

[0041] In a possible implementation of the third aspect, the transceiver module is specifically configured to determine a target forwarding path according to the multiple forwarding paths, and send configuration information to the first bus device via the target forwarding path.

[0042] In a possible implementation of the third aspect, the transceiver module is further configured to send the device information of the bus controller to at least one bus device connected to the bus controller, and the device information of the bus controller is used to instruct at least one bus device to record the information of the port for connecting to the bus controller.

[0043] In a possible implementation of the third aspect, the transceiver module is further configured to receive the device information of the second bus device in the bus network, the device information of the second bus device is actively sent by the second bus device to the bus controller after power-on, and the device information of the second bus device is forwarded by at least one bus device according to the recorded information of the port for connecting to the bus controller.

[0044] In a possible implementation of the third aspect, the transceiver module is further configured to receive the status advertisement message of the first bus device, the status advertisement message of the first bus device is used to indicate that the first bus device will exit the bus network or is still connected to the bus network, and the status advertisement message of the first bus device is forwarded by at least one bus device according to the recorded information of the port for connecting to the bus controller; the determination module is further configured to determine the connection status of the first bus device in the bus network according to the status advertisement message of the first bus device.

[0045] In a possible implementation of the third aspect, the device type of the bus device that forwards the device information of the first bus device in the bus network includes a bus switch.

[0046] In a possible implementation of the third aspect, the device information of the first bus device includes the identifier of the first bus device, and the identifier of the first bus device includes at least one of the device type of the first bus device, the manufacturer identifier of the first bus device, and the device identifier of the first bus device.

[0047] In a possible implementation of the third aspect, the device information of the first bus device includes the size of the address space required by the first bus device.

[0048] In a possible implementation of the third aspect, multiple bus devices are arranged in at least two computer devices.

[0049] In a fourth aspect, the present application further provides a bus device, which includes a processor and a memory. The processor is coupled to the memory, and the processor is configured to execute the method described in the first aspect or any possible implementation of the first aspect based on the instructions stored in the memory.

[0050] In a fifth aspect, the present application further provides a computer program product, including computer-readable instructions, which, when running on a computer, cause the computer to execute the method described in the first aspect or any possible implementation of the first aspect.

[0051] In a sixth aspect, the present application further provides a computer-readable storage medium, in which instructions are stored, and when the instructions run on a computer, cause the computer to execute the method described in the first aspect or any possible implementation of the first aspect.

[0052] In a seventh aspect of the present application, a chip is provided, which includes a processor. The processor is used to read and execute a computer program stored in a memory to execute the method in any possible implementation of any of the above aspects. Optionally, the chip includes a memory, and the memory is connected to the processor through a circuit or a wire. Further optionally, the chip further includes a communication interface, and the processor is connected to the communication interface. The communication interface is used to receive data and / or information that needs to be processed. The processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing result through the communication interface. The communication interface may be an input / output interface.

[0053] In an eighth aspect of the present application, a bus network is provided. The bus network includes multiple bus devices connected through a bus, and a bus controller runs in the bus network. The bus controller is used to execute the method described in any one of the first aspect and various possible implementations above.

[0054] Among them, for the implementation manners and technical effects of the device provided in the present application, reference may be made to the technical effects brought by the corresponding implementation manners in the method provided in the present application, which will not be elaborated here. Description of the Drawings

[0055] Figure 1 Schematically showing a possible structure of a bus network;

[0056] Figure 2 Schematically showing another possible structure of a bus network;

[0057] Figure 3Schematically shows a possible process of the device management method provided by the embodiments of the present application based on bus technology;

[0058] Figure 4 Schematically shows the process of the bus switch 1 broadcasting the announcement message of the CPU;

[0059] Figure 5 Schematically shows the forwarding path of the bus controller sending the configuration message 1 to the CPU through the bus switching network;

[0060] Figure 6 Schematically shows the management method of newly added SSDs in the bus network;

[0061] Figure 7 Schematically shows the management method of SSDs exiting the bus network;

[0062] Figure 8 Schematically shows the structure of the bus controller;

[0063] Figure 9 Schematically shows the structure of the bus device. Detailed implementation manners

[0064] First, some terms in the present application are explained to facilitate the understanding of those skilled in the art.

[0065] The bus is a common communication trunk for transmitting information between various functional components (referred to as bus devices) of a computer. According to the types of information transmitted by the computer, the bus of the computer can be divided into a data bus, an address bus, and a control bus, which are used to transmit data, data addresses, and control signals respectively.

[0066] A bus device refers to an electronic device or a computer device that has a bus interface or supports a bus protocol or can communicate with other devices through a bus. It can be a main processor unit (central processing unit, CPU), a network card, a memory, a solid state drive (SSD), or an input / output device, etc.

[0067] The bus network includes multiple bus devices connected through a bus.

[0068] The bus controller is used to manage the bus devices in the bus network. For example, it can be responsible for discovering and registering the bus devices in the bus network. The bus controller can run on a bus device, and it can be implemented through software and / or hardware. The present application does not limit the type of the bus device where the bus controller is located. For example, the bus controller can run on a bus device such as a CPU or a network card. Hereinafter, the bus controller can also refer to a bus device having the above bus controller function.

[0069] A bus terminal can run on a bus device, which can be implemented by software and / or hardware, and can support mapping all or part of the storage resources in the bus device where it is located to the address space of the bus for direct access by other bus devices. This application does not limit the type of the bus device where the bus terminal is located. For example, the bus terminal can run on bus devices such as a CPU, a network card, a memory, an SSD, or an input / output device. Hereinafter, the bus terminal can also refer to a bus device with the above-mentioned bus terminal function.

[0070] A bus switch is used to implement bus interconnection and routing (or forwarding). The bus switch can run on a bus device, which can be implemented by software and / or hardware. This application does not limit the type of the bus device where the bus switch is located. For example, the bus switch can run on bus devices such as a CPU or a network card. Hereinafter, the bus switch can also refer to a bus device with the above-mentioned bus switch function. One or more bus switches can build one or more physical links or forwarding paths between other different bus devices, so as to realize access between different bus devices.

[0071] A hybrid bus device can have multiple functions. For example, it can have two functions among the above-mentioned bus controller, bus terminal, and bus switch. For the bus controller, bus terminal, and bus switch mentioned hereinafter, they can be hybrid bus devices.

[0072] Network topology refers to the method of studying the relationship between points and lines regardless of size and shape in topology, abstracting the bus devices in the bus network as a point and the transmission medium (such as a bus) as a line. The geometric figure composed of points and lines is the network topology (or topological structure) of the bus network. Among them, the types of network topology can include but are not limited to ring topology, tree topology, star topology, hybrid topology, and mesh topology, etc.

[0073] This application does not limit the type of the bus. For example, the bus can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), or a nvidia link (NVLINK) bus, etc.

[0074] A bus network may include multiple bus devices of the same or different types. For example, it may include a bus controller, bus terminals, and bus switches. The bus domains need to have a unified address assignment before they can access each other. Therefore, after power-on initialization, the bus terminals need to obtain the allocated address space from the bus controller before they can access each other.

[0075] In the management mechanism of the existing bus network, the bus controller discovers and registers the bus terminals by means of enumeration scanning. Figure 1 Schematically shows a possible structure of a bus network. As Figure 1 shown, the bus network includes a bus controller, a bus switch, and three bus terminals. In the drawings of the present application, a hexagon represents the bus switch, and different sides of the hexagon represent different ports of the bus switch. Figure 1 The connections between different bus devices represent buses. Assume that Figure 1 the shown bus is a PCIe bus. As Figure 1 shown, three different ports of the bus switch are respectively connected to two bus terminals and a bus controller, and the bus controller is also directly connected to a bus terminal. The bus controller can adopt a master-slave model and sequentially scan to discover each bus terminal. For example, the bus controller first performs the training of the PCIe link, and then, by means of enumeration scanning, reads the registers of the configuration space (or called PCIe space) of the bus terminal, receives the transaction layer packet (TLP) returned by the bus terminal in response to the enumeration report packet, writes the TLP configuration information, and then allocates and configures the address space for the bus terminal to realize the normal use of the bus terminal.

[0076] However, in order to discover the bus terminals connected to the bus switch, the bus controller needs to first read and configure the configuration space of the bus switch through an enumeration report packet, so that the bus switch determines the forwarding path to the bus controller, for example, determines the port of the bus switch that leads to the bus controller. In this way, the bus switch can forward the enumeration report packet to the connected bus terminal according to the configured forwarding path and forward the TLP to the bus controller. That is to say, the bus controller needs to first configure the bus switch and then can discover the bus terminals connected to the ports of the bus switch, which increases the delay of the bus controller in discovering the bus terminals.

[0077] In addition, during the scanning process, only the CPU acting as the bus controller can initiate, and other bus devices act as slave devices. And due to the limited configuration range space, the registration ability across multiple levels of bus switches (such as 1K+ bus device nodes) cannot be achieved.

[0078] Moreover, as the scale of the bus network continues to increase, the bus network includes a larger number of bus switches and bus terminals. The bus devices in the bus network can be arranged in multiple computing devices (or clusters of computing devices). Figure 2 Schematically shows another possible structure of the bus network. Figure 2 Taking the bus network including a bus controller, 3 bus terminals, and 6 bus switches as an example, these 3 bus terminals are the CPU, network card, and memory respectively, and these 6 bus switches are bus switch 1 to bus switch 6 respectively. For ease of description, bus switch 1 to bus switch 6 are referred to as the bus switching network hereinafter. The bus switching network has multiple ports for connecting other bus devices in the bus network. Other bus devices include a bus controller, CPU, network card, and memory. The multiple ports ( Figure 2 the bolded ports therein) of the bus switching network include port 1 and port 3 of each of bus switch 1 to bus switch 4, and also include port 3 of bus switch 5 and port 3 of bus switch 6. Figure 2 Schematically shows two computing devices (rack 1 and rack 2) including bus devices, and the bus devices in the bus network can be located on a larger or smaller number of computing devices. Figure 2 Taking the computing device as a rack-mounted server as an example, the computing device can be other types of devices.

[0079] As Figure 2 shown, there is at least one forwarding path between any two different external ports of the bus switching network, and each forwarding path passes through at least one bus switch. Moreover, the forwarding path between the bus controller and the bus terminal passes through at least two bus switches. It can be seen that as the scale of the bus network continues to increase, the bus controller needs to penetrate more and more bus switches to discover the bus terminal, which causes the bus controller to need to configure forwarding paths to itself for a larger number of bus switches before it can send an enumeration packet to the bus terminal connected to the bus switch and receive the returned TLP. The latency for the bus controller to discover the bus terminal continues to increase, which is not conducive to ensuring the management efficiency of the bus network. In addition, since the bus controller needs to configure the forwarding paths between different ports among multiple ports in each bus switch respectively, the load of the bus controller is large, which increases the probability of the bus controller failing and reduces the reliability of the bus network.

[0080] In view of this, the present application provides a device management method based on bus technology. After the bus device is powered on, it can actively send its device information to the bus controller without waiting to receive the enumeration message sent by the bus controller. After receiving the device information of the bus device, the bus controller allocates the address space of the bus for the bus device according to the device information of the bus device. In this way, it is not only beneficial to reduce the time delay for the bus controller to discover the bus device and improve the efficiency of the bus controller in managing the bus network, but also beneficial to reduce the load of the bus controller and reduce the probability of the bus controller malfunctioning, thereby improving the reliability of the bus network.

[0081] Based on the following Figure 2 shown structure of the bus network, an example is given to introduce the method flow of the bus controller penetrating bus switches 1 to 6 to manage the CPU. As Figure 2 shown, the bus controller is respectively connected to port 3 of bus switches 5 and 6 in the bus switching network, and the CPU is respectively connected to port 1 of bus switch 1 and port 3 of bus switch 2 in the bus switching network. For the convenience of description, port 3 of bus switch 5 and port 3 of bus switch 6 are collectively referred to as the first port of the bus switching network, and port 1 of bus switch 1 and port 3 of bus switch 2 are collectively referred to as the second port of the bus switching network. Figure 3 Schematically shows the flow of the method provided by the present application, and this method may include steps S301 to S305.

[0082] S301. The CPU sends its announcement message to the second port. Correspondingly, the bus switching network receives the announcement message from the second port, where the announcement message includes the device information of the CPU;

[0083] The CPU can send its announcement message to the second port. Correspondingly, the bus switching network can receive the announcement message from the second port. Among them, the announcement message includes the device information of the CPU. The device information of the CPU may include the identifier of the CPU. The present application does not limit the specific content of the identifier of the CPU, as long as the identifier of the CPU can be used to uniquely identify the identity of the CPU in the bus network. For example, the identifier of the CPU may include at least one of the device type of the CPU, the manufacturer identifier (identification, ID), and the device ID.

[0084] The device information of the CPU may further include the size of the address space required by the CPU. The size of the address space required by the CPU may refer to the size of the address space in the storage space of the CPU that can be directly accessed by other bus devices in the bus network. In this way, it is beneficial for the bus controller to allocate the address space for it according to the size of the address space required by the CPU, and improve the accuracy of the bus controller in allocating the address space for the CPU.

[0085] Table 1 schematically shows the possible content of the advertisement message sent by the CPU to the second port. As shown in Table 1, the advertisement message of the CPU includes six fields, namely the device type field, the device ID field, the manufacturer identification field, the device required address space field, the device start address field, and the device end address field. Among them, the value of the device type field is used to indicate the device type of the device, the value of the device ID field is used to indicate the device ID of the device, the value of the manufacturer ID field is used to indicate the manufacturer ID of the device, the value of the device required address space field is used to indicate the size of the address space required by the device, and the values of the device start address field and the device end address field are respectively used to indicate the start address and the end address of the address space allocated by the bus controller for the device.

[0086] Table 1

[0087] Device Type Field: CPU Device ID Field: D1 Manufacturer ID Field: V1 Device Required Address Space Field: 1KB Device Starting Address Field: Empty Device Ending Address Field: Empty

[0088] Table 1 also schematically shows the information indicated by the values of the above fields in the advertisement message of the CPU through the content after the colon. As shown in Table 1, in the advertisement message of the CPU, the value of the device type field indicates that the device type of the bus device sending this advertisement message is the CPU, the value of the device ID field indicates that the device ID of this bus device is D1, the value of the manufacturer ID field indicates that the manufacturer ID of this bus device is V1, the value of the device required address space field indicates that the size of the address space required by this bus device is 1KB, and the values of the device start address field and the device end address field respectively indicate "empty", and "empty" can refer to an invalid address or a default address. The default address is not used to describe the address space allocated by the bus controller for the bus device, and the default address can be used to indicate that the bus controller has not allocated an address space for this bus device.

[0089] After power-on or initialization, the CPU can actively send its advertisement message to the second port. This application does not limit the specific process of CPU initialization. For example, CPU initialization includes BIOS initialization and / or the second port of its own port and the bus exchange network is connected through physical layer auto-negotiation (link). This application does not limit the specific content of the auto-negotiation between the CPU port and the second port of the bus exchange network. For example, during the process of auto-negotiation between ports, link establishment processes such as the interface rate of the docking ends, serializer / deserializer (SERDES) parameters of the link physical layer training, clock alignment, and channel binding can be executed.

[0090] This application does not limit that the CPU immediately sends its advertisement message after completing initialization. Optionally, the CPU can send its advertisement message after a period of time after completing initialization.

[0091] This application does not limit the CPU to sending an announcement message to the second port once. Optionally, the CPU can send the announcement message to the second port multiple times, which helps to increase the probability that the bus controller successfully receives the announcement message from the CPU.

[0092] As introduced above, the second port may include port 1 of bus switch 1 and port 3 of bus switch 2. The CPU can send its own announcement message to each port in the second port (such as port 1 of bus switch 1 and port 3 of bus switch 2) respectively, which helps to increase the probability that the bus controller successfully receives the announcement message from the CPU. Optionally, the CPU can also send its own announcement message to one port in the second port.

[0093] In practical applications, this application does not limit the number of ports of the bus switching network connected to the CPU. For example, the port of the bus switching network connected to the CPU (i.e., the first port) may include only one port or multiple ports.

[0094] S302. The bus switching network forwards the announcement message by broadcasting. Correspondingly, the bus controller receives the announcement message from the first port;

[0095] After receiving the announcement message of the CPU from the second port, the bus switching network can forward the announcement message by broadcasting. When there are forwarding paths between the second port and all other ports of the bus switching network, the bus switching network can forward the announcement message to all ports other than the second port (such as Figure 4 the ports marked with triangles as shown). Correspondingly, based on the existence of a forwarding path between the second port connected to the CPU and the first port connected to the bus controller, the bus switching network can forward the announcement message of the CPU to the bus controller through the first port, and the bus controller can receive the announcement message of the CPU from the first port.

[0096] As Figure 4 shown, there are forwarding paths between the ports of the bus switching network connected to the network card and the memory and the second port. Therefore, the bus switching network can forward the announcement message of the CPU to the network card through port 3 of bus switch 1 and port 1 of bus switch 2 respectively, and can forward the announcement message of the CPU to the memory through port 1 of bus switch 3 and port 3 of bus switch 4 respectively. The network card and the memory can receive the announcement message respectively, or, based on their device types not being the bus controller, they can not receive or discard the announcement message of the CPU.

[0097] The bus switching network forwards the announcement message by broadcasting can mean that each bus switch in the bus switching network that receives the announcement message forwards the announcement message by broadcasting. Figure 4Schematic diagram showing that the bus switch 1 broadcasts the announcement message after receiving it from the CPU. As Figure 4 shown by the dotted line with an arrow, after receiving the announcement message from the CPU through its own port 1, the bus switch 1 duplicates it to obtain 3 announcement messages, and then forwards these 3 announcement messages through its other ports (i.e., ports 2 to 4) respectively.

[0098] As Figure 4 shown, there can be multiple forwarding paths between the first port and the second port. These multiple forwarding paths include multiple forwarding paths between port 1 of bus switch 1 and port 3 of bus switch 5, multiple forwarding paths between port 1 of bus switch 1 and port 3 of bus switch 6, multiple forwarding paths between port 3 of bus switch 2 and port 3 of bus switch 6, and multiple forwarding paths between port 3 of bus switch 2 and port 3 of bus switch 6. Among the multiple forwarding paths between port 1 of bus switch 1 and port 3 of bus switch 5, port 1 of bus switch 1 can be connected to port 3 of bus switch 5 via its own port 2 and port 1 of bus switch 5 in sequence, or port 1 of bus switch 1 can be connected to port 3 of bus switch 5 via its own port 4, port 5 of bus switch 6, port 4 of bus switch 6, port 4 of bus switch 2, port 2 of bus switch 2 and port 2 of bus switch 5 in sequence, or port 1 of bus switch 1 can be connected to port 3 of bus switch 5 via its own port 4, port 5 of bus switch 6, port 1 of bus switch 6, port 2 of bus switch 3, port 4 of bus switch 3 and port 5 of bus switch 5 in sequence, etc.

[0099] Therefore, after the bus switching network forwards the announcement message by broadcast, it can send multiple announcement messages forwarded through different forwarding paths in the multiple forwarding paths to the bus controller through the first port. The bus controller can receive one or all of the multiple announcement messages.

[0100] S303. The bus controller allocates address space 1 for the CPU according to the device information of the CPU in the announcement message;

[0101] After receiving the announcement message of the CPU, the bus controller can allocate an address space (denoted as address space 1) for the CPU according to the device information of the CPU in the announcement message. The bus controller can allocate address space 1 for the bus device from the global address space (or bus domain) of the bus network, or in other words, the allocated address space 1 for the bus device is a subset of the global address space.

[0102] Among them, the global address space can refer to the maximum addressing space of the address bus in a bus network. As an example, assume that the maximum addressing capacity of the address bus in a bus network is 4GB, and the start address and end address of the global address space (or bus domain) of the bus network can be 1 and 4GB respectively.

[0103] As introduced above, the announcement message of the CPU can include the size of the address space required by the CPU, and the bus controller can allocate address space 1 for the CPU according to the size of the address space required by the CPU in the announcement message of the CPU. As shown in Table 1, assume that the size of the address space required by the CPU is 1KB, and the bus controller can allocate an address space 1 with a size of 1KB for the CPU from the global address space.

[0104] To ensure that the bus controller allocates different address spaces for different bus devices, the bus controller can maintain address allocation information. The address allocation information is used to indicate the unallocated address space in the global address space, and is also used to indicate the binding relationship between each allocated address space and the identifier of the allocated bus device. Assume that the identifier of the CPU in the announcement message of the CPU is "CPU, D1, V1". After the bus controller allocates address space 1 for the CPU according to the size of the address space required in the device information of the CPU, the address allocation information can be updated according to address space 1 and the identifier of the CPU in the device information of the CPU. The updated address allocation information can be used to indicate the binding relationship between address space 1 and "CPU, D1, V1".

[0105] S304. The bus controller sends configuration message 1 to the CPU through the bus switching network. Correspondingly, the CPU receives configuration message 1 through the bus switching network. Among them, configuration message 1 includes address information used to describe address space 1;

[0106] After the bus controller allocates address space 1 for the CPU, it can send configuration message 1 to the CPU through the bus switching network. Correspondingly, the CPU can receive configuration message 1 through the bus switching network. Among them, configuration message 1 includes address information used to describe address space 1 allocated by the bus controller for the CPU. Configuration message 1 can be used to instruct the CPU to map all or part of its storage space to address space 1 described by the address information.

[0107] Address space 1 can be a continuous address range or multiple discontinuous address ranges. This application does not limit the specific way in which the address information in configuration message 1 describes address space 1, as long as the address information can describe each address range of address space 1. For example, for any address range in address space 1, the address information can include at least one of the start address, end address, and length of the address range, etc.

[0108] In addition to the address information describing address space 1, configuration message 1 may also include other information. For example, configuration message 1 may also include all or part of the device information of the CPU (such as the identification of the CPU). Table 2 schematically shows the possible content of configuration message 1. The meanings and contents of the fields of configuration message 1 shown in Table 2 can be understood with reference to the relevant content of Table 1. However, the values of the device start address field and the device end address field in configuration message 1 shown in Table 2 are different from the values of the corresponding fields in Table 1. In configuration message 1 shown in Table 2, the value of the device start address field may indicate the start address of each address range in address space 1 (denoted as address 1), and the value of the device end address field may indicate the end address of each address range in address space 1 (denoted as address 2).

[0109] Table 2

[0110] Device Type Field: CPU Device ID Field: D1 Manufacturer ID Field: V1 Device Required Address Space Field: 1KB Device Starting Address Field: Address 1 Device Ending Address Field: Address 2

[0111] After generating configuration message 1, the bus controller may send configuration message 1 to the first port of the bus switching network. When the first port includes multiple ports (such as Figure 4 the port 3 of the bus switch 5 and the bus switch 6 shown), the bus controller may send configuration message 1 to each port in the first port, which is beneficial to improving the probability that the CPU successfully receives configuration message 1. Alternatively, the bus controller may send configuration message 1 to all or part of the ports in the first port that have received the announcement message from the CPU. Optionally, the bus controller may obtain and record multiple forwarding paths to the CPU to determine a part of the forwarding paths to the CPU (such as the forwarding path with the minimum delay), and then send configuration message 1 to the port located on this forwarding path (such as the port 1 of the bus switching network 5). When there are multiple forwarding paths with the minimum delay, the bus controller may send configuration message 1 to the ports on one or more of these forwarding paths. The possible ways for the bus controller to obtain each forwarding path to the CPU will be introduced later, and will not be elaborated here for the time being.

[0112] This application does not limit the manner in which the bus switching network forwards configuration message 1 to the CPU after receiving it from the first port. In some examples, the bus switching network may forward configuration message 1 by broadcast, so that configuration message 1 can be forwarded to the second port connected to the CPU. Or, in some instances, the bus switching network may forward configuration message 1 to the CPU according to the forwarding path to the CPU (such as Figure 5 the forwarding path indicated by the dotted line with an arrow in), which is beneficial to saving the forwarding resources of the bus switching network and improving the security of configuration message 1.

[0113] This application does not limit the way in which the bus switching network determines the forwarding path to the CPU. Optionally, the bus switching network may associate and record the forwarding path of the CPU and the identifier of the CPU in the advertisement message during the process of receiving and broadcasting the advertisement message of the CPU. In this way, when the bus switching network receives the configuration message 1 carrying the identifier of the CPU, it can determine the forwarding path associated and recorded with the identifier of the CPU, and then forward the configuration message 1 to the CPU according to this forwarding path.

[0114] This application does not limit the way in which the bus switching network records the forwarding path of the CPU during the process of receiving and broadcasting the advertisement message of the CPU. For example, for each bus switch in the bus switching network that receives the advertisement message of the CPU, it may associate and record the port that receives the advertisement message and the identifier of the bus device in the advertisement message. For example, after the bus switch 5 receives the advertisement message of the CPU from port 1, it may associate and record "CPU, D1, V1" and "port 1". After that, after receiving the configuration message 1 carrying "CPU, D1, V1" from its own port 3, it may send the configuration message 1 to port 1.

[0115] As introduced above, since the bus switching network forwards the advertisement message of the CPU in a broadcast manner, a single bus switch can receive the advertisement message of the CPU from multiple ports. The bus switch can send the configuration message 1 to each port that receives the advertisement message, or can send the configuration message 1 to one of the multiple ports. Optionally, the bus switch can obtain and record multiple forwarding paths to the CPU to determine a partial forwarding path to the CPU (such as the forwarding path with the minimum delay), and then send the configuration message 1 to the port located on this forwarding path. When there are multiple forwarding paths with the minimum delay, the bus switch can forward the configuration message 1 according to one or more of these forwarding paths. The possible ways for the bus switch to obtain multiple forwarding paths to the CPU will be introduced later and will not be elaborated here for the time being.

[0116] S305. The CPU maps its storage space 1 to the address space 1 according to the indication of the configuration message 1;

[0117] After receiving the configuration message 1, the CPU can configure its configuration space according to the indication of the configuration message 1. For example, the CPU can map its storage space 1 to the address space 1 according to the indication of the configuration message 1, which is beneficial for other bus devices in the bus network to directly address the storage space 1 of the CPU according to the address space 1, read data from the storage space 1 and / or write data to the storage space 1.

[0118] The size of storage space 1 can be the same as that of address space 1, but the values of the starting address and / or the ending address of the two can be the same or different, and their distribution states can be the same or different. For example, both storage space 1 and address space 1 can respectively correspond to a continuous address range, or storage space 1 corresponds to a continuous address range while address space 1 corresponds to multiple discontinuous address ranges, or storage space 1 corresponds to multiple discontinuous address ranges while address space 1 corresponds to a continuous address range, or both respectively correspond to multiple discontinuous address ranges.

[0119] Figure 3 The shown method flow schematically shows the process of the bus controller discovering and registering the CPU. The bus controller can also discover and register other bus devices connected to the bus switching network. For example, it can also respectively discover and register the network card and the memory. The method flow for the bus controller to discover other bus devices can refer to Figure 3 the shown flow.

[0120] After the bus controller discovers and registers the network card and the memory, it can respectively update the address allocation information introduced above. The updated address allocation information can not only indicate the binding relationship between address space 1 and "CPU, D1, V1", but also indicate the binding relationship between address space 2 and "network card, D2, V2", and the binding relationship between address space 3 and "memory, D3, V3". Among them, address space 2 and address space 3 are different address spaces in the global address space other than address space 1. D2 and V2 respectively represent the device ID and the manufacturer ID of the network card, and D3 and V3 respectively represent the device ID and the manufacturer ID of the memory.

[0121] After the bus device is powered on, it actively sends its own device information to the bus controller without waiting to receive the enumeration message sent by the bus controller. After receiving the device information of the bus device, the bus controller allocates the address space of the bus according to the device information of the bus device. In this way, it is not only beneficial to reduce the delay of the bus controller in discovering the bus device, improve the efficiency of the bus controller in managing the bus network, but also beneficial to reduce the load of the bus controller and reduce the probability of the bus controller failing, thereby improving the reliability of the bus network.

[0122] Optionally, as Figure 3 shown, after S305, the method flow can further include S306 and S307.

[0123] S306. The CPU sends notification message 1 to the bus controller through the bus switching network. Notification message 1 is used to indicate the configuration result of the CPU's own configuration space according to the indication of configuration message 1;

[0124] After the CPU configures its configuration space according to the instructions of configuration message 1, it can send notification message 1 to the bus controller through the bus switching network. Notification message 1 is used to indicate the configuration result of the CPU's configuration space according to the instructions of configuration message 1, and the configuration result is used to indicate successful configuration (pass) or failed configuration (fail).

[0125] S307. The bus controller sends instruction message 1 to the CPU through the bus switching network. Instruction message 1 is used to indicate that the registration of the CPU is completed;

[0126] When notification message 1 indicates successful configuration, the bus controller can determine that the storage space of the CPU can be directly accessed. Optionally, the bus controller can expose all or part of the address space in the CPU's address space 1 to other bus devices (such as network cards or memories) in the bus network for access. After that, the bus controller can send instruction message 1 to the CPU through the bus switching network. Instruction message 1 is used to indicate that the registration of the CPU is completed.

[0127] When notification message 1 indicates failed configuration, the bus controller can repeatedly send configuration message 1 until it receives a notification message indicating successful configuration sent by the CPU or times out. During the period when the CPU fails to configure successfully, the bus controller does not allow other bus devices to access address space 1. If the bus controller fails to receive a notification message indicating successful configuration sent by the CPU after timing out, the bus controller can reclaim the address space 1 allocated to the CPU.

[0128] Optionally, as Figure 3 shown, after S305, the method flow may further include S308 and S309.

[0129] S308. The CPU sends notification message 2 to the bus controller through the bus switching network. Notification message 2 is used to indicate that the status of the CPU is ready;

[0130] When the CPU completes the configuration according to the instructions of configuration message 1, it can send notification message 2 to the bus controller through the bus switching network. Notification message 2 is used to indicate that the status of the CPU is ready.

[0131] S309. The bus controller sends instruction message 2 to the CPU through the bus switching network. Instruction message 2 is used to indicate that notification message 2 is received;

[0132] After receiving notification message 2, the bus controller can send instruction message 2 to the CPU through the bus switching network. Instruction message 2 is used to indicate that notification message 2 is received.

[0133] Optionally, as Figure 3 shown, after S305, the method flow may further include S310 and S311.

[0134] S310. The bus controller sends a keep-alive message to the CPU through the bus switching network;

[0135] S311. The CPU sends a response message to the keep-alive message to the bus controller through the bus switching network.

[0136] If the bus controller receives a response message from the CPU to the keep-alive message within a predetermined time period, the bus controller can determine that the CPU is present. If the bus controller does not receive a response message from the CPU to the keep-alive message within the predetermined time period, the bus controller can determine that the CPU exits the bus network, cancel the registration of the CPU, and execute the device exit process for the CPU.

[0137] As introduced above, the bus switching network can associate and record the forwarding path to the bus device and the identifier of the bus device in the announcement message during the process of receiving and broadcasting the announcement messages of the bus devices connected thereto. Similarly, in some examples, the bus controller can send its own announcement message to the first port of the bus switching network. The announcement message of the bus controller includes the device information of the bus controller, and the device information of the bus controller indicates that its device type is a bus controller. The bus switching network can record the forwarding path to the bus controller during the process of receiving and broadcasting the announcement message of the bus controller. After that, the bus switching network can forward the message sent to the bus controller according to the forwarding path, so that it is beneficial to save forwarding resources and improve the security of the message.

[0138] Figure 3 In the corresponding method example, taking the bus switching network forwarding the announcement message of the CPU by broadcasting as an example in S302, the present application does not limit the way for the bus switching network to forward the announcement message of the CPU.

[0139] Optionally, the bus switch can obtain and record multiple forwarding paths to the bus controller to determine some forwarding paths (such as the forwarding path with the minimum delay), and then send the message sent to the bus controller to the port located on the forwarding path. When there are multiple forwarding paths with the minimum delay, the bus switch can forward the message sent to the bus controller according to one or more of the forwarding paths. The possible ways for the bus switch to obtain multiple forwarding paths to the bus controller will be introduced later.

[0140] Optionally, after receiving the announcement message of the CPU, the bus switch in the bus switching network can add the information of the forwarding path of the bus switch to it in the announcement message of the CPU, and then forward the announcement message according to the forwarding path. In this way, the bus controller can determine the forwarding path through which the announcement message passes in the bus switching network according to the information of the forwarding path in the received announcement message.

[0141] For example, after receiving the announcement message from the CPU on its own port 1, the bus switch 1 can add the information of the forwarding path from its own port 1 to its own port 2 to the announcement message, and then send the announcement message with the added forwarding path information to its own port 2. Table 3 schematically shows this announcement message with the added forwarding path information. The contents of the first two rows in Table 3 can be understood by referring to the announcement message sent by the CPU shown in Table 1. The content of the third row in Table 3 is used to indicate the information (i.e., the information of the forwarding path) for the bus switch 1 to forward the announcement message or the device information therein. As shown in Table 3, the information of the forwarding path may include the device information of the bus switch, the information of the receiving port, and the information of the sending port. As described in Table 3, the information of the forwarding path can indicate that the bus switch 1 receives the announcement message sent by the CPU from its own port 1, and forwards the announcement message through its own port 2. The device information of the bus switch 1 may include the identifier of the bus switch 1. The present application does not limit the specific content of the identifier of the bus switch 1, as long as the identifier of the bus switch 1 can be used to uniquely identify the bus switch 1 in the bus network or the bus switching network. For example, the identifier of the bus switch 1 may include at least one of its device type, manufacturer identification (ID), and device ID. When the storage space of the bus switch can be directly accessed by other bus devices in the bus network, the device information of the bus switch can be understood by referring to the content of the device information of the CPU. For example, the device information of the bus switch may further include the size of the address space required by the bus switch.

[0142] Table 3

[0143]

[0144] For example, after receiving the announcement message of the CPU forwarded by the bus switch 1 on its own port 1, the bus switch 5 can add the information of the forwarding path from its own port 1 to its own port 3 to the announcement message, and then send the announcement message with the added forwarding path information to its own port 3. Table 4 schematically shows this announcement message with the added forwarding path information. The contents of the first three rows in Table 4 can be understood by referring to the announcement message of the CPU sent by the bus switch 1 to its own port 2 shown in Table 3. The content of the fourth row in Table 4 is used to indicate that the bus switch 5 receives the announcement message from its own port 1, and forwards the announcement message through its own port 3. The device information of the bus switch 5 can be understood by referring to the identifier of the bus switch 1 introduced above.

[0145] Table 4

[0146]

[0147] After receiving the advertisement message shown in Table 4 from port 3 of bus switch 5, the bus controller can determine that the third and fourth rows of Table 4 are the information of the forwarding paths added by the bus switching network to the advertisement message. According to the content of the third and fourth rows in Table 4, it can be determined that the CPU is connected to port 1 of bus switch 1, and itself is connected to port 3 of bus switch 5. Moreover, the forwarding path that the CPU's advertisement message passes through in the bus switching network is from port 1 of bus switch 1, sequentially through port 2 of bus switch 1 and port 1 of bus switch 5, to reach port 3 of bus switch 5.

[0148] As introduced above, the bus switching network can forward the CPU's advertisement message in a broadcast manner. Therefore, the bus switching network can forward the CPU's advertisement message to the bus controller through different multiple forwarding paths, and the information of the forwarding paths in the advertisement messages forwarded through different forwarding paths can be different. In this way, the bus controller can determine multiple forwarding paths between the CPU and itself by receiving the CPU's advertisement messages forwarded through different multiple forwarding paths.

[0149] Similarly, the bus switches in the bus switching network can add the information of the forwarding paths to the advertisement messages of other bus devices (such as network cards and memories) being forwarded. In this way, the bus controller can respectively determine multiple forwarding paths between the network card and itself and multiple forwarding paths between the memory and itself.

[0150] Optionally, the bus controller can determine Figure 2 the network topology of the shown bus network based on the respective forwarding paths between the CPU, network card, and memory and itself (i.e., the bus controller). In this way, it is beneficial for the bus controller to manage the bus network more accurately and efficiently.

[0151] Optionally, the bus switches in the bus switching network can record the respective forwarding paths to the bus device according to the information of the forwarding paths in the advertisement messages of the bus devices. This is beneficial for the bus switches to record multiple forwarding paths to each bus device after broadcasting the advertisement messages of the CPU, network card, and memory respectively, and further beneficial for the bus switches to forward messages (such as configuration messages) to each bus device according to the optimal forwarding path (such as the forwarding path with the minimum delay).

[0152] Optionally, after receiving the announcement message from the bus controller, the bus switch in the bus switching network can add information about its forwarding path to the announcement message, and then forward the announcement message according to the forwarding path. As introduced above, the bus switching network can forward the announcement message of the bus controller by broadcasting. Therefore, the bus switches in the bus switching network can receive the announcement messages of the bus controller forwarded from different multiple forwarding paths, and record multiple forwarding paths to the bus controller according to the information of the forwarding paths in the announcement messages of the bus controller. This is beneficial for the bus switch to record multiple forwarding paths to each bus controller after broadcasting the announcement message of the bus controller, and further beneficial for the bus switch to forward messages (such as the announcement message of the newly added bus device and / or the withdrawal announcement message of the bus device introduced later) to the bus controller according to the optimal forwarding path (for example, the forwarding path with the minimum delay).

[0153] After determining multiple forwarding paths to each bus device connected to it, the bus switch in the bus switching network can determine the network topology of the bus network (for example Figure 2 as shown). This is beneficial for the bus controller to forward messages more accurately and efficiently.

[0154] Based on the fact that the bus switch records the network topology of the bus network or the forwarding path to the bus device, when receiving the configuration message of the bus device sent by the bus controller, the bus switch can associate and record the information of the bus device in the network topology or the forwarding path with the address information of the address space of the bus device. This is beneficial for the bus switch to route the message according to the forwarding path to the bus device when receiving the message accessing the address space later.

[0155] Optionally, the bus switch in the bus switching network can also send its own announcement message, and the announcement message of the bus switch can include the device information of the bus switch. And, after receiving the announcement message sent by other bus switches, the bus switch in the bus switching network can forward the announcement message by broadcasting.

[0156] As introduced above, each bus device in the bus network can send its own announcement message. In addition to sending its own announcement message, the bus switch can also forward the announcement messages of other bus devices received by broadcasting, and add the information of the forwarding path to the forwarded announcement message.

[0157] In a possible implementation, after receiving multiple announcement messages, the bus switch can broadcast each of the multiple announcement messages separately. Alternatively, in a possible implementation, after receiving multiple announcement messages, the bus switch can broadcast the multiple announcement messages after merging or aggregating them. In this way, it not only helps reduce the number of times the bus controller receives announcement messages and reduces its load, but also helps reduce the repeated transmission of the same information and saves the transmission resources of the bus network.

[0158] This application does not limit the way the bus switch obtains the aggregated announcement messages. For example, when the device type of the peer device is a bus terminal and does not include a bus switch, after the bus switch receives the device information of the peer device, it can determine that there is no need to receive the device information of other bus devices from the peer device. When the device type of the peer device includes a bus switch, after the bus switch receives the device information of the peer device, it can also wait to receive the device information of other bus devices from the peer device. Then, the bus switch can aggregate the device information of multiple bus devices received (for example, encapsulate them in the same message).

[0159] After the bus switch 1 separately receives the announcement messages from the CPU and the network card, it can send the merged announcement messages to its port 2 and port 4 respectively. Table 5 schematically shows the content of the merged announcement message sent by the bus switch 1 to its port 2. The first row in Table 5 respectively represents the device information of the bus switch 1, the port on the bus switch 1 that received the announcement message, and the port on the bus switch 1 that sent the merged announcement message. The second and third rows in Table 5 represent the content in the announcement message sent by the CPU to port 1 (for example, the device information of the CPU), and the fourth and fifth rows in Table 5 represent the content in the announcement message sent by the network card to port 3 (for example, the device information of the network card).

[0160] Table 5

[0161]

[0162] Similarly, the bus switch 5 can also receive and combine the combined announcement messages sent by the bus switches 2, 3, and 4 respectively. The combined announcement message sent by the bus switch can include the content (such as device information) in the announcement messages of each bus terminal connected under the bus switch. The bus switch 5 can send the combined announcement message to its port 3. Table 6 schematically shows the combined announcement message sent by the bus switch 5 to its port 3. The meaning of the first row in Table 6 can be understood by referring to the meaning of the first row in Table 5. The second row in Table 6 represents the content of the announcement message received by the bus switch 5 from its port 1, that is, the content in the combined announcement message sent by the bus switch 1 to its port 2 (i.e., the content in Table 5). The third row in Table 6 represents the content of the announcement message received by the bus switch 5 from its port 2, that is, the content in the combined announcement message sent by the bus switch 2 to its port 2 (which can be understood by referring to the content in Table 5). The fourth row in Table 6 represents the content of the announcement message received by the bus switch 5 from its port 5, that is, the content in the combined announcement message sent by the bus switch 3 to its port 4 (which can be understood by referring to the content in Table 5). The fifth row in Table 6 represents the content of the announcement message received by the bus switch 5 from its port 4, that is, the content in the combined announcement message sent by the bus switch 4 to its port 4 (which can be understood by referring to the content in Table 5).

[0163] Table 6

[0164]

[0165] This application does not limit the number of announcement messages combined in a single combined announcement message sent by the bus switch, nor does it limit the timing of the bus switch sending the combined announcement message. For example, the bus switch can first determine the ports connecting the bus terminals and the ports connecting other bus switches. After that, the bus switch can, after collecting the announcement messages of all the connected bus terminals, combine them and then forward them separately to the ports connecting other bus switches. This is beneficial for the bus switch to obtain the announcement messages of each bus terminal in the bus network with a shorter delay. For the ports connecting other bus switches, the bus switch can send the combined announcement message after collecting and combining the announcement messages of all the bus devices in the bus network. In this way, it is beneficial to reduce the number of times the bus terminal receives the announcement message and reduce its load.

[0166] The above tables are only examples, and the announcement message may not include one or more of the fields therein.

[0167] After the above process of broadcast announcement messages, the information of all bus devices in the bus domain can be synchronized to all devices. For example, in a small-scale secure trust environment (such as a supercomputer scenario), all bus devices can obtain the information of other devices, including device type, address space, device capabilities, etc. Optionally, in some scenarios (such as scenarios that require security isolation), the bus switch can determine the forwarding policy according to the type of the bus devices (referred to as peer devices) connected to it. For example, when the device type of the peer device includes a bus switch and / or a bus controller, the bus switch can forward the device information of other bus devices it receives to its peer device, while when the device type of the peer device is a bus terminal and its device type does not include a bus switch and a bus controller, the bus switch can not forward the device information of other bus devices it receives to it. In this way, it is beneficial to improve the security of device information on the basis of ensuring that the bus controller obtains the device information of all bus devices in the bus network.

[0168] The bus controller can be generated through bootstrap election or through designation (for example, designating a bus device with a certain type and / or address as the bus controller). After collecting all device information, the bus controller can form a hierarchical bus topology information table and allocate the address space range of each bus device.

[0169] As introduced above, after the bus switching network records the forwarding path to the bus controller, it can forward the messages sent to the bus controller according to the recorded forwarding path. The following introduces several scenarios where the bus switching network forwards messages to the bus controller according to the forwarding path to the bus controller.

[0170] First, introduce the scenario of adding a new bus device to the bus network. Figure 6 A possible method flow of this scenario is schematically shown. As Figure 6 shown, this method flow may include S601 - S605.

[0171] S601. The SSD sends its announcement message to the third port connected to the bus switching network. Correspondingly, the bus switching network receives the announcement message of the SSD from the third port, where the announcement message includes the device information of the SSD;

[0172] S601 can be understood by referring to S301. For example, the CPU in S301 can be replaced with the SSD, and the second port can be replaced with the third port, etc. As Figure 6 shown, the third port includes port 3 of bus switch 3 and port 1 of bus switch 4. Figure 6It is schematically shown that the SSD sends its announcement message to port 1 of the bus switch 4. Optionally, the SSD can also send its message to port 3 of the bus switch 3.

[0173] S602. The bus switching network forwards the SSD's announcement message to the bus controller along the forwarding path from the third port to the first port. Correspondingly, the bus controller receives the announcement message from the first port.

[0174] The method for the bus switching network to determine the forwarding path to the bus controller was introduced above and will not be elaborated here. The bus switching network can record one or more forwarding paths from the third port to the first port and can forward the SSD's announcement message respectively according to all or a part of these forwarding paths. Figure 6 It is schematically shown a forwarding path from port 1 of the bus switch 4 to port 3 of the bus switch 6. As an example, the bus switching network can forward the SSD's announcement message to the bus controller according to this forwarding path.

[0175] Optionally, based on that the bus switch can add the information of the forwarding path in the forwarded announcement message, the bus controller and / or the bus switching network can add the information of the SSD in the network topology of the bus network according to the information of the forwarding path in the SSD's announcement message. In the updated network topology, a new node is added at the location where the SSD is located (i.e., the location connecting port 3 of the bus switch 3 and port 1 of the bus switch 4 respectively), and this node is the SSD.

[0176] S603. The bus controller assigns an address space 4 to the SSD according to the device information of the SSD in the announcement message.

[0177] Suppose the manufacturer ID and device ID of the SSD are D4 and V4 respectively, and the address space assigned by the bus controller to the SSD is address space 4 in the global address space. The size of the address space required by the SSD is not limited in this application.

[0178] S603 can be understood by referring to S303. For example, the CPU in S303 can be replaced with the SSD, the address space 1 can be replaced with the address space 4, and the identifier "CPU, D1, V1" of the CPU can be replaced with the identifier "SSD, D4, V4" of the SSD, etc.

[0179] S604. The bus controller sends a configuration message 4 to the SSD through the bus switching network. Correspondingly, the SSD receives the configuration message 4 through the bus switching network, where the configuration message 4 includes the address information used to describe the address space 4.

[0180] S604 can be understood with reference to S304. For example, the CPU in S304 can be replaced with an SSD, address space 1 can be replaced with address space 4, the identifier of the CPU, "CPU, D1, V1", can be replaced with the identifier of the SSD, "SSD, D4, V4", configuration message 1 can be replaced with configuration message 4, etc.

[0181] Referring to the forwarding method introduced in S304, the bus switching network can forward configuration message 4 along all or part of the forwarding path to the SSD. Figure 6 Schematically showing a forwarding path from port 3 of bus switch 6 to port 1 of bus switch 4, as an example, the bus switching network can forward configuration message 4 to the SSD along this forwarding path.

[0182] S605. The SSD maps its storage space 4 to address space 4 according to the indication of configuration message 4.

[0183] Referring to the configuration method introduced in S305, the SSD can configure its configuration space according to the indication of configuration message 4. For example, the SSD can map its storage space 4 to address space 4, which is beneficial for other bus devices in the bus network to directly address the storage space 4 of the SSD according to address space 4, read data from the storage space 4 and / or write data to the storage space 4.

[0184] and Figure 3 different from the method flow introduced, Figure 6 In the method flow introduced, after receiving the announcement message of the newly added bus device, the bus switching network can forward the announcement message along the forwarding path to the bus controller, which is beneficial for saving forwarding resources and improving the security of the announcement message. The newly added bus device can refer to a bus device newly connected to the bus switching network after the forwarding path to the bus controller is recorded in the bus switching network, or can refer to a bus device newly connected to the bus switching network after the bus network is initialized. The initialization of the bus network can refer to that the bus controller has experienced a preset time period after startup, or no announcement message of the bus device is received within the preset time period, etc. Before the bus network is initialized, the bus switching network generally can record the forwarding path to the bus controller.

[0185] Optionally, after receiving the announcement message of the newly added bus device, the bus switching network can forward the announcement message by broadcasting.

[0186] The following introduces the scenario where the bus network deletes a bus device. Figure 7 Schematically showing a possible method flow of this scenario. As Figure 7 shown, this method flow can include S701 to S705.

[0187] S701. The SSD sends its exit notice message to the third port. Correspondingly, the bus switching network receives the SSD's exit notice message from the third port. The exit notice message is used to indicate that the SSD will exit the bus network.

[0188] When the SSD is about to exit the bus network, for example, when the SSD receives an exit instruction from the user, the SSD can send its exit notice message to the third port of the connected bus switching network. Correspondingly, the bus switching network receives the SSD's exit notice message from the third port. The exit notice message is used to indicate that the SSD will exit the bus network.

[0189] Figure 7 Schematically shows the SSD sending its exit notice message to port 1 of bus switch 4. Optionally, the SSD can also send its exit notice message to port 3 of bus switch 3.

[0190] S702. The bus switching network forwards the SSD's exit notice message to the bus controller along the forwarding path from the third port to the first port. Correspondingly, the bus controller receives the SSD's exit notice message from the first port.

[0191] The method for the bus switching network to determine the forwarding path to the bus controller was introduced earlier and will not be elaborated here. The bus switching network can record one or more forwarding paths from the third port to the first port and can forward the SSD's exit notice message respectively according to all or part of these forwarding paths. Figure 7 Schematically shows a forwarding path from port 1 of bus switch 4 to port 3 of bus switch 6. As an example, the bus switching network can forward the SSD's exit notice message to the bus controller along this forwarding path.

[0192] S703. The bus controller reclaims the address space 4 allocated to the SSD according to the SSD's exit notice message.

[0193] After receiving the SSD's exit notice message, the bus controller can cancel the SSD according to the SSD's exit notice message. For example, the bus controller can reclaim the address space 4 allocated to the SSD. And / or, the bus controller can cancel or delete the information of the SSD in the network topology of the bus network. The updated network topology indicates that the node location where the SSD is located is empty or there is no bus device.

[0194] S704. The bus controller sends a cancellation confirmation message to the SSD through the bus switching network. Correspondingly, the SSD receives the cancellation confirmation message through the bus switching network. The cancellation confirmation message is used to indicate that the bus controller has reclaimed the address space allocated to the SSD.

[0195] Referring to the forwarding method introduced in S304, the bus switching network can forward the cancellation confirmation message along all or a part of the forwarding path to the SSD. Figure 7 Schematically showing a forwarding path from port 3 of bus switch 6 to port 1 of bus switch 4. As an example, the bus switching network can forward the cancellation confirmation message to the SSD along this forwarding path.

[0196] S705. The SSD completes cancellation according to the cancellation confirmation message.

[0197] After receiving the cancellation confirmation message, the SSD can determine that the bus controller has successfully received its exit notification message. After that, the SSD can continue to complete the cancellation and move out of the bus network. For example, the SSD can delete registration information such as the address space configured by the device, and / or disconnect the connections with port 3 of bus switch 3 and port 1 of bus switch 4 respectively.

[0198] Optionally, after receiving the cancellation confirmation message, the SSD can send a cancellation completion notification message to the bus controller through the bus switching network to notify the bus controller that it has successfully received the cancellation confirmation message and completed the cancellation.

[0199] This application does not limit the type of the bus. For example, the bus can be a PCIe bus. With the development of public cloud services, the ability to have different resource combinations is required. Therefore, the bus can also be a CXL bus or an NVLINK bus, etc.

[0200] This application does not limit the number of bus devices in the bus network, nor the type of bus devices. For example, the bus devices in the bus network can include at least one of multiple types such as CPU, memory, network card, SSD, graphics processing unit (GPU), neural network processing unit (NPU), bus switch, and field-programmable gate array (FPGA). The bus switch mentioned in this application can be replaced by other types of bus devices with forwarding functions.

[0201] The device notification information introduced above can refer to one or more notification messages or all or part of the information in one or more notification messages. Optionally, the bus switching network forwarding the notification message actively sent by the bus device can refer to the bus switching network forwarding a part of the information in the notification message (such as the device information of the bus device). The path information introduced above can include the information of the forwarding path introduced above.

[0202] Regarding the above method embodiments, it should be noted that:

[0203] (1) The step numbers in each flowchart described in the embodiments are only examples of the execution process and do not constitute a limitation on the order of step execution. In the embodiments of the present application, there is no strict execution order between steps that have no temporal dependence on each other. In addition, not all the steps shown in each flowchart are steps that must be executed, and some steps can be added or deleted based on the actual needs on the basis of each flowchart.

[0204] (2) In each embodiment of the present application, if there is no special description and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be mutually referred to. The technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0205] The above details the method provided by the embodiments of the present application. Next, the devices and chip systems provided by the embodiments of the present application will be described in detail. It should be understood that the description of the device embodiments corresponds to the description of the method embodiments. Therefore, the content not described in detail can be referred to the above method embodiments. For the sake of brevity, it will not be repeated here.

[0206] As mentioned above, the bus controller can be a bus device or a device deployed on a bus device. The above method mainly introduces from the perspective of the interaction between the bus controller, the bus terminal, and the bus switch. It can be understood that in order to implement the above functions, any bus device includes the corresponding hardware structure and / or software module for executing each function. In order to implement the functions in the above embodiments, the bus controller, the bus terminal, and the bus switch respectively include the corresponding hardware structure and / or software module for executing each function. Those skilled in the art should easily realize that, combined with the units and method steps of each example described in the embodiments disclosed in the present application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application scenario and design constraint conditions of the technical solution.

[0207] Figure 8 This is a structural example diagram of the bus controller provided by the present application. As Figure 8 shown, the bus controller includes: a transceiver module, configured to receive the advertisement message broadcast by the bus switching network; a processing module, which executes S303; and the transceiver module, which also executes S304.

[0208] Optionally, the transceiver module is further configured to execute one or more steps among S306 to S311.

[0209] Optionally, the processing module is further configured to execute S603, and the transceiver module is further configured to execute S604.

[0210] Optionally, the processing module is further configured to execute S703, and the transceiver module is further configured to execute S704.

[0211] Among them, both the transceiver module and the processing module can be implemented by software or by hardware. Exemplarily, next, taking the transceiver module as an example, the implementation manner of the transceiver module will be introduced. Similarly, the implementation manner of the processing module can refer to the implementation manner of the transceiver module.

[0212] As an example of a software functional unit, the transceiver module may include code running on a computing instance. Among them, the computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Further, the above computing instance may be one or more. For example, the transceiver module may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers for running the code may be distributed in the same area or in different areas. Further, the multiple hosts / virtual machines / containers for running the code may be distributed in the same availability zone or in different availability zones, and each availability zone includes one data center or multiple geographically proximate data centers. Among them, generally one area may include multiple availability zones.

[0213] As an example of a hardware functional unit, the transceiver module may include at least one computing device, such as a server, etc. Alternatively, the transceiver module may also be a device implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). Among them, the above PLD may be implemented by a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0214] It should be noted that in other embodiments, the transceiver module may be configured to execute any step in the method of the embodiments of the present application, and the processing module may be configured to execute any step in the method of the embodiments of the present application. The steps to be implemented by the transceiver module and the processing module can be specified as needed, and all functions of the bus controller are implemented by separately implementing different steps in the method of the embodiments of the present application through the transceiver module and the processing module.

[0215] Please refer to Figure 9 , Figure 9This is a schematic structural diagram of a bus device provided by an embodiment of the present application. As Figure 9 shown, the bus device 9 includes: a processor 901, a memory 902, a communication interface 903, and a bus 904. The processor 901, the memory 902, and the communication interface 903 are coupled through a bus (not labeled in the figure). The memory 902 stores instructions. When the execution instructions in the memory 902 are executed, the bus device 9 executes the methods performed by the bus controller, the bus switch, or the bus terminal (such as a CPU or an SSD) in the above method embodiments.

[0216] The bus device 9 may be one or more integrated circuits configured to implement the above methods. For example: one or more application specific integrated circuits (ASICs), or, one or more digital signal processors (DSPs), or, one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms. Again, when the units in the device can be implemented in the form of a processing element scheduler, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call programs. Again, these units may be integrated together to be implemented in the form of a system-on-a-chip (SOC).

[0217] The processor 901 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0218] The memory 902 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0219] Executable program code is stored in the memory 902, and the processor 901 executes the executable program code to respectively implement the functions of the methods executed by the foregoing bus controller or bus switch or bus terminal (such as a CPU or an SSD), thereby implementing the above-mentioned device management method based on the bus technology. That is to say, instructions for executing the above management method are stored on the memory 902.

[0220] The communication interface 903 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the bus device 9 and other devices.

[0221] In addition to including a data bus, the bus 904 may further include a power bus, a control bus, a status signal bus, etc. The bus may be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus may be divided into an address bus, a data bus, a control bus, etc.

[0222] It should be understood that the specific processes for each module to execute the corresponding steps have been described in detail in the above method embodiments. For the sake of brevity, they will not be elaborated here.

[0223] The embodiments of the present application further provide a computer-readable storage medium, on which computer instructions for implementing the methods executed by the bus controller, the bus switch, or the bus terminal (such as a CPU or an SSD) in the above method embodiments are stored. For example, when the computer program is executed by a computer, the computer can implement the methods executed by the corresponding devices in the above method embodiments.

[0224] The embodiments of the present application further provide a computer program product, including instructions, which when executed by a computer, implement the methods executed by the bus controller, the bus switch, or the bus terminal (such as a CPU or an SSD) in the above method embodiments.

[0225] The explanations and beneficial effects of the relevant content in any of the above provided devices can refer to the corresponding method embodiments provided above, and will not be elaborated here.

[0226] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed couplings or direct couplings or communication connections to each other may be through some interfaces. The indirect couplings or communication connections of the devices or units may be in electrical, mechanical or other forms.

[0227] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD), etc.). For example, the foregoing available media include, but are not limited to: USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs and other media that can store program codes.

[0228] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A device management method based on bus technology, characterized in that The method is applied to a bus controller that operates in a bus network. The bus network includes a plurality of bus devices interconnected by a bus. The method includes: Receiving device announcement information, where the device announcement information includes device information of the first bus device, and the device information of the first bus device is actively sent by the first bus device to the bus controller after power-on; Allocating an address space of the bus to the first bus device according to the device information of the first bus device; Sending configuration information to the first bus device, where the configuration information includes address information for describing the address space.

2. The method according to claim 1, wherein The device information of the first bus device is forwarded to the bus controller via one or more bus devices in the bus network after being sent from the first bus device.

3. The method according to claim 2, wherein The device announcement information further includes path information, where the path information is used to indicate information about the forwarding of the device information of the first bus device through one or more bus devices. The method further includes: Determining a forwarding path of the device announcement information between the first bus device and the bus controller according to the path information.

4. The method according to claim 3, characterized in that, When the device information of the first bus device is forwarded to the bus controller via a plurality of bus devices in the bus network, the receiving of the device announcement information includes: Receiving a plurality of device announcement information respectively, where the device information of the first bus device in the plurality of device announcement information is via different forwarding paths; Determining a plurality of forwarding paths according to the path information in each device announcement information in the plurality of device announcement information.

5. The method according to claim 4, characterized in that, The sending of the configuration information to the first bus device includes: Determining a target forwarding path according to the plurality of forwarding paths, and sending the configuration information to the first bus device through the target forwarding path.

6. The method according to any one of claims 2-5, characterized in that, The method further includes: Sending device information of the bus controller to at least one bus device connected to the bus controller, where the device information of the bus controller is used to instruct the at least one bus device to record information about the port for connecting to the bus controller.

7. The method according to claim 6, characterized in that The method further includes: Receiving device information of a second bus device in the bus network, where the device information of the second bus device is actively sent by the second bus device to the bus controller after power-on, and the device information of the second bus device is forwarded by the at least one bus device according to the information about the port of the bus controller.

8. The method according to claim 6 or 7, characterized in that, The method further includes: Receiving status announcement information of the first bus device, where the status announcement information of the first bus device is used to indicate that the first bus device will exit the bus network or is still connected to the bus network, and the status announcement information of the first bus device is forwarded by the at least one bus device according to the recorded information about the port for connecting to the bus controller; Determining the connection status of the first bus device in the bus network according to the status announcement information of the first bus device.

9. The method according to any one of claims 2-8, characterized in that, The device type of the bus device that forwards the device information of the first bus device in the bus network includes a bus switch.

10. The method according to any one of claims 1-9, characterized in that, The device information of the first bus device includes the identifier of the first bus device, and the identifier of the first bus device includes at least one of the device type of the first bus device, the manufacturer identifier of the first bus device, and the device identifier of the first bus device.

11. The method according to any one of claims 1-10, characterized in that, The device information of the first bus device includes the size of the address space required by the first bus device.

12. The method according to any one of claims 1-11, characterized in that, The multiple bus devices are arranged in at least two computer devices.

13. A device management method based on bus technology, characterized in that, A bus network includes multiple bus devices interconnected by a bus, and a bus controller operates in the bus network. The method includes: After power-on, the first bus device in the bus network actively sends the device information of the first bus device; The bus controller receives device announcement information, and the device announcement information includes the device information of the first bus device; The bus controller allocates the address space of the bus to the first bus device according to the device information of the first bus device, and sends configuration information to the first bus device. The configuration information includes address information for describing the address space; The first bus device receives the configuration information, and maps all or part of its storage space to the address space described by the address information according to the indication of the configuration information.

14. The method according to claim 13, wherein The device information of the first bus device is forwarded from the first bus device and then forwarded to the bus controller via one or more bus devices in the bus network.

15. The method according to claim 14, wherein The method further includes: After receiving the device information of the first bus device, the bus device connecting the first bus device in the bus network forwards the device information of the first bus device and path information. The path information is used to indicate the information that the device information of the first bus device is forwarded through one or more bus devices.

16. The method according to claim 14 or 15, characterized in that, The method further includes: After receiving the device information of the first bus device, the bus device connecting the first bus device in the bus network forwards it in a broadcast manner.

17. The method according to any one of claims 14 - 16, characterized in that, The method further includes: The bus controller sends its own device information to at least one bus device connected to itself; The at least one bus device records the information for connecting to the port of the bus controller according to the indication of the device information of the bus controller.

18. The method according to claim 17, wherein The method further includes: After power-on, the second bus device in the bus network actively sends its own device information to the bus controller; The at least one bus device forwards the device information of the second bus device to the bus controller according to the information of the port of the bus controller; The bus controller receives the device information of the second bus device.

19. The method according to claim 17 or 18, characterized in that The method further includes: The first bus device sends its own status announcement information to the bus controller. The status announcement information is used to indicate that the first bus device will exit the bus network or remain connected to the bus network; The at least one bus device forwards the status announcement information to the bus controller according to the information of the port of the bus controller; The bus controller receives the status notification information and determines the connection status of the first bus device in the bus network according to the status notification information.

20. A bus controller, characterized in that, The bus controller operates in a bus network, the bus network includes a plurality of bus devices interconnected by a bus, and the bus controller includes: a transceiver module, configured to receive device notification information, the device notification information includes device information of the first bus device, and the device information of the first bus device is actively sent by the first bus device to the bus controller after power-on; a processing module, configured to allocate an address space of the bus to the first bus device according to the device information of the first bus device; The transceiver module is further configured to send configuration information to the first bus device, and the configuration information includes address information for describing the address space.

21. A bus device, characterized in that, The bus device includes a processor and a bus interface, and the processor is configured to execute the method according to any one of claims 1-12 based on instructions stored in a memory.

22. A cluster of computing devices, characterized in that, The computing device cluster includes at least one computing device, and each computing device in the at least one computing device includes one or more bus devices, and the one or more bus devices are connected to the bus device according to claim 21.

23. A bus network, characterized in that, The bus network includes a plurality of bus devices interconnected by a bus, and a bus controller operates in the bus network, and the bus controller is configured to execute the method according to any one of claims 1 to 12.

24. A computer program product, characterized in that, including computer-readable instructions, when the computer-readable instructions run on a computer, causing the computer to execute the method according to any one of claims 1 to 12.

25. A computer-readable storage medium, characterized in that, Instructions are stored in the computer-readable storage medium, and when the instructions run on a computer, causing the computer to execute the method according to any one of claims 1 to 12.

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