High-speed implementation structure of JPEG2000 encoder

Abstract

The invention relates to the technical field of image compression encoding, in particular to a high-speed implementation structure of a JPEG2000 encoder. Comprising a data reading and preprocessing module, a level shift module, a wavelet transform module, a data partitioning module, a data processing preparation module, a plurality of bit plane parallel coding modules, a bit plane coding result combination module, an MQ coding module, a Tier2 coding module and a data storage module. The method has high-speed compression performance, a JPEG2000 compression algorithm is realized by adopting the FPGA, and the characteristic that the FPGA can be operated in parallel is fully utilized; efficient module cooperation is achieved, all the modules are tightly matched, and the operation efficiency of the whole system is improved; the system adapts to images with different resolutions, and parameters and processing flows of the modules can be flexibly adjusted according to characteristics of the images with different resolutions; and the expansibility is high, the test pins are reserved on the design strategy, the function expansion can be completed by utilizing the reserved pins, and the adaptability and upgradability of the system are enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of image compression coding, and particularly to a high-speed implementation structure of a JPEG2000 encoder. Background Art

[0002] In the current era of rapid development of digital information, the storage and transmission requirements of image data are increasing day by day. As an advanced image compression standard, JPEG2000 has been widely used in many fields because it can provide a high compression ratio, good image quality, and various flexible features, such as resolution scalability, quality scalability, etc. However, traditional JPEG2000 encoders face many challenges in the implementation process, especially in terms of compression speed, and it is difficult to meet some application scenarios with extremely high real-time requirements, such as high-speed video surveillance, rapid medical image processing, etc.

[0003] Some existing encoders adopt software implementation methods, and the JPEG2000 algorithm is executed by a general-purpose processor. Although this method has a certain degree of flexibility, due to the sequential execution characteristics of the processor, the parallelism in the algorithm cannot be fully utilized, resulting in slow compression speed. And some hardware-based implementation schemes, although the speed is improved to a certain extent, there are deficiencies in the structural design, such as low cooperation efficiency between modules and insufficient optimization of the data processing flow, etc., and still cannot achieve the ideal high-speed compression effect. In addition, when dealing with images of different resolutions, traditional encoders often have difficulty maintaining stable high-speed compression performance while maintaining high compression quality.

[0004] Therefore, those skilled in the art have provided a high-speed implementation structure of a JPEG2000 encoder to solve the problems raised in the above background art. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a high-speed implementation structure of a JPEG2000 encoder to solve the problems that the existing JPEG2000 encoder has a slow compression speed, cannot meet the real-time requirements, and it is difficult to balance compression quality and speed at different resolutions. [[ID=2…]]

[0006] It includes

[0007] Data reading and preprocessing module: used to read the original image data from an external storage device, extract pixel information by embedded linux, divide the image data into 256*256 data blocks and transfer them to the input buffer of the FPGA through direct memory;

[0008] Level shift module: for the input unsigned pixel values, first perform DC potential translation to become signed values;

[0009] Wavelet transform module: Implement octave wavelet decomposition using the two-dimensional discrete wavelet transform algorithm to convert image data into wavelet coefficients;

[0010] Data block module: Organize the wavelet coefficients after wavelet transform in the data format of 4*8 for subsequent ebcode encoding;

[0011] Data processing preparation module: When preparing for encoding, calculate S1 and S2 and the highest bit plane in advance, and divide the input encoded matrix into a sign matrix and an absolute value matrix;

[0012] Multiple bit-plane parallel encoding module: After the wavelet coefficients are divided into independent code blocks, the quantized coefficients in the code blocks are organized into several bit planes. Bit-plane encoding is performed sequentially from the most significant bit plane to the least significant bit plane;

[0013] Bit-plane encoding result combination module: Write the D and CX output from each bit plane after multiple bit-plane parallel encoding into a total D and CX in the order from the most significant bit plane to the least significant bit plane;

[0014] MQ encoding module: Receive the context CX and the encoded bit symbol D output from the bit-plane encoding result combination module, and output the compressed code stream CD using the adaptive binary arithmetic coding algorithm;

[0015] Tier2 encoding module: Organize the compressed code stream output from the MQ encoding module in layers according to the rate-distortion optimal principle, select an appropriate truncation point to truncate the code block compressed code stream, and compress the code stream into a final code stream with scalable resolution and quality;

[0016] Data storage module: Transmit the final compressed code stream output from the Tier2 encoding module to an external storage device for storage through direct memory.

[0017] Preferably, the data reading and preprocessing module, level shift module, wavelet transform module, data block module, data processing preparation module, multiple bit-plane parallel encoding module, bit-plane encoding result combination module, MQ encoding module, Tier2 encoding module, and data storage module work together in sequence to achieve high-speed compression and storage of image data.

[0018] Preferably, when the FPGA implements the functions of each module, it makes full use of its characteristics of parallel operation to improve the compression speed.

[0019] Preferably, test pins are reserved in the design of this structure, and the unused FPGA pins are led out for testing and function expansion.

[0020] Preferably, the wavelet transform module uses a 5-level lifting wavelet transform algorithm.

[0021] Preferably, within each bit plane, scans of the "importance propagation channel", "amplitude refinement channel", and "cleaning channel" are sequentially performed.

[0022] Preferably, the "importance propagation channel", "amplitude refinement channel", and "cleaning channel" non-repetitively divide the original bit plane, ensuring that each coefficient bit on the original bit plane can and can only be encoded in one of the encoding channels, and each encoding channel contains one or more encoding primitives.

[0023] Technical effects and advantages of the present invention:

[0024] High-speed compression performance: By implementing the JPEG2000 compression algorithm using FPGA, the characteristics of parallel operation of FPGA are fully utilized; multiple bit plane parallel encoding modules can encode multiple bit planes simultaneously, greatly improving the encoding speed, enabling the overall compression speed to reach 10 frames per second or even higher (for example, up to 3000 frames / second for 256x256 resolution images), meeting the requirements of application scenarios with extremely high real-time requirements.

[0025] Efficient module cooperation: Each module cooperates closely. The data reading and preprocessing module provides preprocessed image data for subsequent modules. The wavelet transform module, data block division and preparation module, multiple bit plane parallel encoding modules, bit plane encoding result combination module, MQ encoding module, and Tier2 encoding module process the data in sequence. Each module is optimized for its own function design, and the data transmission between modules is efficient and orderly, greatly improving the operating efficiency of the overall system.

[0026] Adaptable to different resolution images: Whether it is a high-resolution 4096*4096 image or a low-resolution 256*256 image, the encoder structure of the present invention can achieve high-speed compression while ensuring high compression quality through reasonable data block division, transformation, and encoding methods; for 4096*4096 resolution images, the compression speed can still reach 11 frames / second, and it can flexibly adjust the parameters and processing flow of each module according to the characteristics of different resolution images to ensure good performance in different scenarios.

[0027] Strong scalability: In the design strategy, test pins are reserved and unused FPGA pins are led out; this not only facilitates leading out the signals to be tested through the reserved pins for system debugging and performance detection when testing is required, but also enables function expansion using the reserved pins when function expansion is needed, enhancing the adaptability and upgradability of the system. Description of the Drawings

[0028] Figure 1It is the overall framework block diagram of a high-speed implementation structure of a JPEG2000 encoder provided by an embodiment of the present application;

[0029] Figure 2 It is the sub-band distribution schematic diagram of the wavelet transform module in the high-speed implementation structure of a JPEG2000 encoder provided by an embodiment of the present application;

[0030] Figure 3 It is the 8*8 matrix division diagram of the 48 data block division in the high-speed implementation structure of a JPEG2000 encoder provided by an embodiment of the present application;

[0031] Figure 4 It is the 16*16 matrix division diagram of the 48 data block division in the high-speed implementation structure of a JPEG2000 encoder provided by an embodiment of the present application;

[0032] Figure 5 It is the 32*32 matrix division diagram of the 48 data block division in the high-speed implementation structure of a JPEG2000 encoder provided by an embodiment of the present application;

[0033] Figure 6 It is the input-output schematic diagram of the MQ arithmetic encoder in the high-speed implementation structure of a JPEG2000 encoder provided by an embodiment of the present application; Detailed implementation manners

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. The embodiments of the present invention are given for the purpose of illustration and description, and are not exhaustive or limit the present invention to the disclosed form. Many modifications and variations are obvious to those of ordinary skill in the art. The embodiments are selected and described to better illustrate the principles and practical applications of the present invention, and enable those of ordinary skill in the art to understand the present invention and thus design various embodiments with various modifications suitable for specific purposes.

[0035] Embodiment 1

[0036] Please refer to Figures 1 to 6 , in this embodiment, a high-speed implementation structure of a JPEG2000 encoder is provided, including the following modules that work together:

[0037] 1. Data reading and preprocessing module: This module is connected to an external storage device (such as an SD card) and is responsible for reading the original image data from the storage device;

[0038] For the read BMP format image, the embedded Linux system first extracts the pixel information. For images with different resolutions, such as 4096×4096 or 256×256, etc., the image data is divided into 256×256 data blocks according to specific rules, and then through the direct memory access (DMA) technology, these data blocks are efficiently transferred to the input buffer (inputbuff) of the FPGA.

[0039] 2. Level shift module: Since wavelet transform requires the dynamic range of image sample data to be centered around 0 approximately, for the input unsigned pixel values, first perform DC potential translation to become signed values, and then they can enter the subsequent transformation and encoding modules.

[0040] 3. Wavelet transform module: Adopt two-dimensional discrete wavelet transform as the core transform algorithm to implement octave wavelet decomposition. The wavelet transform module adopts a 5-level lifting wavelet transform algorithm;

[0041] When performing multi-level wavelet decomposition, only the LL sub-band is further decomposed each time until the specified decomposition level is reached; through the optimized hardware structure design, it can quickly perform two-dimensional discrete wavelet transform on the input image data block, convert the image data into wavelet coefficients, and provide a data basis for the subsequent encoding operation.

[0042] 4. Data block module: This module organizes the wavelet coefficients after wavelet transform in the 4×8 data format for subsequent ebcode encoding.

[0043] 5. Data processing preparation module: When preparing for encoding, calculate S1 and S2 and the highest bit plane in advance, and divide the input encoding matrix into a sign matrix and an absolute value matrix, providing preprocessed data for the multiple bit plane parallel encoding module to improve the encoding efficiency.

[0044] 6. Multiple bit plane parallel encoding module: After the wavelet coefficients are divided into independent code blocks, the quantization coefficients in the code blocks are organized into several bit planes. Bit plane encoding is performed sequentially from the most significant bit plane to the least significant bit plane;

[0045] Since the relevant parameter variables are calculated in advance in the data block and preparation module, this module can implement parallel encoding of multiple bit planes;

[0046] Within each bit plane, scans of the "importance propagation channel", "amplitude refinement channel", and "clear channel" are performed sequentially. These three channels divide the original bit plane without repetition, ensuring that each coefficient bit on the original bit plane can and can only be encoded in one of the encoding channels, and each encoding channel contains one or more encoding primitives, greatly improving the encoding speed.

[0047] 7. Bit-plane coding result combination module: After parallel coding of multiple bit-planes is completed, each bit-plane outputs D and CX;

[0048] This module writes D and CX into a total D and CX in sequence from the D and CX of the highest bit-plane to the D and CX of the lowest bit-plane respectively, as the input of the subsequent MQ coding module, ensuring the orderly transmission and processing of data.

[0049] 8. MQ coding module: Adopts the MQ (Multiple Quantization) arithmetic encoder in the JPEG2000 core coding system, which is an adaptive binary arithmetic encoder. This module receives the context CX and the coded bit symbol D from the bit-plane coding, and outputs the compressed code stream CD after efficient arithmetic coding operations, further improving the data compression degree.

[0050] 9. Tier2 coding module: Hierarchically organizes the compressed code stream output by the MQ coding. According to the principle of rate-distortion optimality, selects appropriate truncation points to truncate the compressed code stream of each code block;

[0051] Under the condition of meeting the target code rate requirement, compresses the code stream into a final code stream with resolution scalability and quality (signal-to-noise ratio) scalability to adapt to different requirements of image quality and data volume in different application scenarios.

[0052] 10. Data storage module: Through the DMA technology, transfers the final compressed code stream output by the Tier2 coding module to an external storage device (such as an SD card) for storage, completing the entire image compression and storage process.

[0053] Its working process is as follows:

[0054] Data reading and preprocessing stage: The original image data in bmp format stored in an external storage device (such as an SD card) is read by the embedded linux system and pixel information is extracted. For images with different resolutions, such as images of 4096*4096, the system divides them into data blocks of 256*256; after division, through the DMA technology, these data blocks are quickly transferred to the input buffer of the FPGA; after the data enters the FPGA, the data reading and preprocessing module performs DC potential translation on the input unsigned pixel values, converting them into signed values, providing a data format that meets the requirements for the subsequent wavelet transform module.

[0055] Wavelet transform stage: The preprocessed data enters the wavelet transform module, which adopts the two-dimensional discrete wavelet transform algorithm to perform octave wavelet decomposition. In this embodiment, a 5-level lifting wavelet transform algorithm is used to perform fast two-dimensional discrete wavelet transform on the input data block. When performing multi-level wavelet decomposition, only the LL sub-band is further decomposed each time until 5-level decomposition is reached. In this way, the image data is converted into wavelet coefficients and output to the data block and preparation module.

[0056] Data block and preparation stage: The wavelet coefficients after wavelet transform enter the data block and preparation module. In this module, the wavelet coefficients are organized in the 4*8 data format for subsequent ebcode encoding. At the same time, S1, S2, and the highest bit plane are calculated in advance, and the input coding matrix is divided into a sign matrix and an absolute value matrix to prepare data for the multiple bit plane parallel encoding module.

[0057] Multiple bit plane parallel encoding stage: The data preprocessed by the data block and preparation module enters the multiple bit plane parallel encoding module. Since the relevant parameter variables have been calculated in advance, this module can perform parallel encoding on multiple bit planes composed of the quantization coefficients in the code block from the most significant bit plane to the least significant bit plane. Within each bit plane, scans of the "importance propagation channel", "amplitude refinement channel", and "cleaning channel" are performed in sequence, and each encoding channel encodes the coefficient bits according to specific encoding primitives, greatly improving the encoding speed.

[0058] Bit plane encoding result combination stage: After the multiple bit plane parallel encoding is completed, each bit plane outputs D and CX. The bit plane encoding result combination module writes D and CX into a total D and CX in sequence from the D and CX of the highest bit plane to the D and CX of the lowest bit plane as the input of the MQ encoding module, ensuring the orderly transmission and processing of data.

[0059] MQ encoding stage: The MQ encoding module receives the context CX and the encoded bit symbol D from the bit plane encoding result combination module, and adopts the adaptive binary arithmetic coding algorithm to perform efficient arithmetic coding operation on the input data, and outputs the compressed code stream CD, further improving the data compression degree.

[0060] Tier2 encoding stage: The compressed code stream output by MQ encoding enters the Tier2 encoding module. This module organizes the compressed code stream in layers according to the rate-distortion optimal principle, and selects appropriate cut-off points to cut off the compressed code stream of each code block. Under the condition of meeting the target code rate requirement, the code stream is compressed into a final code stream with resolvable scalability and quality (signal-to-noise ratio) scalability to adapt to different requirements for image quality and data volume in different application scenarios.

[0061] Data storage stage: The final compressed bitstream output by the Tier2 encoding module is transmitted to an external storage device (such as an SD card) for storage through DMA technology, completing the entire image compression and storage process.

[0062] In practical applications, the high-speed implementation structure of the JPEG2000 encoder of the present invention can play an advantage in various scenarios requiring image compression; for example, in a high-speed video surveillance system, it can quickly compress and store the captured video images, ensuring that more video content can be recorded under limited storage space, while ensuring that the image quality does not affect subsequent analysis and processing. In the field of medical images, for a large number of high-resolution medical images, it can quickly complete compression, facilitating data storage and transmission, and improving the efficiency of medical diagnosis.

[0063] All electrical components appearing in this article are electrically connected to the external main controller and the 220V mains power, and the main controller can be a conventional known device such as a computer for control. The detailed descriptions of known functions and known components are omitted in the specific embodiments of the present disclosure. To ensure the compatibility of the device, the operating means adopted are consistent with the parameters of market instruments.

[0064] Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art and related fields without creative efforts shall fall within the protection scope of the present invention. The structures, devices, and operation methods not specifically described and explained in the present invention, unless otherwise specified and limited, are implemented according to the conventional means in the art.

Claims

1. A high-speed implementation structure of a JPEG2000 encoder, characterized in that, including Data reading and preprocessing module: used to read the original image data from an external storage device, extract pixel information by embedded Linux, divide the image data into 256*256 data blocks and transfer them to the input buffer of the FPGA through direct memory access; Level shift module: for the input unsigned pixel values, first perform a DC potential shift to convert them into signed values; Wavelet transform module: perform octave wavelet decomposition using a two-dimensional discrete wavelet transform algorithm to convert the image data into wavelet coefficients; Data block module: organize the wavelet coefficients after wavelet transform in a 4*8 data format for subsequent ebcode encoding; Data processing preparation module: when preparing for encoding, calculate S1 and S2 and the highest bit plane in advance, and divide the input encoding matrix into a sign matrix and an absolute value matrix; Multiple bit plane parallel encoding module: after the wavelet coefficients are divided into independent code blocks, the quantized coefficients in the code blocks are organized into several bit planes; Perform bit plane encoding sequentially from the highest significant bit plane to the lowest bit plane; Bit plane encoding result combination module: write the D and CX output by each bit plane after multiple bit plane parallel encoding into a total D and CX in sequence from the highest bit plane to the lowest bit plane; MQ encoding module: receive the context CX and the encoded bit symbol D output by the bit plane encoding result combination module, and output the compressed code stream CD using an adaptive binary arithmetic coding algorithm; Tier2 encoding module: hierarchically organize the compressed code stream output by the MQ encoding module according to the rate-distortion optimal principle, select an appropriate truncation point to truncate the code block compressed code stream, and compress the code stream into a final code stream with scalable resolution and quality; Data storage module, transfer the final compressed code stream output by the Tier2 encoding module to an external storage device for storage through direct memory access.

2. The high-speed implementation structure of a JPEG2000 encoder according to claim 1, wherein The data reading and preprocessing module, level shift module, wavelet transform module, data block module, data processing preparation module, multiple bit plane parallel encoding module, bit plane encoding result combination module, MQ encoding module, Tier2 encoding module and data storage module work together sequentially to achieve high-speed compression storage of image data.

3. The high-speed implementation structure of a JPEG2000 encoder according to claim 1, characterized in that, When implementing the functions of each module, the FPGA makes full use of its characteristics of parallel operation to improve the compression speed.

4. The high-speed implementation structure of a JPEG2000 encoder according to claim 1, characterized in that, When designing this structure, test pins are reserved, and the unused FPGA pins are led out for testing and function expansion.

5. The high-speed implementation structure of a JPEG2000 encoder according to claim 1, characterized in that, The wavelet transform module adopts a 5-level lifting wavelet transform algorithm.

6. The high-speed implementation structure of a JPEG2000 encoder according to claim 1, characterized in that In each bit plane, scans of the "importance propagation channel", "amplitude refinement channel" and "cleaning channel" are performed sequentially.

7. The high-speed implementation structure of a JPEG2000 encoder according to claim 6, characterized in that, The "importance propagation channel", "amplitude refinement channel" and "cleaning channel" divide the original bit plane without repetition, ensuring that each coefficient bit on the original bit plane can and can only be encoded in one of the encoding channels, and each encoding channel contains one or more encoding primitives.

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