Semiconductor device

Abstract

According to an example embodiment of the present disclosure, a semiconductor device includes: a substrate including a first region and a second region; a capacitor on the substrate in the first region, where the capacitor includes a lower electrode, a support layer connected to the lower electrode, a dielectric layer covering the support layer and the lower electrode, and an upper electrode on the dielectric layer; a first upper conductive pattern in contact with an upper surface of the upper electrode; a second upper conductive pattern on the first upper conductive pattern; an upper contact plug between the first upper conductive pattern and the second upper conductive pattern; an interlayer insulating layer disposed on the second region of the substrate and disposed on an outer surface of the upper electrode; and a first peripheral conductive line disposed on the interlayer insulating layer and disposed on the same vertical level as that of at least a portion of the first upper conductive pattern.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0012460, filed with the Korean Intellectual Property Office on January 26, 2024, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0002] Example embodiments relate to a semiconductor device including a capacitor. Background Art

[0003] Recently, electronic devices include semiconductor devices having a reduced size and processing high-capacity data. Specifically, in the case of a memory semiconductor device, since the size of memory cells has been reduced for high integration density, and the interconnection structure for applying an electrical signal for the operation of the memory cells included in the semiconductor device has become complex. Therefore, there is a need for a semiconductor device that can be easily manufactured with increased integration density and sufficient reliability. Summary of the Invention

[0004] Example embodiments include a semiconductor device having increased integration density and improved reliability.

[0005] According to an example embodiment of the present disclosure, a semiconductor device includes: a substrate including a first region and a second region; a capacitor on the substrate in the first region, wherein the capacitor includes a lower electrode, a support layer connected to the lower electrode, a dielectric layer covering the support layer and the lower electrode, and an upper electrode on the dielectric layer; a first upper conductive pattern in contact with an upper surface of the upper electrode; a second upper conductive pattern on the first upper conductive pattern; an upper contact plug between the first upper conductive pattern and the second upper conductive pattern; an interlayer insulating layer disposed on the second region of the substrate and on an outer surface of the upper electrode; and a first peripheral wire disposed on the interlayer insulating layer and at a vertical level identical to at least a part of the first upper conductive pattern.

[0006] According to an exemplary embodiment of the present disclosure, a semiconductor device includes: a substrate including a cell region and a peripheral region, the cell region including bit lines and memory structures, the memory structures being disposed at a vertical level higher than a vertical level of the bit lines, the peripheral region including a peripheral circuit; a first upper conductive pattern disposed on the memory structures in the cell region; a second upper conductive pattern on the first upper conductive pattern; a first peripheral wire extending in a first direction over the peripheral region and disposed at a vertical level the same as at least a portion of the first upper conductive pattern; a first peripheral pattern and a second peripheral pattern disposed on the first peripheral wire at a vertical level the same as at least a portion of the second upper conductive pattern and spaced apart from each other in the first direction; a first intermediate contact plug disposed between the first peripheral wire and the first peripheral pattern; and a second intermediate contact plug disposed between the first peripheral wire and the second peripheral pattern.

[0007] According to an exemplary embodiment of the present disclosure, a semiconductor device includes: a substrate including a cell region and a peripheral region surrounding the cell region; bit lines disposed on the cell region; a capacitor disposed on the cell region and at a vertical level higher than a vertical level of the bit lines, wherein the capacitor includes a lower electrode structure among a plurality of lower electrode structures, a support layer adjacent to the lower electrode structure and being part of a support layer formed between the lower electrode structures among the plurality of lower electrode structures, a dielectric layer covering the lower electrode structure and also covering the plurality of lower electrode structures, and an upper electrode on the dielectric layer; a first upper conductive pattern in contact with an upper surface of the upper electrode and vertically located above the upper surface of the upper electrode; a second upper conductive pattern on the first upper conductive pattern; an upper contact plug electrically connecting the first upper conductive pattern to the second upper conductive pattern; a first interlayer insulating layer disposed on the substrate in the peripheral region and on an outer side surface of the upper electrode; a first peripheral wire disposed at the first interlayer insulating layer and at a vertical level the same as at least a portion of the first upper conductive pattern; a first peripheral pattern and a second peripheral pattern disposed at a horizontal level the same as at least a portion of the second upper conductive pattern on the first peripheral wire and spaced apart from each other; and intermediate contact plugs respectively disposed between each of the first peripheral pattern and the second peripheral pattern and the first peripheral wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] These and other aspects, features, and advantages of the exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A is a plan view showing a cell region of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 1B is a plan view showing a peripheral region of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 2A is a cross-sectional view of a cell region taken along line I-I' and line V-V' in Figure 1A in accordance with an exemplary embodiment of the present disclosure; Figure 2B is a cross-sectional view of a second peripheral region taken along line II-II' and line III-III' in Figure 1B in accordance with an exemplary embodiment of the present disclosure; Figure 2C is a cross-sectional view of a first peripheral region taken along line IV-IV' in Figure 1B in accordance with an exemplary embodiment of the present disclosure; Figure 3A is a plan view of a second peripheral region of a semiconductor device in accordance with another exemplary embodiment of the present disclosure; Figure 3B is a cross-sectional view of a second peripheral region taken along line A-A' and line B-B' in Figure 3A in accordance with an exemplary embodiment of the present disclosure; Figures 4A to 4C is a cross-sectional view of a semiconductor device in accordance with another exemplary embodiment of the present disclosure; Figure 5A and Figure 5B is a cross-sectional view of a semiconductor device in accordance with another exemplary embodiment of the present disclosure; Figure 6A and Figure 6B is a cross-sectional view of a first peripheral region and a second peripheral region in accordance with an exemplary embodiment of the present disclosure; Figure 7 is a cross-sectional view of a first peripheral region of a semiconductor device in accordance with an exemplary embodiment of the present disclosure; Figure 8A is a plan view of a cell connection structure provided in a cell region of a semiconductor device and a peripheral connection structure provided in a peripheral region in accordance with an exemplary embodiment of the present disclosure; Figure 8B is a perspective view of a peripheral connection structure shown in Figure 8A in accordance with an exemplary embodiment of the present disclosure; Figure 9A is a plan view of a cell connection structure provided in a cell region of a semiconductor device and a peripheral connection structure provided in a peripheral region in accordance with an exemplary embodiment of the present disclosure; Figure 9B is a perspective view of a peripheral connection structure shown in Figure 9A in accordance with an exemplary embodiment of the present disclosure; Figure 10Ais a plan view showing a cell connection structure disposed in a cell region of a semiconductor device and a peripheral connection structure disposed in a peripheral region according to an exemplary embodiment of the present disclosure; Figure 10B is a view showing an exemplary embodiment according to the present disclosure Figure 10A a perspective view of the peripheral connection structure in Figure 11 is a plan view showing a cell connection structure disposed in a cell region of a semiconductor device and a peripheral connection structure disposed in a peripheral region according to an exemplary embodiment of the present disclosure; and Figures 12A to 12D is a view showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings as follows.

[0010] Throughout the specification, unless the context otherwise indicates, when a component is described as "including" a specific element or group of elements, it should be understood that the component is formed only by the element or the group of elements, or the element or the group of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component is formed only by the listed one or more elements.

[0011] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for specific elements, steps, etc. to distinguish such elements, steps, etc. from each other. Terms not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. Additionally, a term referred to by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim).

[0012] For ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", "on top of", "at the bottom of", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to one or more other elements or features. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" another element or feature will be oriented "above" that other element or feature. Thus, the term "below" can include both the upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly. As described herein, "level" may be a vertical level (e.g., a height along a vertical direction as a specific distance from a horizontal plane such as the top surface of a substrate).

[0013] It will be understood that when an element is referred to as "connected" or "coupled" to another element or "on" another element, the element may be directly connected or coupled to the other element or on the other element, or intervening elements may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, or is referred to as "contacting" or "in contact with" another element (or any form of the word "contact" is used), no intervening elements are present at the point of contact.

[0014] When referring to an orientation, layout, position, shape, size, composition, quantity, or other metric, terms such as "same", "equal", "flat", or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, composition, quantity, or other metric, but are intended to encompass nearly equivalent orientations, layouts, positions, shapes, sizes, compositions, quantities, or other metrics within the typical variations that can occur due to conventional manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, an item described as "substantially the same", "substantially equal", or "substantially flat" may be exactly the same, equal, or flat, or may be the same, equal, or flat within acceptable variations that can occur, for example, due to the manufacturing process.

[0015] Components described herein as "integrated" or "integrated with each other" are formed to include continuously formed materials so as to form an integral structure.

[0016] Figure 1A is a plan view showing a cell region of a semiconductor device according to an exemplary embodiment. Figure 1B is a plan view showing a peripheral region of a semiconductor device according to an exemplary embodiment.

[0017] Figure 2A is a cross-sectional view of a cell region taken along line I-I' and line V-V' in Figure 1A in accordance with an exemplary embodiment. Figure 2B is a cross-sectional view of a second peripheral region taken along line Ⅱ-Ⅱ' and line Ⅲ-Ⅲ' in Figure 1B in accordance with an exemplary embodiment. Figure 2C is a cross-sectional view of a first peripheral region taken along line Ⅳ-Ⅳ' in Figure 1B in accordance with an exemplary embodiment.

[0018] Referring to Figure 1A and Figure 1B the semiconductor device 100 may include a cell region CA and peripheral regions PA1 and PA2 adjacent to the cell region CA.

[0019] The cell region CA may be a region in which memory cells of a dynamic random access memory (DRAM) device are provided, and the peripheral regions PA1 and PA2 may be regions in which a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit are provided.

[0020] The peripheral regions PA1 and PA2 may be provided adjacent to the cell region CA. The peripheral regions PA1 and PA2 may surround the cell region CA (e.g., when viewed from a plan view, arranged around the cell region CA). The peripheral regions PA1 and PA2 may include a first peripheral region PA1 and a second peripheral region PA2 extending from the first peripheral region PA1. In some embodiments, the second peripheral region PA2 may be provided between the cell region CA and the first peripheral region PA1. In some embodiments, the cell region CA, the second peripheral region PA2, and the first peripheral region PA1 may be provided to be adjacent to each other in sequence. From Figures 2B to 2C it can be seen that only a part of the peripheral region is shown. In the exemplary embodiment, the peripheral regions PA1 and PA2 may be between the cell region CA and the edge of the substrate 3 and may be adjacent to the edge of the substrate 3.

[0021] Referring to Figure 1A and Figure 2A the semiconductor device 100 may include a substrate 3 including a first active region 10 in the cell region CA, a bit line structure BLS including bit lines BL on the substrate 3, a cell gate structure GS on the substrate 3, a capacitor CAP on the bit line structure BLS, a first upper conductive pattern PL1 on the capacitor CAP, and a second upper conductive pattern PL2 on the first upper conductive pattern PL1. The capacitor CAP may store data and may be, for example, a capacitor structure of a DRAM. The capacitor CAP may be referred to as a data storage structure.

[0022] For example, the semiconductor device 100 may include a cell array of a dynamic random access memory (DRAM). For example, a bit line BL may be connected to a first impurity region 9a on a first active region 10, and a second impurity region 9b on the first active region 10 may be electrically connected to a capacitor CAP on a landing pad 70 through a contact plug 32 and the landing pad 70.

[0023] The capacitor CAP may be electrically connected to the contact plug 32 and the landing pad 70 on a lower structure. The lower structure may include a substrate 3, a cell gate structure GS, and a bit line structure BLS.

[0024] The capacitor CAP may include a lower electrode 170, a dielectric layer 171 on the lower electrode 170, and an upper electrode 173 on the dielectric layer 171. The capacitor CAP may further include support layers (or, support member layers) SPa and SPb (for example, a first support member layer SPa and a second support member layer SPb). A plurality of capacitors may be formed by a plurality of lower electrodes 170.

[0025] The semiconductor device 100 may include a substrate 3, a cell gate structure GS, a buffer layer 21, a bit line structure BLS, a contact plug 32, a landing pad 70, an insulating pattern 76, and a capacitor CAP (or a data storage structure) in a cell region CA. As can be seen from the figure, various items described herein in the singular (for example, having a single reference numeral and a single instance of the item discussed) may be provided in the plural.

[0026] The substrate 3 may include a semiconductor material (such as a Group-IV semiconductor, a Group-III-V compound semiconductor, or a Group-II-VI compound semiconductor). For example, the Group-IV semiconductor may be silicon, germanium, or silicon germanium. The substrate 3 may be configured as a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a substrate including an epitaxial layer.

[0027] In the cell region CA, the substrate 3 may include a first active region 10, a first device isolation layer 11, a first impurity region 9a, and a second impurity region 9b. The first device isolation layer 11 may be configured as an insulating layer extending downward from an upper surface of the substrate 3, and may define the first active region 10. For example, the first active region 10 may correspond to a part of the substrate 3 surrounded by the first device isolation layer 11.

[0028] The first active region 10 may be connected to a first impurity region 9a and a second impurity region 9b that extend from the upper surface of the substrate 3 to a predetermined depth. The first impurity region 9a and the second impurity region 9b may be spaced apart from each other. The first impurity region 9a and the second impurity region 9b may be configured as the source region / drain region of a transistor. For example, with respect to a single first active region 10, two unit gate structures GS may intersect the first active region 10, and a drain region may be formed between the two unit gate structures GS, and a source region may be formed in a region opposite to the drain region of the two unit gate structures GS. For example, the first impurity region 9a may correspond to the drain region, and the second impurity region 9b may correspond to the source region. The source region and the drain region may be formed from the first impurity region 9a and the second impurity region 9b by doping or ion implantation of substantially the same impurity, and may be interchangeably referred to according to the circuit configuration of the ultimately formed transistor. The first impurity region 9a and the second impurity region 9b may include impurities having a conductivity type opposite to that of the substrate 3. For example, the first active region 10 may include p-type impurities, and the first impurity region 9a and the second impurity region 9b may have N-type impurities.

[0029] The first device isolation layer 11 may extend downward from the upper surface of the substrate 3 and may define the first active region 10. The first device isolation layer 11 may surround the first active region 10 and may allow the regions to be separated. The first device isolation layer 11 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may be a single layer or multiple layers.

[0030] In the cell region CA, the unit gate structures GS may extend in a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction). In addition, the unit gate structures GS may intersect the first active region 10. For example, in one first active region 10, two unit gate structures GS may intersect the first active region 10. A transistor including the unit gate structures GS and the first impurity region 9a and the second impurity region 9b may form a buried-channel array transistor (BCAT), but the exemplary embodiments are not limited thereto.

[0031] In a cross-sectional view, the unit gate structure GS may be buried in the substrate 3. For example, the unit gate structure GS may be disposed in a gate trench 12 formed in the substrate 3. The unit gate structure GS may include a gate dielectric layer 14, a gate electrode 16, and a gate capping layer 18 disposed in the gate trench 12. The gate dielectric layer 14 may be conformally formed on the inner wall of the gate trench 12. The gate electrode 16 may be disposed below the gate trench 12 (e.g., below the top of the gate trench 12), and the gate capping layer 18 may be disposed on the gate electrode 16 and may fill the gate trench 12.

[0032] The gate dielectric layer 14 may include silicon oxide or a high-κ material. In an illustrative example embodiment, the gate dielectric layer 14 may be formed by oxidizing the first active region 10 or may be formed by deposition. The gate electrode 16 may include at least one of, for example, polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). The gate capping layer 18 may include silicon nitride.

[0033] In the cell region CA, a buffer layer 21 may be disposed over the first active region 10, the first device isolation layer 11, and the cell gate structure GS. The buffer layer 21 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The buffer layer 21 may be configured as a single layer or multiple layers.

[0034] In the cell region CA, the bit line structure BLS may extend in a second direction (Y direction) and may be spaced apart from each other in a first direction (X direction). The bit line structure BLS may have a bar shape extending in the second direction (Y direction). The bit line structure BLS may include a bit line BL and a bit line capping layer BC on the bit line BL. The bit line BL may include a first conductive layer 25a, a second conductive layer 25b, and a third conductive layer 25c stacked in sequence over the buffer layer 21. In one embodiment, the first conductive layer 25a may be polysilicon, and the second conductive layer 25b may be a metal-semiconductor compound. For example, the metal-semiconductor compound may be configured as a layer in which a portion of the first conductive layer 25a is silicided. For example, the metal-semiconductor compound may be cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides, or may include a nitride (such as, TiSiN). The third conductive layer 25c may be a metal material (such as, titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al)). The bit line BL may further include a plug portion disposed below the first conductive layer 25a, the plug portion extending downward and contacting the second impurity region 9b.

[0035] The bit line capping layer BC may include a first capping layer 28a, a second capping layer 28b, and a third capping layer 28c disposed on the bit line BL. The side surface of the first capping layer 28a may be coplanar with the side surfaces of the first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c. The first capping layer 28a, the second capping layer 28b, and the third capping layer 28c may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof (such as, silicon nitride).

[0036] The spacer structure SP can be respectively disposed on two (e.g., opposite) side surfaces of the bit line structure BLS, and can extend in a second direction (Y direction) along the side surface of the bit line structure BLS. The spacer structure SP can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The spacer structure SP in the exemplary embodiment is only an example, and the material of the spacer structure SP and the number of layers of the spacer structure SP are not limited thereto and can vary.

[0037] The lower end of the contact plug 32 can be disposed at a level lower than the upper surface level of the substrate 3, and the upper surface of the contact plug 32 can be disposed at a level lower than the upper end level of the bit line structure BLS. The contact plug 32 can extend into the substrate 3, can penetrate the buffer layer 21, can contact the second impurity region 9b on the first active region 10, and can be electrically connected to the second impurity region 9b. The contact plug 32 can be formed of a conductive material and can include at least one of, for example, polysilicon (Poly-Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In one exemplary embodiment, the contact plug 32 includes doped polysilicon and includes an N-type impurity (such as one or more of phosphorus (P), arsenic (As), and antimony (Sb)).

[0038] Referring to Figure 1A , the semiconductor device 100 may further include a fence structure 63 disposed between the bit line structures BLS. In a plan view, the fence structure 63 may be stacked with the unit gate structure GS in a vertical direction and may be alternately disposed with the contact plug 32 in a second direction (Y direction). The fence structure 63 can spatially isolate the contact plugs 32 from each other and can electrically insulate the contact plugs 32 from each other. The fence structure 63 can have a strip shape or a column shape extending in the vertical direction. Although not shown, the lower surface of the fence structure 63 can contact the gate capping layer 18 of the unit gate structure GS. The fence structure 63 can include an insulating material (e.g., silicon nitride).

[0039] The metal-semiconductor compound layer 34 can be disposed between the contact plug 32 and the bonding pad 70. For example, when the contact plug 32 includes a semiconductor material, the metal-semiconductor compound layer 34 can be obtained by siliciding a part of the contact plug 32. The metal semiconductor compound layer 34 can include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. In another example, the metal-semiconductor compound layer 34 may not be provided.

[0040] The bonding pad 70 can be disposed on the contact plug 32. The contact plug 32 can extend into the region between the spacer structures SP, and can cover the upper surface of the metal-semiconductor compound layer 34. The bonding pad 70 can include a barrier layer 71 and a conductive layer 72. The barrier layer 71 can cover the lower surface and the side surfaces of the conductive layer 72. The barrier layer 71 can include at least one metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)). The conductive layer 72 can include a conductive material (such as at least one of polysilicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)).

[0041] The insulating pattern 76 can be disposed to penetrate the bonding pad 70. The bonding pad 70 can be divided into a plurality of parts by the insulating pattern 76. The insulating pattern 76 can include at least one of insulating materials (e.g., silicon oxide, silicon nitride, and silicon oxynitride).

[0042] The etch stop layer 68 can cover the insulating pattern 76 between the lower electrodes 170. The etch stop layer 68 can extend into the peripheral regions PA1 and PA2. The etch stop layer 68 can contact the lower regions of the side surfaces of the lower electrodes 170. The etch stop layer 68 can be disposed below the support layers SPa and SPb. The upper surface of the etch stop layer 68 can include a portion that is in direct contact with the dielectric layer 171. For example, the etch stop layer 68 can include at least one of silicon nitride and silicon oxynitride.

[0043] The lower electrodes 170 can be disposed on the conductive layer 72. The lower electrodes 170 can penetrate the etch stop layer 68 and can contact the conductive layer 72. The lower electrodes 170 and the conductive layer 72 can have a column shape, but the exemplary embodiments are not limited thereto. Each of the lower electrodes 170 and the conductive layer 72 can include at least one of niobium nitride (NbN), niobium oxide (NbOx), polysilicon (Si), iridium (Ir), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al), or a combination thereof, metal nitrides, metal compounds, etc.

[0044] The dielectric layer 171 can cover the side surfaces and the upper surfaces of each of the lower electrodes 170 on the surface of the lower electrodes 170. The dielectric layer 171 can be disposed between the lower electrodes 170 and the upper electrodes 173. The dielectric layer 171 can cover the upper surfaces and the lower surfaces of the support layers SPa and SPb. The dielectric layer 171 can cover the upper surface of the etch stop layer 68.

[0045] The dielectric layer 171 may include a high-κ material, silicon oxide, silicon nitride, or a combination thereof. However, in an exemplary embodiment, the dielectric layer 171 may be an oxide, nitride, silicide, oxynitride, or silicon oxynitride doped with fluorine (F) and at least one of titanium (Ti), tantalum (Ta), hafnium (Hf), aluminum (Al), zirconium (Zr), and lanthanum (La), or including a combination thereof.

[0046] The upper electrode 173 may be disposed on the dielectric layer 171. The upper electrode 173 may fill the space between the lower electrodes 170 and the space between the support layers Spa and SPb. The upper electrode 173 may include a conductive material. In one example, the upper electrode 173 may include at least one of silicon germanium (SiGe) and silicon (Si).

[0047] The upper electrode 173 may include a first portion 173a, a second portion 173b, and a third portion 173c. In an exemplary embodiment, the first portion 173a may fill the space between the lower electrode 170 and the support layers Spa and SPb on the substrate 3, and may be disposed on the dielectric layer 171. For example, the portion of the upper electrode 173 directly above the top surface of the dielectric layer 171 and the portion of the upper electrode 173 formed between the lower electrodes 170 may be the first portion 173a. In an exemplary embodiment, the second portion 173b may extend from the first portion 173a and may surround other components of the capacitor CAP in the horizontal direction. The second portion 173b may surround the first portion 173a and may extend horizontally from above the top of the lower electrode 170 to a level below the level where the support layer Spa is formed. The second portion 173b may include a curved side surface. The second portion 173b may also include at least one protrusion. At least one protrusion (not shown) may be stacked with the support layers Spa and SPb in the horizontal direction. In an exemplary embodiment, the third portion 173c may be a portion extending from the second portion 173b and protruding toward the peripheral regions PA1 and PA2. The third portion 173c may extend horizontally on the etch stop layer 68 and extend horizontally along the etch stop layer 68. The third portion 173c may not be stacked with the support layers Spa and SPb in the horizontal direction.

[0048] The support layers Spa and SPb may include a first support layer Spa and a second support layer SPb above the first support layer Spa. The support layers Spa and SPb may be spaced apart from the substrate 3 in a direction perpendicular to the upper surface of the substrate 3. The support layers Spa and SPb may be in contact with the lower electrode 170 and may extend in a direction parallel to the upper surface of the substrate 3.

[0049] The support layers SPa and SPb may be configured to support the lower electrode 170 having a high aspect ratio. The support layers SPa and SPb may include at least one of, for example, silicon nitride, silicon oxynitride, and materials similar thereto. The number of the support layers SPa and SPb, the thickness of the support layers SPa and SPb, and / or the arrangement relationship between the support layers Spa and SPb are not limited to the illustrated example and may vary in the exemplary embodiment.

[0050] The first insulating layer ILD1 (or, the interlayer insulating layer) may fill the step difference formed due to the capacitor CAP provided in the cell region CA. The first insulating layer ILD1 may surround the capacitor CAP in the first direction (X direction) and may extend to the peripheral regions PA1 and PA2. The upper surface of the first insulating layer ILD1 may be disposed at the same level as the upper surface of the upper electrode 173. In an example, the upper surface of the first insulating layer ILD1 may be disposed at the same level as the upper surface of the first portion 173a of the upper electrode 173. The first insulating layer ILD1 may be in contact with the second portion 173b and the third portion 173c of the upper electrode 173.

[0051] The first upper conductive pattern PL1 may be disposed on the upper electrode 173 in the cell region CA and may be electrically connected to the upper electrode 173. In one exemplary embodiment, the first upper conductive pattern PL1 may be disposed on the first portion 173a of the upper electrode 173. The first upper conductive pattern PL1 may be in contact with the upper surface of the first portion 173a of the upper electrode 173. In one exemplary embodiment, the first upper conductive pattern PL1 may not overlap with the second portion 173b and the third portion 173c of the upper electrode 173 in the vertical direction (Z direction). For example, when viewed from a plan view, the first upper conductive pattern PL1 may be formed within the footprint of the upper electrode 173, and the second portion 173b and the third portion 173c may be formed outside the footprint.

[0052] The first upper conductive pattern PL1 may include a first barrier layer PL1a and a first electrode layer PL1b. The first barrier layer PL1a may be disposed on the lower surface of the first electrode layer PL1b. In an example, the width of the first barrier layer PL1a in the horizontal direction may decrease upward. The first barrier layer PL1a may include a metal nitride (such as titanium nitride (TiN)). In one example, the first electrode layer PL1b may include at least one of silicon germanium (SiGe), tungsten (W), tungsten nitride (WN), and titanium nitride (TiN).

[0053] The second insulating layer ILD2 may be disposed on the first insulating layer ILD1. The second insulating layer ILD2 may surround the side surface of the first upper conductive pattern PL1. In an example embodiment, the upper surface of the second insulating layer ILD2 may be disposed at substantially the same level as the upper surface of the first upper conductive pattern PL1.

[0054] The second upper conductive pattern PL2 may be disposed on the first upper conductive pattern PL1. The second upper conductive pattern PL2 may be stacked with the first upper conductive pattern PL1 in the vertical direction (Z direction). The width of the second upper conductive pattern PL2 in the horizontal direction may decrease downward. In an example embodiment, the second upper conductive pattern PL2 may extend in the first direction (X direction).

[0055] The third insulating layer ILD3 may be disposed on the second insulating layer ILD2. The second upper conductive pattern PL2 may be disposed on the third insulating layer ILD3. The upper surface of the third insulating layer ILD3 may be disposed at substantially the same level as the lower surface of the second upper conductive pattern PL2.

[0056] The second upper conductive pattern PL2 may be electrically connected to the first upper conductive pattern PL1 through an upper contact plug CCP. The upper contact plug CCP may penetrate the third insulating layer ILD3 and may electrically connect the first upper conductive pattern PL1 to the second upper conductive pattern PL2. The lower surface of the upper contact plug CCP may be disposed at a level lower than the upper surface of the first upper conductive pattern PL1.

[0057] The second upper conductive pattern PL2 may include a conductive material. In one example, the second upper conductive pattern PL2 may include copper (Cu).

[0058] The fourth insulating layer ILD4 may be disposed on the third insulating layer ILD3. The fourth insulating layer ILD4 may cover the side surface of the second upper conductive pattern PL2.

[0059] The first insulating layer ILD1 to the fourth insulating layer ILD4 may extend to the peripheral regions PA1 and PA2. Each of the first insulating layer ILD1 to the fourth insulating layer ILD4 may include at least one of silicon oxide and silicon nitride.

[0060] Refer to Figure 1B and Figure 2B, the second peripheral region PA2 of the semiconductor device 100 may include a plurality of interconnect structures L1, L2, and L3. The plurality of interconnect structures L1, L2, and L3 may provide a circuit path between the peripheral circuits or a circuit path for connecting the cell region CA to the peripheral circuits. The plurality of interconnect structures L1, L2, and L3 may be sequentially arranged in the horizontal direction (X direction or Y direction). In an example, the plurality of interconnect structures L1, L2, and L3 may include a first peripheral interconnect structure L1, a second peripheral interconnect structure L2, and a third peripheral interconnect structure P3 sequentially arranged in one direction. Figure 1B The plurality of interconnect structures L1, L2, and L3 shown in Figure 1B may be spaced apart from each other in the second direction (Y direction) and may extend in the first direction (X direction) as shown in the drawings, but the example embodiments are not limited thereto, and the plurality of interconnect structures L1, L2, and L3 may be spaced apart from each other in the first direction (X direction) and may extend in the second direction (Y direction).

[0061] The first peripheral interconnect structure L1 may include a first upper wire UPL1, and the third peripheral interconnect structure L3 may include a third upper wire UPL3, and the first upper wire UPL1 and the third upper wire UPL3 may be disposed at the same level. The first upper wire UPL1 and the third upper wire UPL3 may be (for example, by extending in the second direction (Y direction) and not connected by the connection portions shown in Figure 1B ) integrated wires extending in the first direction (X direction). Figure 1B or Figure 2B Figure 1B .

[0062] The first upper wire UPL1 and the third upper wire UPL3 may be spaced apart by a first distance Da in the second direction (Y direction).

[0063] The first upper wire UPL1 may provide a circuit path in the first direction (X direction) from the first end of the first upper wire UPL1 to the second end of the first upper wire UPL1 opposite to the first end. The third upper wire UPL3 may provide a circuit path in the first direction (X direction) from the first end of the third upper wire UPL3 to the second end of the third upper wire UPL3 opposite to the first end.

[0064] The second peripheral interconnect structure L2 may be disposed between the first peripheral interconnect structure L1 and the third peripheral interconnect structure L3. In an example embodiment, the second peripheral interconnect structure L2 may include a first peripheral wire MPL1, and a first peripheral pattern MPL2a and a second peripheral pattern MPL2b stacked with the first peripheral wire MPL1 in the vertical direction (Z direction). The first peripheral wire MPL1 may be configured as a conductive pattern (or plate) extending in the first direction (X direction). The first peripheral pattern MPL2a and the second peripheral pattern MPL2b may be disposed at the same level with each other and may be spaced apart from each other in the first direction (X direction).

[0065] Intermediate contact plugs MCPa and MCPb can be disposed between the first peripheral wire MPL1 and the first peripheral pattern MPL2a and the second peripheral pattern MPL2b, and can be part of the second peripheral interconnect structure L2. In one example, the intermediate contact plugs MCPa and MCPb can include a first intermediate contact plug MCPa and a second intermediate contact plug MCPb. The first intermediate contact plug MCPa is disposed between the first peripheral wire MPL1 and the first peripheral pattern MPL2a, and the second intermediate contact plug MCPb is disposed between the first peripheral wire MPL1 and the second peripheral pattern MPL2b. In the example, the first intermediate contact plug MCPa can penetrate the third insulating layer ILD3 and can electrically connect the first peripheral wire MPL1 to the first peripheral pattern MPL2a, and the second intermediate contact plug MCPb can penetrate the third insulating layer ILD3 and can electrically connect the first peripheral wire MPL1 to the second peripheral pattern MPL2b.

[0066] The first peripheral wire MPL1 can be disposed at a level lower than the levels of the first upper wire UPL1 and the third upper wire UPL3. In one example, the first peripheral pattern MPL2a and the second peripheral pattern MPL2b can be disposed at the same level as the levels of the first upper wire UPL1 and the third upper wire UPL3.

[0067] The second peripheral interconnect structure L2 can include the first peripheral pattern MPL2a and the second peripheral pattern MPL2b that are electrically connected to each other through the intermediate contact plugs MCPa and MCPb and the first peripheral wire MPL1.

[0068] The first peripheral wire MPL1 can be disposed at a level substantially the same as at least a part of the level of the first upper conductive pattern PL1 in the cell region CA. In one example, the first peripheral wire MPL1 can be disposed at the same level as at least a part of the level of the first upper conductive pattern PL1 in the cell region CA. The side surface of the first peripheral wire MPL1 can be surrounded by the second insulating layer ILD2.

[0069] The first peripheral wire MPL1 can include a first peripheral barrier layer MPL1a and a first peripheral electrode layer MPL1b on the first peripheral barrier layer MPL1a. In one example, the first peripheral barrier layer MPL1a can include a metal nitride (such as titanium nitride (TiN)). In one example, the first peripheral electrode layer MPL1b can include at least one of silicon germanium (SiGe), tungsten (W), tungsten nitride (WN), and titanium nitride (TiN). In one example, the first peripheral wire MPL1 can include a material the same as the material of the first upper conductive pattern PL1. In one example, the first peripheral wire MPL1 can have a width that decreases upward.

[0070] The first peripheral pattern MPL2a and the second peripheral pattern MPL2b may be disposed at a level substantially the same as at least a part of the second upper conductive pattern PL2 of the cell region CA. In one example, the first peripheral conductive pattern MPL2a and the second peripheral conductive pattern MPL2b may be disposed at a level substantially the same as that of the second upper conductive pattern PL2.

[0071] The intermediate contact plugs MCPa and MCPb may be disposed at the same level as the upper contact plug CCP in the cell region CA.

[0072] The first peripheral interconnect structure L1, the second peripheral interconnect structure L2, and the third peripheral interconnect structure L3 may be stacked in the vertical direction (Z direction) with the bit line BL and the bit line capping layer BC extending from the cell region CA.

[0073] The semiconductor device 100 may further include peripheral device isolation layers 67 and 69 disposed in the second peripheral region PA2. The peripheral device isolation layers 67 and 69 may extend downward from the upper surface of the substrate 3. The peripheral device isolation layers 67 and 69 may surround the active regions in the substrate 3 and may allow the regions to be separated. The peripheral device isolation layers 67 and 69 may include an insulating material.

[0074] Reference Figure 1B and Figure 2C As shown in FIGS. 17 and 18, the first peripheral region PA1 of the semiconductor device 100 may include a substrate 3, the substrate 3 including a second active region 8, a first peripheral impurity region (or, peripheral circuit) 5a, and a second peripheral impurity region (or, peripheral circuit) 5b. The second device isolation layer 7 may be an insulating layer extending downward from the upper surface of the substrate 3 and may define the second active region 8. For example, the second active region 8 may correspond to a part of the substrate 3 surrounded by the second device isolation layer 7. The first peripheral impurity region 5a and the second peripheral impurity region 5b may be spaced apart from each other, and a peripheral gate structure GSp is between the first peripheral impurity region 5a and the second peripheral impurity region 5b. In an exemplary embodiment, the peripheral gate structure GSp may form the peripheral circuit of the semiconductor device 100.

[0075] The second device isolation layer 7 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may be formed of a single layer or multiple layers. The first peripheral impurity region 5a and the second peripheral impurity region 5b may be provided as source / drain regions of a transistor formed by the peripheral gate structure GSp. The first peripheral impurity region 5a and the second peripheral impurity region 5b may include impurities having a conductivity type opposite to that of the substrate 3.

[0076] The peripheral gate structure GSp may include a peripheral gate dielectric layer 120, peripheral gate layers 125a, 125b, and 125c, and a peripheral capping pattern 128a. The peripheral gate layers 125a, 125b, and 125c may have a structure similar to that of the bit line BL and may be formed of a material similar to that of the bit line BL.

[0077] The peripheral gate layers 125a, 125b, and 125c may include a first conductive pattern 125a, a second conductive pattern 125b, and a third conductive pattern 125c stacked in sequence on the peripheral gate dielectric layer 120 of the substrate 3. The peripheral gate dielectric layer 120 may include silicon oxide, silicon nitride, or a high-κ material. The high-κ material may represent a dielectric material having a dielectric constant higher than that of silicon oxide. The first conductive pattern 125a, the second conductive pattern 125b, and the third conductive pattern 125c in the peripheral gate layers 125a, 125b, and 125c may include the same materials as the first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c of the bit line BL, respectively. The first peripheral capping layer pattern 128a may be disposed on the peripheral gate layers 125a, 125b, and 125c. The first peripheral capping pattern 128a may include the same material as the first capping layer 28a of the bit line capping layer BC.

[0078] The semiconductor device 100 may further include a peripheral gate spacer 129, a second peripheral capping pattern 128b, an interlayer insulating layer 130, and a third peripheral capping pattern 128c in the first peripheral region PA1. The peripheral gate spacer 129 may cover the side surfaces of the peripheral gate structure GSp. For example, the peripheral gate spacers 129 may be spaced apart from each other, the peripheral gate structure GSp may be between the peripheral gate spacers 129, and the peripheral gate spacers 129 may cover the side surfaces of the peripheral gate layers 125a, 125b, and 125c, and the first peripheral capping pattern 128a.

[0079] The second peripheral capping layer pattern 128b may cover the substrate 3, the peripheral gate spacer 129, and the peripheral gate structure GSp and may be formed conformally. The interlayer insulating layer 130 may partially cover the second peripheral capping pattern 128b. The upper surface of the interlayer insulating layer 130 may be coplanar with the upper surface of the second peripheral capping pattern 128b. The third peripheral capping pattern 128c may cover the interlayer insulating layer 130 and the second peripheral capping pattern 128b.

[0080] The second peripheral capping pattern 128b and the third peripheral capping pattern 128c may include the same materials as the second capping layer 28b and the third capping layer 28c of the bit line capping layer BC, respectively, and may include, for example, silicon nitride. The interlayer insulating layer 130 may include silicon oxide.

[0081] The semiconductor device 100 may further include peripheral plugs and peripheral interconnections. The peripheral plugs include composite layers 162 and 164, and the peripheral interconnections include composite layers 172 and 174 electrically connected to a first peripheral impurity region 5a and a second peripheral impurity region 5b in a first peripheral region PA1. The peripheral plugs may penetrate the interlayer insulating layer 130, may be disposed adjacent to the peripheral gate structure GSp, and may contact the first peripheral impurity region 5a and the second peripheral impurity region 5b. The peripheral interconnections may be disposed on the third peripheral covering pattern 128c and the peripheral plugs, and may extend in a horizontal direction. In one exemplary embodiment, the layers of the peripheral interconnections may be integrated with the layers of the peripheral plugs. For example, the peripheral interconnections may include a peripheral conductive layer 172 and a peripheral barrier layer 174, and the peripheral plugs may include a peripheral conductive layer 162 and a peripheral barrier layer 164. The peripheral barrier layer 164 and the peripheral barrier layer 174 may be integrated with each other and may extend vertically and downward. The peripheral conductive layer 162 and the peripheral conductive layer 172 may be integrated with each other and may extend vertically and downward. In some exemplary embodiments, the peripheral interconnections 172 and 174 may not be integrated with the peripheral plugs 162 and 164 separately.

[0082] The semiconductor device 100 may further include an insulating pattern 165 that penetrates the peripheral interconnections 172 and 174. The insulating pattern 165 may spatially isolate the peripheral plugs 162 and 164 and may electrically insulate the peripheral plugs 162 and 164 from each other.

[0083] The semiconductor device 100 may further include an etch stop layer 168 disposed on the peripheral interconnections 172 and 174. The etch stop layer 168 may be integrated with the etch stop layer 68. For example, the etch stop layer 168 may be formed by extending the etch stop layer 68 of the cell region CA to the peripheral regions PA1 and PA2.

[0084] The semiconductor device 100 may include a peripheral contact plug PCP and a second peripheral wire PPL disposed on the peripheral interconnections 172 and 174. The peripheral contact plug PCP may penetrate the first insulating layer ILD1, the second insulating layer ILD2, the third insulating layer ILD3, and the etch stop layer 168, and may contact the peripheral interconnections 172 and 174. The peripheral contact plug PCP may be electrically connected to the first peripheral impurity region 5a and / or the second peripheral impurity region 5b through the peripheral interconnections 172 and 174 and the peripheral plugs 162 and 164. The upper surface of the peripheral contact plug PCP may be coplanar with the upper surfaces of the upper contact plug CCP and the third insulating layer ILD3.

[0085] The second peripheral wire PPL may be disposed on the peripheral contact plug PCP. The second peripheral wire PPL may be disposed at a level substantially the same as the level of the second upper conductive pattern PL2 of the cell region CA. In one example, the second peripheral wire PPL may be disposed at the same level as at least a portion of the second upper conductive pattern PL2. The cell region CA and the peripheral region PA2 may be arranged such that the first peripheral pattern MPL2a and the second peripheral pattern MPL2b are disposed (e.g., physically located) between the second upper conductive pattern PL2 and the second peripheral wire PPL.

[0086] In the semiconductor device 100, dummy structures DPL1, DPL2, and DCP may be disposed in a region adjacent to the peripheral contact plug PCP in the first peripheral region PA1. In an example, the dummy structures DPL1, DPL2, and DCP may include a first dummy conductive pattern DPL1, a second dummy conductive pattern DPL2 on the first dummy conductive pattern DPL1, and a dummy contact plug DCP disposed between the first dummy conductive pattern DPL1 and the second dummy conductive pattern DPL2.

[0087] The first dummy conductive pattern DPL1 may be disposed at a level substantially the same as the level of the first upper conductive pattern PL1 of the cell region CA. The second dummy conductive pattern DPL2 may be disposed at a level substantially the same as the level of the second upper conductive pattern PL2 of the cell region CA. The dummy contact plug DCP may be disposed at a level substantially the same as the level of the upper contact plug CCP of the cell region CA. The cell region CA and the peripheral region PA2 may be arranged such that the second peripheral wire PPL is disposed between the second dummy pattern DPL2 and the second peripheral pattern MPL2b.

[0088] The first dummy conductive pattern DPL1 may include a dummy barrier layer DPL1a and a dummy electrode layer DPL1b. The dummy barrier layer DPL1a may be disposed on the lower surface of the dummy electrode layer DPL1b. In an example, the width of the first dummy conductive pattern DPL1 in the horizontal direction may have a width that decreases upward.

[0089] The first upper conductive pattern PL1, the first peripheral wire MPL1, and the first dummy conductive pattern DPL1 may be formed and / or disposed by a patterning process.

[0090] The dummy structures DPL1, DPL2, and DCP may be in a floating state and thus may not be electrically connected to any circuitry for transmitting signals or voltages.

[0091] The semiconductor device 100 according to an exemplary embodiment may include dummy structures DPL1, DPL2, and DCP such that defects in contact and corrosion of the peripheral contact plug PCP may be reduced during the process of manufacturing the semiconductor device 100, thereby improving reliability.

[0092] Figure 3A is a plan view showing a second peripheral region of a semiconductor device according to another exemplary embodiment. Figure 3B is a cross-sectional view showing a second peripheral region taken along line A-A' and line B-B' in Figure 3A in accordance with an exemplary embodiment.

[0093] Figure 3A and Figure 3B Components of the semiconductor device 100' shown in Figure 1B and Figure 2B except for the first upper wire UPL1' and the third upper wire UPL3' may be the same as or corresponding to the components shown in

[0094] The first peripheral interconnect structure L1 may include a first upper wire UPL1', the third peripheral interconnect structure L3 may include a third upper wire UPL3', and the first upper wire UPL1' and the third upper wire UPL3' may be disposed at the same level. The first upper wire UPL1' and the third upper wire UPL3' may each be configured as a single wire extending in a first direction (X direction).

[0095] The first upper wire UPL1' and the third upper wire UPL3' may be spaced apart from each other by a second distance (Db) in a second direction (Y direction).

[0096] The first peripheral wire MPL1 may be stacked at least partially on the first upper wire UPL1' and the third upper wire UPL3' in a vertical direction (Z direction). In this example, a portion of the first upper wire UPL1' and a portion of the third upper wire UPL3' may be stacked on the first peripheral wire MPL1.

[0097] Figures 4A to 4C is a cross-sectional view showing a semiconductor device according to another exemplary embodiment. Figure 4A is a cross-sectional view showing a Figure 1A unit region taken along line I-I' in accordance with another exemplary embodiment. Figure 4B is a cross-sectional view showing a Figure 1B second peripheral region taken along line II-II' and III-III' in accordance with another exemplary embodiment. Figure 4C is a cross-sectional view showing a Figure 1B first peripheral region taken along line IV-IV' in accordance with another exemplary embodiment.

[0098] Reference Figure 4A 、 Figure 4B and Figure 4C , other components of the semiconductor device 100a except for the first upper conductive pattern PL1', the peripheral wire MPL1', and the first dummy conductive pattern DPL1' may be the same as or corresponding to the components shown in Figure 2A 、 Figure 2B and Figure 2C . A repeated description of the same or corresponding components will not be provided.

[0099] The first upper conductive pattern PL1' may include a first barrier layer PL1a' and a first electrode layer PL1b'. The first barrier layer PL1a' may cover the side surface and the bottom surface of the first electrode layer PL1b'. In this example, the width of the first upper conductive pattern PL1' in the horizontal direction may increase upward.

[0100] The peripheral wire MPL1' may include a first peripheral barrier layer MPL1a' and a first peripheral electrode layer MPL1b'. The first peripheral barrier layer MPL1a' may cover the side surface and the bottom surface of the first peripheral electrode layer MPL1b'. In this example, the peripheral wire MPL1' may have a width that increases upward in the horizontal direction.

[0101] The first dummy conductive pattern DPL1' may include a dummy barrier layer DPL1a' and a dummy electrode layer DPL1b'. The dummy barrier layer DPL1a' may cover the side surface and the bottom surface of the dummy electrode layer DPL1b'. In this example, the width of the first dummy conductive pattern DPL1' in the horizontal direction may increase upward.

[0102] The first upper conductive pattern PL1', the peripheral wire MPL1', and the first dummy conductive pattern DPL1' may be set and / or formed by a damascene process.

[0103] The peripheral wire MPL1' and the first dummy conductive pattern DPL1' may be set at a level that is substantially the same as the level of the first upper conductive pattern PL1' in the horizontal direction.

[0104] Figure 5A and Figure 5B are cross-sectional views showing a semiconductor device according to another exemplary embodiment.

[0105] Figure 5A is a cross-sectional view showing the unit region in Figure 1A taken along line V-V' according to another exemplary embodiment. Figure 5B is a cross-sectional view showing the first peripheral region in Figure 1B taken along line IV-IV' according to another exemplary embodiment.

[0106] ReferenceFigure 5A and Figure 5B components of the semiconductor device 100b other than the first etch stop layers 68a and 168a, the second etch stop layers 68b and 168b, and the first peripheral contact plug PCP1 and the second peripheral contact plug PCP2 may be the same as or corresponding to the components shown in Figure 2A and Figure 2C No repeated description of the same or corresponding components will be provided.

[0107] Referring to Figure 5A the first etch stop layers 68a and the second etch stop layers 68b may cover the insulating pattern 76 between the lower electrodes 170. The first etch stop layer 68a may be disposed on the insulating pattern 76, and the second etch stop layer 68b may be disposed on the first etch stop layer 68a.

[0108] The second etch stop layer 68b may contact a lower region of the side surface of the lower electrode 170. The upper surface of the second etch stop layer 68b may include a portion in contact with the dielectric layer 171. The first etch stop layer 68a and the second etch stop layer 68b may include at least one of, for example, silicon nitride and silicon oxynitride.

[0109] The lower electrode 170 may penetrate the first etch stop layer 68a and the second etch stop layer 68b and may contact the conductive layer 72.

[0110] Referring to Figure 5B the first etch stop layer 168a may be disposed on the peripheral interconnects 172 and 174. The first etch stop layer 168a may be obtained by extending and disposing the first etch stop layer 68a of the cell region CA in the first peripheral region PA1.

[0111] The first peripheral contact plug PCP1 may penetrate the first etch stop layer 168a and may contact the peripheral interconnect 172. The first peripheral contact plug PCP1 may be electrically connected to the peripheral interconnects 172 and 174.

[0112] The peripheral intermediate pad 185 may be disposed on the first peripheral contact plug PCP1.

[0113] The peripheral interlayer insulating layer 175 may be disposed on the side surface of the first peripheral contact plug PCP1. The peripheral interlayer insulating layer 175 may be disposed at a level higher than that of the first etch stop layer 168a. The peripheral interlayer insulating layer 175 may cover the side surface of the first peripheral contact plug PCP1. The peripheral interlayer insulating layer 175 may be disposed at a level lower than the upper surface level of the peripheral intermediate pad 185.

[0114] The second etch stop layer 168b may be disposed on the first peripheral contact plug PCP1 and the peripheral intermediate pad 185. The second etch stop layer 168b may be obtained by extending and disposing the second etch stop layer 68b of the cell region CA in the first peripheral region PA1. The second etch stop layer 168b may have a surface profile corresponding to the shapes of the peripheral intermediate pad 185 and the peripheral interlayer insulating layer 175.

[0115] The second peripheral contact plug PCP2 may be electrically connected to the peripheral intermediate pad 185 by penetrating through the first insulating layer ILD1 to the third insulating layer ILD3 and the second etch stop layer 168b. The combined first peripheral contact plug PCP1 and the second peripheral contact plug PCP2 may be described together as a contact plug (e.g., including two connection portions).

[0116] The second peripheral wire PPL may be disposed on the second peripheral contact plug PCP2. In this example, the second peripheral wire PPL may be electrically connected to the peripheral circuit through the first peripheral contact plug PCP1 and the second peripheral contact plug PCP2.

[0117] Figure 6A and Figure 6B are cross-sectional views showing a first peripheral region and a second peripheral region according to an exemplary embodiment.

[0118] Referring to Figure 6A and Figure 6B , components of the semiconductor device 100c other than the bit line contact structures 80 and 81, the bit line contact plugs BCP, and the third peripheral pattern MPL3a and the fourth peripheral pattern MPL3b may be the same as or corresponding to the components shown in Figure 2B and Figure 2C . A repeated description of the same or corresponding components will not be provided.

[0119] Referring to Figure 6A and Figure 6B , the semiconductor device 100c may include a first bit line BL1 and a second bit line BL2. The first bit line BL1 and the second bit line BL2 may extend from the cell region (e.g., the cell region CA in Figure 2A ), and may be respectively disposed in the first peripheral region PA1 and the second peripheral region PA2 in Figure 6A and Figure 6B .

[0120] The semiconductor device 100c may include bit line contact structures 80 and 81 in the second peripheral region PA2, a first peripheral wire MPL1'', a third peripheral pattern MPL3a and a fourth peripheral pattern MPL3b disposed on the first peripheral wire MPL1'', intermediate contact plugs MCPa'' and MCPb'', and a bit line contact plug BCP. In an exemplary embodiment, the first peripheral wire MPL1'' may include a first peripheral barrier layer MPL1a'' and a first peripheral electrode layer MPL1b'' on the first peripheral barrier layer MPL1a''.

[0121] The semiconductor device 100c may further include bit line contact structures 80 and 81. The bit line contact structures 80 and 81 may penetrate a bit line capping layer BC in the second peripheral region PA2 and may be electrically connected to a first bit line BL1.

[0122] The bit line contact structures 80 and 81 may include a conductive layer 80 and a barrier layer 81 covering side and bottom surfaces of the conductive layer 80. The conductive layer 80 may include a metal material (e.g., tungsten (W)). The barrier layer 81 may include at least one of metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0123] Insulating structures 41a and 42a may be disposed in a portion of the second peripheral region PA2 adjacent to the first peripheral region PA1. The insulating structures 41a and 42a may allow the first bit line BL1 to be spaced apart from the peripheral circuits GSp, 5a, and 5b from each other.

[0124] The first peripheral wire MPL1'' may be disposed on a first insulating layer ILD1. The third peripheral pattern MPL3a and the fourth peripheral pattern MPL3b may be disposed on the first peripheral wire MPL1''. The third peripheral pattern MPL3a and the fourth peripheral pattern MPL3b may be spaced apart from each other in one direction.

[0125] The first peripheral wire MPL1'' may be disposed at a level the same as that of a first upper conductive pattern PL1 in the cell region CA. In this example, the third peripheral conductive pattern MPL3a and the fourth peripheral conductive pattern MPL3b may be disposed at a level the same as that of a second upper conductive pattern PL2 in the cell region CA.

[0126] Intermediate contact plugs MCPa'' and MCPb'' may be disposed between the first peripheral wire MPL1'' and the third peripheral pattern MPL3a and the fourth peripheral pattern MPL3b. In this example, the intermediate contact plugs MCPa'' and MCPb'' may include a third intermediate contact plug MCPa'' and a fourth intermediate contact plug MCPb''. The third intermediate contact plug MCPa'' is disposed between the first peripheral wire MPL1'' and the third peripheral pattern MPL3a, and the fourth intermediate contact plug MCPb'' is disposed between the first peripheral wire MPL1'' and the fourth peripheral pattern MPL3b.

[0127] The bit line contact plug BCP may penetrate the first insulating layer ILD1 to the third insulating layer ILD3 and the etch stop layer 68, and may be electrically connected to the third peripheral pattern MPL3a.

[0128] The fourth peripheral pattern MPL3b may extend from the second peripheral region PA2 and may be disposed in the first peripheral region PA1. The fourth peripheral pattern MPL3b may be electrically connected to the peripheral circuits GSp, 5a, and 5b through the peripheral contact plug PCP''. In another exemplary embodiment, the fourth peripheral pattern MPL3b may be a structure in which a second peripheral pattern (e.g., Figure 2B the second peripheral pattern MPL2b in Figure 2C and a second peripheral wire (e.g.,

[0129] The first bit line BL1 may be electrically connected to the peripheral circuits GSp, 5a, and 5b through the bit line contact structures 80 and 81, the bit line contact plug BCP, the first peripheral wire MPL1'', the third conductive pattern MPL3a, and the fourth conductive pattern MPL3b.

[0130] Referring to Figure 6B , the second bit line BL2 may extend from the cell region CA to the second peripheral region PA2 and the first peripheral region PA1, and may be electrically connected to the peripheral circuits GSp, 5a, and 5b.

[0131] The bit line contact structures 80 and 81, the bit line contact plug BCP, the first peripheral wire MPL1'', the third peripheral pattern MPL3a, the fourth peripheral pattern MPL3b, and the peripheral contact plug PCP'' of the semiconductor device 100c according to the exemplary embodiment may be connection structures for electrically connecting the first bit line BL1 to the peripheral circuits GSp, 5a, and 5b.

[0132] The semiconductor device 100c according to an exemplary embodiment may include a first bit line BL1 and a second bit line BL2. The first bit line BL1 is electrically connected to the peripheral circuits GSp, 5a, and 5b through a connection structure. The second bit line BL2 extends to the first peripheral region PA1 and is directly electrically connected to the peripheral circuits GSp, 5a, and 5b.

[0133] Figure 7 is a cross-sectional view showing a first peripheral region of a semiconductor device according to an exemplary embodiment.

[0134] Referring to Figure 7 , in the semiconductor device 100d, components other than the 2-1 peripheral wire PPL a, the 2-2 peripheral wire PPL b, and the first peripheral contact plug PCP a, the second peripheral contact plug PCP b, and the third peripheral contact plug PCP c may be the same as or corresponding to the components shown in Figure 1B and Figure 2C . A repeated description of the same or corresponding components will not be provided.

[0135] The semiconductor device 100d may include a 2-1 peripheral wire PPL a and a 2-2 peripheral wire PPL b disposed in the first peripheral region PA1. In the example, the 2-1 peripheral wire PPL a may be electrically connected to the peripheral circuits GSp, 5a, and 5b through the first peripheral contact plug PCP a. The 2-2 peripheral wire PPL b may be disposed adjacent to the edge of the substrate 3 (e.g., closer to the edge of the substrate 3 than the 2-1 peripheral wire PPL a in the horizontal direction), and may be electrically connected to the conductive layer 72 through the second peripheral contact plug PCP b and the third peripheral contact plug PCP c.

[0136] First dummy conductive patterns DPL1a, DPL1b, and DPL1c may be disposed in a region adjacent to the 2-1 peripheral wire PPL a and the first peripheral contact plug PCP a. Second dummy conductive patterns DPL2a, DPL2b, and DPL2c may be disposed on the first dummy conductive patterns DPL1a, DPL1b, and DPL1c.

[0137] The first dummy conductive patterns DPL1a, DPL1b, and DPL1c may include a 1-1 dummy conductive pattern DPL1a, a 1-2 dummy conductive pattern DPL1b, and a 1-3 dummy conductive pattern DPL1c. The 1-1 dummy conductive pattern DPL1a and the 1-2 dummy conductive pattern DPL1b are disposed on one side of the 2-1 peripheral wire PPL a, and the 1-3 dummy conductive pattern DPL1c is disposed between the 2-1 peripheral wire PPL a and the 2-2 peripheral wire PPL b.

[0138] The first dummy conductive patterns DPL1a, DPL1b, and DPL1c may be disposed at the same level as the first upper conductive pattern PL1 in the cell region CA, and the second dummy conductive patterns DPL2a, DPL2b, and DPL2c may be disposed at the same level as the second upper conductive pattern PL2 in the cell region CA.

[0139] Dummy contact plugs DCP1, DCP2, and DCP3 that connect the first dummy conductive patterns DPL1a, DPL1b, and DPL1c to the second dummy conductive patterns DPL2a, DPL2b, and DPL2c may be disposed between the first dummy conductive patterns DPL1a, DPL1b, and DPL1c and the second dummy conductive patterns DPL2a, DPL2b, and DPL2c. The first dummy contact plug DCP1 may be disposed between the 1-1 dummy conductive pattern DPL1a and the 2-1 dummy conductive pattern DPL2a. The second dummy contact plug DCP2 may be disposed between the 1-2 dummy conductive pattern DPL1b and the 2-2 dummy conductive pattern DPL2b. The third dummy contact plug DCP3 may be disposed between the 1-3 dummy conductive pattern DPL1c and the 2-3 dummy conductive pattern DPL2c.

[0140] The first dummy conductive patterns DPL1a, DPL1b, and DPL1c and the second dummy conductive patterns DPL2a, DPL2b, and DPL2c may be disposed in a region having a relatively low interconnect density or in a region adjacent to an edge of the substrate 3.

[0141] The first dummy conductive patterns DPL1a, DPL1b, and DPL1c and the second dummy conductive patterns DPL2a, DPL2b, and DPL2c may be formed in a region adjacent to the 2-1 peripheral wire PPL a and the first peripheral contact plug PCPa, such that a defect in which the first peripheral contact plug PCPa is not open during the process of forming the first peripheral contact plug PCPa in the process of manufacturing the semiconductor device 100d can be solved.

[0142] Since the 1-3 dummy conductive pattern DPL1c and the 2-3 dummy conductive pattern DPL2c are disposed in a region adjacent to a plurality of peripheral contact plugs PCPb and PCPc, the 1-3 dummy conductive pattern DPL1c and the 2-3 dummy conductive pattern DPL2c can prevent corrosion of contact plugs disposed on the edges of the plurality of peripheral contact plugs PCPb and PCPc during the manufacturing process. Accordingly, by including the first dummy conductive patterns DPL1a, DPL1b, and DPL1C and the second dummy conductive patterns DPL2a, DPL2b, and DPL2c according to the exemplary embodiment, a semiconductor device having improved reliability can be provided.

[0143] Figure 8Ais a plan view showing a cell connection structure disposed in a cell region of a semiconductor device and a peripheral connection structure disposed in a peripheral region according to an exemplary embodiment. Figure 8B is a view showing according to an exemplary embodiment Figure 8A a perspective view of the peripheral connection structure shown in

[0144] Referring to Figure 8A , the semiconductor device 100e may include a cell region CA and peripheral regions (e.g., Figure 1B peripheral regions PA1 and PA2 in ), and in the peripheral regions PA1 and PA2, a plurality of sub-word line driver blocks SWD may be arranged in a direction in which word lines extend, and sense amplifier blocks (S / A) may be arranged in a direction in which bit lines extend.

[0145] A connection block CJT may be arranged at a point where the sub-word line driver block SWD and the sense amplifier block (S / A) intersect. A power driver and a ground driver for driving a bit line sense amplifier may be alternately provided in the connection block CJT.

[0146] Referring to Figure 8A , a cell interconnect structure CLS extending in a first direction (X direction) may be provided on the cell region CA. In one example, a peripheral interconnect structure PLS passing through the sense amplifier block (S / A) and electrically connecting the connection blocks CJT to each other may be provided on the peripheral regions (e.g., Figure 1B peripheral regions PA1 and PA2 in ).

[0147] The peripheral interconnect structure PLS may include a plurality of peripheral interconnects spaced apart from each other in a second direction (Y direction). In one example, the peripheral interconnect structure PLS may extend in the same direction as the cell interconnect structure CLS. However, embodiments of the peripheral interconnect structure PLS are not limited thereto. For example, the peripheral interconnect structure PLS may extend in the first direction (X direction) or the second direction (Y direction).

[0148] Each of the peripheral interconnects in the peripheral interconnect structure PLS may be electrically connected to a first contact hole CNT and a second contact hole CNT', the first contact hole CNT being connected to a connection block CJT provided on one side of the sense amplifier block (S / A), and the second contact hole CNT' being connected to a connection block CJT provided on the other side of the sense amplifier block (S / A).

[0149] The peripheral interconnect structure PLS may include a first peripheral interconnect structure PLSa and a second peripheral interconnect structure PLSb spaced apart from the first peripheral interconnect structure PLSa.

[0150] The first peripheral interconnection structure PLSa can be electrically connected to the first contact hole CNTa and the second contact hole CNTa', and the first contact hole CNTa and the second contact hole CNTa' electrically connect the connection blocks CJT disposed on both sides of the sense amplifier block (S / A) to each other. The first peripheral interconnection structure PLSa can include multiple wires and can form a signal path having via holes VIAa and VIAb. The multiple wires include the first peripheral wire MPL1 and multiple upper wires.

[0151] The second peripheral interconnection structure PLSb can be electrically connected to the first contact hole CNTb and the second contact hole CNTb', and the first contact hole CNTb and the second contact hole CNTb' electrically connect the connection blocks CJT disposed on both sides of the sense amplifier block (S / A) to each other. The second peripheral interconnection structure PLSb can form a signal path having a single wire (or pattern) and via holes VIAa and VIAb connected to the single wire.

[0152] The first peripheral interconnection structure PLSa and the second peripheral interconnection structure PLSb can be alternately arranged. However, the exemplary embodiments of the first peripheral interconnection structure PLSa and the second peripheral interconnection structure PLSb are not limited thereto, and the arrangement of the peripheral interconnection structure PLS can vary.

[0153] Figure 8B An exemplary electrical connection relationship between the second peripheral interconnection structure PLSb and the first peripheral interconnection structure PLSa disposed between the second peripheral interconnection structures PLSb is shown.

[0154] The first peripheral wire MPL1, the first upper peripheral wire MPL4a, and the second upper peripheral wire MPL4b spaced apart from each other in the second direction (Y direction) can form the second peripheral interconnection structure PLSb. In an exemplary embodiment, the first upper peripheral wire MPL4a and the second upper peripheral wire MPL4b can be collectively referred to as the third peripheral wire.

[0155] The first peripheral wire MPL1 and the first peripheral patterns MPL2a and MPL2b can be disposed between the first upper peripheral wire MPL4a and the second upper peripheral wire MPL4b. In this example, the first upper peripheral wire MPL4a and the second upper peripheral wire MPL4b can extend in the first direction (X direction) and can be spaced apart from each other in the second direction (Y direction) by the first peripheral patterns MPL2a and MPL2b.

[0156] The intermediate contact plugs MCPa and MCPb can connect the first peripheral wire MPL1 to the first peripheral patterns MPL2a and MPL2b, and the first peripheral wire MPL1 and the first peripheral patterns MPL2a and MPL2b can form the first peripheral interconnection structure PLSa.

[0157] The first upper peripheral line MPL4a and the second upper peripheral line MPL4b may be disposed at the same level as the first peripheral pattern MPL2a and the second peripheral pattern MPL2b.

[0158] The lengths of the first upper peripheral line MPL4a and the second upper peripheral line MPL4b in the first direction (X direction) may be equal to or less than the interval distance between the first peripheral pattern MPL2a and the second peripheral pattern MPL2b in the first direction (X direction). In one example, the first upper peripheral line MPL4a and the second upper peripheral line MPL4b may not overlap with the first peripheral pattern MPL2a and the second peripheral pattern MPL2b in the second direction (Y direction).

[0159] The first peripheral wire MPL1 may be disposed at a level lower than the levels of the first upper peripheral line MPL4a and the second upper peripheral line MPL4b in the vertical direction.

[0160] The first upper peripheral line MPL4a (or the second upper peripheral line MP4b) may be electrically connected to the connection block CJT through a single interconnect.

[0161] The electrical signals of the first peripheral pattern MPL2a and the second peripheral pattern MPL2b may be connected to each other through the intermediate contact plugs MCPa and MCPb and the first peripheral wire MPL1.

[0162] The first peripheral wire MPL1, the first upper peripheral line MPL4a, and the second upper peripheral line MPL4b may have a first width W1 in the second direction (Y direction).

[0163] In the semiconductor device 100e, the width of the sense amplifier block (S / A) in which the peripheral interconnect structure PLS is provided may be a first width H1. The first upper peripheral line MPL4a and the second upper peripheral line MPL4b may be spaced apart from each other by a first length D1 in the second direction (Y direction), and the first peripheral pattern MPL2a and the second peripheral pattern MPL2b are disposed between the first upper peripheral line MPL4a and the second upper peripheral line MPL4b.

[0164] Figure 9A is a plan view showing a cell connection structure provided in a cell region of a semiconductor device and a peripheral connection structure provided in a peripheral region according to an exemplary embodiment. Figure 9B is a view showing according to an exemplary embodiment Figure 9A of the peripheral connection structure in

[0165] Referring to Figure 9A and Figure 9B, in the semiconductor device 100e-1, the width of the sense amplifier block (S / A) in which the peripheral interconnection structure PLS is provided may have a second width H2. The first upper peripheral line MPL4a and the second upper peripheral line MPL4b may be spaced apart from each other by a second length D2 in the second direction (Y direction), and the first peripheral pattern MPL2a and the second peripheral pattern MPL2b are disposed between the first upper peripheral line MPL4a and the second upper peripheral line MPL4b.

[0166] Referring to Figure 8A and Figure 9A , the second width H2 of the sense amplifier block (S / A) of the semiconductor device 100e-1 may be smaller than the first width H1 of the sense amplifier block (S / A) of the semiconductor device 100e. The area of the sense amplifier block (S / A) in the semiconductor device 100e-1 in which the peripheral interconnection structure PLS is provided may be smaller than the area of the sense amplifier block (S / A) in the semiconductor device 100e in which the peripheral interconnection structure PLS is provided. By moving one of the peripheral lines (MPL1) to a level lower than the other peripheral lines MPL4a and MPL4b, all these lines (as viewed from a plan view) may be closer to each other in the Y direction without the possibility of short circuit or interference with each other.

[0167] Therefore, the semiconductor device according to the exemplary embodiment can reduce the width of the sense amplifier block (S / A) in the horizontal direction (Y direction) by forming a circuit path through the first peripheral interconnection structure PLSa, thereby improving the integration density of the semiconductor device.

[0168] Figure 10A is a plan view showing a cell connection structure provided in a cell region of a semiconductor device and a peripheral connection structure provided in a peripheral region according to an exemplary embodiment. Figure 10B is a view showing according to an exemplary embodiment Figure 10A a perspective view of the peripheral connection structure in

[0169] Referring to Figure 10A and Figure 10B , the semiconductor device 100e-2 may include a peripheral interconnection structure PLS'. The peripheral interconnection structure PLS' may include a first peripheral interconnection structure PLSa and a second peripheral interconnection structure PLSb' spaced apart from the first peripheral interconnection structure PLSa.

[0170] Referring to Figure 10B , shows the electrical connection relationship between the first peripheral interconnection structure PLSa and the second peripheral interconnection structure PLSb' provided between the second peripheral interconnection structures PLSb'.

[0171] Each of the first upper peripheral line MPL4a' and the second upper peripheral line MPL4b' may form the second peripheral interconnection structure PLSb'.

[0172] The semiconductor device 100e-2 may include a first peripheral wire MPL1 having a first width W1, and a first upper peripheral wire MPL4a' and a second upper peripheral wire MPL4b' having a second width W2 greater than the first width W1.

[0173] In the semiconductor device 100e-2 according to an exemplary embodiment, a first peripheral pattern MPL2a and a second peripheral pattern MPL2b may be spaced apart from each other in a first direction (X direction), and may be electrically connected to each other through the first peripheral wire MPL1, such that a space in which an interconnect is disposed may be ensured by an interval between the first peripheral pattern MPL2a and the second peripheral pattern MPL2b. In this example, the first peripheral pattern MPL2a and the second peripheral pattern MPL2b may have a width greater than the width of the first peripheral wire MPL1 in a second direction (Y direction).

[0174] Figure 11 is a plan view showing a cell connection structure provided in a cell region of a semiconductor device and a peripheral connection structure provided in a peripheral region according to an exemplary embodiment.

[0175] Referring to Figure 11 , the peripheral interconnect structure PLS'' may include a first peripheral interconnect structure PLSa and a second peripheral interconnect structure PLSb'' spaced apart from the first peripheral interconnect structure PLSa.

[0176] The second peripheral interconnect structure PLSb'' may have the same structure as that of the first peripheral interconnect structure PLSa. The first peripheral interconnect structure PLSa and the second peripheral interconnect structure PLSb'' may correspond to first contact holes CNTa and CNTb and second contact holes CNTa' and CNTb' that electrically connect connection blocks CJT disposed on both sides of a sense amplifier block (S / A) to each other. The first peripheral interconnect structure PLSa and the second peripheral interconnect structure PLSb'' may include a plurality of wires, and may form a circuit path along vias VIAa and VIAb, and the plurality of wires include the first peripheral wire MPL1 and a plurality of wires above.

[0177] Figures 12A to 12D is a view showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0178] Referring to Figure 12A, a capacitor CAP can be formed on the etch stop layer 68 formed in the cell region CA during the formation of the substrate 3. An interlayer insulating layer ILD1 can be formed on the side surfaces of the capacitor CAP on the substrate 3. In one example, the interlayer insulating layer ILD1 can be formed on the outer side surfaces of the upper electrode 173. The interlayer insulating layer ILD1 may not cover the upper surface (e.g., the topmost vertical-facing surface) of the upper electrode 173.

[0179] The upper surface (e.g., the topmost surface) of the upper electrode 173 can be formed at the same level as the upper surface (e.g., the topmost surface) of the interlayer insulating layer ILD1. In one example, since a CMP process can be performed on the upper electrode 173 and the interlayer insulating layer ILD1 to planarize the interlayer insulating layer ILD1 across the cell region CA and the first peripheral region PA1 and the second peripheral region PA2, the upper surface of the upper electrode 173 can be at the same level as the upper surface of the interlayer insulating layer ILD1.

[0180] A cell gate structure GS, a bit line BL, and a bit line capping layer BC can be formed below the etch stop layer 68.

[0181] Referring to Figure 12B , a first plate PL1p can be formed on the upper electrode 173 and the interlayer insulating layer ILD1 through the cell region CA and the first peripheral region PA1 and the second peripheral region PA2. In one example, the first plate PL1p can include a first preliminary barrier layer PL1ap and a first preliminary electrode layer PL1bp formed on the first preliminary barrier layer PL1ap.

[0182] Referring to Figure 12C , by removing a part of the first plate PL1p, a first upper conductive pattern PL1 on the cell region CA, a first dummy conductive pattern DPL1 on the first peripheral region PA1, and a first peripheral wire MPL1 on the second peripheral region PA2 can be formed.

[0183] By exposing a part of the first plate PL1p using a mask layer (not shown) to remove a part of the first preliminary barrier layer PL1ap and the first preliminary electrode layer PL1bp, the first upper conductive pattern PL1, the first dummy conductive pattern DPL1, and the first peripheral wire MPL1 can be formed. The mask layer can be configured as a hard mask layer. The first upper conductive pattern PL1, the first dummy conductive pattern DPL1, and the first peripheral wire MPL1 can be spaced apart from each other in one direction. In the example, the first dummy conductive pattern DPL1 and the first peripheral wire MPL1 can be formed by the same process as the process of forming the first upper conductive pattern PL1. In the example, the first upper conductive pattern PL1, the first dummy conductive pattern DPL1, and the first peripheral wire MPL1 can be formed at substantially the same level.

[0184] The upper surface of the upper electrode 173 may be covered by the first upper conductive pattern PL1, and the upper surface of the upper electrode 173 may not be exposed (e.g., may not be completely exposed). The first upper conductive pattern PL1 may be formed on the upper surface of the upper electrode 173, and the first upper conductive pattern PL1 may be in contact with the upper electrode 173.

[0185] Referring to Figure 12D , a second insulating layer ILD2 may be formed to fill the gaps between the first upper conductive pattern PL1, the first dummy conductive pattern DPL1, and the first peripheral wire MPL1. A third insulating layer ILD3 may be formed on the first upper conductive pattern PL1, the first dummy conductive pattern DPL1, and the first peripheral wire MPL1.

[0186] An upper contact plug CCP may be formed on the first upper conductive pattern PL1. Intermediate contact plugs MCPa and MCPb may be formed on the first peripheral wire MPL1. A dummy contact plug DCP may be formed on the first dummy conductive pattern DPL1. In this example, the upper surfaces of the upper contact plug CCP, the intermediate contact plugs MCPa and MCPb, and the dummy contact plug DCP may be coplanar with the upper surface of the third insulating layer ILD3.

[0187] A second upper conductive pattern PL2 may be formed on the upper contact plug CCP. First and second peripheral patterns MPL2a and MPL2b may be formed on the intermediate contact plugs MCPa and MCPb. A second dummy conductive pattern DPL2 may be formed on the dummy contact plug DCP. In this example, the second upper conductive pattern PL2, the first and second peripheral patterns MPL2a and MPL2b, and the second dummy conductive pattern DPL2 may be formed by the same process.

[0188] In the method of manufacturing a semiconductor device according to an exemplary embodiment, in the process of forming the first upper conductive pattern PL1 and the second upper conductive pattern PL2 on the cell region CA, the first peripheral wire MPL1 and the first and second peripheral patterns MPL2a and MPL2b may be formed on the second peripheral region PA2. In addition, the first and second peripheral patterns MPL2a and MPL2b may provide a circuit path to the first peripheral wire MPL1 disposed below the first and second peripheral patterns MPL2a and MPL2b, thereby reducing the number of processes and ensuring an effective interconnection space.

[0189] In addition, dummy pattern structures DPL1, DPL2, and DCP may be disposed on the first peripheral region PA1, and the dummy pattern structures DP1, DPL2, and DCP may be structures formed in the processes of forming the first upper conductive pattern PL1 and the second upper conductive pattern PL2, and the dummy pattern structures DP1, DPL2, and DCP may solve corrosion of the peripheral contact plug PCP and poor electrical connection with the peripheral circuit, such that a semiconductor device having improved reliability may be provided.

[0190] According to the foregoing exemplary embodiment, in a semiconductor device including a capacitor, since a circuit path is provided by the peripheral conductive pattern disposed in the peripheral region adjacent to the cell region together with the first peripheral pattern and the second peripheral pattern disposed on the peripheral conductive pattern, a semiconductor device having an increased integration density may be provided.

[0191] In addition, in a semiconductor device including a capacitor, by including a dummy pattern disposed adjacent to the peripheral contact plug connected to the peripheral circuit, damage to the peripheral contact plug during the manufacturing process may be solved, such that a semiconductor device having increased reliability may be provided.

[0192] Although the exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: A substrate including a first region and a second region; A capacitor on the first region of the substrate, wherein the capacitor includes a lower electrode, a support layer connected to the lower electrode, a dielectric layer covering the support layer and the lower electrode, and an upper electrode on the dielectric layer; A first upper conductive pattern in contact with the upper surface of the upper electrode; A second upper conductive pattern on the first upper conductive pattern; An upper contact plug between the first upper conductive pattern and the second upper conductive pattern; An interlayer insulating layer provided on the second region of the substrate and on the outer surface of the upper electrode; and A first peripheral wire provided on the interlayer insulating layer and at a vertical level the same as at least a part of the first upper conductive pattern.

2. The semiconductor device according to claim 1, further comprising: A first peripheral pattern and a second peripheral pattern provided on the first peripheral wire and spaced apart from each other; And A plurality of intermediate contact plugs respectively provided between each of the first peripheral pattern and the second peripheral pattern and the first peripheral wire, wherein the first peripheral pattern and the second peripheral pattern are provided at a vertical level the same as at least a part of the second upper conductive pattern.

3. The semiconductor device according to claim 2, Among them, The second upper conductive pattern extends in a first direction, and wherein the first peripheral pattern and the second peripheral pattern are spaced apart from each other in the first direction.

4. The semiconductor device according to claim 2, wherein, The second region is between the first region and the edge of the substrate and is adjacent to the edge of the substrate.

5. The semiconductor device according to claim 2, further comprising: A second peripheral wire provided on the second region of the substrate and at a vertical level the same as the vertical level of the second upper conductive pattern; A peripheral contact plug penetrating the interlayer insulating layer, extending upward, and connected to the second peripheral wire; And A peripheral circuit provided at a vertical level lower than the vertical level of the interlayer insulating layer and electrically connected to the peripheral contact plug.

6. The semiconductor device according to claim 5, further comprising: A first etch stop layer provided on the peripheral circuit; And A second etch stop layer provided on the first etch stop layer, wherein the peripheral contact plug further includes: A first peripheral contact plug having an outer side surface covered by the second etch stop layer, penetrating the first etch stop layer, and electrically connected to the peripheral circuit; and A second peripheral contact plug penetrating the interlayer insulating layer and the second etch stop layer and electrically connected to the first peripheral contact plug.

7. The semiconductor device according to claim 5, wherein, The first peripheral pattern and the second peripheral pattern are provided between the second upper conductive pattern and the second peripheral wire.

8. The semiconductor device according to claim 5, further comprising: A dummy structure provided on one side of the second peripheral wire and configured to be in a floating state, wherein the dummy structure includes: A first dummy pattern in the second region and at a vertical level the same as the vertical level of the first peripheral wire; A second dummy pattern provided at a vertical level the same as the vertical level of the second peripheral wire and stacked with the first dummy pattern in the vertical direction; and A dummy contact plug connecting the first dummy pattern to the second dummy pattern, Among them, the second peripheral wire is disposed between the second dummy pattern and the second peripheral pattern.

9. The semiconductor device according to claim 5, further comprising: a bit line disposed at a vertical level lower than the vertical levels of the capacitor and the interlayer insulating layer; a bit line contact structure electrically connected to the bit line extending to the second region; and a bit line contact plug penetrating the interlayer insulating layer upward from the bit line contact structure disposed below the interlayer insulating layer and connected to the first peripheral pattern.

10. The semiconductor device according to claim 9, wherein, The second peripheral pattern and the second peripheral wire are integrated with each other.

11. The semiconductor device according to any one of claims 1 to 10, wherein, The upper surface of the interlayer insulating layer is disposed at the same vertical level as the upper surface of the upper electrode.

12. The semiconductor device according to any one of claims 1 to 10, wherein, The first upper conductive pattern and the first peripheral wire include a first interconnect material layer and a first barrier layer, and the first barrier layer covers the side surface and the bottom surface of the first interconnect material layer.

13. The semiconductor device according to any one of claims 1 to 10, Among them, the first upper conductive pattern includes at least one of tungsten and silicon germanium, and wherein the second upper conductive pattern includes copper.

14. A semiconductor device, comprising: a substrate including a cell region and a peripheral region; a bit line and a memory structure disposed on the cell region, and the memory structure is disposed at a vertical level higher than the vertical level of the bit line; a peripheral circuit disposed on the peripheral region; a first upper conductive pattern disposed on the memory structure on the cell region; a second upper conductive pattern on the first upper conductive pattern; a first peripheral wire extending in a first direction on the peripheral region and disposed at the same vertical level as at least a part of the first upper conductive pattern; a first peripheral pattern and a second peripheral pattern disposed on the first peripheral wire at the same vertical level as at least a part of the second upper conductive pattern and spaced apart from each other in the first direction; a first intermediate contact plug disposed between the first peripheral wire and the first peripheral pattern; and a second intermediate contact plug disposed between the first peripheral wire and the second peripheral pattern.

15. The semiconductor device according to claim 14, further comprising: a second peripheral wire disposed at the same vertical level as the first peripheral pattern and the second peripheral pattern on the peripheral region, arranged side by side with the first peripheral pattern and the second peripheral pattern in a second direction intersecting the first direction, and extending in the first direction.

16. The semiconductor device according to claim 15, wherein, The width of the second peripheral wire in the second direction is greater than the width of the first peripheral wire in the second direction.

17. The semiconductor device according to claim 15, wherein, At least a part of the second peripheral wire overlaps with the first peripheral wire in the vertical direction.

18. A semiconductor device, comprising: a substrate including a cell region and a peripheral region surrounding the cell region; a bit line disposed on the cell region; a capacitor disposed on the cell region and disposed at a vertical level higher than the vertical level of the bit line, wherein the capacitor includes a plurality of lower electrode structures, a support layer between the plurality of lower electrode structures, a dielectric layer covering the plurality of lower electrode structures, and an upper electrode on the dielectric layer; a first upper conductive pattern in contact with the upper surface of the upper electrode and vertically located above the upper surface of the upper electrode; A second upper conductive pattern, on the first upper conductive pattern; An upper contact plug, electrically connecting the first upper conductive pattern to the second upper conductive pattern; A first interlayer insulating layer, disposed on the peripheral region and on an outer side surface of the upper electrode; A first peripheral wire, disposed on the first interlayer insulating layer and at a vertical level the same as at least a part of the first upper conductive pattern; A first peripheral pattern and a second peripheral pattern, disposed at a vertical level the same as at least a part of the second upper conductive pattern on the first peripheral wire and spaced apart from each other; and A plurality of intermediate contact plugs, respectively disposed between each of the first peripheral pattern and the second peripheral pattern and the first peripheral wire.

19. The semiconductor device according to claim 18, wherein, The first interlayer insulating layer contacts an outer side surface of the upper electrode and exposes an upper surface of the upper electrode.

20. The semiconductor device according to claim 18, wherein The first peripheral pattern and the second peripheral pattern are stacked with the first peripheral wire in a vertical direction.

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