Method for forming field effect transistor and semiconductor device

Abstract

The invention relates to the technical field of semiconductors, and discloses a method for forming a field effect transistor and a semiconductor device. The invention discloses a method for forming a field effect transistor. The method comprises the following steps: forming a source region on a substrate; forming a drain region on the substrate; forming a channel region on the substrate; forming a compound film on the channel region as a gate dielectric layer; and forming a gate on the gate dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a method for forming a field effect transistor and a semiconductor device. Background Art

[0002] As Moore's Law approaches the physical limit, the manufacturing process of traditional field effect transistors faces many challenges, such as the problem of increased gate leakage current, which restricts the further improvement of device performance. Summary of the Invention

[0003] The present disclosure provides a method for forming a field effect transistor, including: forming a source region on a substrate; forming a drain region on the substrate; forming a channel region on the substrate; forming a compound film on the channel region as a gate dielectric layer; and forming a gate on the gate dielectric layer.

[0004] The present disclosure provides another method for forming a field effect transistor, including: forming a gate on a substrate; forming a compound film on the substrate as a gate dielectric layer; forming a channel layer on the gate dielectric layer; and forming a source region and a drain region on the substrate, the gate dielectric layer or the channel layer.

[0005] The present disclosure also provides a semiconductor device, including: a field effect transistor formed by the method for forming a field effect transistor according to any embodiment of the present disclosure. Brief Description of the Drawings

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only one embodiment of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0007] Figure 1A A flowchart showing a method for forming a field effect transistor according to some embodiments of the present disclosure;

[0008] Figure 1B A flowchart showing a method for forming a field effect transistor according to other embodiments of the present disclosure;

[0009] Figure 1C A flowchart showing a method for forming a gate dielectric layer according to some embodiments of the present disclosure;

[0010] Figure 1D A flowchart showing a method for forming a gate dielectric layer according to some embodiments of the present disclosure;

[0011] Figure 1ESchematic structural diagram of a field-effect transistor obtained by a method of forming a field-effect transistor according to some embodiments of the present disclosure;

[0012] Figure 1F Schematic structural diagram of a field-effect transistor obtained by a method of forming a field-effect transistor according to other embodiments of the present disclosure;

[0013] Figure 1G Exemplary flowchart showing a method of forming a compound film according to some embodiments of the present disclosure;

[0014] Figure 1H Exemplary flowchart showing a method of forming a compound film according to still other embodiments of the present disclosure;

[0015] Figure 2A Schematic structural diagram of an active source according to some embodiments of the present disclosure;

[0016] Figure 2B Partial schematic structural diagram of an active source according to some embodiments of the present disclosure;

[0017] Figure 2C Showing according to some embodiments of the present disclosure along Figure 2B Cross-sectional view taken along A-A;

[0018] Figure 2D Showing according to other embodiments of the present disclosure along Figure 2B Cross-sectional view taken along A-A;

[0019] Figure 3A Schematic structural diagram of an active source according to other embodiments of the present disclosure;

[0020] Figure 3B Showing according to some embodiments of the present disclosure along Figure 3A Cross-sectional view taken along D-D;

[0021] Figure 3C Showing according to other embodiments of the present disclosure along Figure 3A Cross-sectional view taken along D-D;

[0022] Figure 4 Partial schematic structural diagram of an electromagnetic field generator according to some embodiments of the present disclosure;

[0023] Figure 5 Partial enlarged view of the structure of an electromagnetic field generator according to some embodiments of the present disclosure;

[0024] Figure 6 Showing according to some embodiments of the present disclosure Figure 2C or Figure 2D Enlarged schematic view of part A;

[0025] Figure 7A An enlarged schematic view of another angle of part B of Figure 2C shown in accordance with some embodiments of the present disclosure;

[0026] Figure 7B An enlarged schematic view of another angle of part B of Figure 2D shown in accordance with some embodiments of the present disclosure;

[0027] Figure 8 A cross-sectional schematic view of a current-limiting tube shown in accordance with some embodiments of the present disclosure;

[0028] Figure 9 A structural schematic view of a flow-dividing tube shown in accordance with some embodiments of the present disclosure;

[0029] Figure 10A An enlarged schematic view of another angle of part A of Figure 2C shown in accordance with some embodiments of the present disclosure;

[0030] Figure 10B An enlarged schematic view of another angle of part A of Figure 2C shown in accordance with some embodiments of the present disclosure;

[0031] Figure 11A An enlarged schematic view of another angle of part B of Figure 2C shown in accordance with some embodiments of the present disclosure;

[0032] Figure 11B An enlarged schematic view of another angle of part B of Figure 2D shown in accordance with some embodiments of the present disclosure;

[0033] Figure 12 A cross-sectional schematic view of a partition block shown in accordance with some embodiments of the present disclosure;

[0034] Figure 13A A partial cross-sectional schematic view of an active source shown in accordance with some embodiments of the present disclosure;

[0035] Figure 13B A partial cross-sectional schematic view of an active source including a neutralizer shown in accordance with some other embodiments of the present disclosure;

[0036] Figure 14 A schematic view of a sealing structure in the case where the outer side surface of a sealing ring may include a conical surface shown in accordance with some embodiments of the present disclosure;

[0037] Figure 15 A schematic view of a sealing structure in the case where the outer side surface of a sealing ring may include an arc surface shown in accordance with some embodiments of the present disclosure.

[0038] Figure 16 A structural schematic view of the position setting of a magnet fixing mechanism shown in accordance with some embodiments of the present disclosure;

[0039] Figure 17A Shows a schematic structural diagram of a magnetic field confinement mechanism according to some embodiments of the present disclosure;

[0040] Figure 17B Shows Figure 17A B-B sectional view of;

[0041] Figure 18A Shows a partial schematic structural diagram of an active source according to some other embodiments of the present disclosure;

[0042] Figure 18B Shows Figure 18A C-C sectional view of;

[0043] Figure 19 Shows a three-dimensional schematic structural diagram of an active source according to some embodiments of the present disclosure;

[0044] Figure 20 A-C shows the geometric arrangement diagram of the magnet during simulation according to some embodiments of the present disclosure, where Figure 20 A shows the x-y plane arrangement diagram of the magnet; Figure 20 B shows the x-z plane arrangement diagram of the magnet; Figure 20 C shows the three-dimensional arrangement diagram of the magnet;

[0045] Figure 21 A-C shows the multi-section magnetic field spatial distribution obtained after magnet simulation according to some embodiments of the present disclosure, where Figure 21 A shows the multi-section magnetic field spatial distribution in the x-y plane; Figure 21 B shows the multi-section magnetic field spatial distribution in the x-z plane; Figure 21 C shows the three-dimensional multi-section magnetic field spatial distribution;

[0046] Figure 22 A-C shows the surface magnetic field spatial distribution obtained after magnet simulation according to some embodiments of the present disclosure, where Figure 22 A shows the surface magnetic field spatial distribution in the x-y plane; Figure 22 B shows the surface magnetic field spatial distribution in the x-z plane; Figure 22 C shows the surface magnetic field spatial distribution in the y-z plane;

[0047] Figure 23 A-C shows the line result diagram obtained after magnet simulation according to some embodiments of the present disclosure, where Figure 23 A shows the line result diagram of the x-axis; Figure 23 B shows the line result diagram of the y-axis; Figure 23 C shows the line result diagram of the z-axis;

[0048] Figure 24Shows the change of the charged particle beam current before and after adding a neutralizer to the active source 100 according to some embodiments of the present disclosure;

[0049] Figure 25A Shows a schematic structural diagram of a vacuum system according to some embodiments of the present disclosure;

[0050] Figure 25B Shows a schematic diagram of the epitaxial growth process of a vacuum system according to some embodiments of the present disclosure;

[0051] Figure 26 A shows that the RHEED diffraction pattern of Si(111) at room temperature after removing the surface oxide at 920°C presents a 7*7 diffraction spot;

[0052] Figure 26 B shows the RHEED diffraction pattern of Si(111) taken at 920°C after removing the surface oxide at 920°C;

[0053] Figure 27 Shows the RHEED diffraction pattern after depositing a 7nm single-crystal Al film on the Si(111) surface;

[0054] Figure 28 Shows the RHEED diffraction pattern after nitriding the surface of the single-crystal Al film for 5 minutes;

[0055] Figure 29 Shows the RHEED diffraction pattern of GaN(001) after heating and degassing;

[0056] Figure 30 Shows the RHEED diffraction pattern after depositing a single-crystal Al film on the GaN(001) surface;

[0057] Figure 31 Shows the RHEED diffraction pattern after nitriding the surface of the single-crystal Al film for 30 minutes;

[0058] Figure 32A Shows the (002) plane rocking curve of the GaN thin film epitaxially grown at different temperatures;

[0059] Figure 32B Shows a scanning electron microscope cross-sectional view of the GaN thin film epitaxially grown at 350°C;

[0060] In the above-mentioned drawings, each reference numeral represents respectively:

[0061] 10000, 10000a - field effect transistor, 110, 110a - substrate, 120, 120a - source region, 130, 130a - drain region, 140 - channel region, 140a - channel layer, 150, 150a - gate dielectric layer, 160, 160a - gate, 170a - dielectric layer covering the substrate

[0062] 1000 - Vacuum system, 100, 100a - Active source, 10, 10a - Electromagnetic field generator, 11, 11a - Radio frequency power supply, 12 - Conduction line, 121 - Feeding line, 1211 - Feeding end, 122, 122a - Inductive coil, 123 - Grounding line, 13 - Electrode feedthrough, 14 - First connecting member, 15 - Support block, 16 - Signal shielding cover, 18, 18a - Limit block, 19, 19a - Shielding housing, 20, 20a - Plasma generation chamber, 21, 21a - Chamber, 22, 22a - Shrinkage section, 23 - Limiting assembly, 231 - First limiting member, 232 - Second limiting member, 30, 30a - Gas introduction assembly, 31, 31a - Outer tube, 311 - Near end, 32 - Partition block, 321 - First connection channel, 322 - Second connection channel, 33 - Intake inner tube, 331 - Main body, 332 - Expansion section, 34 - Flow limiting tube, 341 - First gas channel, 342 - Second gas channel, 35 - Shunt tube, 351, 351a, 351b, 351c, 351d - Shunt holes, 40, 40a - Cooling device, 41, 41a - Liquid inlet, 42 - First connecting pipe, 43 - Second connecting pipe, 44, 44a - Liquid outlet, 45 - Third connecting pipe, 46 - Fourth connecting pipe, 50, 50a - Support mechanism, 51, 51a - Support flange, 52 - Straight flange, 60, 60a - Neutralizer, 61 - Through hole, 62 - Main body, 70, 70a - Sealing assembly, 71 - Sealing ring, 72 - Sealing nut, 80 - Electrode, 90 - Magnetic field constraint mechanism, 91 - Magnet, 91a, 91b - Magnet group, 911a - First row of magnets, 911b - Second row of magnets, 911c - Third row of magnets, 92 - Magnet cooling mechanism, 921 - Inner magnet cooling tube, 922 - Outer magnet cooling tube, 923 - Liquid inlet pipe, 924 - Liquid outlet pipe, 925 - Magnetic field inner liquid outlet pipe, 926 - Magnet cooling channel, 93 - Flange, 94 - Magnet fixing mechanism, 941 - Fixing ring, 942 - Support portion, 200 - Vacuum chamber, 210 - Heater, 300 - Sample, 400 - Deposition source Detailed implementation manners

[0063] Some embodiments of the present disclosure will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only exemplary embodiments of the present disclosure, rather than all embodiments.

[0064] In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "top", "bottom", "transverse", "longitudinal", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present disclosure. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In the description of the present disclosure, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the communication inside two elements. In the description of the present disclosure, the distal end or the far side refers to the end or side that extends deep into the vacuum environment (for example, the vacuum chamber), and the proximal end or the near side is the end or side opposite to the distal end or the far side (for example, the end or side away from the vacuum chamber, or the end or side near the vacuum chamber wall inside the vacuum chamber, etc.). Alternatively, the end or side close to the driving device is the proximal end or the near side, and the end or side away from the driving device is the distal end or the far side. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0065] Figure 1A A flowchart showing a method S10 for forming a field effect transistor according to some embodiments of the present disclosure.

[0066] As Figure 1A shown, in some embodiments of the present disclosure, the method S10 for forming a field effect transistor may include step S11 - step S15. In step S11, a source region is formed on the substrate. In step S12, a drain region is formed on the substrate. In step S13, a channel region is formed on the substrate. In step S14, a compound film is formed on the channel region as the gate dielectric layer. In step S15, a gate is formed on the gate dielectric layer.

[0067] In some embodiments of the present disclosure, the substrate 110 may employ a conventional semiconductor substrate. The substrate 110 may include materials such as silicon wafers, quartz, mica, glass, alumina, ceramics, plastics, polyimides, etc. according to specific application requirements and the like.

[0068] In some embodiments of the present disclosure, the material of the gate dielectric layer may include any one or more of materials such as aluminum nitride (AlN), aluminum oxide (Al2O3), gallium oxide (Ga2O3), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), silicon dioxide (SiO2), silicon nitride (Si3N4), etc.

[0069] In some embodiments of the present disclosure, the material of the gate may include metal materials (e.g., silver (Ag), platinum (Pt), gold (Au), aluminum (Al), copper (Cu), titanium (Ti), scandium (Sc), yttrium (Y), chromium (Cr), nickel (Ni), etc.). The gate material may also include non-metal materials (e.g., doped polysilicon, etc.).

[0070] Figure 1E FIG. shows a schematic structural diagram of a field effect transistor 10000 obtained by a method of forming a field effect transistor according to some embodiments of the present disclosure.

[0071] Below, taking Figure 1E the field effect transistor 10000 shown as an example, the method S10 of forming a field effect transistor according to some embodiments of the present disclosure will be further described.

[0072] As Figure 1E shown, in some embodiments of the present disclosure, the field effect transistor 10000 may include a substrate 110, a source region 120, a drain region 130, a channel region 140, a gate dielectric layer 150, and a gate 160. In some embodiments of the present disclosure, the source region 120, the drain region 130, and the channel region 140 are all disposed on the substrate. The gate dielectric layer 150 is formed on the channel region 140. The gate 160 is formed on the gate dielectric layer 150.

[0073] Those skilled in the art can understand that, in some embodiments of the present disclosure, the field effect transistor 10000 may further include a source electrode coupled to the source region 120 and a drain electrode coupled to the drain region 130 (not shown in the figure).

[0074] As Figure 1E shown, in some embodiments of the present disclosure, the method S10 of forming a field effect transistor may include: in step S11, forming the source region 120 on the substrate 110. In step S12, forming the drain region 130 on the substrate 110. In step S13, forming the channel region 140 on the substrate 110. In step S14, forming a compound film on the channel region 140 as the gate dielectric layer 150. In step S14, forming the gate 160 on the gate dielectric layer 150.

[0075] As Figure 1EAs shown, in some embodiments of the present disclosure, forming the source region 120 on the substrate 110 may include: forming a source region mask pattern on the substrate 110 and implanting doping elements. Forming the drain region 130 on the substrate 110 may include: forming a drain region mask pattern on the substrate 110 and implanting doping elements.

[0076] In some embodiments of the present disclosure, the execution order of steps S11 and S12 is not time-sequential, and they can be executed independently of each other or simultaneously. For example, step S11 can be executed first, or step S12 can be executed first, or steps S11 and S12 can be executed simultaneously.

[0077] As Figure 1E shown, in some embodiments of the present disclosure, it may further include: a step of performing high-temperature annealing on the formed source region 120 and / or drain region 130. The channel region 140 is formed between the source region 120 and the drain region 130.

[0078] Figure 1B The flowchart of a method S20 for forming a field effect transistor according to some other embodiments of the present disclosure is shown.

[0079] As Figure 1B shown, in some embodiments of the present disclosure, the method S20 for forming a field effect transistor may include steps S21 - S24. In step S21, a gate is formed on the substrate. In step S22, a compound film is formed on the substrate as the gate dielectric layer. In step S23, a channel layer is formed on the gate dielectric layer. In step S24, source and drain regions are formed on the substrate, the gate dielectric layer, or the channel layer.

[0080] Figure 1F The schematic structural diagram of a field effect transistor 10000a obtained by the method for forming a field effect transistor according to some other embodiments of the present disclosure is shown.

[0081] Next, taking Figure 1F the field effect transistor 10000a shown as an example, Figure 1B the method S20 for forming a field effect transistor shown according to some embodiments of the present disclosure will be introduced.

[0082] As Figure 1F shown, in some embodiments of the present disclosure, the field effect transistor 10000a may include a substrate 110a, a source region 120a, a drain region 130a, a channel layer 140a, a gate dielectric layer 150a, and a gate 160a.

[0083] As Figure 1FAs shown, in some embodiments of the present disclosure, the method S20 for forming a field-effect transistor may include: In step S21, an embedded gate 160a is formed on the substrate 110a. In step S22, a compound film is formed on the substrate as the gate dielectric layer 150a. In step S23, a channel layer 140a is formed on the gate dielectric layer 150a. In step S24, a source region 120a and a drain region 130a are formed on the gate dielectric layer 150a.

[0084] As Figure 1F shown, in some embodiments of the present disclosure, forming the embedded gate 160a may include: coating a layer of photoresist on the upper surface of the substrate 110a; patterning the photoresist layer to remove a portion of the photoresist layer covering the upper surface of the substrate 110a; performing plasma etching on the upper surface of the substrate 110a using the remaining photoresist layer as a mask to form a groove on the upper surface of the substrate 110a; and forming a gate material layer filling the groove, wherein the thickness of the gate material layer is greater than or equal to the depth of the groove.

[0085] In some embodiments of the present disclosure, a source region 120a and a drain region 130a may be formed on the gate dielectric layer 150a. For example, the channel layer 140a may be etched to form a source notch and a drain notch, and the source region 120a and the drain region 130a are respectively formed in the source notch and the drain notch. For example, as Figure 1F shown, step S23 may include forming a channel layer on the gate dielectric layer 150a. Coating a photoresist on the channel layer and applying a mask, and removing the remaining part of the channel layer by etching to form a source notch and a drain notch. The channel layer 140a above the remaining gate 160a, and the remaining channel layer 140a is processed to reduce the carrier concentration. With the source notch and the drain notch located on both sides of the channel layer 140a, the source region 120a and the drain region 130a are respectively formed.

[0086] In some embodiments of the present disclosure, a source region 120a and a drain region 130a may be formed on the channel layer 140a. For example, a photoresist may be coated on the channel layer 140a or a mask may be applied to expose the portion of the channel layer 140a above the gate 160a, and the exposed portion of the channel layer 140a may be processed (such as heat treatment) to form the channel region 140a and the source region 120a and the drain region 130a are formed on both sides of the channel region 140a.

[0087] A channel layer is formed on the gate dielectric layer 150a. The specific choice of channel material can be determined according to the specific type of the device. Next, a metal oxide semiconductor material will be used for illustration. In some embodiments of the present disclosure, a metal oxide semiconductor material (e.g., an amorphous zinc oxide-based metal oxide semiconductor material) can be formed on the gate dielectric layer 150a by radio frequency magnetron sputtering. Through photolithography technology, a mask is applied on the metal oxide semiconductor layer, and only the middle part is exposed. The uncovered part is etched to remove the unnecessary metal oxide semiconductor material. In an oxygen atmosphere, the middle part of the exposed metal oxide semiconductor layer is heat-treated (e.g., treated at 250 °C for half an hour) to repair the oxygen vacancies in this area and transform it into a material with a low carrier concentration. After removing the photoresist mask, the middle part of the metal oxide semiconductor layer has been converted into the channel region, while the two ends that are not affected by the heat treatment still maintain a high carrier concentration, forming low-resistance regions, which become the source region 120a and the drain region 130a.

[0088] As Figure 1F shown, in some embodiments of the present disclosure, the field effect transistor 10000a may further include a dielectric layer 170a covering the substrate. The gate 160a can be embedded on the gate dielectric layer 170a. The gate dielectric layer 170a can use conventional dielectric materials, such as silicon dioxide, etc.

[0089] As Figure 1F shown, in some embodiments of the present disclosure, processes such as chemical vapor deposition, physical vapor deposition, etc. can be used to form the dielectric layer 170a on the upper surface of the substrate 110a.

[0090] As Figure 1F shown, in some embodiments of the present disclosure, the reaction gas for plasma etching the upper surface of the substrate 110a can include fluorine-based gases such as carbon tetrafluoride or sulfur hexafluoride. In some embodiments of the present disclosure, the gate material layer can be formed by methods such as thermal evaporation, electron beam evaporation, or sputtering.

[0091] Figure 1C FIG. shows a flowchart of a method S14 for forming a gate dielectric layer according to some embodiments of the present disclosure.

[0092] As Figure 1C shown, referring to Figure 1E , in some embodiments of the present disclosure, the method S14 can be a method for forming a compound film on the channel region, and can include: in step S141, emitting at least one deposition particle beam to the channel region 140. The method S14 for forming a compound film on the channel region may further include: in step S142, emitting active particles to the channel region 140 to form a compound film on the channel region 140 as the gate dielectric layer 150.

[0093] As Figure 1C shown, with reference to Figure 1E or Figure 1F , in some embodiments of the present disclosure, method S14 may be a method for forming a compound film on substrate 110, and may include: in step S141, emitting at least one beam of deposition particles towards substrate 110 or 110a. The method S14 for forming a compound film on a substrate may further include: in step S142, emitting active particles towards substrate 110 or 110a to form a compound film on substrate 110 or 110a as gate dielectric layer 150. The method S14 for forming a compound film on a substrate may further include: etching gate dielectric layer 150 to remove the remaining portion other than the portion corresponding to the gate.

[0094] Figure 1D The flowchart showing method S22 for forming a gate dielectric layer according to some other embodiments of the present disclosure.

[0095] As Figure 1D shown, in some other embodiments of the present disclosure, a compound film may be formed on the channel region in an indirect manner. For example, method S22 for forming a compound film on the channel region may include: in step S221, emitting at least one beam of deposition particles towards an auxiliary substrate. Method S22 for forming a compound film on the channel region may further include: in step S222, emitting active particles towards the auxiliary substrate to form a compound film on the auxiliary substrate. Method S22 for forming a compound film on the channel region may further include: in step S223, transferring the compound film formed on the auxiliary substrate to the channel region (e.g., Figure 1E the channel region 140 shown) to serve as the gate dielectric layer (e.g., Figure 1E the gate dielectric layer 150 shown).

[0096] In some other embodiments of the present disclosure, transferring the compound film to the channel region may include: bonding the compound film to the channel region (e.g Figure 1E the channel region 130 shown) and separating the compound film from the auxiliary substrate. The steps of bonding the compound film to the channel region and separating the compound film from the auxiliary substrate are not executed in a specific time sequence and are independent of each other. For example, the compound film may be bonded to the channel region first, or the compound film may be separated from the auxiliary substrate first.

[0097] As Figure 1DAs shown, in some other embodiments of the present disclosure, a compound film may be formed on the substrate 110 in an indirect manner. The method S22 for forming a compound film on the substrate may include: in step S221, emitting at least one beam of deposition particles towards the auxiliary substrate. The method S22 for forming a compound film on the substrate may further include: in step S222, emitting active particles towards the auxiliary substrate to form a compound film on the auxiliary substrate. The method S22 for forming a compound film on the substrate may further include: in step S223, transferring the compound film formed on the auxiliary substrate to the substrate (e.g., Figure 1F the substrate 110a shown). The method S22 for forming a compound film on the substrate may further include etching the compound film to remove the remaining portion other than the portion corresponding to the gate.

[0098] In some other embodiments of the present disclosure, transferring the compound film formed on the auxiliary substrate to the substrate may include: bonding the compound film to the substrate (e.g., Figure 1E the substrate 110 shown, or Figure 1F the substrate 110a shown). And separating the compound film from the auxiliary substrate. Similarly, the execution of these two actions is independent of each other and there is no time sequence.

[0099] In some other embodiments of the present disclosure, the Smart Cut process may be used to transfer the compound film formed on the auxiliary substrate to the channel region or the substrate. Taking the transfer of the compound film to the substrate as an example, it may include: injecting hydrogen ions into the auxiliary substrate to form a brittle layer. Aligning the auxiliary substrate and the substrate (e.g., Figure 1E the substrate 110 shown, or Figure 1F the substrate 110a shown) precisely and bringing them into contact. By applying pressure, heating or other means, a firm bond is formed between the auxiliary substrate and the substrate (e.g., Figure 1E the substrate 110 shown, or Figure 1F the substrate 110a shown). By applying mechanical or thermal stress, the brittle layer is induced to break. The compound film is separated from the auxiliary substrate and transferred to the substrate (e.g., Figure 1E the substrate 110 shown, or Figure 1F the substrate 110a shown).

[0100] In some embodiments of the present disclosure, the method S20 for forming a field effect transistor may further include a step of processing the compound film formed on the substrate (including the compound film directly formed on the substrate or the compound film transferred to the substrate).

[0101] In some embodiments, such as Figure 1EAs shown, forming a compound film on the channel region 140 may further include: forming a compound film on the source region 120, the drain region 130, and the channel region 140, and etching away the compound film on the source region 120 and the drain region 130 so that the compound film on the channel region 140 serves as the gate dielectric layer 150.

[0102] In some embodiments of the present disclosure, the step of processing the compound film formed on the substrate may further include: performing a cleaning after etching to remove residual etchant and photoresist, etc.

[0103] Those skilled in the art can understand that, in some embodiments of the present disclosure, etching may include wet etching and / or dry etching.

[0104] In some embodiments of the present disclosure, the channel region (e.g., Figure 1E the channel region 140 shown) or the channel layer (e.g., Figure 1F the channel layer 140a shown) may include channel materials such as metal oxide semiconductors (e.g., silicon dioxide, zinc oxide, indium oxide), graphene, transition metal chalcogenides (e.g., molybdenum disulfide (MoS2), tungsten disulfide (WS2)), black phosphorus, or titanium carbide, etc.

[0105] Integrated circuits centered around traditional silicon-based semiconductors / oxides (such as Si / SiO2, Si / HfO2) meet the requirements of chip iteration through continuous miniaturization of device dimensions. As Moore's Law advances and approaches the physical limit, traditional silicon-based semiconductor materials encounter key challenges such as short-channel effects at the limit of chip size miniaturization, and bottleneck problems such as rising power consumption and insufficient computing power become increasingly prominent. Two-dimensional integrated circuits are constructed with two-dimensional semiconductor materials that are only one or a few atomic layers thick, and have advantages such as high carrier mobility and suppression of short-channel effects, and are expected to break through the physical limits of traditional chips.

[0106] In some embodiments of the present disclosure, the channel region (e.g Figure 1E the channel region 140 shown, Figure 1F the channel region 140a shown) may include channel materials such as two-dimensional materials, e.g., graphene, transition metal chalcogenides, black phosphorus, or titanium carbide, etc.

[0107] In some embodiments of the present disclosure, the active particles may include plasma or neutral particles.

[0108] In some embodiments of the present disclosure, step S142 may include emitting plasma to the channel region or the substrate to form a compound film on the channel region or the substrate.

[0109] In some other embodiments of the present disclosure, step S142 may include emitting neutral particles to the channel region or the substrate to form a compound film on the channel region or the substrate.

[0110] In some embodiments of the present disclosure, step S221 may include emitting plasma onto the auxiliary substrate to form a compound film on the auxiliary substrate.

[0111] In some other embodiments of the present disclosure, step S221 may include emitting neutral particles onto the auxiliary substrate to form a compound film on the auxiliary substrate.

[0112] For simplicity hereinafter, semiconductor materials or devices including a channel region, a substrate, an auxiliary substrate, etc. are collectively referred to as samples.

[0113] In some embodiments of the present disclosure, the plasma may include nitrogen plasma, hydrogen plasma, oxygen plasma, etc. In some embodiments of the present disclosure, the neutral particles may include neutral nitrogen, neutral hydrogen, neutral oxygen, etc. with kinetic energy.

[0114] In some embodiments of the present disclosure, the deposited particle beam may include a metal particle beam or a non-metal particle beam. In some embodiments of the present disclosure, the metal particle beam may include an aluminum particle beam, a gallium particle beam, etc. In some embodiments of the present disclosure, the non-metal particle beam may include a silicon particle beam, etc.

[0115] In some embodiments of the present disclosure, the compound film may include a single-crystal compound film (e.g., a single-crystal metal compound film) or other forms of compound films (e.g., an amorphous (non-crystalline) compound film, a polycrystalline compound film, etc.). In some embodiments of the present disclosure, the single-crystal compound film may include a single-crystal aluminum nitride film, a single-crystal gallium nitride film, a single-crystal aluminum oxide film, etc. In some embodiments of the present disclosure, other forms of compound films may include a silicon nitride film, a silicon dioxide film, an amorphous aluminum oxide film, etc.

[0116] The preparation of single-crystalline compound films (e.g., single-crystalline metal compound films including single-crystalline aluminum nitride films, etc.) usually requires a relatively high temperature, which limits their practical applications. For example, the performance of two-dimensional semiconductor devices depends not only on the characteristics of two-dimensional semiconductor channel materials but also, to a large extent, on the performance of gate dielectric materials. Amorphous oxide gate dielectric materials that perform well in traditional silicon technology, such as SiO2 and HfO2, have a large number of surface dangling bonds, and there are a large number of electron traps at the interface formed with two-dimensional semiconductor channel materials, thus affecting the performance of two-dimensional semiconductor devices. Although traditional single-crystalline gate dielectric materials can overcome the interface quality problem, they usually require a relatively high process temperature and post-annealing treatment, which are likely to cause unintentional damage or unintentional doping to two-dimensional semiconductor materials. The lack of high-quality gate dielectric materials that match two-dimensional semiconductor channel materials is one of the important reasons for the large difference between the performance of two-dimensional semiconductor material devices and the theoretical calculated values. In some embodiments of the present disclosure, by using active particles (e.g., neutral nitrogen, nitrogen plasma, etc.), the chemical activity of, for example, nitrogen can be increased, so that nitrogen can react with deposition particle materials at near room temperature to achieve the near-room-temperature preparation of compound films (e.g., single-crystalline aluminum nitride films).

[0117] The single-crystalline metal compound film prepared at near room temperature according to some embodiments of the present disclosure is an ideal dielectric material for two-dimensional channel material field-effect transistors. In some embodiments of the present disclosure, using the single-crystalline metal compound film prepared at near room temperature as the gate dielectric layer and combining it with a two-dimensional channel can significantly reduce the current leakage rate of the device and suppress the current collapse effect.

[0118] In some embodiments of the present disclosure, emitting at least one deposition particle beam to a sample may include: emitting at least one deposition particle beam to the sample to form a deposition particle film. Emitting active particles to the sample may include: emitting active particles to the deposition particle film to form a compound film.

[0119] In some embodiments of the present disclosure, the deposition particle film may include a single-crystalline film (e.g., single-crystalline metal film) or other forms of films (e.g., amorphous (non-crystalline) film, polycrystalline film, etc.). In some embodiments of the present disclosure, the single-crystalline film may include a single-crystalline aluminum film, a single-crystalline gallium film, etc. Other forms of films may include amorphous silicon films, etc.

[0120] Figure 1G An exemplary flowchart of a method S100a for forming a compound film according to some other embodiments of the present disclosure is shown.

[0121] As Figure 1GAs shown, in some embodiments of the present disclosure, the method S100a for forming a compound film may include: in step S110a, emitting at least one beam of deposition particles towards a sample to form a deposition particle film. The method S100a for forming a compound film may further include: in step S120a, emitting active particles towards the deposition particle film to form a compound film.

[0122] In some embodiments of the present disclosure, step S120a may include emitting plasma towards the deposition particle film to form a compound film on the sample.

[0123] In some other embodiments of the present disclosure, step S120a may include emitting neutral particles towards the deposition particle film to form a compound film on the sample.

[0124] In some embodiments of the present disclosure, the active particles provide active nitrogen for the preparation of nitrides of the deposition particle film (such as single-crystal metal films, etc.). The active nitrogen particles can penetrate into, for example, the metal surface and bond with the atoms in the lattice at near room temperature to form an ordered structure, resulting in a single-crystal nitride, such as single-crystal aluminum nitride.

[0125] In some embodiments of the present disclosure, emitting active particles towards the deposition particle film may include: emitting active particles towards the deposition particle film at a temperature of 0°C - 100°C.

[0126] In some embodiments of the present disclosure, the sample includes a single-crystal semiconductor surface. Emitting at least one beam of deposition particles towards the sample to form a deposition particle film includes emitting at least one beam of deposition particles towards the single-crystal semiconductor surface to epitaxially grow a deposition particle film on the single-crystal semiconductor surface.

[0127] In some embodiments of the present disclosure, the low-temperature epitaxy of a metal film is carried out on the surface of a semiconductor substrate by utilizing the wetting property of a deposition particle beam (such as a metal particle beam) at low temperature to form a deposition particle film (such as a single-crystal metal film).

[0128] In some embodiments of the present disclosure, the method for forming a compound film may further include: annealing the deposition particle film. The annealing treatment can improve the crystal quality of the deposition particle film, but the annealing temperature should not be too high, otherwise the surface of the deposition particle film (such as a metal film) will become rough.

[0129] In some embodiments of the present disclosure, the method for forming a compound film may further include: during the epitaxial growth of the deposition particle film, controlling the temperature of the single-crystal semiconductor surface not to exceed 100°C.

[0130] In some other embodiments of the present disclosure, emitting active particles towards the sample may include: emitting active particles towards the sample during the emission of at least one beam of deposition particles towards the sample to form a compound film.

[0131] Figure 1H FIG. 100b is an exemplary flowchart showing a method of forming a compound film according to still further embodiments of the present disclosure.

[0132] As Figure 1H shown, in some embodiments of the present disclosure, the method S100b of forming a compound film may include: in step S110b, emitting at least one deposition particle beam onto a sample to form a deposition particle film. The method S100b of forming a compound film may further include: in step S120b, emitting active particles onto the sample during the process of emitting at least one deposition particle beam onto the sample to form a compound film.

[0133] In some embodiments of the present disclosure, step S120b may include emitting plasma onto the sample during the process of emitting at least one deposition particle beam onto the sample to form a compound film.

[0134] In some other embodiments of the present disclosure, step S120b may include emitting neutral particles onto the sample during the process of emitting at least one deposition particle beam onto the sample to form a compound film.

[0135] In some embodiments of the present disclosure, methods of forming a compound film, such as S100, S100a, S100b, etc., may be operated by a vacuum system (e.g., Figure 25A the vacuum system 1000 shown).

[0136] In some embodiments of the present disclosure, the method of forming a compound film may further include: performing a surface treatment on the surface of the sample (e.g., single crystal semiconductor) to remove contaminants or amorphous oxides on the surface of the sample.

[0137] In some embodiments of the present disclosure, performing a surface treatment on the substrate of the sample (e.g., single crystal semiconductor) may include chemical wet treatment, heat treatment, and / or hydrogen plasma deoxidation treatment, etc. The purpose is to remove surface contaminants or amorphous oxides and expose a clean single crystal surface.

[0138] In some embodiments of the present disclosure, the method of forming a compound film may further include: forming an epitaxial buffer layer on the surface of the single crystal semiconductor. The epitaxial buffer layer may improve the quality of the compound film.

[0139] In some embodiments of the present disclosure, the sample may include a single crystal silicon substrate, a single crystal aluminum nitride substrate, or a single crystal gallium nitride substrate. In some embodiments of the present disclosure, a channel region (e.g., Figure 1E the channel region 140 shown) is established on the single crystal silicon substrate, the single crystal aluminum nitride substrate, or the single crystal gallium nitride substrate. In some embodiments of the present disclosure, the substrate (e.g., Figure 1E the substrate 110 shown or Figure 1FThe substrate 110a) shown or the auxiliary substrate includes a single-crystalline silicon substrate, a single-crystalline aluminum nitride substrate, or a single-crystalline gallium nitride substrate.

[0140] In some embodiments of the present disclosure, the lattice matching degree between the semiconductor substrate material and the metal material to be plated is high, so as to effectively ensure the crystal quality of the epitaxial film.

[0141] In some embodiments of the present disclosure, the active particles can be generated by an active source.

[0142] Figure 2A The schematic structural diagram of the active source 100 according to some embodiments of the present disclosure is shown. [[ID=1 The partial schematic structural diagram of the active source 100 according to some embodiments of the present disclosure is shown. ​ Shown according to some embodiments of the present disclosure along ​ The A-A sectional view. ​ Shown according to some embodiments of the present disclosure ​ The enlarged schematic diagram of another angle of part B.

[0143] As ​ , ​ And ​ As shown, in some embodiments of the present disclosure, the active source 100 may include an electromagnetic field generator 10 and a plasma generation chamber 20. The electromagnetic field generator 10 can be used to generate an electromagnetic field after being powered on, and the plasma generation chamber 20 is coupled with the electromagnetic field generator 10 and can be used to accommodate the working gas and the plasma generated by the working gas under the action of the electromagnetic field.

[0144] In some embodiments of the present disclosure, the electrons in the plasma generation chamber 20 make cyclotron motions under the action of the electromagnetic field, increasing the collision probability with gas molecules and the ionization efficiency of gas molecules, so as to be able to generate a plasma with a relatively high density. For example, the nitrogen plasma generated by the active source according to some embodiments of the present disclosure can fully nitride the deposition particle films such as the single-crystalline metal gallium (Ga) film or the single-crystalline metal aluminum (Al) film attached to the substrate, and obtain a single-crystalline gallium nitride layer or a single-crystalline aluminum nitride layer by means of epitaxial growth.

[0145] ​ The schematic structural diagram of the active source 100a according to some other embodiments of the present disclosure is shown. ​ Shown according to some embodiments of the present disclosure along ​ The D-D sectional view.

[0146] As shown in 3A and ​As shown, the active source 100a may include an electromagnetic field generator 10a, a magnetic field confinement mechanism 90, and a plasma generation chamber 20a. The electromagnetic field generator 10a can be used to generate an electromagnetic field after being powered on. The magnetic field confinement mechanism 90 is used to generate a confinement magnetic field. The plasma generation chamber 20a is coupled to the electromagnetic field generator 10a and the magnetic field confinement mechanism 90, and can be used to accommodate a working gas and the plasma generated by the working gas under the action of the electromagnetic field and the confinement magnetic field.

[0147] In some embodiments of the present disclosure, it may include introducing nitrogen, hydrogen, or oxygen into the active source 100 or 100a shown, for example, as ​ , 2B , 2C, ​ , ​ etc., to form nitrogen plasma, hydrogen plasma, or oxygen plasma.

[0148] In some embodiments of the present disclosure, the active source 100 or 100a may further include an ion filter (not shown in the figure). The ion filter can be disposed at the distal end of a shielding housing (e.g., the shielding housing 19 shown), and covers the distal end of the cavity 21 of the plasma generation chamber 20, and can be used to filter the plasma. Through the screening of the ion filter, high-energy plasma can be inhibited from reaching the sample surface, reducing damage. The obtained nitrogen plasma, hydrogen plasma, oxygen plasma, etc. can be widely used in the growth of nitrides, nitrogen atom implantation and doping, oxide growth, oxygen atom implantation and doping, hydride growth, and hydrogen atom surface cleaning in a vacuum system (e.g., a molecular beam epitaxy system). ​ As shown, a cross-sectional view along A-A of

[0149] ​ is shown according to some other embodiments of the present disclosure. ​ The cross-sectional view of D-D along ​ is shown according to some other embodiments of the present disclosure. ​ The cross-sectional view of D-D along ​ As shown according to some embodiments of the present disclosure, ​ an enlarged schematic view of another angle of part B of

[0150] As ​ , ​ , ​ shown, the active source 100 or 100a may further include a neutralizer 60. The neutralizer 60 is disposed at the distal end of the plasma outlet of the plasma generation chamber 20. The neutralizer 60 may include a plurality of through holes 61. The plurality of through holes 61 are used to allow the plasma to pass through and form neutral particles.

[0151] In some embodiments of the present disclosure, the neutralizer 60 can be grounded. The plasma coming out of the plasma outlet of the plasma generation chamber 20 passes through the grounded neutralizer 60 and is converted into neutral particles. Grounding the neutralizer 60 can facilitate the neutralization and exchange of the charges of the plasma.

[0152] In some other embodiments of the present disclosure, the neutralizer 60 can be biased. The plasma coming out of the plasma outlet of the plasma generation chamber 20 passes through the biased neutralizer 60 and is converted into neutral particles. Biasing the neutralizer 60 can control the screening and acceleration processes of the plasma and improve the neutralization efficiency.

[0153] In some embodiments of the present disclosure, the kinetic energy of the neutral particles can be regulated by regulating the gas flow rate of the working gas. For example, the kinetic energy of the neutral particles can be adjusted between 0 eV and 30 eV (including this value), such as neutral particles with kinetic energies of 0.5 eV - 30 eV, 0.5 eV - 20 eV, etc., so as to meet the requirements of epitaxial growth. And the neutral particles obtained through the plasma source in some embodiments of the present disclosure are more reactive. For example, the nitrogen atoms generated by the active source in some embodiments of the present disclosure can sufficiently nitride the deposited particle films such as single-crystal gallium metal (Ga) film or single-crystal aluminum metal (Al) film attached to the substrate, and a single-crystal gallium nitride layer or a single-crystal aluminum nitride layer can be obtained by means of epitaxial growth.

[0154] As ​ shown, in some embodiments of the present disclosure, the active source 100 may further include an electrode bias power supply (not shown in the figure) and an electrode 80. The electrode 80 is connected to the electrode bias power supply. The electrode 80 is disposed inside the proximal end of the plasma generation chamber 20 and is used to direct the charged particles in the plasma towards the neutralizer 60.

[0155] In some embodiments of the present disclosure, the electrode 80 connected to the electrode bias power supply can be used to accelerate the charged particles, and thus can be used to increase the kinetic energy of the neutral particles obtained from the neutralizer 60. For example, neutral particles with any point value or range between 0 eV and 2000 eV (including this value) can be obtained, including neutral particles with kinetic energies of 10 eV - 30 eV, 20 eV - 1000 eV, 50 eV - 200 eV, 200 eV - 2000 eV, etc. In some embodiments of the present disclosure, the kinetic energy of the neutral particles can also be regulated by regulating the output power of the electrode bias power supply.

[0156] In some embodiments of the present disclosure, as ​ and ​ shown, the neutralizer 60 may include a plate-shaped main body 62, and a plurality of through holes 61 are formed in the main body 62. The main body 62 can be made of any suitable material, such as metal, carbon, etc. As ​As shown in FIGS. 6 and 7, in some embodiments of the present disclosure, the ratio of the depth to the width of the through hole 61 is between 2:1 and 20:1. Wherein, the depth is the length of the through hole 61 along the plasma outlet direction. In some embodiments, the through hole 61 adopts a slot design, which can extend the path of the plasma in the neutralizer 60, thereby improving the neutralization efficiency. ​ Although FIGS. 6 and 7 show the through hole 61 as a straight hole, this is only exemplary, and the through hole 61 can also be designed as an inclined hole.

[0157] In some embodiments of the present disclosure, during operation, the plasma generated in the plasma generation chamber 20 passes through the through hole 61, impacts the inner surface of the through hole 61 at a grazing angle, and is converted into neutral particles. The neutral particles can be used to mitigate charging damage in processes such as epitaxial growth, etching, and cleaning, and can be widely applied to various production and experiments, such as the manufacture of microelectronic devices.

[0158] In some embodiments of the present disclosure, it may include introducing nitrogen, hydrogen, or oxygen into the active source 100 or 100a as shown in FIGS. ​ , ​ , ​ to form neutral nitrogen, neutral hydrogen, or neutral oxygen.

[0159] ​ FIG. shows the change in the charged particle beam current before and after installing the neutralizer on the active source 100 according to some embodiments of the present disclosure.

[0160] As shown in ​ , after installing the neutralizer 60, the charged particle flow (ion flow and electron flow) passing through the neutralizer 60 is basically 0.

[0161] In some embodiments of the present disclosure, the kinetic energy of the neutral particles can also be regulated by adjusting the output power of the radio frequency power supply 11. For example, neutral particles with any point value or range of kinetic energy between 0 eV and 2000 eV can be regulated, including neutral particles with kinetic energy of 10 eV - 30 eV, 20 eV - 1000 eV, 50 eV - 200 eV, 200 eV - 2000 eV, etc.

[0162] Additionally, in some embodiments, the working gas is cracked into plasma by radio frequency inductive coupling. After the plasma passes through the neutralizer 60, a highly active neutral particle source is provided, which can meet the epitaxial growth of samples such as substrates, effectively reduce the temperature of substrate epitaxial growth, and obtain high-quality epitaxial thin films.

[0163] ​ FIG. shows a partial structural schematic diagram of the electromagnetic field generator 10 according to some embodiments of the present disclosure.

[0164] As shown in ​As shown, in some embodiments of the present disclosure, the electromagnetic field generator 10 may include a conductive line 12. In some embodiments, the electromagnetic field generator 10 may further include a radio frequency power supply 11. Those skilled in the art can understand that the electromagnetic field generator 10 may or may not include the radio frequency power supply 11, but is separated from the radio frequency power supply 11 and is connected to the external radio frequency power supply 11 during use.

[0165] As ​ shown, the conductive line 12 may include a feeding line 121, an inductor coil 122, and a grounding line 123. The feeding line 121 may be used to connect to the radio frequency power supply 11. The inductor coil 122 is connected to the feeding line 121 and wound around the plasma generation chamber 20, and can be used to generate an electromagnetic field. The grounding line 123 is connected to the inductor coil 122 and can be used for grounding. The radio frequency power supply 11 is electrically connected to the conductive line 12 and delivers a radio frequency current to the conductive line 12, such as a radio frequency current with a relatively low frequency (for example, 13.56 MHz), causing the inductor coil 122 to generate an alternating magnetic field. As the radio frequency current continues to be delivered, the alternating magnetic field of the inductor coil 122 will excite an induced electric field in the surrounding space, which can cyclotron accelerate the electrons in the plasma generation chamber 20 surrounded by it, increasing the collision probability with gas molecules and the ionization efficiency of gas molecules, thereby being able to generate a plasma with a relatively high density.

[0166] Those skilled in the art can understand that although a radio frequency current with a frequency of 13.56 MHz is selected in some embodiments of the present disclosure, this is only exemplary. In some other embodiments of the present disclosure, a radio frequency current with a frequency of 27.12 MHz or other suitable frequencies may also be used to pass through the inductor coil to generate an electromagnetic field. ​ Shows an enlarged partial structure diagram of the electromagnetic field generator 10 according to some embodiments of the present disclosure.

[0167] As ​As shown, in some embodiments of the present disclosure, the electromagnetic field generator 10 may further include an electrode feedthrough 13, a first connector 14, and a second connector (not shown in the figure). The electrode feedthrough 13 connects the feed line 121 to the RF power supply 11. The first connector 14 is disposed between the feed line 121 and the electrode feedthrough 13 and can be used to connect the feed line 121 and the electrode feedthrough 13. The first connector 14 is in an "L" shape. The feed end 1211 of the feed line 121 is in contact with the short side of the first connector 14 and abuts against the long side of the first connector 14 to form an electrical conduction path. The distal end of the electrode feedthrough 13 is connected to the long side of the first connector 14 by a bolt, which can conduct the RF current generated by the RF power supply 11 into the feed line 121 through the first connector 14. Moreover, the electrode feedthrough 13 and the feed line 121 are detachably connected by bolts, which is convenient for maintenance and replacement. The second connector is disposed between the electrode feedthrough 13 and the RF power supply 11 and can be used to connect the electrode feedthrough 13 and the RF power supply 11. One end of the second connector is connected to the proximal end of the electrode feedthrough 13, and the other end is connected to the RF power supply 11 by a bolt, which can be used to conduct the RF current generated by the RF power supply 11 into the feed line 121. In some embodiments, the electrode feedthrough 13 can pass through a support flange (such as ​ and ​ the support flange 51 in ​ shown, the support flange 51a), to achieve electrical feeding between the vacuum environment and the outside.

[0168] Those skilled in the art can understand that although the first connector 14 is in an "L" shape in some embodiments of the present disclosure, this is only exemplary. The first connector 14 can also be in other suitable shapes, such as "I" shape, "S" shape, and straight line shape.

[0169] As ​ and ​ shown, in some embodiments of the present disclosure, the conduction line 12 may include a first wire and a second wire. The first wire and the second wire are connected at the feed end 1211 of the feed line 121 (for example, forming a U-shaped connection structure), and form a double-wound structure at the inductor coil 122. The first wire and the second wire are wound to form a sequentially connected feed line 121, inductor coil 122, and ground line 123. To avoid confusion, the first wire and the second wire are not separately marked in the figure.

[0170] As ​ shown, in some embodiments of the present disclosure, the electromagnetic field generator 10 may further include a protective member. The protective member may be, for example, at least one insulating ceramic tube. The insulating ceramic tube can be sleeved on the feed line 121 and the ground line 123 and can be used for insulation. The insulating ceramic tube can be composed of multiple small ceramic tubes, which can facilitate the adjustment of the direction. The insulating ceramic tube can also be composed of a whole ceramic tube.

[0171] Those skilled in the art can understand that the electromagnetic field generator 10a in some other embodiments may have a structure the same as or similar to that of the ​ , ​ electromagnetic field generator 10 shown, which will not be elaborated herein.

[0172] As ​ -D, ​ -B shown, in some embodiments of the present disclosure, the plasma generation cavity 20 may include a cavity 21 and a constriction section 22. As ​ shown, the inductance coil 122 may be wound around the cavity 21, and the induced electric field generated by the inductance coil 122 covers the cavity 21, so that the working gas is ionized into plasma in the cavity 21.

[0173] Those skilled in the art can understand that the plasma generation cavity 20a in some other embodiments may have a structure the same as or similar to that of the ​ -D, ​ -B shown plasma generation cavity 20, which will not be elaborated herein.

[0174] ​ Shown is an enlarged schematic view of part ​ or ​ A according to some embodiments of the present disclosure.

[0175] As ​ -D, ​ shown, in some embodiments of the present disclosure, the active source 100 may further include a gas introduction assembly 30. The gas introduction assembly 30 may include an outer tube 31, a partition block 32, and an intake inner tube 33. The partition block 32 is sealingly connected to the outer tube 31 and is located at the proximal end of the outer tube 31, and defines a proximal end portion 311 at the proximal end of the outer tube 31. The proximal end of the intake inner tube 33 is sealingly passed through the outer tube 31 through the partition block 32 and communicates with a gas source (not shown in the figure) through the proximal end portion 311, and can be used to introduce the gas generated by the gas source. At the same time, the partition block 32 also makes the inside of the outer tube 31 in a watertight state with its proximal end portion 311, preventing the coolant around the intake inner tube 33 from seeping into the proximal end portion 311. The intake inner tube 33 may include a main body 331 and an expansion section 332 located at the distal end. The expansion section 332 is engaged with the distal end of the outer tube 31 and can be used to input gas into the cavity 21. Those skilled in the art can understand that although in some embodiments of the present disclosure, the outer tube 31 is in two sections and connected together by the partition block 32, this is only exemplary. The outer tube may also be integrally formed, and the partition block is provided inside the outer tube and defines a proximal end portion at the proximal end of the outer tube.

[0176] Those skilled in the art can understand that although in some embodiments of the present disclosure, the main body 331 and the expansion section 332 of the intake inner tube 33 are divided into two sections and connected by a process such as welding, this is only exemplary, and the main body 331 and the expansion section 332 can also be integrally formed.

[0177] Those skilled in the art can understand that in some other embodiments, the active source 100a can have a gas introduction component 30a with the same or similar structure as the ​ -D, ​ shown gas introduction component 30, which will not be elaborated here.

[0178] ​ Schematic diagram showing the structure of the flow limiting tube 34 according to some embodiments of the present disclosure.

[0179] As ​ -D, ​ -B, ​ shown, in some embodiments of the present disclosure, the gas introduction component 30 may further include a flow limiting tube 34. The flow limiting tube 34 is at least partially disposed in the expansion section 332, and the distal end extends into the contraction section 22 of the plasma generation chamber 20. The outer diameter of the proximal end of the flow limiting tube 34 is greater than the inner diameter of the main body 331 of the intake inner tube 33, and the inner diameter of the flow limiting tube 34 is less than the inner diameter of the main body 331 of the intake inner tube 33. The flow limiting tube 34 may include a first gas channel 341 and a second gas channel 342, and the diameter of the first gas channel 341 may be greater than that of the second gas channel 342. The working gas flows from the first gas channel 341 through the second gas channel 342 and then enters the plasma generation chamber 20, which can limit the flow of the working gas, so that gas molecules are fully ionized and the ionization efficiency is improved.

[0180] Those skilled in the art can understand that, as ​ shown, in some other embodiments, the gas introduction component 30a may also include a flow limiting tube 34 ( ​ not shown).

[0181] ​ Schematic diagram showing the structure of the flow dividing tube 35 according to some embodiments of the present disclosure.

[0182] As ​ -D, ​ -B, ​As shown, in some embodiments of the present disclosure, the gas introduction assembly 30 may further include a shunt pipe 35. The shunt pipe 35 is sleeved on the distal end of the flow-limiting pipe 34, and its proximal end extends into the expansion section 332, and the distal end extends into the contraction section 22. At least one shunt hole 351 (for example, shunt hole 351a, shunt hole 351b, shunt hole 351c, shunt hole 351d) is provided at the distal end of the shunt pipe 35, which can be used to shunt the introduced working gas to increase the disorder between gas molecules, fully ionize the gas molecules, and improve the ionization efficiency.

[0183] Those skilled in the art can understand that, as ​ shown, in some other embodiments, the gas introduction assembly 30a may also include a shunt pipe 35 ( ​ not shown).

[0184] ​ An enlarged schematic view of another angle of part A of ​ is shown according to some embodiments of the present disclosure. ​ An enlarged schematic view of another angle of part A of ​ is shown according to some embodiments of the present disclosure. ​ An enlarged schematic view of another angle of part B of ​ is shown according to some embodiments of the present disclosure. ​ An enlarged schematic view of another angle of part B of ​ is shown according to some embodiments of the present disclosure

[0185] As ​ shown, the active source 100 may further include a cooling device 40. In some other embodiments, the active source 100a may also include a cooling device 40. The cooling device 40 may include a liquid inlet 41 (the inlet pipe is not shown), a first connecting pipe 42, a second connecting pipe 43, a liquid outlet 44 (the outlet pipe is not shown), a third connecting pipe 45, and a fourth connecting pipe 46. The conduction line 12 may include a hollow first wire and a second wire, and the first wire and the second wire are connected at the feeding end of the feeding line. The liquid inlet 41 is connected to the first wire through the third connecting pipe 45 at the proximal end of the grounding line 123, and can be used to introduce a coolant into the conduction line 12. The first connecting pipe 42 is connected to the second wire at the proximal end of the grounding line 123 and is connected to a part of the outer pipe 31 at the distal end of the partition block 32. The coolant enters the outer pipe 31, and the second connecting pipe 43 extends along the outer pipe 31 and its distal end is connected to the outer pipe 31. When the liquid level of the coolant in the outer pipe 31 is higher than that of the second connecting pipe 43, it can be discharged from the second connecting pipe 43 to ensure the cooling effect of the coolant on the gas introduction assembly 30. The liquid outlet 44 is connected to the proximal end of the second connecting pipe 43 through a fifth connecting pipe 46, and can be used to discharge the coolant in the outer pipe 31.

[0186] During the process of generating plasma by radio frequency inductive coupling, generally, the inductive coil will generate high-temperature heat, which is likely to bring destructive risks to the active source itself. Therefore, the inductive coil itself also needs to be cooled. In some embodiments of the present disclosure, the coolant passes through the hollow first wire and second wire to cool the feeding line 121, the inductive coil 122, and the grounding line 123, and then cools the gas introduction assembly 30. The coolant circulation route is long and the cooling is sufficient, preventing the equipment from being damaged due to overheating and effectively extending the service life of the equipment. The cooling device 40 can cool the conduction line 12 and the gas introduction assembly, simplifies the cooling pipeline, reduces welding, reduces the risk of poor sealing at the welded joints, and reduces the processing cost. And in some embodiments of the present disclosure, low-frequency low-voltage alternating current is used. Even if the coolant is passed into the conduction line 12, no conduction problem will occur. In addition, as ​ shown, both the liquid inlet 41 and the liquid outlet 44 are arranged on the support flange 51, and the pipeline hidden in the support flange 51 plays a role in cooling the support flange 51, avoiding the support flange 51 from outgassing due to heat and affecting the system vacuum.

[0187] Those skilled in the art can understand that although in some embodiments of the present disclosure, the cooling device 40 cools both the conduction line 12 and the gas introduction assembly 30, this is only a preferred embodiment. In some embodiments, only the conduction line 12 can be cooled, or only the gas introduction assembly 30 can be cooled, or the conduction line 12 or the gas introduction assembly 30 can be cooled independently. For example, the conduction line may also include a hollow first wire and second wire, and the active source may also include a cooling device. The cooling device may include: an inlet pipe, which communicates with the first wire at the proximal end of the grounding line and is used to introduce the coolant into the conduction line; an outlet, which communicates with the second wire at the proximal end of the grounding line and is used to discharge the coolant.

[0188] ​ Shows a cross-sectional schematic view of the partition block 32 according to some embodiments of the present disclosure.

[0189] As ​ shown, in some embodiments of the present disclosure, the partition block 32 may include a first connection channel 321 and a second connection channel 322. The first connection channel 321 and the second connection channel 322 are L-shaped channels. The first connection channel 321 can be used to connect the first connection pipe 42 with the outer pipe 31, and the second connection channel 322 connects the second connection pipe 43 with the liquid outlet 44.

[0190] Those skilled in the art can understand that although the first connection channel 321 and the second connection channel 322 of the partition block 32 are L-shaped channels in some embodiments of the present disclosure, this is only exemplary. The first connection channel and the second connection channel can also be S-shaped channels or Z-shaped channels. Similarly, although the first connection channel 321 and the second connection channel 322 are provided in the partition block 32 in some embodiments of the present disclosure, this is only exemplary. First connection holes and second connection holes can also be opened in the partition block. The first connection hole can be used to communicate the first connection pipe 42 with the outer pipe 31, and the second connection hole can be used to communicate the second connection pipe 43 with the liquid outlet 44.

[0191] As shown in FIGS. 1, ​ -D, ​ and ​ in some embodiments of the present disclosure, the active source 100 may further include a support mechanism 50. In some embodiments of the present disclosure, the active source 100 may further include a limit block 18. The support mechanism 50 may include a support flange 51. The outer pipe 31 is passed through the support flange 51. The limit block 18 is provided at the distal end of the outer pipe 31, and the grounding line 123 is passed through the limit block 18. The limit block 18 can be used to fix the position of the grounding line 123. When adjusting the angle and / or position of the conduction line 12, only the feed line 121 needs to be adjusted. The support flange 51 or 51a can be used to mount the active source 100 or 100a to the vacuum chamber to achieve vacuum sealing.

[0192] As ​ shown, in some other embodiments, the active source 100a may include a support mechanism 50a. The support mechanism 50 may further include a straight-through flange 52. The distal end of the straight-through flange 52 is hermetically connected to the flange 93, and the proximal end of the straight-through flange 52 is connected to the support flange 51.

[0193] As ​ -D, ​ -B and ​ -B shown, in some embodiments of the present disclosure, the active source 100 may further include a sealing assembly 70. The sealing assembly 70 may include a sealing ring 71 and a sealing nut 72. The sealing ring 71 is sleeved on the contraction section 22 and partially located in the expansion section 332 of the intake inner pipe 33. The sealing nut 72 is threadedly connected to the expansion section 332 and can be used to compress the sealing ring 71 to hermetically connect the contraction section 22 and the expansion section 332 of the intake inner pipe 33.

[0194] Those skilled in the art can understand that in some other embodiments, the active source 100a may also include a sealing assembly (such as ​ the sealing assembly 70a in). The sealing assembly 70a may have the same or similar structure as the sealing assembly 70, which will not be elaborated herein.

[0195] Currently, in terms of the materials of the sealing ring, the existing vacuum seals are mainly composed of synthetic materials such as rubber and metal materials such as sealed indium wire parts. Rubber synthetic materials have the advantages of high elasticity, high wear resistance, and appropriate mechanical strength, making them widely used in vacuum seals. However, they have a large outgassing rate and permeability, and cannot be baked at high temperatures or are not radiation-resistant. The melting point of the metal indium wire seal is relatively low, and the baking temperature cannot be higher than 150°C. It is often used in vacuum seals in low-temperature environments, and the indium wire is prone to flow after being pressed. In plasma research, due to the increase in different powers of the plasma or the observation of different test effects of the plasma over a long time, there have been phenomena such as the sealing rubber ring parts being charred and the sealed indium wire parts melting and flowing into the vacuum chamber, causing vacuum environmental pollution and thus affecting the plasma research results.

[0196] Therefore, in some embodiments of the present disclosure, the sealing ring 71 may include pyrolytic boron nitride (PBN) and / or boron nitride (BN). For example, the sealing ring 71 may be made of pyrolytic boron nitride (PBN) material or boron nitride (BN) material. The melting point of pyrolytic boron nitride (PBN) is 1750°C - 2300°C, and the melting point of boron nitride (BN) can be as high as 2700°C, which can prevent deformation due to overheating and melting of the equipment, thereby greatly improving the sealing effect. In addition, PBN and BN are non-metallic materials. Parts using PBN and / or BN as sealing materials also have characteristics such as high temperature resistance, corrosion resistance, high resistance, good electrical insulation performance, smooth surface, no pores, non-wetting with most semiconductor melts, good oxidation resistance, and good thermal shock resistance, so that the equipment will not interfere with the vacuum degree of the vacuum chamber during use and can better maintain the vacuum degree of the vacuum environment. At the same time, during the loading and unloading process, it can also play a protective role for the internal parts of the present invention.

[0197] As ​ shown, in some embodiments of the present disclosure, the electromagnetic field generator 10 may further include a shielding housing 19. The shielding housing 19 can be sleeved on the electromagnetic field generator 10 and can be used to shield electromagnetic signals. The proximal end of the shielding housing 19 is fixedly connected to the support flange 51.

[0198] Those skilled in the art can understand that although in some embodiments of the present disclosure, the shielding housing 19 is only an integral housing, this is only exemplary. The shielding housing 19a can also be composed of multiple housings. For example, the shielding housing 19 may include a first housing and a second housing.

[0199] As ​ shown, in some other embodiments, the electromagnetic field generator 10a may also include a shielding housing 19a.

[0200] ​Partial cross-sectional schematic diagram of the active source 100 according to some embodiments of the present disclosure is shown. ​ Partial cross-sectional schematic diagram of the active source 100 including the neutralizer 60 according to some other embodiments of the present disclosure is shown.

[0201] As ​ As shown in -B, in some embodiments of the present disclosure, the plasma generation chamber 20 may further include a limiting component 23. The limiting component 23 may include a first limiting member 231 and a second limiting member 232. The first limiting member 231 is sleeved on the contraction section 22 of the plasma generation chamber 20, and the second limiting member 232 is disposed at the distal end of the shielding housing 19. The first limiting member 231 and the second limiting member 232 can be processed from high melting point metals such as tantalum or molybdenum, which can block the outward diffusion of the electric field, so that the plasma can converge within the range of the plasma generation chamber 20, limit the movement of the plasma towards the proximal end of the shielding housing 19, prevent ion corrosion of the device, and extend the service life of the device.

[0202] As ​ As shown in -C, in some other embodiments of the present disclosure, the plasma generation chamber 20a may also include a limiting component 23 (not shown in the figure).

[0203] ​ Schematic diagram of the sealing structure in the case where the outer side of the sealing ring 71 according to some embodiments of the present disclosure may include a tapered surface is shown. ​ Schematic diagram of the sealing structure in the case where the outer side of the sealing ring 71 according to some embodiments of the present disclosure may include an arc surface is shown.

[0204] As ​ And ​ As shown, the sealing nut 72 cooperates with the sealing ring 71 and is sleeved on the contraction section 22. The sealing nut 72 and the expansion section 332 pre-tighten the sealing ring 71 through threads, so that the sealing ring 71 forms a line seal on the contact surfaces of the sealing nut 72, the expansion section 332 and the contraction section 22, achieving the prevention of leakage of the media on both sides, enabling the media to flow in from the middle, and having the characteristics of good sealing performance and convenient disassembly.

[0205] In some embodiments of the present disclosure, as ​ shown, the outer side of the sealing ring 71 may include a tapered surface, and the expansion section 332 and the sealing nut 72 may include tapered concave surfaces that cooperate with the outer side of the sealing ring 71. Those skilled in the art can understand that the outer side of the sealing ring 71 may include two oppositely arranged tapered surfaces, and the cross-section may be a triangle, a trapezoid, a triangle or trapezoid with truncated bottom angles, etc.

[0206] In some embodiments of the present disclosure, as ​As shown, the outer side surface of the sealing ring 71 may include an arc surface, and the expansion section 332 and the sealing nut 72 may include an arc concave surface that mates with the outer side surface of the sealing ring 71. Those skilled in the art can understand that the arc surface may include a circular arc surface or an elliptical arc surface, etc.

[0207] In some embodiments of the present disclosure, when the outer side surface of the sealing ring 71 may include a conical surface or an arc surface, it can withstand the pressure on both sides of the sealing nut 72 and the expansion section 332 without breaking or deforming, and at the same time can seal and connect the contraction section 22 and the expansion section 332 of the intake inner tube 33, preventing the working gas from escaping into the vacuum chamber and causing a decrease in vacuum degree, which affects the vacuum treatment (such as coating) effect.

[0208] In some embodiments of the present disclosure, the confinement magnetic field is a closed magnetic field, and the central magnetic field direction of the confinement magnetic field is horizontal (for example, as ​ A and ​ B shown).

[0209] In some embodiments, the electromagnetic field propagates in the plasma generation chamber (for example, ​ the plasma generation chamber 20a shown) in the form of electromagnetic waves, and the electromagnetic waves are parallel to the confinement magnetic field. For example, ​ the electromagnetic field generated by the inductance coil 122a shown through the radio frequency current will propagate outward in the form of electromagnetic waves. The electromagnetic waves enter the plasma generation chamber (for example, ​ the plasma generation chamber 20a shown) parallel to the externally applied magnetic field. When propagating in the plasma discharge region, the electrons and ions in the plasma generation chamber (for example, ​ the plasma generation chamber 20a shown) will perform cyclotron motion under the action of the electromagnetic field. The electromagnetic waves are split into left-handed polarization components and right-handed polarization components in the plasma discharge region. Among them, the right-handed polarization component rotates synchronously with the cyclotron electrons, and the electrons will be continuously synchronously accelerated to obtain higher energy. Through the interaction between the electromagnetic waves and the plasma, the energy of the electrons is transferred to the plasma, greatly increasing the plasma density, thereby increasing the concentration of neutral particles. At the same time, the higher collision frequency also provides a higher density of plasma under low-pressure conditions. The design of the confinement magnetic field enables the active source (for example, ​ the active source 100a shown) to operate at a wider working gas pressure.

[0210] ​ A schematic structural diagram showing the position setting of the magnet 91 according to some embodiments of the present disclosure.

[0211] In some embodiments of the present disclosure, the magnetic field confinement mechanism 90 may include at least one magnet 91 to generate a confinement magnetic field.

[0212] Those skilled in the art can understand that a closed magnetic field can be generated by any appropriate number of magnets, and the magnets can also be in any appropriate form, such as permanent magnets (e.g., magnets, etc.), electromagnets (e.g., coils, etc.), and so on. In some embodiments, the magnetic field constraint mechanism 90 can include a magnetic coil (not shown in the figure), and a closed magnetic field is generated through the magnetic coil.

[0213] As ​ shown, in some embodiments of the present disclosure, at least one magnet 91 is disposed around the inductance coil 122a.

[0214] As ​ shown, in some embodiments of the present disclosure, at least one magnet 91 may include a plurality of magnets, such as magnet groups 91a and 91b symmetrically arranged. Both magnet groups 91a and 91b may include three rows of magnets arranged at intervals. Taking magnet group 91a as an example, it may include a first row of magnets 911a, a second row of magnets 911b, and a third row of magnets 911c arranged at intervals, and each row of magnets may in turn include three laterally spaced magnets.

[0215] Those skilled in the art can understand that the arrangement of the magnets shown ​ is only exemplary. For example, the plurality of magnets 91 may include magnets with other arrangements, and the magnet groups 91a and 91b may also include other numbers of rows of magnets, such as one row of magnets, two rows of magnets, or may include four or more rows of magnets, etc. The fact that each row of magnets may include three laterally spaced magnets is also only exemplary. Each row of magnets may also include other numbers of magnets, such as one magnet, two magnets, or four or more magnets, etc.

[0216] As ​ shown, in some embodiments of the present disclosure, the magnet may be a cylindrical magnet. Those skilled in the art can understand that this is only exemplary, and other shaped magnets may also be selected, such as cubic magnets, prismatic magnets, etc.

[0217] As ​ shown, in some embodiments of the present disclosure, the magnetic field constraint mechanism 90 may further include a magnet fixing mechanism 94. The magnet fixing mechanism 94 can be used to dispose the magnet 91 around the inductance coil 122a.

[0218] As ​ shown, in some embodiments, the magnet fixing mechanism 94 may include a support portion 942 for disposing the magnet 91 around the inductance coil 122. The support portion 942 may include a plurality of magnet fixing holes (not shown in the figure) for fixing a plurality of magnets. The support portion 942 may be generally cylindrical and may also include a plurality of opposite or spaced-apart portions, as ​Two relatively arranged parts as shown. The magnet fixing mechanism 94 may further include a fixing ring 941 disposed at the distal end of the support portion 942.

[0219] ​ Schematic structural diagram of the magnetic field confinement mechanism 90 according to some embodiments of the present disclosure. ​ Shown ​ B - B sectional view. ​ Schematic partial structural diagram of the active source according to some other embodiments of the present disclosure. ​ Shown ​ C - C sectional view of A.

[0220] As ​ and ​ shown, in some embodiments of the present disclosure, the magnetic field confinement mechanism 90 may further include a magnet cooling mechanism 92. As ​ shown, the magnet cooling mechanism 92 may include an inner magnet cooling tube 921 and an outer magnet cooling tube 922. The inner magnet cooling tube 921 is disposed inside the support portion 942 (the support portion 942 is omitted in the figure for convenience of illustration). The outer magnet cooling tube 922 is sleeved outside the inner magnet cooling tube 921 and is disposed outside the support portion 942. A magnet cooling channel 926 for circulating the coolant is formed between the inner magnet cooling tube 921 and the outer magnet cooling tube 922. Since the inner magnet cooling tube 921 and the outer magnet cooling tube 922 are respectively disposed inside and outside the support portion 942, a plurality of magnets 91 (such as magnet groups 91a, 91b) may be located in the magnet cooling channel 926, thereby being immersed in the coolant, so as to enhance the cooling effect.

[0221] As ​ shown, the magnet cooling mechanism 92 may further include a magnet cooling inlet pipe 923 and a magnet cooling outlet pipe 924. The magnet cooling inlet pipe 923 is used to introduce the coolant into the magnet cooling channel 926. The magnet cooling outlet pipe 924 is used to discharge the coolant in the magnet cooling channel 926.

[0222] As ​ and 18B shown, in some embodiments of the present disclosure, the magnet cooling mechanism 92 may further include a magnet cooling inner outlet pipe 925. The magnet cooling inner outlet pipe 925 extends along the outer magnet cooling tube 922 and the distal end communicates with the magnet cooling channel 926. When the liquid level height of the coolant in the magnet cooling channel 926 is higher than that of the magnet cooling inner outlet pipe 925, the coolant can be discharged from the magnet cooling inner outlet pipe 925. The magnet cooling inner outlet pipe 925 is connected to the magnet cooling outlet pipe 924 and can be used to discharge the coolant in the magnet cooling channel 926.

[0223] The fixing ring 941 of the magnet fixing mechanism 94 can be arranged at the distal end of the magnet cooling mechanism 92 and is hermetically connected to the distal end of the magnet cooling channel 926. The supporting part 942 is connected to the fixing ring 941 and extends towards the proximal end of the magnet cooling channel 926. As ​ shown, the magnetic field confinement mechanism 90 can further include a flange 93. The flange 93 is hermetically connected to the proximal end of the magnet cooling channel 926. The flange 93 can include a channel allowing the magnet cooling inlet pipe 923 and the magnet cooling outlet pipe 924 to pass through.

[0224] ​ Shows a schematic three-dimensional structure diagram of the active source 100 according to some embodiments of the present disclosure.

[0225] As ​ shown, the active source 100 can further include a support block 15 and a signal shielding cover 16. The support block 15 is used to support the radio frequency power supply 11. The signal shielding cover 16 can be arranged at the electrode feedthrough 13 as ​ shown. For example, the electrode feedthrough 13 is arranged inside the signal shielding cover 16 to shield the signal interference at the electrode feedthrough 13. In some embodiments, the signal shielding cover 16 can further include a fan (not shown in the figure) for dissipating heat at the electrode feedthrough 13 shielded therein.

[0226] ​ A-C show the geometric arrangement diagrams of the magnets during simulation according to some embodiments of the present disclosure, where ​ A shows the arrangement diagram of the magnets in the x-y plane; ​ B shows the arrangement diagram of the magnets in the x-z plane; ​ C shows the three-dimensional arrangement diagram of the magnets. ​ A-C show, according to some embodiments of the present disclosure, for the geometric arrangement of the magnets as ​ shown in A-C, the multi-section magnetic field spatial distribution obtained after magnet simulation, where ​ A shows the multi-section magnetic field spatial distribution in the x-y plane; ​ B shows the multi-section magnetic field spatial distribution in the x-z plane; ​ C shows the three-dimensional multi-section magnetic field spatial distribution. ​ A-C show, according to some embodiments of the present disclosure, for the geometric arrangement of the magnets as ​ shown in A-C, the surface magnetic field spatial distribution obtained after magnet simulation, where ​ A shows the surface magnetic field spatial distribution in the x-y plane; ​ B shows the surface magnetic field spatial distribution in the x-z plane; ​ C shows the surface magnetic field spatial distribution in the y-z plane. ​ A-C show, according to some embodiments of the present disclosure, for the geometric arrangement of the magnets as ​The geometric arrangement of the magnets shown in A-C, and the line result diagram obtained after magnet simulation, where ​ A shows the line result diagram of the x-axis; ​ B shows the line result diagram of the y-axis; ​ C shows the line result diagram of the z-axis. It can be seen that there are uniformly or relatively uniformly distributed magnetic flux densities on the x-axis, y-axis, and z-axis.

[0227] As ​ shown in A-20C, in some embodiments of the present disclosure, a magnet arrangement method as ​ is adopted, and three rows of magnets are arranged at intervals from bottom to top for simulation experiments. The simulation experiment results are as ​ shown in A to ​ C.

[0228] Those skilled in the art can understand that although ​ the magnets shown in A- ​ C are similar in shape to cylinders, this is only exemplary. In some embodiments of the present disclosure, magnet materials of other shapes can also be used, such as rectangular magnets.

[0229] ​ shows a schematic structural diagram of a vacuum system 1000 according to some embodiments of the present disclosure. ​ shows a schematic diagram of the epitaxial growth process of a vacuum system (for example, the vacuum system 1000) according to some embodiments of the present disclosure.

[0230] As ​ shown, the vacuum system 1000 may include a vacuum chamber 200, an active source (for example, ​ the active source 100 shown or ​ the active source 100a shown, etc.) and a sample 300. The active source 100 or 100a can be at least partially disposed in the vacuum chamber 200 through a support flange 51, and can be used to emit neutral particles to the sample 300 in the vacuum chamber 200, so as to perform various vacuum processes, such as coating, cleaning, etching, and so on.

[0231] As ​ shown, in some embodiments of the present disclosure, the vacuum system 1000 may further include a deposition source 400. The deposition source 400 is vacuum-sealedly connected to the vacuum chamber 200 and is used to emit a deposition particle beam to the sample 300.

[0232] As ​ shown, in some embodiments of the present disclosure, the deposition source 400 may include a metal source or a non-metal source. The metal source may include an aluminum (Al) evaporation source, a gallium (Ga) evaporation source, etc. The non-metal source may include, for example, a silicon (Si) evaporation source, etc.

[0233] In some embodiments of the present disclosure, a heater 210 may further be included in the vacuum chamber 200 for heating the sample.

[0234] As ​ shown, in some embodiments of the present disclosure, a method for forming a compound film using active particles may include: a deposition source 400 (e.g., an aluminum evaporation source, a gallium evaporation source, a silicon evaporation source) emits at least one deposition particle beam towards the sample 300. The active source 100 or 100a emits active particles towards the sample 300 to form a compound film (e.g., a single crystal aluminum nitride film, a single crystal gallium nitride film, a single crystal silicon nitride film, etc.) on the sample 300.

[0235] As ​ shown, in some embodiments of the present disclosure, a method for forming a compound film using active particles may include: a deposition source 400 (e.g., an aluminum evaporation source, a gallium evaporation source, a silicon evaporation source) emits a deposition particle beam towards the sample 300 to form a deposition particle film (e.g., an aluminum film, a gallium film, a silicon film, etc.). The active source 100 or 100a emits active particles towards the deposition particle film of the sample 300 to form a compound film (e.g., an aluminum nitride film, a gallium nitride film, a silicon nitride film, etc.).

[0236] As ​ shown, in some other embodiments of the present disclosure, a method for forming a compound film using active particles may include: during the process of the deposition source 400 (e.g., an aluminum evaporation source, a gallium evaporation source, a silicon evaporation source) emitting a deposition particle beam towards the sample 300, the active source 100 or 100a emits active particles towards the sample 300 to form a compound film (e.g., an aluminum nitride film, a gallium nitride film, silicon nitride, etc.).

[0237] In some embodiments of the present disclosure, a method for forming a compound film (e.g., a single crystal metal compound film) using active particles may include: treating the surface of a single crystal Si(111) semiconductor to remove contaminants or amorphous oxides on the surface of the single crystal Si(111) semiconductor. Emitting an aluminum particle beam towards the surface of the single crystal Si(111) semiconductor and controlling the temperature of the surface of the single crystal Si(111) semiconductor not to exceed 100 °C to obtain a single crystal aluminum film. After annealing the single crystal aluminum film, while maintaining the temperature of the surface of the single crystal Si(111) semiconductor not to exceed 100 °C, emitting active particles towards the single crystal aluminum film, thereby obtaining a single crystal aluminum nitride film at near room temperature.

[0238] In some embodiments of the present disclosure, the preparation of a single crystal AlN film may include:

[0239] S1. The sample is a single crystal Si(111) substrate. Perform surface deoxidation treatment on the single crystal Si(111) substrate. For example, the Si(111) polished wafer can be placed in a vacuum chamber (e.g., ​The shown vacuum chamber 200), and then maintained at a high temperature of 920 °C for 20 minutes to remove surface oxides. Then the temperature of the single-crystal Si(111) substrate was lowered to 60 °C to prepare for depositing a particle film. ​ A shows that the RHEED diffraction pattern of Si(111) at room temperature presents a 7*7 diffraction spot. ​ B shows the RHEED diffraction pattern of Si(111) after removing surface oxides at 920 °C. It can be seen that the amorphous oxides on the surface of the single-crystal Si(111) substrate have been cleaned;

[0240] S2. Open the shutter of the Al evaporation source (deposition source 400), and deposit a single-crystal Al film of about 7 nm on the surface of the cleaned single-crystal Si(111) substrate at a rate of 2 nm / minute. The substrate temperature is always maintained at 60 °C. ​ Shows the RHEED diffraction pattern of the Si(111) surface after depositing a 7-nm single-crystal Al film. The RHEED diffraction pattern after depositing the single-crystal Al film presents fine stripes, indicating that the deposited film is single-crystal Al. According to the lattice spacing of the Si(2-20) crystal plane and the RHEED stripe spacing, as well as the RHEED stripe spacing value of the Al film at the same azimuth angle, the lattice spacing of the (110) crystal plane of the Al film can be obtained as exactly the same as the lattice spacing of the bulk Al(110) crystal plane;

[0241] S3. Keep the single-crystal Al film at 100 °C for 15 min to improve the crystal quality. No obvious change is observed from the RHEED stripes;

[0242] S4. Keep the sample temperature at 100 °C, introduce nitrogen at a flow rate of 1 sccm, then turn on the activation source, set the power to 450 W, and the activation source emits nitrogen plasma to nitride the single-crystal Al film. ​ Shows the RHEED diffraction pattern of the surface of the single-crystal Al film after 5 minutes of nitridation. After 5 minutes of nitridation, the diffraction pattern still remains striped, indicating that a single-crystal AlN film is obtained. The difference is that the stripe spacing has changed. According to the new stripe spacing, the corresponding lattice spacing of AlN can be calculated as only differs by 1% from the theoretical value of the bulk AlN(110) crystal plane only by 1%.

[0243] In some embodiments of the present disclosure, the preparation of the single-crystal AlN film may include:

[0244] (1) The sample may include sapphire and a GaN(001) buffer layer epitaxially grown on the sapphire to obtain a GaN(001) substrate. (For example, GaN(001) can be epitaxially grown on sapphire by metalorganic chemical vapor deposition (MOCVD) method). The surface of the single-crystal GaN(001) substrate is heated for degassing treatment. First, the GaN substrate is placed in a vacuum chamber (for example, the vacuum chamber 200 shown in ​ ), and then held at 700 °C for 20 min to remove surface water vapor. Then the substrate temperature is lowered to 50 °C to prepare for Al film deposition. ​ shows the RHEED diffraction pattern of GaN(001) after surface degassing. It can be seen that the RHEED diffraction pattern of GaN(001) after surface degassing treatment presents bright and sharp diffraction fringes, indicating that the GaN substrate has high crystal quality and a clean surface.

[0245] (2) Open the shutter of the Al evaporation source (deposition source 400), and deposit about 10 nm of Al on the surface of GaN(001) at a rate of 1.3 nm / minute. The substrate temperature is always maintained at 50 °C. ​ shows the RHEED diffraction pattern of the single-crystal Al film deposited on the surface of GaN(001). The RHEED diffraction pattern after Al deposition is still fine stripes, indicating that the deposited film is single-crystal Al. According to the lattice plane spacing along the GaN(1-10) crystal plane and the RHEED stripe spacing, as well as the RHEED stripe spacing of the Al film at the same azimuth angle, the lattice plane spacing of the (110) crystal plane of the Al film can be calculated to be relatively close to the bulk value of the Al(110) crystal plane (with a difference of 3.5%). Considering that Al is under tensile stress from the underlying GaN substrate during epitaxy on GaN, it is reasonable that the lattice expands in the in-plane direction.

[0246] (3) Keep the sample with the single-crystal epitaxial Al film at 100 °C for 15 min to improve the crystal quality. There is no obvious change in the stripes as seen from RHEED.

[0247] (4) Keep the sample temperature at 100 °C, introduce nitrogen at a flow rate of 1 sccm, then turn on the activation source, set the power to 450 W, and the activation source emits nitrogen plasma to nitride the single-crystal metal aluminum film. ​ shows the RHEED diffraction pattern of the single-crystal Al film surface after 30 minutes of nitridation. The diffraction pattern still remains striped, indicating that a single-crystal AlN film is obtained. The difference is that the stripe spacing has changed. According to the new stripe spacing, the corresponding lattice plane spacing can be calculated to be relatively different from the lattice plane spacing value of the (110) crystal plane of bulk AlN It increased by 3.2%. Considering the lattice plane spacing of the Al film (110) before nitridation compared with the bulk value also increased by 3.5%, it is reasonable that the lattice plane spacing of the (110) plane of the AlN single crystal film increased accordingly.

[0248] In some embodiments, the growth rate of aluminum nitride can be changed by changing the power of the RF source of the active source and the flow rate of the working gas (e.g., nitrogen). In some embodiments, single crystal aluminum nitride films with different thicknesses can also be synthesized by changing the nitridation time.

[0249] In some embodiments of the present disclosure, plasma is obtained using an active source, which can react with metallic aluminum at near room temperature to achieve the preparation of single crystal aluminum nitride thin films at near room temperature. Utilize the wetting property of the metal on the semiconductor surface at low temperature and the near room temperature nitridation process to obtain single crystal aluminum nitride thin films with an atomically smooth surface.

[0250] In some embodiments of the present disclosure, the sample may include a Si(111) substrate and an aluminum nitride (AlN) buffer layer on the Si(111) substrate (e.g., by epitaxial growth). For example, a vacuum system 1000 as shown in ​ can be used. The deposition source 400 uses an aluminum evaporation source, and the active source 100 or 100a emits a neutral nitrogen beam to obtain an aluminum nitride (AlN) buffer layer, thereby obtaining an AlN / Si(111) sample. As shown in ​ the vacuum system 1000 can continue to be used to prepare a series of GaN epitaxial layers with growth temperatures lower than conventional ones (e.g., 680 - 750 °C for a plasma-assisted molecular beam epitaxy system (PAMBE)) on the obtained AlN / Si(111) sample.

[0251] As shown in ​ In some other embodiments of the present disclosure, the method of forming a compound film using neutral particles may include: during the deposition source 400 (e.g., a gallium evaporation source) emitting a deposition particle beam to the sample 300, the active source 100 or 100a emits neutral particles (e.g., a neutral nitrogen beam) to the sample 300 to form a GaN epitaxial layer.

[0252] ​ Shows the (002) plane rocking curve of the GaN thin film epitaxially grown at different temperatures by the vacuum system according to some embodiments of the present disclosure. ​ Shows a scanning electron microscope cross-sectional view of the GaN thin film epitaxially grown at 350 °C.

[0253] For GaN epitaxy, the active source works at the same RF power of 300 W and the same nitrogen flow rate of 3 sccm. The GaN sample prepared at 720 °C is used as a reference.Figure 32A It shows that the (002) plane rocking curves of GaN epitaxially grown at 450 °C and 720 °C almost completely overlap. As Figure 32A shown, the full width at half maximum (FWHM) of the (002) rocking curves of GaN epitaxially grown at 450 °C and 720 °C is both 0.34°, indicating that the crystal quality of the GaN epitaxial film is almost unaffected by the substrate temperature in the range of 450 °C - 720 °C. This shows that single-crystal GaN epitaxial growth similar to that at high temperatures can be achieved at 450 °C using neutral particles. Below 450 °C, the rocking curve of GaN (002) has a broadening trend, indicating that the crystal quality decreases as the substrate temperature decreases, which is related to the insufficient migration of atoms on the substrate surface at low temperatures. However, even the GaN film obtained at 200 °C still has a narrow rocking curve (FWHM = 0.5°), indicating that the GaN epitaxially grown at this temperature still has a high crystal quality. The kinetic energy adjustable neutral particles obtained by using the active source in any one of the embodiments of the present disclosure are used for molecular beam epitaxy to achieve near-room-temperature epitaxy of GaN.

[0254] Figure 32B The scanning electron microscope cross-sectional view of the GaN sample epitaxially grown at 350 °C is shown, and it can be seen that the AlN / GaN interface prepared on the Si substrate is clear.

[0255] The active source 100 or 100a according to some embodiments of the present disclosure provides richer adjustable parameters. By adjusting the radio frequency power of the active source, the output power of the electrode bias power supply, the working gas flow rate, etc., the kinetic energy of the neutral particles can be adjusted, improving the flexibility, adaptability and controllability of vacuum treatment using neutral particles, such as improving the controllability of compound film epitaxial growth. For example, in some embodiments, the growth rate of aluminum nitride can be changed by changing the power of the radio frequency source of the active source and the flow rate of the working gas nitrogen.

[0256] According to the active source 100 or 100a of some embodiments of the present disclosure, the kinetic energy of the neutral particles can be controlled within an appropriate range, which can not only overcome the chemical reaction potential barrier and promote film growth, but also avoid the lattice damage problem caused by charged particles. Therefore, epitaxial growth similar to that at high temperatures can be achieved at much lower temperatures.

[0257] In some embodiments, the active source can output active nitrogen particles with different kinetic energies, which can include nitrogen molecules and a small amount of nitrogen atoms. The kinetic energy of the active nitrogen particles is used to further regulate the nitriding ability, thereby changing the film thickness of single-crystal aluminum nitride.

[0258] The present disclosure also provides a semiconductor device.

[0259] In some embodiments of the present disclosure, a semiconductor device may include a field-effect transistor formed by the method of forming a field-effect transistor according to any one of the embodiments of the present disclosure (e.g., Figure 1E the field-effect transistor 10000 shown, Figure 1F the field-effect transistor 10000a shown).

[0260] In some embodiments of the present disclosure, a semiconductor device may include a multi-terminal device, a switching device, an amplifier, an oscillator, a mixer, a filter, a sensor, a rectifier, etc.

[0261] It should be noted that the above are only exemplary embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method of forming a field effect transistor, characterized in that, Comprising: Forming a source region on a substrate; Forming a drain region on the substrate; Forming a channel region on the substrate; Forming a compound film on the channel region as a gate dielectric layer; And Forming a gate on the gate dielectric layer.

2. A method of forming a field effect transistor, characterized in that, Comprising: Forming a gate on a substrate; Forming a compound film on the substrate as a gate dielectric layer; Forming a channel layer on the gate dielectric layer; And Forming a source region and a drain region on the substrate, the gate dielectric layer or the channel layer.

3. The method of forming a field effect transistor according to claim 1, characterized in that, Forming the compound film on the channel region includes: Forming a compound film on the source region, the drain region and the channel region; and Etching and removing the compound film on the source region and the drain region so that the compound film on the channel region serves as the gate dielectric layer.

4. The method of forming a field effect transistor according to claim 2, wherein, Forming the source region and the drain region on the channel layer includes: Coating a photoresist on the channel layer or applying a mask to expose a portion of the channel layer above the gate; and Processing the exposed portion of the channel layer to form a channel region and forming the source region and the drain region in regions on both sides of the channel region.

5. The method for forming a field effect transistor according to any one of claims 1-4, characterized in that Forming the compound film includes: Emitting at least one deposition particle beam towards the channel region or the substrate; and Emitting active particles towards the channel region or the substrate to form the compound film on the channel region or the substrate.

6. The method for forming a field effect transistor according to any one of claims 1-4, characterized in that, Forming the compound film includes: Emitting at least one deposition particle beam towards an auxiliary substrate; Emitting active particles towards the auxiliary substrate to form the compound film on the auxiliary substrate; and Transferring the compound film onto the channel region or the substrate.

7. The method for forming a field effect transistor according to claim 6, wherein Transferring the compound film onto the channel region or the substrate includes: Binding the compound film to the channel region or the substrate; and Separating the compound film from the auxiliary substrate.

8. The method of forming a field effect transistor according to any one of claims 1-4, characterized in that, The compound film includes: a single crystal aluminum oxide film, a single crystal aluminum nitride film or a single crystal gallium oxide film.

9. The method for forming a field effect transistor according to claim 5 or 6, wherein The active particles include plasma or neutral particles.

10. The method for forming a field effect transistor according to claim 5 or 6, wherein Emitting the at least one deposition particle beam towards the channel region, the substrate or the auxiliary substrate includes: Emitting the at least one deposition particle beam towards the channel region, the substrate or the auxiliary substrate to form a deposition particle film; Emitting the active particles towards the channel region, the substrate or the auxiliary substrate includes: Emitting the active particles towards the deposition particle film to form a compound film.

11. The method for forming a field effect transistor according to claim 10, wherein The channel region, the substrate or the auxiliary substrate includes a single crystal semiconductor surface, and emitting the at least one deposition particle beam towards the channel region, the substrate or the auxiliary substrate to form a deposition particle film includes emitting the at least one deposition particle beam towards the single crystal semiconductor surface to epitaxially grow a deposition particle film on the single crystal semiconductor surface; And / or The method for forming a field effect transistor further includes: annealing the deposition particle film.

12. The method for forming a field effect transistor according to claim 5 or 6, characterized in that, Emitting active particles to the channel region, the substrate or the auxiliary substrate includes: During the process of emitting at least one beam of deposition particles to the channel region, the substrate or the auxiliary substrate, active particles are emitted to the channel region, the substrate or the auxiliary substrate to form the compound film.

13. The method for forming a field effect transistor according to claim 5 or 6, wherein The method for forming a field effect transistor further includes: Performing surface treatment on the channel region, the substrate or the auxiliary substrate to remove contaminants or amorphous oxides on the surface of the channel region or the substrate; and / or Forming an epitaxial buffer layer on the surface of the channel region, the substrate or the auxiliary substrate.

14. The method for forming a field effect transistor according to claim 13, wherein The channel region is formed on a single crystal silicon substrate, a single crystal aluminum nitride substrate or a single crystal gallium nitride substrate, or the substrate or the auxiliary substrate includes a single crystal silicon substrate, a single crystal aluminum nitride substrate or a single crystal gallium nitride substrate; and / or The at least one beam of deposition particles includes an aluminum particle beam or a gallium particle beam.

15. The method for forming a field effect transistor according to claim 9, wherein The active particles are generated by an active source, and the active source includes: An electromagnetic field generator for generating an electromagnetic field after being powered on; and A plasma generation chamber coupled to the electromagnetic field generator for accommodating a working gas and plasma generated by the working gas under the action of the electromagnetic field.

16. The method of forming a field effect transistor according to claim 15, wherein, The active source further includes: A neutralizer disposed at the far end of the plasma outlet of the plasma generation chamber. The neutralizer includes a plurality of through holes for allowing the plasma to pass through and form neutral particles. The neutralizer is grounded or the neutralizer is connected to a bias voltage.

17. The method of forming a field effect transistor according to claim 16, wherein, The active source further includes: An electrode bias power supply; and An electrode connected to the electrode bias power supply and disposed inside the proximal end of the plasma generation chamber for guiding charged particles to the neutralizer.

18. The method for forming a field effect transistor according to claim 16, wherein The ratio of the depth to the width of the through hole is 2:1 - 20:1; and / or The kinetic energy of the neutral particles is between 0 eV and 2000 eV.

19. The method of forming a field effect transistor according to any one of claims 18-22, characterized in that, The active source further includes a magnetic field confinement mechanism for generating a confinement magnetic field; The plasma generation chamber is coupled to the electromagnetic field generator and the magnetic field confinement mechanism for accommodating a working gas and plasma generated by the working gas under the action of the electromagnetic field and the confinement magnetic field.

20. The method for forming a field effect transistor according to claim 19, wherein The confinement magnetic field is a closed magnetic field, and the central magnetic field direction of the confinement magnetic field is horizontal; and / or The electromagnetic field propagates in the plasma generation chamber in the form of electromagnetic waves, and the electromagnetic waves are parallel to the confinement magnetic field.

21. The method of forming a field effect transistor according to any one of claims 15-18, characterized in that, The electromagnetic field generator includes: A conduction line, including: A feeding line for connecting to a radio frequency power supply; An inductance coil connected to the feeding line and wound around the plasma generation chamber for generating an electromagnetic field; and A grounding line connected to the inductance coil.

22. The method of forming a field effect transistor according to claim 21, wherein, The conduction line includes a first wire and a second wire, The first wire and the second wire are connected at the feeding end of the feeding line and form a double-wound structure at the inductance coil.

23. The method of forming a field effect transistor according to claim 21, wherein The plasma generation chamber includes a cavity and a contraction section, and the inductance coil is wound around the cavity. The active source further includes a gas introduction component. The gas introduction component includes: An outer tube; A partition block, which is hermetically connected to the outer tube and defines a proximal end portion at the proximal end of the outer tube; and An intake inner tube, the proximal end of which is hermetically inserted into the outer tube through the partition block and communicates with the gas source through the proximal end portion for introducing the gas generated by the gas source. The intake inner tube includes a main body and an expansion section at the distal end, and the expansion section is engaged with the distal end of the outer tube for inputting gas into the cavity.

24. The method for forming a field effect transistor according to claim 21, wherein The conduction line includes a first wire and a second wire with a hollow interior. The neutral beam active source further includes a cooling device. The cooling device includes: A liquid inlet, which communicates with the first wire at the proximal end of the grounding line for introducing a coolant into the conduction line; and A liquid outlet pipe, which communicates with the second wire at the proximal end of the grounding line for discharging the coolant.

25. A semiconductor device, comprising: A field effect transistor formed by the method for forming a field effect transistor according to any one of claims 1-25.

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