Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: S1, providing a substrate, sequentially etching a hard mask layer, an oxide layer and a part of thickness of the substrate, and forming a plurality of first grooves; s2, carrying out isotropic wet etching on the hard mask layer, and etching the two side walls of the hard mask layer between two adjacent first grooves by the same width; s3, performing N-type ion implantation in the substrate to form a first drift region and a second drift region which are spaced from each other; s4, filling the first groove with an isolation layer; s5, executing P-type ion implantation to form a P-type body region; the distance between the shallow trench isolation in the first drift region and the P-type body region is equal to the distance between the shallow trench isolation in the second drift region and the P-type body region. Through isotropic wet processes, the ion implantation processes of the first drift region and the second drift region are ensured to be bilaterally symmetrical in switch tube implantation. After the hard mask layer is etched by the isotropic wet method, the morphology is relatively stable, and the influence of machine fluctuation is small.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The process of simultaneously fabricating bipolar transistors, CMOS devices, and DMOS devices on the same chip is the BCD process. And the switching LDMOS device is a commonly used device in the BCD process. The LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is widely adopted at present because of its advantages such as high voltage resistance, large current driving ability, extremely low power consumption, and the ability to be integrated with CMOS.

[0003] In a switching LDMOS device, the substrate includes a P-type body region and a first drift region and a second drift region located on both sides of the P-type body region; shallow trench isolations are formed in both the first drift region and the second drift region. Since the drift region is associated with the active region, the photoresist topography for forming the drift region and the lithography offset will cause the distance between the shallow trench isolation in the first drift region and the P-type body region and the distance between the shallow trench isolation in the second drift region and the P-type body region to be inconsistent, with poor consistency, resulting in reliability problems of the switching LDMOS device. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, which ensure the symmetry of ion implantation processes in the first drift region and the second drift region through an isotropic wet process. The topography after isotropic wet etching of the hard mask layer is relatively stable and less affected by machine fluctuations. Finally, the left and right dimensions of the transistors on both sides of the present invention are symmetric, with good consistency, improving the reliability of the switching LDMOS device.

[0005] The present invention provides a manufacturing method of a semiconductor device, including:

[0006] Step S1: Provide a substrate, form an oxide layer and a hard mask layer on the surface of the substrate, and sequentially etch the hard mask layer, the oxide layer, and a part of the thickness of the substrate to form a plurality of first trenches;

[0007] Step S2: Isotropically wet-etch the hard mask layer, and the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width;

[0008] Step S3: Using the isotropically etched hard mask layer as a mask, perform N-type ion implantation into the substrate to form spaced first drift regions and second drift regions;

[0009] Step S4: Fill the isolation layer in the first trench; Remove the hard mask layer; Wet-etch and remove the part of the isolation layer that protrudes above the substrate, and the isolation layer remaining in the substrate forms a shallow trench isolation.

[0010] Step S5: Form a gate oxide layer that covers the shallow trench isolation and the substrate; Form a first gate and a second gate above the gate oxide layer; Perform P-type ion implantation into the substrate from the opening between the first gate and the second gate to form a P-type body region between the first drift region and the second drift region; The distance between the shallow trench isolation in the first drift region and the P-type body region is equal to the distance between the shallow trench isolation in the second drift region and the P-type body region.

[0011] Further, in step S1, in a cross-section perpendicular to the substrate, the first trench is rectangular or trapezoidal in an inverted shape.

[0012] Further, in step S2, the hard mask layer includes a silicon nitride layer; The hard mask layer is wet-etched isotropically using a hot phosphoric acid solution.

[0013] Further, step S3 specifically includes: Form the spaced first drift region and second drift region in the substrate by N-type ion implantation and thermal drive; Both the first drift region and the second drift region extend downward from the upper surface of the substrate into the substrate by a certain depth.

[0014] Further, in step S5, inclined ion implantation is used to make the width of the P-type body region greater than the width of the opening; The angle of the ion implantation for forming the part of the P-type body region covered by the first gate tilts to the left is equal to the angle of the ion implantation for forming the part of the P-type body region covered by the second gate tilts to the right.

[0015] Further, after step S5, it further includes:

[0016] Form sidewalls on both sides of the first gate and the second gate respectively.

[0017] Further, after forming the sidewalls, it further includes:

[0018] Selectively perform source-drain ion implantation to form an N-type heavily doped region and a P-type heavily doped region. The N-type heavily doped region includes a source region and a drain region; The source region is located in the upper region of the P-type body region; The drain region is located in the drift region on the side of the shallow trench isolation away from the P-type body region.

[0019] The present invention also provides a semiconductor device, including:

[0020] A substrate, the substrate including a P-type body region and a first drift region and a second drift region located on both sides of the P-type body region; shallow trench isolation is formed in both the first drift region and the second drift region; the distance between the shallow trench isolation in the first drift region and the P-type body region is equal to the distance between the shallow trench isolation in the second drift region and the P-type body region;

[0021] A gate oxide layer is formed on the surface of the substrate, and spaced first and second gates are formed on the surface of the gate oxide layer.

[0022] Further, the width of the first gate is equal to the width of the second gate, and the width of the P-type body region covered by the first gate is equal to the width of the P-type body region covered by the second gate.

[0023] Further, sidewalls are formed on both sides of each of the first gate and the second gate; an N-type heavily doped region is formed in the substrate, the N-type heavily doped region including a source region and a drain region; the source region is located in the upper region of the P-type body region; the drain region is located in the drift region on the side of the shallow trench isolation away from the P-type body region.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention provides a semiconductor device and a manufacturing method thereof, including: S1, providing a substrate, forming an oxide layer and a hard mask layer on the surface of the substrate, etching the hard mask layer, the oxide layer and a part of the thickness of the substrate in sequence to form a plurality of first trenches; S2, isotropically wet-etching the hard mask layer, and the sidewalls on both sides of the hard mask layer between two adjacent first trenches are etched by the same width; S3, using the isotropically etched hard mask layer as a mask, performing N-type ion implantation into the substrate to form spaced first and second drift regions; S4, filling an isolation layer in the first trenches; removing the hard mask layer; wet-etching to remove the part of the isolation layer protruding above the substrate, and the isolation layer remaining in the substrate constitutes shallow trench isolation;

[0026] S5, forming a gate oxide layer, the gate oxide layer covering the shallow trench isolation and the substrate; forming a first gate and a second gate above the gate oxide layer; performing P-type ion implantation into the substrate from the opening between the first gate and the second gate to form a P-type body region located between the first drift region and the second drift region; the distance between the shallow trench isolation in the first drift region and the P-type body region is equal to the distance between the shallow trench isolation in the second drift region and the P-type body region. By the isotropic wet process, it is ensured that the ion implantation processes in the first drift region and the second drift region are symmetric about the switch tube injection. The morphology after isotropically wet-etching the hard mask layer is relatively stable and is less affected by the machine platform fluctuation. The left and right dimensions of the transistors on the left and right sides of the present invention are finally symmetric, with good consistency, improving the reliability of the switch-type LDMOS device. Description of the Drawings

[0027] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Figures 2 to 6 It is a schematic diagram of each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] Among them, the reference numerals are as follows:

[0030] 10 - Substrate; 10a - First drift region; 10b - P - type body region; 10c - Second drift region; 20 - Oxide layer; 30 - Hard mask layer; 40 - Shallow trench isolation; P - Photoresist layer; 11 - Gate oxide layer; 120 - First gate; 220 - Second gate; 13 - Sidewall; D - Drain region; S - Source region. Detailed Embodiments

[0031] The present invention will be further described in detail below with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0032] For the convenience of description, some embodiments of the present application may use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the drawings of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatial relative terms are also intended to include different orientations during the use or operation of the device. For example, if the device in the drawing is flipped, the element or component described as "below" or "beneath" other elements or components will subsequently be positioned "above" or "on" other elements or components. The terms "first", "second", etc. in the following text are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that these terms can be replaced under appropriate circumstances.

[0033] An embodiment of the present invention provides a method for manufacturing a semiconductor device, as Figure 1 shown, including:

[0034] Step S1: Provide a substrate, form an oxide layer and a hard mask layer on the surface of the substrate, and etch the hard mask layer, the oxide layer, and a part of the thickness of the substrate in sequence to form a plurality of first trenches;

[0035] Step S2: Isotropically wet - etch the hard mask layer, and the two side walls of the hard mask layer between two adjacent first trenches are etched by the same width;

[0036] Step S3: Using the isotropically etched hard mask layer as a mask, perform N-type ion implantation into the substrate to form spaced-apart first and second drift regions.

[0037] Step S4: Fill the first trench with an isolation layer; remove the hard mask layer; wet-etch the portion of the isolation layer that protrudes above the substrate, and the isolation layer remaining in the substrate forms a shallow trench isolation.

[0038] Step S5: Form a gate oxide layer that covers the shallow trench isolation and the substrate; form a first gate and a second gate above the gate oxide layer; perform P-type ion implantation into the substrate through the opening between the first gate and the second gate to form a P-type body region between the first drift region and the second drift region; the distance between the shallow trench isolation in the first drift region and the P-type body region is equal to the distance between the shallow trench isolation in the second drift region and the P-type body region.

[0039] The following details each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention with reference to the accompanying drawings.

[0040] As Figure 2 shown, provide a substrate 10, where the substrate includes a single-layer silicon substrate or a SOI substrate, and the SOI substrate includes a bottom silicon layer, an N-type buried layer, and a top silicon layer (such as an epitaxial layer) from bottom to top. The substrate 10 can be any suitable substrate material known in the art, for example, it can be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., or is silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or can also be a double-side polished silicon wafer. Exemplarily, in this embodiment, the substrate is, for example, a silicon wafer.

[0041] Form an oxide layer 20 and a hard mask layer 30 on the surface of the substrate 10, use active area lithography to open the shallow trench isolation (STI) region, and sequentially etch the hard mask layer 30, the oxide layer 20, and a partial thickness of the substrate 10 to form a plurality of first trenches. Exemplarily, in a cross-section perpendicular to the substrate 10, the first trenches are rectangular or trapezoidal in reverse.

[0042] As Figure 3 shown, isotropically wet-etch the hard mask layer 30, and Figure 2The formed semiconductor structure is placed in a hot phosphoric acid solution. After wet etching for a preset time, due to isotropic etching, the sidewalls of the hard mask layer 30 exposed in each first trench are laterally etched by the same width under the same time and the same solution conditions; correspondingly, the two sidewalls of the intermediate hard mask layer 30 between two adjacent first trenches are etched by the same width, the etching width on the left is La, the etching width on the right is Lb, and La = Lb. After wet etching the hard mask layer 30, the part of the first trench located in the hard mask layer 30 is widened, and the first trench after wet etching the hard mask layer 30 is in a T shape. When isotropically wet etching the hard mask layer 30, a photoresist layer P is formed on the upper surface of the hard mask layer 30 to protect the part of the hard mask layer 30 that does not need to be etched.

[0043] As Figure 4 shown, an N-type deep well is formed in the substrate 10 through N-type ion implantation and thermal drive, and the N-type deep well is used as a drift region. The N-type deep well is located in the substrate 10 and extends downward from the upper surface of the substrate 10 to a certain depth. The N-type deep wells on both sides in the substrate 10 are the first drift region 10a and the second drift region 10c respectively. Through an isotropic wet process, the ion implantation processes of the first drift region 10a and the second drift region 10c are guaranteed to be symmetric about the injection in the switching tube. The morphology after isotropic wet etching of the hard mask layer is relatively stable and is less affected by machine fluctuations.

[0044] As Figure 4 and Figure 5 shown, an isolation layer is filled in the T-shaped first trench. Then, the hard mask layer 30 is removed, and the hard mask layer 30 can be removed by wet etching with a hot phosphoric acid solution. Then, the part of the isolation layer that is higher than the substrate 10 is removed by wet etching, and the isolation layer remaining in the substrate forms the shallow trench isolation 40. A wet etching solution for etching silicon oxide is selected, and the preset final etching state is achieved by controlling the etching time and the etching speed.

[0045] As Figure 5 shown, a gate oxide layer 11 is formed, and the gate oxide layer 11 covers the shallow trench isolation 40 and the substrate 10. First gates 120 and second gates 220 with equal widths are formed above the gate oxide layer 11. There is an opening between the first gates 120 and the second gates 220. P-type ion implantation is performed into the substrate 10 from the opening to form a P-type body region 10b between the first drift region 10a and the second drift region 10c. Through inclined ion implantation, the width of the P-type body region is made larger than the width of the opening between the first gates 120 and the second gates 220. By controlling the inclined angle and the implantation concentration of the ion implantation, the width of the P-type body region covered by the first gate 120 can be made equal to the width of the P-type body region covered by the second gate 220. The width of the first gate 120 is equal to the width of the second gate 220.

[0046] Next, sidewalls 13 are formed on both sides of the first gate 120 and the second gate 220 respectively. Selective source-drain ion implantation is performed to form an N-type heavily doped region N+ and a P-type heavily doped region P+. The N-type heavily doped region N+ includes a source region S and a drain region D. The source region S is located in the upper region of the P-type body region 10b. The drain region D is located in the drift region on the side of the shallow trench isolation 40 away from the P-type body region 10b. The first drift region 10a and the second drift region 10c of the present invention adopt an N-type deep well to achieve a higher breakdown voltage. Shallow trench isolations 40 are formed in both the first drift region 10a and the second drift region 10c. The shallow trench isolation 40 optimizes the electric field in the drift region, shortens the current path in the drift region, and brings benefits to the breakdown voltage and leakage current characteristics of the LDMOS device. The process flow of the shallow trench isolation 40 is simple and is easy to integrate with the CMOS process.

[0047] The present invention also provides a semiconductor device, including:

[0048] A substrate 10, the substrate includes a P-type body region 10b and a first drift region 10a and a second drift region 10c located on both sides of the P-type body region 10b; shallow trench isolations 40 are formed in both the first drift region 10a and the second drift region 10c; the distance La between the shallow trench isolation in the first drift region 10a and the P-type body region 10b is equal to the distance Lb between the shallow trench isolation in the second drift region 10a and the P-type body region 10b;

[0049] A gate oxide layer 11 is formed on the surface of the substrate 10, and a first gate 120 and a second gate 220 are formed on the surface of the gate oxide layer 11.

[0050] In a cross-section perpendicular to the substrate 10, the first trench is rectangular or trapezoidal in an inverted shape. A shallow trench isolation 40 is formed in the first trench. Figure 5 It shows that the first trench is rectangular, Figure 6 It shows that the first trench is trapezoidal in an inverted shape.

[0051] In summary, the present invention provides a semiconductor device and a manufacturing method thereof, including: S1. Providing a substrate, forming an oxide layer and a hard mask layer on the surface of the substrate, sequentially etching the hard mask layer, the oxide layer and a part of the thickness of the substrate to form a plurality of first trenches; S2. Isotropically wet-etching the hard mask layer, and the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width; S3. Using the isotropically etched hard mask layer as a mask, performing N-type ion implantation into the substrate to form spaced-apart first drift regions and second drift regions; S4. Filling an isolation layer in the first trenches; removing the hard mask layer; wet-etching to remove the part of the isolation layer that protrudes above the substrate, and the isolation layer remaining in the substrate constitutes shallow trench isolation; Step S5. Forming a gate oxide layer, the gate oxide layer covering the shallow trench isolation and the substrate; forming a first gate and a second gate above the gate oxide layer; performing P-type ion implantation into the substrate from the opening between the first gate and the second gate to form a P-type body region between the first drift region and the second drift region; the distance between the shallow trench isolation in the first drift region and the P-type body region is equal to the distance between the shallow trench isolation in the second drift region and the P-type body region. By using an isotropic wet process, it is ensured that the ion implantation processes in the first drift region and the second drift region are symmetric about the injection of the switching transistor. The morphology after isotropically wet-etching the hard mask layer is relatively stable and less affected by machine fluctuations. Finally, the left and right dimensions of the transistors on both sides of the present invention are symmetric, with good consistency, improving the reliability of the switching LDMOS device.

[0052] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same and similar parts among the various embodiments, reference can be made to each other. For the methods disclosed in the embodiments, since they correspond to the devices disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part.

[0053] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A manufacturing method of a semiconductor device, characterized in that, Including: Step S1: Provide a substrate, form an oxide layer and a hard mask layer on the surface of the substrate, etch the hard mask layer, the oxide layer and a part of the thickness of the substrate in sequence to form a plurality of first trenches; Step S2: Isotropically wet-etch the hard mask layer, and the side walls on both sides of the hard mask layer between two adjacent first trenches are etched with the same width; Step S3: Using the isotropically etched hard mask layer as a mask, perform N-type ion implantation into the substrate to form spaced first drift regions and second drift regions; Step S4: Fill the isolation layer in the first trenches; Remove the hard mask layer; Wet-etch and remove the part of the isolation layer that protrudes above the substrate, and the isolation layer remaining in the substrate constitutes shallow trench isolation; Step S5: Form a gate oxide layer, the gate oxide layer covering the shallow trench isolation and the substrate; form a first gate and a second gate above the gate oxide layer; perform P-type ion implantation into the substrate through the opening between the first gate and the second gate to form a P-type body region between the first drift region and the second drift region; the distance between the shallow trench isolation in the first drift region and the P-type body region is equal to the distance between the shallow trench isolation in the second drift region and the P-type body region.

2. The manufacturing method of the semiconductor device according to claim 1, wherein: In step S1, in the cross-section perpendicular to the substrate, the first trench is rectangular or trapezoidal in reverse.

3. The manufacturing method of the semiconductor device according to claim 1, wherein: In step S2, the hard mask layer includes a silicon nitride layer; the hard mask layer is isotropically wet-etched using a hot phosphoric acid solution.

4. The manufacturing method of the semiconductor device according to claim 1, wherein: Step S3 specifically includes: forming the spaced first drift regions and second drift regions in the substrate through N-type ion implantation and thermal drive; both the first drift region and the second drift region extend downward from the upper surface of the substrate into the substrate by a certain depth.

5. The manufacturing method of the semiconductor device according to claim 1, wherein: In step S5, inclined ion implantation is used to make the width of the P-type body region greater than the width of the opening; the angle of the ion implantation for the part of the P-type body region covered by the first gate tilting to the left is equal to the angle of the ion implantation for the part of the P-type body region covered by the second gate tilting to the right.

6. The manufacturing method of the semiconductor device according to claim 1, wherein: After step S5, it further includes: Form sidewalls on both sides of the first gate and the second gate respectively.

7. The manufacturing method of the semiconductor device according to claim 6, wherein: After forming the sidewalls, it further includes: Selectively perform source-drain ion implantation to form an N-type heavily doped region and a P-type heavily doped region, the N-type heavily doped region including a source region and a drain region; the source region is located in the upper region of the P-type body region; the drain region is located in the drift region on the side of the shallow trench isolation away from the P-type body region.

8. A semiconductor device, characterized in that, Including: A substrate, the substrate including a P-type body region and a first drift region and a second drift region located on both sides of the P-type body region; shallow trench isolation is formed in both the first drift region and the second drift region; the distance between the shallow trench isolation in the first drift region and the P-type body region is equal to the distance between the shallow trench isolation in the second drift region and the P-type body region; A gate oxide layer is formed on the surface of the substrate, and spaced first and second gates are formed on the surface of the gate oxide layer.

9. The semiconductor device according to claim 8, wherein, the width of the first gate is equal to the width of the second gate, and the width of the P-type body region covered by the first gate is equal to the width of the P-type body region covered by the second gate.

10. The semiconductor device according to claim 8, wherein, sidewalls are formed on both sides of the first gate and the second gate respectively; an N-type heavily doped region is formed in the substrate, the N-type heavily doped region including a source region and a drain region; the source region is located in the upper region of the P-type body region; the drain region is located in the drift region on the side of the shallow trench isolation away from the P-type body region.

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