Semiconductor device, manufacturing method thereof, power amplifier chip and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof, a power amplifier chip and electronic equipment. The semiconductor device includes a semiconductor substrate, an epitaxial layer, and a first electrode. A first groove is formed in the surface of the epitaxial layer, one part of the first electrode is located in the first groove, and the other part of the first electrode protrudes out of the surface of the side, away from the semiconductor substrate, of the epitaxial layer. The first electrode is a source electrode or a drain electrode and comprises a contact layer, a metal isolation layer and an anti-oxidation metal layer, the contact layer is in contact with the epitaxial layer on the inner wall of the first groove, and the metal isolation layer is located between the contact layer and the anti-oxidation metal layer; the thickness of the surface, protruding out of the side, away from the semiconductor substrate, of the metal isolation layer, of the anti-oxidation metal layer is larger than or equal to 400 nm and larger than or equal to two times of the thickness of the channel layer. The thickness of the anti-oxidation metal layer is large, in the annealing treatment process, the thick anti-oxidation metal layer can fully isolate air, good and reliable ohmic contact is formed, and the resistivity of the ohmic contact is reduced.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority of a Chinese patent application with the application number 202410103088.3 and the application title "A Semiconductor Device and Its Manufacturing Method", which was filed with the China National Intellectual Property Administration on January 24, 2024. The entire content of which is incorporated herein by reference. Technical Field

[0003] This application relates to the technical field of radio frequency devices, and particularly to a semiconductor device, a manufacturing method thereof, a power amplifier chip, and an electronic device. Background Art

[0004] The GaN / GaAs-based high electron mobility transistor (HEMT) device is used as a radio frequency front-end device and has outstanding advantages such as large output power and high efficiency. During the process of manufacturing the HEMT device, a stacked metal is deposited on the surface of the epitaxial layer, and an ohmic contact can be formed at the interface between the epitaxial layer and the stacked metal through annealing treatment. However, in the related art, the resistivity of the ohmic contact of the HEMT device is relatively high, which affects the performance of the HEMT device, such as output power and efficiency. Summary of the Invention

[0005] Embodiments of this application provide a semiconductor device, a manufacturing method thereof, a power amplifier chip, and an electronic device to reduce the resistivity of the ohmic contact of the semiconductor device. The semiconductor device in the embodiments of this application can be applied to radio frequency application devices, especially in terminal portable devices such as mobile phones, tablet computers, and laptop computers.

[0006] In a first aspect, embodiments of this application provide a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device provided by the embodiments of this application may include:

[0007] Step 1: Form an epitaxial layer on a semiconductor substrate, and perform patterning on the epitaxial layer to form a first groove on the surface of the epitaxial layer on the side facing away from the semiconductor substrate; wherein, the epitaxial layer includes: a channel layer;

[0008] Step 2: forming a first electrode having a portion located within the first groove and another portion protruding from a surface of the epitaxial layer facing away from the semiconductor substrate; wherein the first electrode is a source electrode or a drain electrode, and comprises: a contact layer, a metal isolation layer, and an anti-oxidation metal layer; the contact layer contacts the epitaxial layer on an inner wall of the first groove; the anti-oxidation metal layer is located on a side of the contact layer facing away from the semiconductor substrate; and the metal isolation layer is located between the contact layer and the anti-oxidation metal layer; the thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer;

[0009] Step 3: performing annealing treatment on the structure after forming the anti-oxidation metal layer to obtain a semiconductor device.

[0010] In the method for manufacturing a semiconductor device provided by an embodiment of the present application, during the process of manufacturing the first electrode, the thickness of the anti-oxidation metal layer formed is greater than or equal to 400nm and greater than or equal to twice the thickness of the channel layer, that is, a thicker anti-oxidation metal layer is formed in the first electrode, and then the structure after the anti-oxidation metal layer is formed is annealed. In this way, during the annealing process, the thicker anti-oxidation metal layer can fully isolate the air, prevent the air from reacting with the metal in the first electrode, and avoid the formation of holes in the ohmic contact area, so that the contact layer and the epitaxial layer can react well, thereby forming a good and reliable ohmic contact and reducing the resistivity of the ohmic contact. Moreover, during the annealing process, a small amount of metal elements in the anti-oxidation metal layer can diffuse into the epitaxial layer to participate in the ohmic contact reaction, that is, the metal elements in the anti-oxidation metal layer can also serve as reactants in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact. In addition, compared with the manufacturing process of the related art, the manufacturing method provided by the embodiment of the present application can also save the subsequent metal thickening process, avoid multiple metal deposition processes, and avoid stability problems caused by interface exposure. It should be explained that ohmic contact means that when the first electrode contacts the epitaxial layer, a very small contact barrier is formed at the contact interface, or no contact barrier is formed at the contact interface. In other words, the contact resistivity of ohmic contact is low.

[0011] Moreover, in the method for manufacturing a semiconductor device provided in an embodiment of the present application, a first groove is formed on the surface of the epitaxial layer facing away from the semiconductor substrate, and a portion of the subsequently formed first electrode is located within the first groove. This can increase the contact area between the contact layer in the first electrode and the epitaxial layer, thereby further reducing the resistivity of the ohmic contact between the first electrode and the epitaxial layer.

[0012] In the embodiment of the present application, the semiconductor substrate may be made of a high-resistance semiconductor material. For example, the semiconductor substrate may include a Si material with a resistivity greater than 5000Ω.cm. For example, the semiconductor substrate may include a Si material with a resistivity greater than 1e4 Si material with resistivity in Ω·cm; or, the semiconductor substrate may include SiC material with resistivity greater than 1e 6 Ω·cm; or, the semiconductor substrate may include GaN material with resistivity greater than 1e4 Ω·cm; or, the semiconductor substrate may include sapphire material with resistivity greater than 1e11 Ω·cm. Of course, the semiconductor substrate in the embodiments of the present application may also adopt other high-resistance semiconductor materials, which are not limited in this application.

[0013] In the above step 1, forming an epitaxial layer on the semiconductor substrate may specifically include: forming a channel layer with a thickness in the range of 100 nm to 400 nm on the semiconductor substrate. Exemplarily, an undoped gallium nitride (GaN) material may be used to form the channel layer. Then, a barrier layer with a thickness in the range of 4 nm to 35 nm is formed on the channel layer. For example, an aluminum gallium nitride (AlGaN) material may be used to form a barrier layer with a thickness in the range of 10 nm to 35 nm. Alternatively, an aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN) material may be used to form a barrier layer with a thickness in the range of 4 nm to 10 nm.

[0014] In a possible implementation, in the above step 1, forming an epitaxial layer on the semiconductor substrate may further include: forming a cap layer with a thickness in the range of 1 nm to 5 nm on the barrier layer. Exemplarily, materials such as gallium nitride (GaN) and in-situ silicon nitride (SiN) may be used to form the cap layer.

[0015] In a possible implementation, in the above step 1, forming an epitaxial layer on the semiconductor substrate may further include: before forming the channel layer, sequentially forming a nucleation layer, a transition layer, and a buffer layer on the semiconductor substrate. Specifically, an aluminum nitride (AlN) material may be used to form a nucleation layer with a thickness in the range of 100 nm to 300 nm. An aluminum gallium nitride (AlGaN) material may be used to form a transition layer with a thickness in the range of 100 nm to 500 nm. A high-resistance semiconductor material may be used to fabricate the buffer layer. For example, a high-resistance gallium nitride (GaN) material may be used to form the buffer layer. The buffer layer may be doped with carbon (C) element with a concentration greater than 1e 17 ~2e 19 ; or, the buffer layer may be doped with iron (Fe) element with a concentration greater than 1e 17 . The thickness of the buffer layer may be in the range of 0.5 μm to 2 μm.

[0016] In a possible implementation, epitaxial growth processes such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and atomic layer deposition (ALD) can be used to fabricate each film layer in the epitaxial layer.

[0017] In the above step one, the epitaxial layer can be patterned to form a first groove on the surface of the epitaxial layer. In specific implementation, the depth of the first groove is related to factors such as the material of the subsequent contact layer to be formed and the annealing temperature of the subsequent annealing process, which will be described in detail below in conjunction with the drawings.

[0018] In some embodiments of the present application, a metal material can be used to fabricate the contact layer, and annealing treatment can be performed at a relatively high temperature. Exemplarily, the temperature of the annealing treatment can be in the range of 500°C to 1000°C, and the bottom of the first groove can be located inside the barrier layer. The following method can be used to pattern the epitaxial layer:

[0019] A photoresist layer is formed on the surface of the epitaxial layer, and processes such as photolithography and development are performed on the photoresist layer to pattern the photoresist layer, so that the pattern of the photoresist layer covers the area other than the first groove to be formed, and the area of the first groove to be formed is exposed. Using the pattern of the photoresist layer as a mask, the epitaxial layer is etched. Exemplarily, an inductively coupled plasma (ICP) etching process can be used to etch the epitaxial layer. Specifically, an inductively coupled plasma process containing a Cl-based gas can be used to etch the epitaxial layer. During the etching process, the etching depth can be controlled by adjusting parameters such as the time and power of the etching process, so as to form a first groove extending from the surface of the epitaxial layer on the side away from the semiconductor substrate to the inside of the barrier layer.

[0020] For the case of using a metal material to fabricate the contact layer, the above step two can specifically include:

[0021] A contact layer is formed using a metal material, and a part of the contact layer is located inside the first groove, and the other part extends to the area of the surface of the epitaxial layer other than the first groove, and a second groove is formed on the surface of the contact layer on the side away from the semiconductor substrate. The formed contact layer can contact the epitaxial layer on the inner wall of the first groove. Such a setting can make the contact area between the contact layer and the epitaxial layer larger, thereby reducing the resistivity of the ohmic contact between the contact layer and the epitaxial layer. Exemplarily, a metal titanium (Ti) material can be used to fabricate the contact layer, and the thickness of the formed contact layer can be in the range of 4 nm to 20 nm.

[0022] A metal isolation layer is formed of a metal material, and a part of the metal isolation layer is located in the second groove, and the other part extends to the area on the contact layer other than the second groove, and a third groove is formed on the surface of the metal isolation layer on the side facing away from the semiconductor substrate. By forming the metal isolation layer on the surface of the contact layer, it is possible to prevent the material in the subsequently formed antioxidant metal layer from diffusing into the contact layer, and avoid excessive downward diffusion of metal elements in the antioxidant metal layer, resulting in reliability problems of semiconductor devices. Specifically, the metal isolation layer may include at least one of Ti, Ni, Mo, Pt, Mo, Ir, Nb, and the thickness of the metal isolation layer may be in the range of 20 nm to 100 nm. In a possible implementation manner, after forming the contact layer and before forming the metal isolation layer, it may further include: forming a first metal layer on the surface of the contact layer, a part of the first metal layer is located in the second groove, and the other part extends to the area on the surface of the contact layer other than the second groove, and a groove is also formed on the side of the first metal layer facing away from the semiconductor substrate. Then, the metal isolation layer may be formed on the surface of the first metal layer, and a part of the metal isolation layer is located in the groove on the surface of the first metal layer, and the other part extends to the area on the surface of the first metal layer other than the groove. Exemplarily, the first metal layer may include an aluminum (Al) material, and the thickness of the first metal layer may be between 80 nm and 200 nm. During the subsequent annealing process, the first metal layer may diffuse downward. For example, it may diffuse into the channel layer and participate in the ohmic contact reaction, which is beneficial to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0023] An antioxidant metal layer is formed of a metal material, and a part of the antioxidant metal layer is located in the third groove, and the other part protrudes from the surface of the metal isolation layer on the side facing away from the semiconductor substrate. In the embodiment of the present application, a relatively thick antioxidant metal layer is formed before the annealing treatment. The antioxidant metal layer can fill the third groove, and the surface of the antioxidant metal layer on the side facing away from the semiconductor substrate can be a flat surface. The thickness of the antioxidant metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer. In a possible implementation manner, inert metal materials such as gold (Au) and platinum (Pt) that are not easily oxidized during the annealing treatment (the annealing temperature is in the range of 200 °C to 1000 °C) can be used to make the antioxidant metal layer; and / or, an alloy material with antioxidant properties can be used to make the antioxidant metal layer. For example, titanium nitride (TiN) material with good electrical conductivity and good stability can be used.

[0024] In addition, in order to prevent the subsequent etching process of the dielectric layer from damaging the antioxidant metal layer, step two described above may further include: forming an etch stop layer on the antioxidant metal layer. Exemplarily, metal materials such as Ti and Ni with slow etching characteristics of F-based reactive ion etching (RIE) can be used, and the thickness of the etch stop layer can be greater than or equal to 20 nm.

[0025] After forming the etch stop layer, step two described above may further include: patterning the contact layer, the first metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer, removing the portions of the contact layer, the first metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer in the regions outside the first groove, and then removing the photoresist layer to obtain the first electrode. That is to say, the pattern of the first electrode is consistent with the region of the first groove. Moreover, the contact layer, the first metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer can be patterned using the same lithography process. In this way, in the first electrode fabricated, the outer edges formed by the contact layer, the first metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer are flush, which can make the morphology of the first electrode better and improve the electrical performance of the semiconductor device. It can be understood that in the embodiments of the present application, due to the limitation of the manufacturing process level, the outer edges of some film layers in the first electrode being flush means that the outer edges of these film layers are substantially flush within a certain error range. In the embodiments of the present application, the semiconductor device may include at least one transistor, and each transistor may include a source electrode, a drain electrode, and a gate electrode. The first electrode in the embodiments of the present application may be a source electrode or a drain electrode.

[0026] For the case where the contact layer is made of a metal material, step three described above may specifically include: annealing the structure after forming the antioxidant metal layer at a temperature in the range of 500 °C to 1000 °C. Since the annealing temperature is relatively high, during the annealing process, the contact layer reacts with the epitaxial layer, and the metal elements in the contact layer can penetrate into the channel layer through the barrier layer, thereby forming a good and reliable ohmic contact. Specifically, processes such as rapid thermal processing (RTP) and laser annealing can be used for annealing. Moreover, during the annealing process, the metal elements in the antioxidant metal layer and the first metal layer can also diffuse into the channel layer and participate in the ohmic contact reaction, which is beneficial to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0027] In other embodiments of the present application, the contact layer includes a semiconductor doping layer and a second metal layer, and is annealed at a relatively low temperature. For example, the annealing temperature may be in the range of 200°C to 500°C. The bottom of the first recess may be located inside the channel layer. The epitaxial layer may be patterned using the following methods:

[0028] A hard mask layer is formed on the surface of the epitaxial layer. In a possible implementation, the hard mask layer can be made of silicon oxide (SiOx) material or silicon nitride (SiNx) material.

[0029] The hard mask layer is patterned so that the pattern of the hard mask layer covers the area outside the first groove to be formed, exposing the area of the first groove to be formed. The epitaxial layer is etched using the pattern of the hard mask layer as a shield. For example, an inductively coupled plasma (ICP) etching process can be used to etch the epitaxial layer. Specifically, an inductively coupled plasma process containing a Cl-based gas can be used to etch the epitaxial layer. During the etching process, the etching depth can be controlled by adjusting parameters such as the etching process time and power, thereby forming a first groove extending from the surface of the epitaxial layer on the side facing away from the semiconductor substrate to the interior of the channel layer.

[0030] In the case where the contact layer includes a semiconductor doped layer and a second metal layer, the above step 2 may specifically include:

[0031] A semiconductor doped layer is formed using a semiconductor material doped with impurities, so that the semiconductor doped layer fills the first groove. In one possible implementation, the semiconductor doped layer can be formed using a gallium nitride (GaN) material doped with a high concentration of N-type impurities. In a specific implementation, in order to ensure that the semiconductor doped layer formed by the epitaxial process can fill the first groove, the formed semiconductor doped layer is generally slightly higher than the surface of the epitaxial layer (i.e., the surface of the cap layer).

[0032] Afterwards, the hard mask layer on the surface of the epitaxial layer (ie, the surface of the cap layer) is removed. For example, a wet etching process may be used to remove the hard mask layer.

[0033] A second metal layer is formed on the semiconductor doped layer using a metal material. The second metal layer can serve as a reactant for an ohmic contact reaction. By forming the semiconductor doped layer within the first recess of the epitaxial layer, the semiconductor doped layer can reduce the potential barrier between the epitaxial layer and the second metal layer, thereby facilitating the formation of an ohmic contact. For example, the second metal layer can include titanium (Ti).

[0034] After that, a metal isolation layer is formed on the surface of the second metal layer, that is, a metal isolation layer is formed on the surface of the contact layer. By forming a metal isolation layer on the surface of the contact layer, it is possible to prevent the material in the subsequently formed antioxidant metal layer from diffusing into the contact layer, and avoid excessive downward diffusion of metal elements in the antioxidant metal layer, which may cause reliability problems in the semiconductor device. In a possible implementation, the metal isolation layer may include platinum (Pt) material.

[0035] After that, an antioxidant metal layer is formed on the metal isolation layer using a metal material, and the thickness of the formed antioxidant metal layer is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer. In a possible implementation, inert metal materials such as gold (Au) and platinum (Pt) that are not easily oxidized during the annealing process (the annealing temperature is in the range of 200 °C to 1000 °C) can be used to fabricate the antioxidant metal layer; and / or, an alloy material with antioxidant properties can be used to fabricate the antioxidant metal layer. For example, TiN material with good electrical conductivity and good stability can be used.

[0036] In addition, in order to prevent damage to the antioxidant metal layer during the etching process of the subsequent dielectric layer, step two above may further include: forming an etch stop layer on the antioxidant metal layer. Exemplarily, metal materials such as Ti and Ni with slow etching characteristics of F-based reactive ion etching (RIE) can be used, and the thickness of the etch stop layer can be greater than or equal to 20 nm.

[0037] During the manufacturing process, the second metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer can be deposited over the entire surface, and then, the second metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer are patterned to remove the portions of the second metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer outside the first groove region to obtain the first electrode. That is to say, the pattern of the first electrode is consistent with the region of the first groove. And, the second metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer can be patterned using the same lithography process. In this way, in the fabricated first electrode, the outer edges of the second metal layer, the metal isolation layer, the antioxidant metal layer, and the etch stop layer are flush, which can make the morphology of the first electrode better and improve the electrical performance of the semiconductor device. It can be understood that in the embodiments of the present application, due to the limitation of the manufacturing process level, the outer edges of some film layers in the first electrode being flush means that the outer edges of these film layers are basically flush within a certain error range. In the embodiments of the present application, the semiconductor device may include at least one transistor, and each transistor may include a source electrode, a drain electrode, and a gate electrode. The first electrode in the embodiments of the present application may be a source electrode or a drain electrode.

[0038] For the case where the contact layer includes a semiconductor doped layer and a second metal layer, step three above may specifically include: annealing the structure after forming the anti-oxidation metal layer at a temperature in the range of 200°C to 500°C. Since in the embodiments of the present application, the bottom of the first groove is inside the channel layer, the semiconductor doped layer in the contact layer can be in direct contact with the channel layer. Therefore, by using a relatively low annealing temperature, a good and reliable ohmic contact can be formed. Specifically, annealing treatment can be carried out by processes such as rapid thermal processing (RTP) and laser annealing.

[0039] For the case where the contact layer is made of a metal material and the contact layer includes a semiconductor doped layer and a second metal layer, after step three above, it may further include: forming an interconnect structure in contact connection with the etch stop layer, and the specific process is as follows:

[0040] Form a passivation layer covering the first electrode. Exemplarily, the passivation layer can be made of silicon nitride (SiN) material.

[0041] Pattern the passivation layer to form a fourth groove penetrating the passivation layer in the area where the gate is to be formed. The bottom surface of the fourth groove is a part of the surface of the epitaxial layer.

[0042] Form a gate contact metal layer on the sidewall and bottom surface of the fourth groove of the passivation layer, and fill the fourth groove with a metal material to form a gate interconnect structure. The gate interconnect structure fills the part of the fourth groove except the gate contact metal layer and protrudes from the surface of the passivation layer. Exemplarily, metal materials such as nickel (Ni) or tungsten (W) can be used to make the gate contact metal layer. The gate contact metal layer can be used as the gate of the transistor. The gate contact metal layer can be in contact with the epitaxial layer to form a Schottky contact. It should be noted that a Schottky contact means that when the gate contact metal layer and the epitaxial layer are in contact, the energy band of the epitaxial layer at the contact interface bends to form a contact potential barrier (which can be called a Schottky barrier). In a possible implementation, the gate interconnect structure can be made of gold (Au) material. The gate interconnect structure can play a role in leading out the gate contact metal layer, and also has the function of anti-oxidation and reducing the gate resistance.

[0043] A dielectric layer is formed to cover the gate interconnect structure, and the dielectric layer covers the passivation layer in the region where the first electrode is located. Exemplarily, a silicon nitride (SiN) material can be used to fabricate the dielectric layer. Then, an etching process is employed to pattern the dielectric layer and the passivation layer, thereby exposing the first electrode. Since the surface of the antioxidant metal layer has an etch stop layer, during the etching process, the etch stop layer can protect the antioxidant metal layer and prevent the antioxidant metal layer from being damaged during the etching process. In a specific implementation, the upper surface of the etch stop layer can be a flat surface, or, during the etching process, the upper surface of the etch stop layer may be etched, that is, a groove may be formed on the upper surface of the etch stop layer.

[0044] A metal material, such as gold (Au) material, is filled in the grooves on the surfaces of the passivation layer and the dielectric layer to form an interconnect structure in contact connection with the etch stop layer, so that the interconnect structure is electrically connected to the first electrode, and the interconnect structure is used to lead out the first electrode. In the direction parallel to the surface of the semiconductor substrate, the width of the grooves on the surfaces of the passivation layer and the dielectric layer is smaller than the width of the antioxidant metal layer. Therefore, the width of the formed interconnect structure is smaller than the width of the antioxidant metal layer.

[0045] In a second aspect, an embodiment of the present application further provides a semiconductor device. The semiconductor device provided by the embodiment of the present application may include: a semiconductor substrate, an epitaxial layer, and a first electrode. In the embodiment of the present application, the semiconductor device may include at least one transistor, and each transistor may include a source electrode, a drain electrode, and a gate electrode. The first electrode in the embodiment of the present application may be a source electrode or a drain electrode. Among them, the epitaxial layer is located above the semiconductor substrate, and a first groove is provided on the surface of the epitaxial layer facing away from the semiconductor substrate. A part of the first electrode is located inside the first groove, and the other part protrudes from the surface of the epitaxial layer facing away from the semiconductor substrate. The first electrode may include: a contact layer, a metal isolation layer, and an antioxidant metal layer. The contact layer contacts the epitaxial layer on the inner wall of the first groove, the antioxidant metal layer is located on the side of the contact layer facing away from the semiconductor substrate, and the metal isolation layer is located between the contact layer and the antioxidant metal layer. The thickness of the antioxidant metal layer protruding from the surface of the metal isolation layer facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer.

[0046] In the semiconductor device provided in the embodiment of the present application, the first electrode includes a contact layer, a metal isolation layer, and an anti-oxidation metal layer. The thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer. The thickness of the anti-oxidation metal layer in the embodiment of the present application is relatively thick. During the annealing process, the thicker anti-oxidation metal layer can fully isolate the air, prevent the air from reacting with the metal in the first electrode, and avoid the formation of holes in the ohmic contact area, so that the contact layer and the epitaxial layer can react well, thereby forming a good and reliable ohmic contact and reducing the resistivity of the ohmic contact. In addition, during the annealing process, a small amount of metal elements in the anti-oxidation metal layer can diffuse into the epitaxial layer to participate in the ohmic contact reaction. In other words, the metal elements in the anti-oxidation metal layer can also serve as reactants in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact. In addition, a first groove is provided on the surface of the epitaxial layer on the side facing away from the semiconductor substrate. A portion of the first electrode is located within the first groove, and the contact layer contacts the epitaxial layer on the inner wall of the first groove. In this way, the contact area between the contact layer and the epitaxial layer can be increased, thereby further reducing the resistivity of the ohmic contact between the first electrode and the epitaxial layer.

[0047] In one possible implementation, the semiconductor device provided in the embodiment of the present application can be manufactured using the manufacturing method in the first aspect mentioned above. Of course, in some cases, the semiconductor device in the embodiment of the present application can also be manufactured using other manufacturing methods, which is not limited in this application.

[0048] In the embodiment of the present application, the semiconductor substrate may include a high-resistance semiconductor material. For example, the semiconductor substrate may include a Si material with a resistivity greater than 5000 Ω.cm. For example, the semiconductor substrate may include a Si material with a resistivity greater than 1e 4 Ω.cm Si material; alternatively, the semiconductor substrate may include a resistivity greater than 1e 6 Ω.cm; or, the semiconductor substrate may include a GaN material with a resistivity greater than 1e4 Ω.cm; or, the semiconductor substrate may include a sapphire material with a resistivity greater than 1e11 Ω.cm. Of course, the semiconductor substrate in the embodiment of the present application may also include other high-resistance semiconductor materials, which is not limited in this application.

[0049] In a possible implementation, the epitaxial layer may include: a channel layer and a barrier layer, and the barrier layer is located on a side of the channel layer away from the semiconductor substrate. Exemplarily, the channel layer may include an undoped gallium nitride (GaN) material, and the thickness of the channel layer may be in the range of 100 nm to 400 nm. The barrier layer may include materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN), etc., and the thickness of the barrier layer may be in the range of 4 nm to 35 nm. For example, when the barrier layer includes an aluminum gallium nitride (AlGaN) material, the thickness of the barrier layer may be in the range of 10 nm to 35 nm. Also, for example, when the barrier layer includes materials such as aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN), etc., the thickness of the barrier layer may be in the range of 4 nm to 10 nm.

[0050] In addition, the epitaxial layer may further include: a cap layer located on a side of the barrier layer away from the semiconductor substrate, and the first groove penetrates through the cap layer in a direction perpendicular to the surface of the semiconductor substrate. Exemplarily, the cap layer may include materials such as gallium nitride (GaN), in-situ silicon nitride (SiN), etc., and the thickness of the cap layer may be in the range of 1 nm to 5 nm.

[0051] In a specific setting, the epitaxial layer may further include: a nucleation layer located between the semiconductor substrate and the channel layer, a transition layer located between the nucleation layer and the channel layer, and a buffer layer between the transition layer and the channel layer. Specifically, the nucleation layer may include an aluminum nitride (AlN) material, and the thickness of the nucleation layer may be in the range of 100 nm to 300 nm. The transition layer may include an aluminum gallium nitride (AlGaN) material, and the thickness of the transition layer may be in the range of 100 nm to 500 nm. The buffer layer may include a high-resistance gallium nitride (GaN) material, and the buffer layer may be doped with carbon elements having a concentration greater than 1e 17 ~2e 19 ; or, the buffer layer may be doped with iron elements having a concentration greater than 1e 17 . The thickness of the buffer layer may be in the range of 0.5 um to 2 um.

[0052] In a possible implementation, the first electrode may further include: an etch stop layer located on a side of the antioxidant metal layer away from the semiconductor substrate, and the etch stop layer may include a metal material. Exemplarily, the etch stop layer may include titanium (Ti) or nickel (Ni), and the thickness of the etch stop layer may be greater than or equal to 20 nm. The etch stop layer can protect the antioxidant metal layer and prevent damage to the antioxidant metal layer during the etching process of the dielectric layer. During the etching process of the dielectric layer, the upper surface of the etch stop layer may be etched, causing the upper surface of the etch stop layer to have grooves. Of course, in some cases, the upper surface of the etch stop layer may also be a flat surface.

[0053] In a possible implementation, the semiconductor device provided by the embodiments of the present application may further include: an interconnect structure located on the side of the first electrode away from the semiconductor substrate. The interconnect structure is in contact connection with the etch stop layer so that the interconnect structure is electrically connected to the first electrode, and the interconnect structure is used to lead out the first electrode. Exemplarily, the interconnect structure may include a metal material such as gold (Au). When specifically arranged, in the direction parallel to the surface of the semiconductor substrate, the width of the interconnect structure may be smaller than the width of the antioxidant metal layer.

[0054] In addition, the semiconductor device in the embodiments of the present application may further include: a passivation layer, a gate contact metal layer, and a gate interconnect structure. Exemplarily, the passivation layer may include a silicon nitride (SiN) material. The passivation layer has a fourth groove that penetrates the passivation layer in the direction perpendicular to the surface of the semiconductor substrate, and the bottom surface of the fourth groove is a part of the surface of the epitaxial layer. The gate contact metal layer covers the side wall and the bottom surface of the fourth groove, and the gate interconnect structure fills the part of the fourth groove except the gate contact metal layer and protrudes from the surface of the passivation layer. Exemplarily, the gate contact metal layer may include a metal material such as nickel (Ni) or tungsten (W). The gate contact metal layer may serve as the gate of the transistor, and the gate contact metal layer may be in contact with the epitaxial layer to form a Schottky contact. It should be noted that a Schottky contact means that when the gate contact metal layer and the epitaxial layer are in contact, the energy band of the epitaxial layer at the contact interface bends to form a contact potential barrier (which can be called a Schottky barrier). In a possible implementation, the gate interconnect structure may include a gold (Au) material. The gate interconnect structure can play a role in leading out the gate contact metal layer, and moreover, the gate interconnect structure can also play a role in antioxidation and reduce the gate resistance.

[0055] In the embodiments of the present application, the depth of the first groove on the surface of the epitaxial layer is related to factors such as the material of the contact layer and the annealing temperature of the annealing treatment.

[0056] In some embodiments of the present application, the contact layer may include a metal material, and the first groove extends from the surface of the epitaxial layer on the side away from the semiconductor substrate to the inside of the barrier layer. During the manufacturing process, annealing treatment can be performed at a relatively high temperature. Exemplarily, the temperature of the annealing treatment may be in the range of 500°C to 1000°C. Due to the relatively high temperature of the annealing treatment, during the annealing treatment, the contact layer reacts with the epitaxial layer, and the metal elements in the contact layer can penetrate into the channel layer through the barrier layer, thereby forming a good and reliable ohmic contact.

[0057] For the case where the contact layer includes a metal material, the first electrode can be arranged in the following manner.

[0058] Specifically, a portion of the contact layer is located within the first recess, while another portion protrudes from the surface of the epitaxial layer facing away from the semiconductor substrate. The contact layer also has a second recess on the surface facing away from the semiconductor substrate. The contact layer can contact the epitaxial layer at the inner wall of the first recess. This arrangement can increase the contact area between the contact layer and the epitaxial layer, thereby reducing the resistivity of the ohmic contact between the contact layer and the epitaxial layer. Exemplarily, the contact layer can include titanium (Ti) material, and the thickness of the contact layer can be in the range of 4nm to 20nm.

[0059] A portion of the metal isolation layer is located within the second groove, while another portion protrudes from the surface of the contact layer facing away from the semiconductor substrate. The metal isolation layer also has a third groove on the surface facing away from the semiconductor substrate. Providing the metal isolation layer on the surface of the contact layer prevents materials in the anti-oxidation metal layer from diffusing into the contact layer, thus preventing excessive metal elements in the anti-oxidation metal layer from diffusing downward and causing reliability issues in the semiconductor device. Specifically, the metal isolation layer can include at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and the thickness of the metal isolation layer can be in the range of 20 nm to 100 nm. In one possible implementation, the first electrode may further include a first metal layer located between the contact layer and the metal isolation layer, with a portion of the first metal layer located within the second groove and another portion extending to an area of the contact layer surface excluding the second groove. The first metal layer also has a groove on the side facing away from the semiconductor substrate. A portion of the metal isolation layer is located within the groove on the surface of the first metal layer and another portion extends to an area of the first metal layer surface excluding the groove. Exemplarily, the first metal layer may include aluminum (Al) material, and the thickness of the first metal layer may be between 80 nm and 200 nm. During the annealing process, the first metal layer may diffuse downward, for example, may diffuse into the channel layer, and participate in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0060] A part of the anti-oxidation metal layer is located in the third groove, and another part protrudes from the surface of the metal isolation layer facing away from the semiconductor substrate. The anti-oxidation metal layer can fill the third groove, and the surface of the anti-oxidation metal layer facing away from the semiconductor substrate can be a flat surface. The thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer. In a possible implementation, the anti-oxidation metal layer can include: inert metal materials. For example, the anti-oxidation metal layer can include inert metal materials such as gold (Au), platinum (Pt), etc. The inert metal materials are not easily oxidized during the annealing process (the annealing temperature is in the range of 200 °C to 1000 °C), which can enable the anti-oxidation metal layer to play a better role in isolating air. And / or, the anti-oxidation metal layer can include: alloy materials with anti-oxidation properties. For example, the anti-oxidation metal layer can include titanium nitride (TiN) materials. The alloy materials with anti-oxidation properties are not easily oxidized during the annealing process (the annealing temperature is in the range of 200 °C to 1000 °C), and can also enable the anti-oxidation metal layer to play a better role in isolating air. Of course, in some cases, other anti-oxidation materials can also be used for the anti-oxidation metal layer, which is not limited in this application.

[0061] In some other embodiments of the present application, the contact layer can include a semiconductor doping layer and a second metal layer. The first groove extends from the surface of the epitaxial layer facing away from the semiconductor substrate to the inside of the channel layer. During the manufacturing process, annealing can be performed at a relatively low temperature. Exemplarily, the annealing temperature can be in the range of 200 °C to 500 °C. Since in the embodiments of the present application, the bottom of the first groove is located inside the channel layer, the semiconductor doping layer in the contact layer can be in direct contact with the channel layer. Therefore, a good and reliable ohmic contact can be formed by using a relatively low annealing temperature.

[0062] For the case where the contact layer includes a semiconductor doping layer and a second metal layer, the first electrode can be arranged in the following manner.

[0063] Specifically, the semiconductor doping layer can include a semiconductor material doped with impurities. Exemplarily, the semiconductor doping layer can include gallium nitride (GaN) material highly doped with N-type impurities. The semiconductor doping layer can fill the first groove. In a possible implementation, the surface of the semiconductor doping layer can be flush with the upper surface of the epitaxial layer, or the surface of the semiconductor doping layer can be slightly higher than the upper surface of the epitaxial layer. The second metal layer is located on the side of the semiconductor doping layer facing away from the semiconductor substrate. Exemplarily, the second metal layer can include titanium (Ti) material. The second metal layer can be a reactant for the ohmic contact reaction. By filling the semiconductor doping layer in the first groove of the epitaxial layer, the semiconductor doping layer can play a role in reducing the barrier between the epitaxial layer and the second metal layer, which is beneficial to the formation of an ohmic contact.

[0064] A metal isolation layer is provided on a side of the contact layer facing away from the semiconductor substrate. The metal isolation layer can prevent the materials in the antioxidant metal layer from diffusing into the contact layer, avoiding excessive downward diffusion of metal elements in the antioxidant metal layer and causing reliability problems in the semiconductor device. In a possible implementation manner, the metal isolation layer may include platinum (Pt) material.

[0065] An antioxidant metal layer is provided on a side of the metal isolation layer facing away from the semiconductor substrate. The thickness of the antioxidant metal layer is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer. In a possible implementation manner, the antioxidant metal layer may include: inert metal materials. For example, the antioxidant metal layer may include inert metal materials such as gold (Au), platinum (Pt), etc. The inert metal materials are not easily oxidized during the annealing process (the annealing temperature is in the range of 200 °C to 1000 °C), which can enable the antioxidant metal layer to play a better role in isolating air. And / or, the antioxidant metal layer may include: alloy materials with antioxidant properties. For example, the antioxidant metal layer may include titanium nitride (TiN) material. The alloy materials with antioxidant properties are not easily oxidized during the annealing process (the annealing temperature is in the range of 200 °C to 1000 °C), and can also enable the antioxidant metal layer to play a better role in isolating air. Of course, in some cases, the antioxidant metal layer may also adopt other antioxidant materials, which are not limited in this application.

[0066] For the case where the contact layer includes a metal material and the contact layer includes a semiconductor doped layer and a second metal layer, the first electrode may also be arranged in the following manner.

[0067] In a possible implementation manner, the outer edges formed by the antioxidant metal layer and the metal isolation layer in the first electrode are flush. In this way, the morphology of the first electrode can be better, improving the electrical performance of the semiconductor device. During the manufacturing process, the metal isolation layer and the antioxidant metal layer can be patterned by the same lithography process to make the outer edges formed by the antioxidant metal layer and the metal isolation layer flush. In some embodiments of the present application, the first electrode may further include an etch stop layer. When specifically arranged, the edge of the etch stop layer can also be set to be flush with the edge of the antioxidant metal layer. In this way, the morphology of the first electrode can be better, improving the electrical performance of the semiconductor device. During the manufacturing process, the metal isolation layer, the antioxidant metal layer, and the etch stop layer can be patterned by the same lithography process to make the outer edges formed by the metal isolation layer, the antioxidant metal layer, and the etch stop layer flush.

[0068] During the manufacturing process, the metal film layers in the first electrode can be deposited sequentially, and then, the same patterning process can be used to pattern each metal film layer so that the outer edges formed by the metal film layers in the first electrode are flush. Specifically, for the case where the contact layer includes a metal material, the contact layer, the first metal layer, the metal isolation layer, the anti-oxidation metal layer, and the etching barrier layer can be deposited over the entire surface, and the same patterning process can be used to pattern the contact layer, the first metal layer, the metal isolation layer, the anti-oxidation metal layer, and the etching barrier layer, so that the outer edges formed by the contact layer, the first metal layer, the metal isolation layer, the anti-oxidation metal layer, and the etching barrier layer in the first electrode are flush. For the case where the contact layer includes a semiconductor doped layer and a second metal layer, the second metal layer, the metal isolation layer, the anti-oxidation metal layer, and the etching barrier layer can be deposited over the entire surface, and the same patterning process can be used to pattern the second metal layer, the metal isolation layer, the anti-oxidation metal layer, and the etching barrier layer, so that the outer edges formed by the second metal layer, the metal isolation layer, the anti-oxidation metal layer, and the etching barrier layer in the first electrode are flush. It can be understood that in the embodiments of the present application, due to the limitations of the manufacturing process level, the outer edges of some film layers in the first electrode being flush means that the outer edges of these film layers are substantially flush within a certain error range.

[0069] In a third aspect, an embodiment of the present application further provides a power amplifier chip. The power amplifier chip in the embodiment of the present application may include any one of the semiconductor devices in the second aspect above, or the power amplifier chip in the embodiment of the present application may include a semiconductor device manufactured by the manufacturing method in the first aspect above. Since the resistivity of the ohmic contact of the semiconductor device in the embodiment of the present application is low, the electrical performance of the power amplifier chip including the semiconductor device is good.

[0070] In a fourth aspect, an embodiment of the present application further provides an electronic device. The electronic device in the embodiment of the present application may include the above-mentioned power amplifier chip, and the electronic device is a terminal portable device. For example, the electronic device in the embodiment of the present application may be a device such as a mobile phone, a tablet computer, or a laptop computer. Since the electrical performance of the power amplifier chip in the embodiment of the present application is good, the performance of the electronic device including the power amplifier chip is also good. Description of the Drawings

[0071] Figure 1 Schematic diagram of the manufacturing process of a semiconductor device in the related art;

[0072] Figure 2 Flowchart of the manufacturing method of the semiconductor device provided by the embodiment of the present application;

[0073] Figures 3 to 23 Schematic diagrams of the structures corresponding to the steps in the manufacturing method provided by the embodiment of the present application;

[0074] Figure 24 Schematic structural diagram of the semiconductor device provided by the embodiment of the present application;

[0075] Figure 25 Schematic comparison diagram between the technical solution of the related art and the technical solution of the present application.

[0076] Reference numerals:

[0077] 101, 10 - semiconductor substrate; 102 - epitaxial layer; 103 - stacked metal; 11 - epitaxial layer; 111 - channel layer; 112 - barrier layer; 113 - cap layer; 114 - nucleation layer; 115 - transition layer; 116 - buffer layer; 12 - first electrode; 121 - contact layer; 121a - semiconductor doping layer; 121b - second metal layer; 122 - metal isolation layer; 123 - antioxidant metal layer; 124 - etch stop layer; 125 - first metal layer; 13 - gate contact metal layer; 14 - gate interconnect structure; 15 - interconnect structure; 301 - photoresist layer; 302 - passivation layer; 303 - dielectric layer; 304 - hard mask layer; M1 - surface metal layer; M2 - thickened metal layer; U1 - first groove; U2 - second groove; U3 - third groove; T - fourth groove. Detailed implementation manners

[0078] In order to reduce the resistivity of the ohmic contact of the semiconductor device, the embodiment of the present application provides a semiconductor device, a manufacturing method thereof, a power amplifier chip and an electronic device. The semiconductor device in the embodiment of the present application may be a high electron mobility transistor device. Exemplarily, the semiconductor device in the embodiment of the present application may be a GaN / GaAs-based high electron mobility transistor device. Of course, in some cases, the semiconductor device in the embodiment of the present application may also be other types of transistor devices, which are not limited in the present application.

[0079] The semiconductor device in the embodiment of the present application can be applied to radio frequency application devices, and the drain supply voltage of the radio frequency application device can be in the range of 5V to 48V. The radio frequency application device in the embodiment of the present application may be a terminal radio frequency power amplifier device, a base station radio frequency power amplifier device, etc. Exemplarily, the semiconductor device in the embodiment of the present application can be applied to a power amplifier chip, and the power amplifier chip can be applied to various types of electronic devices, for example, it can be applied to terminal portable devices such as mobile phones, tablet computers, laptop computers, etc.

[0080] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

[0081] It should be noted that the accompanying drawings of this application are only used to illustrate the relative positional relationship and do not represent the true scale. In the accompanying drawings of this application, the same reference numerals represent the same or similar structures, and thus the repeated description thereof will be omitted.

[0082] The words expressing positions and directions described in this application, for example, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are all described based on the orientation or positional relationship shown in the accompanying drawings as examples. They are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation on this application. Changes can be made as needed, and all changes made are included in the protection scope of this application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0083] Figure 1 As a schematic diagram of the manufacturing process of semiconductor devices in the related art, as Figure 1 shown in (1) of, after forming an epitaxial layer 102 on a semiconductor substrate 101, a stacked metal 103 is deposited on the surface of the epitaxial layer 102. Among them, the surface metal layer M1 of the stacked metal 103 is generally made of gold (Au) material, the thickness of the surface metal layer M1 is about 150 nm, and the total thickness of the stacked metal 103 is within 300 nm. Then, an ohmic contact can be formed at the interface between the epitaxial layer 102 and the stacked metal 103 through annealing treatment. As Figure 1 shown in (2) of, after the annealing treatment, the stacked metal 103 is thickened twice, that is, a thickened metal layer M2 is formed on the surface metal layer M1. Since the surface metal layer M1 in the stacked metal 103 formed before the annealing treatment is relatively thin, during the annealing treatment, the surface metal layer M1 is not sufficient to isolate the air, which will cause impurities such as oxygen (O) to diffuse downward, and it is easy to form holes in the ohmic contact region, resulting in a relatively large resistivity of the formed ohmic contact. Thus, it affects the performance of semiconductor devices. For example, it will affect the output power, efficiency and other performances of semiconductor devices.

[0084] Based on this, in order to reduce the resistivity of the ohmic contact of semiconductor devices, an embodiment of this application provides a method for manufacturing a semiconductor device. Figure 2 As a flowchart of the method for manufacturing a semiconductor device provided by an embodiment of this application, as Figure 2 shown, the method for manufacturing a semiconductor device provided by an embodiment of this application may include:

[0085] S201. Form an epitaxial layer on the semiconductor substrate, and perform patterning on the epitaxial layer to form a first groove on the surface of the epitaxial layer on the side facing away from the semiconductor substrate; wherein, the epitaxial layer includes: a channel layer.

[0086] S202, forming a first electrode having a portion located within the first groove and another portion protruding from a surface of the epitaxial layer facing away from the semiconductor substrate; wherein the first electrode is a source electrode or a drain electrode, and comprises: a contact layer, a metal isolation layer, and an anti-oxidation metal layer; the contact layer contacts the epitaxial layer on an inner wall of the first groove; the anti-oxidation metal layer is located on a side of the contact layer facing away from the semiconductor substrate; and the metal isolation layer is located between the contact layer and the anti-oxidation metal layer; the thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer;

[0087] S203 , performing annealing treatment on the structure after the anti-oxidation metal layer is formed to obtain a semiconductor device.

[0088] In the method for manufacturing a semiconductor device provided by an embodiment of the present application, during the process of manufacturing the first electrode, the thickness of the anti-oxidation metal layer formed is greater than or equal to 400nm and greater than or equal to twice the thickness of the channel layer, that is, a thicker anti-oxidation metal layer is formed in the first electrode, and then the structure after the anti-oxidation metal layer is formed is annealed. In this way, during the annealing process, the thicker anti-oxidation metal layer can fully isolate the air, prevent the air from reacting with the metal in the first electrode, and avoid the formation of holes in the ohmic contact area, so that the contact layer and the epitaxial layer can react well, thereby forming a good and reliable ohmic contact and reducing the resistivity of the ohmic contact. Moreover, during the annealing process, a small amount of metal elements in the anti-oxidation metal layer can diffuse into the epitaxial layer to participate in the ohmic contact reaction, that is, the metal elements in the anti-oxidation metal layer can also serve as reactants in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact. In addition, compared with the manufacturing process of the related art, the manufacturing method provided by the embodiment of the present application can also save the subsequent metal thickening process, avoid multiple metal deposition processes, and avoid stability problems caused by interface exposure. It should be explained that ohmic contact means that when the first electrode contacts the epitaxial layer, a very small contact barrier is formed at the contact interface, or no contact barrier is formed at the contact interface. In other words, the contact resistivity of ohmic contact is low.

[0089] Moreover, in the method for manufacturing a semiconductor device provided in an embodiment of the present application, a first groove is formed on the surface of the epitaxial layer facing away from the semiconductor substrate, and a portion of the subsequently formed first electrode is located within the first groove. This can increase the contact area between the contact layer in the first electrode and the epitaxial layer, thereby further reducing the resistivity of the ohmic contact between the first electrode and the epitaxial layer.

[0090] Figures 3 to 23The following is a schematic diagram corresponding to each step in the manufacturing method provided by the embodiments of the present application. With reference to the accompanying drawings, the manufacturing method of the semiconductor device provided by the embodiments of the present application will be described in detail below.

[0091] As Figure 3 shown, in the embodiments of the present application, the semiconductor substrate 10 may be made of a high-resistance semiconductor material. Exemplarily, the semiconductor substrate 10 may include Si material with a resistivity greater than 5000 Ω·cm. For example, the semiconductor substrate 10 may include Si material with a resistivity greater than 1e 4 Ω·cm; or, the semiconductor substrate 10 may include SiC material with a resistivity greater than 1e 6 Ω·cm; or, the semiconductor substrate 10 may include GaN material with a resistivity greater than 1e4 Ω·cm; or, the semiconductor substrate 10 may include sapphire material with a resistivity greater than 1e11 Ω·cm. Of course, the semiconductor substrate 10 in the embodiments of the present application may also be made of other high-resistance semiconductor materials, which are not limited in the present application.

[0092] In the above step S201, forming the epitaxial layer 11 on the semiconductor substrate 10 may specifically include: forming a channel layer 111 with a thickness in the range of 100 nm to 400 nm on the semiconductor substrate 10. Exemplarily, the channel layer 111 may be formed of undoped gallium nitride (GaN) material. Then, a barrier layer 112 with a thickness in the range of 4 nm to 35 nm is formed on the channel layer 111. For example, the barrier layer 112 with a thickness in the range of 10 nm to 35 nm may be formed of aluminum gallium nitride (AlGaN) material, or the barrier layer 112 with a thickness in the range of 4 nm to 10 nm may be formed of aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN) material.

[0093] In a possible implementation manner, in the above step S201, forming the epitaxial layer 11 on the semiconductor substrate 10 may further include: forming a cap layer 113 with a thickness in the range of 1 nm to 5 nm on the barrier layer 112. Exemplarily, the cap layer 113 may be formed of materials such as gallium nitride (GaN), in-situ silicon nitride (SiN), etc.

[0094] In a possible implementation, in the above step S201, when forming the epitaxial layer 11 on the semiconductor substrate 10, it may further include: before forming the channel layer 111, sequentially forming a nucleation layer 114, a transition layer 115, and a buffer layer 116 on the semiconductor substrate 10. Specifically, aluminum nitride (AlN) material may be used to form the nucleation layer 114 with a thickness in the range of 100 nm to 300 nm. Aluminum gallium nitride (AlGaN) material may be used to form the transition layer 115 with a thickness in the range of 100 nm to 500 nm. A high-resistance semiconductor material may be used to fabricate the buffer layer 116. For example, a high-resistance gallium nitride (GaN) material may be used to form the buffer layer 116. The buffer layer 116 may be doped with carbon (C) element with a concentration greater than 1e 17 ~2e 19 ; alternatively, the buffer layer 116 may be doped with iron (Fe) element with a concentration greater than 1e 17 . The thickness of the buffer layer 116 may be in the range of 0.5 μm to 2 μm.

[0095] In a possible implementation, epitaxial growth processes such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and atomic layer deposition (ALD) may be used to fabricate each film layer in the epitaxial layer 11.

[0096] In the above step S201, the epitaxial layer 11 may be patterned to form a first groove ( Figure 3 not shown in the figure) on the surface of the epitaxial layer 11. In specific implementation, the depth of the first groove is related to factors such as the material of the contact layer to be formed subsequently and the annealing temperature of the subsequent annealing process, which will be described in detail below with reference to the accompanying drawings.

[0097] In some embodiments of the present application, a metal material may be used to fabricate the contact layer, and annealing treatment may be performed at a relatively high temperature. Exemplarily, the temperature of the annealing treatment may be in the range of 500 °C to 1000 °C, and the bottom of the first groove may be located inside the barrier layer. The following method may be used to pattern the epitaxial layer:

[0098] As Figure 4 shown, a photoresist layer 301 is formed on the surface of the epitaxial layer 11, and processes such as photolithography and development are performed on the photoresist layer 301 to pattern the photoresist layer 301, so that the pattern of the photoresist layer 301 covers the area other than the first groove to be formed, and the area where the first groove is to be formed is exposed. As Figure 5As shown, the epitaxial layer 11 is etched with the pattern of the photoresist layer 301 as a shield. Figure 5 The direction indicated by the arrow in the middle may be the etching direction. For example, an inductively coupled plasma (ICP) etching process may be used to etch the epitaxial layer 11. Specifically, an inductively coupled plasma process containing a Cl-based gas may be used to etch the epitaxial layer 11. During the etching process, the etching depth may be controlled by adjusting parameters such as the etching process time and power, thereby forming a first recess U1 extending from the surface of the epitaxial layer 11 facing away from the semiconductor substrate 10 to the interior of the barrier layer 112.

[0099] like Figure 6 As shown, in the case where the contact layer 121 is made of metal material, the above step S202 may specifically include:

[0100] A contact layer 121 is formed using a metal material, with a portion of the contact layer 121 located within the first recess U1 and another portion extending to the surface of the epitaxial layer 11 outside the first recess U1. A second recess U2 is formed on the surface of the contact layer 121 facing away from the semiconductor substrate 10. The contact layer 121 can contact the epitaxial layer 11 at the inner wall of the first recess U1. This arrangement increases the contact area between the contact layer 121 and the epitaxial layer 11, thereby reducing the resistivity of the ohmic contact between the contact layer 121 and the epitaxial layer 11. For example, the contact layer 121 can be made of titanium (Ti) and have a thickness ranging from 4 nm to 20 nm.

[0101] A metal isolation layer 122 is formed of a metal material, and a part of the metal isolation layer 122 is located in the second groove U2, and the other part extends to the area on the contact layer 121 other than the second groove U2, and a third groove U3 is formed on the surface of the metal isolation layer 122 on the side facing away from the semiconductor substrate 10. By forming the metal isolation layer 122 on the surface of the contact layer 121, the material in the subsequently formed antioxidant metal layer 123 can be prevented from diffusing into the contact layer 121, and excessive metal elements in the antioxidant metal layer 123 can be prevented from diffusing downward, thus avoiding reliability problems in the semiconductor device. Specifically, the metal isolation layer 122 may include at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and the thickness of the metal isolation layer 122 may be in the range of 20 nm to 100 nm. In a possible implementation, after forming the contact layer 121 and before forming the metal isolation layer 122, it may further include: forming a first metal layer 125 on the surface of the contact layer 121, a part of the first metal layer 125 is located in the second groove U2, and the other part extends to the area on the surface of the contact layer 121 other than the second groove U2, and a groove is also formed on the side of the first metal layer 125 facing away from the semiconductor substrate 10. Then, the metal isolation layer 122 may be formed on the surface of the first metal layer 125, and a part of the metal isolation layer 122 is located in the groove on the surface of the first metal layer 125, and the other part extends to the area on the surface of the first metal layer 125 other than the groove. Exemplarily, the first metal layer 125 may include an aluminum (Al) material, and the thickness of the first metal layer 125 may be between 80 nm and 200 nm. During the subsequent annealing process, the first metal layer 12 may diffuse downward. For example, it may diffuse into the channel layer 111 and participate in the ohmic contact reaction, which is beneficial to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0102] The anti-oxidation metal layer 123 is formed of a metal material, with a portion of the anti-oxidation metal layer 123 positioned within the third recess U3 and another portion protruding from the surface of the metal isolation layer 122 facing away from the semiconductor substrate 10. In the embodiment of the present application, a relatively thick anti-oxidation metal layer 123 is formed before the annealing process. The anti-oxidation metal layer 123 can fill the third recess U3. Furthermore, the surface of the anti-oxidation metal layer 123 facing away from the semiconductor substrate 10 can be flat. The thickness of the anti-oxidation metal layer 123 protruding from the surface of the metal isolation layer 122 facing away from the semiconductor substrate 10 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In one possible implementation, the anti-oxidation metal layer 123 can be made of inert metal materials such as gold (Au) and platinum (Pt) that are not easily oxidized during annealing (annealing temperature is in the range of 200°C to 1000°C); and / or, the anti-oxidation metal layer 123 can be made of alloy materials with anti-oxidation properties, for example, titanium nitride (TiN) material with good conductive properties and good stability can be used.

[0103] Furthermore, to prevent the subsequent etching process of the dielectric layer from damaging the anti-oxidation metal layer 123, step S202 may further include forming an etch stop layer 124 on the anti-oxidation metal layer 123. For example, a metal material such as Ti or Ni having a slow etching characteristic of F-based reactive ion etching (RIE) may be used, and the thickness of the etch stop layer 124 may be greater than or equal to 20 nm.

[0104] like Figure 7As shown, after the formation of the etch stop layer 124, the above step S202 may further include: patterning the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124, removing the portions of the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 in the regions outside the first groove U1, and then removing the photoresist layer to obtain the first electrode 12. That is to say, the pattern of the first electrode 12 is consistent with the region of the first groove U1. Moreover, the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 can be patterned by the same lithography process. In this way, in the fabricated first electrode 12, the outer edges of the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 are flush, which can make the morphology of the first electrode 12 better and improve the electrical performance of the semiconductor device. It can be understood that in the embodiments of the present application, due to the limitation of the manufacturing process level, the outer edges of some film layers in the first electrode 12 being flush means that the outer edges of these film layers are substantially flush within a certain error range. In the embodiments of the present application, the semiconductor device may include at least one transistor, and each transistor may include a source electrode, a drain electrode, and a gate electrode. The first electrode 12 in the embodiments of the present application may be a source electrode or a drain electrode.

[0105] Continuing to refer to Figure 7 , for the case where the contact layer 121 is made of a metal material, the above step S203 may specifically include: annealing the structure after the formation of the anti-oxidation metal layer 123 at a temperature in the range of 500°C to 1000°C. Since the annealing temperature is relatively high, during the annealing process, the contact layer 121 reacts with the epitaxial layer 11, and the metal elements in the contact layer 121 can penetrate into the channel layer 111 through the barrier layer 112, thereby forming a good and reliable ohmic contact. Specifically, rapid thermal processing (RTP) technology, laser annealing and other processes can be used for annealing. Moreover, during the annealing process, the metal elements in the anti-oxidation metal layer 123 and the first metal layer 125 can also diffuse into the channel layer 111 and participate in the ohmic contact reaction, which is beneficial to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0106] For the case where the contact layer 121 is made of a metal material, after the above step S203, it may further include: forming an interconnect structure in contact connection with the etch stop layer. The specific process is as follows:

[0107] As Figure 8As shown, a passivation layer 302 covering the first electrode 12 is formed. Exemplarily, the passivation layer 302 can be made of silicon nitride (SiN) material.

[0108] As Figure 9 shown, the passivation layer 302 is patterned to form a fourth groove T penetrating the passivation layer 302 in the region where the gate is to be formed. The bottom surface of the fourth groove T is a part of the surface of the epitaxial layer 11.

[0109] As Figure 10 shown, a gate contact metal layer 13 is formed on the sidewalls and the bottom surface of the fourth groove T of the passivation layer 302, and a metal material is filled in the fourth groove T to form a gate interconnect structure 14. The gate interconnect structure 14 fills the part of the fourth groove T except the gate contact metal layer 13 and protrudes from the surface of the passivation layer 302. Exemplarily, the gate contact metal layer 13 can be made of a metal material such as nickel (Ni) or tungsten (W). The gate contact metal layer 13 can serve as the gate of the transistor. The gate contact metal layer 13 can contact the epitaxial layer 11 to form a Schottky contact. It should be noted that the Schottky contact means that when the gate contact metal layer 13 and the epitaxial layer 11 are in contact, the energy band of the epitaxial layer 11 at the contact interface bends to form a contact barrier (which can be called a Schottky barrier). In a possible implementation, the gate interconnect structure 14 can be made of gold (Au) material. The gate interconnect structure 14 can play a role in leading out the gate contact metal layer 13, and moreover, the gate interconnect structure 14 can also play a role in antioxidation and reduce the gate resistance.

[0110] As Figure 11 shown, a dielectric layer 303 covering the gate interconnect structure 14 is formed. The dielectric layer 303 covers the passivation layer 302 in the region where the first electrode 12 is located. Exemplarily, the dielectric layer 303 can be made of silicon nitride (SiN) material.

[0111] As Figure 12 shown, an etching process is used to pattern the dielectric layer 303 and the passivation layer 302 to expose the first electrode 12. Since the surface of the antioxidation metal layer 123 has an etching barrier layer 124, during the etching process, the etching barrier layer 124 protects the antioxidation metal layer 123 from being damaged during the etching process. In a specific implementation, the upper surface of the etching barrier layer 124 can be a flat surface, or during the etching process, the upper surface of the etching barrier layer 124 may be etched, that is, grooves may be formed on the upper surface of the etching barrier layer 124.

[0112] As Figure 13As shown, the grooves on the surfaces of the passivation layer 302 and the dielectric layer 303 are filled with a metal material, for example, gold (Au), to form an interconnect structure 15 that is in contact with the etch stop layer 124, so that the interconnect structure 15 is electrically connected to the first electrode 12. The interconnect structure 15 is used to lead out the first electrode 12. In a direction parallel to the surface of the semiconductor substrate 10, the width of the grooves on the surfaces of the passivation layer 302 and the dielectric layer 303 is smaller than the width of the anti-oxidation metal layer 123. Therefore, the width of the formed interconnect structure 15 is smaller than the width of the anti-oxidation metal layer 123.

[0113] In other embodiments of the present application, the contact layer includes a semiconductor doping layer and a second metal layer, and is annealed at a relatively low temperature. For example, the annealing temperature may be in the range of 200°C to 500°C. The bottom of the first recess may be located inside the channel layer. The epitaxial layer may be patterned using the following methods:

[0114] like Figure 14 As shown, a hard mask layer 304 is formed on the surface of the epitaxial layer 11. In a possible implementation, the hard mask layer 304 can be made of silicon oxide (SiOx) material or silicon nitride (SiNx) material.

[0115] like Figure 15 As shown, the hard mask layer 304 is patterned so that the pattern of the hard mask layer 304 covers the area outside the first groove U1 to be formed, exposing the area of the first groove U1 to be formed. Using the pattern of the hard mask layer 304 as a shield, the epitaxial layer 11 is etched. Figure 15 The direction indicated by the arrow in the middle may be the etching direction. For example, an inductively coupled plasma (ICP) etching process may be used to etch the epitaxial layer 11. Specifically, an inductively coupled plasma process containing a Cl-based gas may be used to etch the epitaxial layer 11. During the etching process, the etching depth may be controlled by adjusting parameters such as the etching process time and power, thereby forming a first groove U1 extending from the surface of the epitaxial layer 11 on the side facing away from the semiconductor substrate 10 to the interior of the channel layer 111.

[0116] In the case where the contact layer includes a semiconductor doped layer and a second metal layer, the above step S202 may specifically include:

[0117] like Figure 16As shown, a semiconductor doped layer 121a is formed using a semiconductor material doped with impurities, and the semiconductor doped layer 121a fills the first groove U1. In a possible implementation, the semiconductor doped layer 121a can be made of gallium nitride (GaN) material highly doped with N-type impurities. In specific implementation, in order for the semiconductor doped layer 121a formed by the epitaxial process to fill the first groove U1, generally the formed semiconductor doped layer 121a is slightly higher than the surface of the epitaxial layer (i.e., the surface of the cap layer 113).

[0118] After that, the hard mask layer 304 on the surface of the epitaxial layer (i.e., the surface of the cap layer 113) is removed. For example, the hard mask layer 304 can be removed by a wet etching process, and the structure shown as Figure 17 is obtained.

[0119] As shown in Figure 18 , a second metal layer 121b is formed on the semiconductor doped layer 121a using a metal material. The second metal layer 121b can be used as a reactant for the ohmic contact reaction. By forming the semiconductor doped layer 121a in the first groove U1 of the epitaxial layer, the semiconductor doped layer 121a can play a role in reducing the barrier between the epitaxial layer and the second metal layer 121b, which is beneficial to forming an ohmic contact. Exemplarily, the second metal layer 121b can include titanium (Ti) material.

[0120] After that, a metal isolation layer 122 is formed on the surface of the second metal layer 121b, that is, a metal isolation layer 122 is formed on the surface of the contact layer 121. By forming the metal isolation layer 122 on the surface of the contact layer 121, it can prevent the materials in the subsequent formed antioxidant metal layer 123 from diffusing into the contact layer 121, and avoid excessive downward diffusion of metal elements in the antioxidant metal layer 123, which may cause reliability problems in the semiconductor device. In a possible implementation, the metal isolation layer 122 can include platinum (Pt) material.

[0121] After that, an antioxidant metal layer 123 is formed on the metal isolation layer 122 using a metal material, and the thickness of the formed antioxidant metal layer 123 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In a possible implementation, inert metal materials such as gold (Au) and platinum (Pt) that are not easily oxidized during the annealing process (the annealing temperature is in the range of 200 °C to 1000 °C) can be used to make the antioxidant metal layer 123; and / or, alloy materials with antioxidant properties can be used to make the antioxidant metal layer 123. For example, TiN material with good electrical conductivity and good stability can be used.

[0122] In addition, in order to prevent the subsequent etching process of the dielectric layer from damaging the antioxidant metal layer 123, the above step S202 may further include: forming an etching barrier layer 124 on the antioxidant metal layer 123. Exemplarily, metal materials such as Ti and Ni with slow etching characteristics of F-based reactive ion etching (RIE) can be used, and the thickness of the etching barrier layer 124 may be greater than or equal to 20 nm.

[0123] During the manufacturing process, the second metal layer 121b, the metal isolation layer 122, the antioxidant metal layer 123, and the etching barrier layer 124 can be deposited over the entire surface, and then, the second metal layer 121b, the metal isolation layer 122, the antioxidant metal layer 123, and the etching barrier layer 124 are patterned to remove the portions of the second metal layer 121b, the metal isolation layer 122, the antioxidant metal layer 123, and the etching barrier layer 124 in the regions outside the first groove U1, so as to obtain the first electrode 12. That is to say, the pattern of the first electrode 12 is consistent with the region of the first groove U1. Moreover, the second metal layer 121b, the metal isolation layer 122, the antioxidant metal layer 123, and the etching barrier layer 124 can be patterned by the same lithography process. In this way, in the first electrode 12 thus fabricated, the outer edges formed by the second metal layer 121b, the metal isolation layer 122, the antioxidant metal layer 123, and the etching barrier layer 124 are flush, which can make the morphology of the first electrode 12 better and improve the electrical performance of the semiconductor device. It can be understood that in the embodiments of the present application, due to the limitation of the manufacturing process level, the outer edges of some film layers in the first electrode 12 being flush means that the outer edges of these film layers are substantially flush within a certain error range. In the embodiments of the present application, the semiconductor device may include at least one transistor, and each transistor may include a source electrode, a drain electrode, and a gate electrode. The first electrode 12 in the embodiments of the present application may be a source electrode or a drain electrode.

[0124] Continue to refer to Figure 18 , for the case where the contact layer includes a semiconductor doped layer and a second metal layer, the above step S203 may specifically include: annealing the structure after forming the antioxidant metal layer 123 at a temperature in the range of 200 °C to 500 °C. Since in the embodiments of the present application, the bottom of the first groove U1 is located inside the channel layer 111, the semiconductor doped layer 121a in the contact layer 121 can be in direct contact with the channel layer 111. Therefore, a good and reliable ohmic contact can be formed by using a relatively low annealing temperature. Specifically, rapid thermal processing (RTP) process, laser annealing, etc. can be used for the annealing treatment.

[0125] For the case where the contact layer includes a semiconductor doped layer and a second metal layer, after the above step S203, the following may further be included: forming an interconnect structure in contact connection with the etch stop layer, and the specific process is as follows:

[0126] As Figure 19 shown, a passivation layer 302 covering the first electrode 12 is formed. Exemplarily, the passivation layer 302 can be made of silicon nitride (SiN) material.

[0127] As Figure 20 shown, the passivation layer 302 is patterned to form a fourth groove T penetrating the passivation layer 302 in the region where the gate is to be formed. The bottom surface of the fourth groove T is a part of the surface of the epitaxial layer 11.

[0128] As Figure 21 shown, a gate contact metal layer 13 is formed on the sidewalls and the bottom surface of the fourth groove T of the passivation layer 302, and a metal material is filled in the fourth groove T to form a gate interconnect structure 14. The gate interconnect structure 14 fills the part of the fourth groove T except the gate contact metal layer 13 and protrudes from the surface of the passivation layer 302. Exemplarily, the gate contact metal layer 13 can be made of a metal material such as nickel (Ni) or tungsten (W). The gate contact metal layer 13 can serve as the gate of the transistor. The gate contact metal layer 13 can be in contact with the epitaxial layer 11 to form a Schottky contact. It should be noted that a Schottky contact means that when the gate contact metal layer 13 and the epitaxial layer 11 are in contact, the energy band of the epitaxial layer 11 at the contact interface bends to form a contact barrier (which can be called a Schottky barrier). In one possible implementation, the gate interconnect structure 14 can be made of gold (Au) material. The gate interconnect structure 14 can play a role in leading out the gate contact metal layer 13, and further, the gate interconnect structure 14 can also play a role in antioxidation and reduce the gate resistance.

[0129] As Figure 22 shown, a dielectric layer 303 covering the gate interconnect structure 14 is formed. The dielectric layer 303 covers the passivation layer 302 in the region where the first electrode 12 is located. Exemplarily, the dielectric layer 303 can be made of silicon nitride (SiN) material. Then, an etching process is used to pattern the dielectric layer 303 and the passivation layer 302 to expose the first electrode 12. Since the surface of the antioxidation metal layer 123 has an etch stop layer 124, during the etching process, the etch stop layer 124 can protect the antioxidation metal layer 123 from being damaged during the etching process. In a specific implementation, the upper surface of the etch stop layer 124 can be a flat surface, or during the etching process, the upper surface of the etch stop layer 124 may be etched, that is, grooves may be formed on the upper surface of the etch stop layer 124.

[0130] As shown Figure 23 In the grooves on the surfaces of the passivation layer 302 and the dielectric layer 303, a metal material is filled. For example, a gold (Au) material can be filled to form an interconnect structure 15 in contact connection with the etch stop layer 124, so that the interconnect structure 15 is electrically connected to the first electrode 12. The interconnect structure 15 is used to lead out the first electrode 12. In the direction parallel to the surface of the semiconductor substrate 10, the width of the grooves on the surfaces of the passivation layer 302 and the dielectric layer 303 is smaller than the width of the anti-oxidation metal layer 123. Therefore, the width of the formed interconnect structure 15 is smaller than the width of the anti-oxidation metal layer 123.

[0131] Based on the same inventive concept, an embodiment of the present application further provides a semiconductor device. Figure 24 As shown in the structural schematic diagram of the semiconductor device provided by the embodiment of the present application, Figure 24 The semiconductor device provided by the embodiment of the present application may include: a semiconductor substrate 10, an epitaxial layer 11, and a first electrode 12. In the embodiment of the present application, the semiconductor device may include at least one transistor, and each transistor may include a source electrode, a drain electrode, and a gate electrode. The first electrode 12 in the embodiment of the present application may be a source electrode or a drain electrode. Among them, the epitaxial layer 11 is located on the semiconductor substrate 10, and a first groove U1 is provided on the surface of the epitaxial layer 11 facing away from the semiconductor substrate 10. A part of the first electrode 12 is located inside the first groove U1, and another part protrudes from the surface of the epitaxial layer 11 facing away from the semiconductor substrate 10. The first electrode 12 may include: a contact layer 121, a metal isolation layer 122, and an anti-oxidation metal layer 123. The contact layer 121 contacts the epitaxial layer 11 on the inner wall of the first groove U1. The anti-oxidation metal layer 123 is located on the side of the contact layer 121 facing away from the semiconductor substrate 10, and the metal isolation layer 122 is located between the contact layer 121 and the anti-oxidation metal layer 123. The thickness of the anti-oxidation metal layer 123 protruding from the surface of the metal isolation layer 122 facing away from the semiconductor substrate 10 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111.

[0132] In the semiconductor device provided by the embodiment of the present application, the first electrode 12 includes a contact layer 121, a metal isolation layer 122, and an antioxidant metal layer 123. The thickness of the antioxidant metal layer 123 protruding from the surface of the metal isolation layer 122 on the side facing away from the semiconductor substrate 10 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. The thickness of the antioxidant metal layer 123 in the embodiment of the present application is relatively thick. During the annealing process, the relatively thick antioxidant metal layer 123 can fully isolate air, prevent air from reacting with the metal in the first electrode 12, avoid forming holes in the ohmic contact region, enable the contact layer 121 to react well with the epitaxial layer 11, thereby forming a good and reliable ohmic contact, and reducing the resistivity of the ohmic contact. Moreover, during the annealing process, a small amount of metal elements in the antioxidant metal layer 123 can diffuse into the epitaxial layer 11 to participate in the ohmic contact reaction. That is to say, the metal elements in the antioxidant metal layer 123 can also serve as reactants for the ohmic contact reaction, which is beneficial to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact. In addition, a first groove U1 is provided on the surface of the epitaxial layer 11 on the side facing away from the semiconductor substrate 10, and a part of the first electrode 12 is located inside the first groove U1, and the contact layer 121 contacts the epitaxial layer 11 on the inner wall of the first groove U1. In this way, the contact area between the contact layer 121 and the epitaxial layer 11 can be increased, thereby further reducing the resistivity of the ohmic contact between the first electrode 12 and the epitaxial layer 11.

[0133] In a possible implementation manner, the semiconductor device provided by the embodiment of the present application can be manufactured by using the above manufacturing method. Of course, in some cases, the semiconductor device in the embodiment of the present application can also be manufactured by using other manufacturing methods, which are not limited in the present application.

[0134] In the embodiment of the present application, the semiconductor substrate 10 may include a high-resistance semiconductor material. Exemplarily, the semiconductor substrate 10 may include Si material with a resistivity greater than 5000 Ω·cm. For example, the semiconductor substrate 10 may include Si material with a resistivity greater than 1e 4 Ω·cm; or, the semiconductor substrate 10 may include SiC material with a resistivity greater than 1e 6 Ω·cm; or, the semiconductor substrate 10 may include GaN material with a resistivity greater than 1e4 Ω·cm; or, the semiconductor substrate 10 may include sapphire material with a resistivity greater than 1e11 Ω·cm. Of course, the semiconductor substrate 10 in the embodiment of the present application may also include other high-resistance semiconductor materials, which are not limited in the present application.

[0135] In a possible implementation, the epitaxial layer 11 may include: a channel layer 111 and a barrier layer 112, and the barrier layer 112 is located on a side of the channel layer 111 facing away from the semiconductor substrate 10. Exemplarily, the channel layer 111 may include undoped gallium nitride (GaN) material, and the thickness of the channel layer 111 may be in the range of 100 nm to 400 nm. The barrier layer 112 may include materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN), etc., and the thickness of the barrier layer 112 may be in the range of 4 nm to 35 nm. For example, when the barrier layer 112 includes aluminum gallium nitride (AlGaN) material, the thickness of the barrier layer 112 may be in the range of 10 nm to 35 nm; for another example, when the barrier layer 112 includes materials such as aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN), etc., the thickness of the barrier layer 112 may be in the range of 4 nm to 10 nm.

[0136] In addition, the epitaxial layer 11 may further include: a cap layer 113 located on a side of the barrier layer 112 facing away from the semiconductor substrate 10, and the first groove U1 penetrates through the cap layer 113 in a direction perpendicular to the surface of the semiconductor substrate 10. Exemplarily, the cap layer 113 may include materials such as gallium nitride (GaN), in-situ silicon nitride (SiN), etc., and the thickness of the cap layer 113 may be in the range of 1 nm to 5 nm.

[0137] In specific settings, the epitaxial layer 11 may further include: a nucleation layer 114 located between the semiconductor substrate 10 and the channel layer 111, a transition layer 115 located between the nucleation layer 114 and the channel layer 111, and a buffer layer 116 located between the transition layer 115 and the channel layer 111. Specifically, the nucleation layer 114 may include aluminum nitride (AlN) material, and the thickness of the nucleation layer 114 may be in the range of 100 nm to 300 nm. The transition layer 115 may include aluminum gallium nitride (AlGaN) material, and the thickness of the transition layer 115 may be in the range of 100 nm to 500 nm. The buffer layer 116 may include high-resistance gallium nitride (GaN) material, and the buffer layer 116 may be doped with carbon element with a concentration greater than 1e 17 ~2e 19 ; or, the buffer layer 116 may be doped with iron element with a concentration greater than 1e 17 . The thickness of the buffer layer 116 may be in the range of 0.5 um to 2 um.

[0138] In one possible implementation, the first electrode 12 may further include: an etch stop layer 124 located on the side of the anti-oxidation metal layer 123 facing away from the semiconductor substrate 10, and the etch stop layer 124 may include a metal material. For example, the etch stop layer 124 may include titanium (Ti) or nickel (Ni), and the thickness of the etch stop layer 124 may be greater than or equal to 20 nm. The etch stop layer 124 may protect the anti-oxidation metal layer 123 and prevent the anti-oxidation metal layer 123 from being damaged by the etching process of the dielectric layer. During the etching process of the dielectric layer, the upper surface of the etch stop layer 124 may be etched, resulting in a groove on the upper surface of the etch stop layer 124. Of course, in some cases, the upper surface of the etch stop layer 124 may also be a flat surface.

[0139] In one possible implementation, the semiconductor device provided in an embodiment of the present application may further include: an interconnect structure 15 located on a side of the first electrode 12 facing away from the semiconductor substrate 10, the interconnect structure 15 being in contact with the etch stop layer 124 so as to electrically connect the interconnect structure 15 to the first electrode 12, and the interconnect structure 15 being used to lead out the first electrode 12. For example, the interconnect structure 15 may include a metal material such as gold (Au). In a specific configuration, the width of the interconnect structure 15 may be smaller than the width of the anti-oxidation metal layer 123 in a direction parallel to the surface of the semiconductor substrate 10.

[0140] In addition, the semiconductor device in the embodiment of the present application may further include: a passivation layer 302, a gate contact metal layer 13 and a gate interconnection structure 14. For example, the passivation layer 302 may include a silicon nitride (SiN) material. The passivation layer 302 has a fourth groove T, which penetrates the passivation layer 302 in a direction perpendicular to the surface of the semiconductor substrate 10, and the bottom surface of the fourth groove T is a portion of the surface of the epitaxial layer 11. The gate contact metal layer 13 covers the sidewalls and bottom surface of the fourth groove T, and the gate interconnection structure 14 fills the portion of the fourth groove T except the gate contact metal layer 13, and protrudes from the surface of the passivation layer 302. For example, the gate contact metal layer 13 may include a metal material such as nickel (Ni) or tungsten (W). The gate contact metal layer 13 can serve as the gate of the transistor, and the gate contact metal layer 13 can contact the epitaxial layer 11 to form a Schottky contact. It should be explained that a Schottky contact refers to the bending of the energy band of the epitaxial layer 11 at the contact interface when the gate contact metal layer 13 and the epitaxial layer 11 are in contact, forming a contact barrier (which may be called a Schottky barrier). In one possible implementation, the gate interconnect structure 14 may include gold (Au) material. The gate interconnect structure 14 can serve to lead out the gate contact metal layer 13. In addition, the gate interconnect structure 14 can also provide anti-oxidation and reduce gate resistance.

[0141] In the embodiment of the present application, the depth of the first groove U1 on the surface of the epitaxial layer 11 is related to factors such as the material of the contact layer 121 and the annealing temperature of the annealing process.

[0142] In some embodiments of the present application, Figure 24 As shown, the contact layer 121 may include a metal material, and the first groove U1 extends from the surface of the epitaxial layer 11 on the side facing away from the semiconductor substrate 10 to the interior of the barrier layer 112. During the manufacturing process, a relatively high temperature annealing process may be used. For example, the annealing temperature may be in the range of 500°C to 1000°C. Due to the high annealing temperature, during the annealing process, the contact layer 121 reacts with the epitaxial layer 11, and the metal elements in the contact layer 121 may penetrate into the channel layer 111 through the barrier layer 112, thereby forming a good and reliable ohmic contact.

[0143] In the case where the contact layer 121 includes a metal material, the first electrode 12 may be configured as follows.

[0144] Specifically, a portion of the contact layer 121 is located within the first recess U1, while another portion protrudes from the surface of the epitaxial layer facing away from the semiconductor substrate 10. The contact layer 121 has a second recess U2 on the surface facing away from the semiconductor substrate 10. The contact layer 121 can contact the epitaxial layer 11 at the inner wall of the first recess U1. This arrangement can increase the contact area between the contact layer 121 and the epitaxial layer 11, thereby reducing the resistivity of the ohmic contact between the contact layer 121 and the epitaxial layer 11. Exemplarily, the contact layer 121 can include titanium (Ti) material, and the thickness of the contact layer 121 can be in the range of 4 nm to 20 nm.

[0145] A portion of the metal isolation layer 122 is located within the second recess U2, while another portion protrudes from the surface of the contact layer 121 facing away from the semiconductor substrate 10. The metal isolation layer 122 also has a third recess U3 on the surface facing away from the semiconductor substrate 10. Providing the metal isolation layer 122 on the surface of the contact layer 121 prevents the anti-oxidation metal layer 123 from diffusing into the contact layer 121, thus preventing excessive metal elements in the anti-oxidation metal layer 123 from diffusing downward and potentially causing reliability issues in the semiconductor device. Specifically, the metal isolation layer 122 can include at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and can have a thickness ranging from 20 nm to 100 nm. In one possible implementation, the first electrode 12 may further include: a first metal layer 125 located between the contact layer 121 and the metal isolation layer 122, a portion of the first metal layer 125 being located in the second groove U2, and another portion extending to the surface of the contact layer 121 excluding the second groove U2, and the first metal layer 125 also having a groove on the side facing away from the semiconductor substrate 10, a portion of the metal isolation layer 122 being located in the groove on the surface of the first metal layer 125, and another portion extending to the surface of the first metal layer 125 excluding the groove. Exemplarily, the first metal layer 125 may include aluminum (Al) material, and the thickness of the first metal layer 125 may be between 80 nm and 200 nm. During the annealing process, the first metal layer 125 may diffuse downward, for example, may diffuse into the channel layer 111, participate in the ohmic contact reaction, facilitate the formation of a good and reliable ohmic contact, and further reduce the resistivity of the ohmic contact.

[0146] A portion of the anti-oxidation metal layer 123 is located within the third groove U3, and another portion protrudes from the surface of the metal isolation layer 123 on the side facing away from the semiconductor substrate 10. The anti-oxidation metal layer 123 can fill the third groove U3, and the surface of the anti-oxidation metal layer 123 on the side facing away from the semiconductor substrate 10 can be a flat surface. The thickness of the anti-oxidation metal layer 123 protruding from the surface of the metal isolation layer 122 on the side facing away from the semiconductor substrate 10 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In one possible implementation, the anti-oxidation metal layer 123 may include an inert metal material. For example, the anti-oxidation metal layer 123 may include an inert metal material such as gold (Au) or platinum (Pt). The inert metal material is not easily oxidized during annealing (annealing temperature is within the range of 200°C to 1000°C), so that the anti-oxidation metal layer 123 can effectively isolate the anti-oxidation metal layer 123 from the air. Alternatively, the anti-oxidation metal layer 123 may include an alloy material having anti-oxidation properties. For example, the anti-oxidation metal layer 123 may include titanium nitride (TiN). The anti-oxidation alloy material is not easily oxidized during annealing (annealing temperature is within the range of 200° C. to 1000° C.), and can also effectively isolate the anti-oxidation metal layer 123 from air. Of course, in some cases, the anti-oxidation metal layer 123 may also be made of other anti-oxidation materials, which is not limited in this application.

[0147] In other embodiments of the present application, Figure 23 As shown, the contact layer 121 may include a semiconductor doping layer 121a and a second metal layer 121b, and the first groove U1 extends from the surface of the epitaxial layer away from the semiconductor substrate 10 (i.e., the upper surface of the cap layer 113 in the figure) to the inside of the channel layer 111. During the manufacturing process, a lower temperature can be used for annealing. For example, the temperature of the annealing treatment can be in the range of 200°C to 500°C. Since the bottom of the first groove U1 is located inside the channel layer 111 in the embodiment of the present application, the semiconductor doping layer 121a in the contact layer 121 can be in direct contact with the channel layer 111. Therefore, a good and reliable ohmic contact can be formed by using a lower annealing temperature.

[0148] In the case where the contact layer 121 includes the semiconductor doping layer 121 a and the second metal layer 121 b , the first electrode 12 may be configured as follows.

[0149] Specifically, the semiconductor doping layer 121a may include a semiconductor material doped with impurities. Exemplarily, the semiconductor doping layer 121a may include a gallium nitride (GaN) material highly doped with N-type impurities. The semiconductor doping layer 121a may fill the first groove U1. In a possible implementation, the surface of the semiconductor doping layer 121a may be flush with the upper surface of the epitaxial layer, or the surface of the semiconductor doping layer 121a may be slightly higher than the upper surface of the epitaxial layer. The second metal layer 121b is located on the side of the semiconductor doping layer 121a facing away from the semiconductor substrate 10. Exemplarily, the second metal layer 121b may include titanium (Ti) material. The second metal layer 121b may be a reactant for the ohmic contact reaction. By filling the semiconductor doping layer 121a in the first groove U1 of the epitaxial layer, the semiconductor doping layer 121a can play a role in reducing the barrier between the epitaxial layer and the second metal layer 121b, which is beneficial to the formation of an ohmic contact.

[0150] A metal isolation layer 122 is provided on the side of the contact layer 121 facing away from the semiconductor substrate 10. The metal isolation layer 122 can prevent the materials in the antioxidant metal layer 123 from diffusing into the contact layer 121, avoiding excessive downward diffusion of metal elements in the antioxidant metal layer 123 and causing reliability problems in the semiconductor device. In a possible implementation, the metal isolation layer 122 may include platinum (Pt) material.

[0151] An antioxidant metal layer 123 is provided on the side of the metal isolation layer 122 facing away from the semiconductor substrate 10. The thickness of the antioxidant metal layer 123 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In a possible implementation, the antioxidant metal layer 123 may include: inert metal materials. For example, the antioxidant metal layer 123 may include inert metal materials such as gold (Au), platinum (Pt), etc. Inert metal materials are not easily oxidized during the annealing process (the annealing temperature is in the range of 200 °C to 1000 °C), which can enable the antioxidant metal layer 123 to play a better role in isolating air. And / or, the antioxidant metal layer 123 may include: alloy materials with antioxidant properties. For example, the antioxidant metal layer 123 may include titanium nitride (TiN) material. Alloy materials with antioxidant properties are not easily oxidized during the annealing process (the annealing temperature is in the range of 200 °C to 1000 °C), and can also enable the antioxidant metal layer 123 to play a better role in isolating air. Of course, in some cases, the antioxidant metal layer 123 may also use other antioxidant materials, which are not limited in this application.

[0152] As Figure 23 and Figure 24 shown, for the case where the contact layer 121 includes a metal material and the contact layer 121 includes the semiconductor doping layer 121a and the second metal layer 121b, the first electrode 12 may also be arranged in the following manner.

[0153] In a possible implementation, the outer edges formed by the antioxidant metal layer 123 and the metal isolation layer 122 in the first electrode 12 are flush. In this way, the morphology of the first electrode 12 can be improved, and the electrical performance of the semiconductor device can be enhanced. During the manufacturing process, the metal isolation layer 122 and the antioxidant metal layer 123 can be patterned using the same lithography process, so that the outer edges formed by the antioxidant metal layer 123 and the metal isolation layer 122 are flush. In some embodiments of the present application, the first electrode 12 may further include an etch stop layer 124. Specifically, the edge of the etch stop layer 124 can also be set to be flush with the edge of the antioxidant metal layer 123. In this way, the morphology of the first electrode 12 can be improved, and the electrical performance of the semiconductor device can be enhanced. During the manufacturing process, the metal isolation layer 122, the antioxidant metal layer 123, and the etch stop layer 124 can be patterned using the same lithography process, so that the outer edges formed by the metal isolation layer 122, the antioxidant metal layer 123, and the etch stop layer 124 are flush.

[0154] During the manufacturing process, the metal film layers in the first electrode 12 can be deposited sequentially, and then, the metal film layers can be patterned using the same lithography process, so that the outer edges formed by the metal film layers in the first electrode 12 are flush. Specifically, as Figure 24 shown, for the case where the contact layer 121 includes a metal material, the contact layer 121, the first metal layer 125, the metal isolation layer 122, the antioxidant metal layer 123, and the etch stop layer 124 can be deposited over the entire surface, and the contact layer 121, the first metal layer 125, the metal isolation layer 122, the antioxidant metal layer 123, and the etch stop layer 124 can be patterned using the same lithography process, so that the outer edges formed by the contact layer 121, the first metal layer 125, the metal isolation layer 122, the antioxidant metal layer 123, and the etch stop layer 124 in the first electrode 12 are flush. As Figure 23 shown, for the case where the contact layer 121 includes a semiconductor doped layer 121a and a second metal layer 121b, the second metal layer 121b, the metal isolation layer 122, the antioxidant metal layer 123, and the etch stop layer 124 can be deposited over the entire surface, and the second metal layer 121b, the metal isolation layer 122, the antioxidant metal layer 123, and the etch stop layer 124 can be patterned using the same lithography process, so that the outer edges formed by the second metal layer 121b, the metal isolation layer 122, the antioxidant metal layer 123, and the etch stop layer 124 in the first electrode 12 are flush. It can be understood that in the embodiments of the present application, due to the limitations of the manufacturing process level, the outer edges of some film layers in the first electrode being flush means that the outer edges of these film layers are substantially flush within a certain error range.

[0155] Figure 25 Schematic diagram for comparison between the technical solution of the related art and the technical solution of the present application Figure 25 In (1) of [figure reference], it is a schematic diagram of the relationship between the current and voltage of a semiconductor device in the related art Figure 25 In (2) of [figure reference], it is a schematic diagram of the relationship between the resistivity and distance of a semiconductor device in the related art Figure 25 In (3) of [figure reference], it is a schematic diagram of the relationship between the current and voltage of a semiconductor device in the present application Figure 25 In (4) of [figure reference], it is a schematic diagram of the relationship between the resistivity and distance of a semiconductor device in the present application. In the semiconductor device provided by the embodiment of the present application, the thickness of the antioxidant metal layer in the first electrode is greater than or equal to 400 nm. In the technical solution of the related art, the thickness of the antioxidant metal layer in the first electrode is about 50 nm. By comparing Figure 25 (1) and (3), (2) and (4) in [figure reference], it can be clearly seen that in the embodiment of the present application, using a thicker antioxidant metal layer can play a better antioxidant role and can significantly reduce the resistivity of the ohmic contact of the semiconductor device

[0156] Based on the same inventive concept, the embodiment of the present application also provides a power amplifier chip. The power amplifier chip in the embodiment of the present application may include any of the above semiconductor devices, or the power amplifier chip in the embodiment of the present application may include the semiconductor device manufactured by the above manufacturing method. Since the resistivity of the ohmic contact of the semiconductor device in the embodiment of the present application is low, therefore, the electrical performance of the power amplifier chip including this semiconductor device is good

[0157] Based on the same inventive concept, the embodiment of the present application also provides an electronic device. The electronic device in the embodiment of the present application may include the above power amplifier chip, and the electronic device is a terminal portable device. For example, the electronic device in the embodiment of the present application may be a device such as a mobile phone, a tablet computer, a laptop computer, etc. Since the electrical performance of the power amplifier chip in the embodiment of the present application is good, therefore, the performance of the electronic device including this power amplifier chip is also good

[0158] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application

[0159] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and modifications

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate; An epitaxial layer located above the semiconductor substrate, with a first groove provided on the surface of the epitaxial layer on the side facing away from the semiconductor substrate; the epitaxial layer includes: a channel layer; A first electrode, which is a source electrode or a drain electrode, with a part of the first electrode located inside the first groove and another part protruding from the surface of the epitaxial layer on the side facing away from the semiconductor substrate; The first electrode includes: a contact layer, a metal isolation layer, and an antioxidant metal layer. The contact layer contacts the epitaxial layer on the inner wall of the first groove. The antioxidant metal layer is located on the side of the contact layer facing away from the semiconductor substrate, and the metal isolation layer is located between the contact layer and the antioxidant metal layer; the thickness of the antioxidant metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer.

2. The semiconductor device according to claim 1, wherein, The outer edges formed by the antioxidant metal layer and the metal isolation layer in the first electrode are flush.

3. The semiconductor device according to claim 1, wherein, The antioxidant metal layer includes: an inert metal material; and / or, the antioxidant metal layer includes: an alloy material with antioxidant properties.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, Further comprising: An interconnect structure located on the side of the first electrode facing away from the semiconductor substrate; The first electrode further includes: an etching stop layer located on the side of the antioxidant metal layer facing away from the semiconductor substrate; The etching stop layer includes a metal material, and the interconnect structure is in contact connection with the etching stop layer; The edge of the etching stop layer is flush with the edge of the antioxidant metal layer.

5. The semiconductor device according to claim 4, wherein, In the direction parallel to the surface of the semiconductor substrate, the width of the interconnect structure is smaller than the width of the antioxidant metal layer; The etching stop layer includes Ti or Ni, and the thickness of the etching stop layer is greater than or equal to 20 nm.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The epitaxial layer further includes: a barrier layer, and the barrier layer is located on the side of the channel layer facing away from the semiconductor substrate; The thickness of the channel layer is in the range of 100 nm to 400 nm, and the thickness of the barrier layer is in the range of 4 nm to 35 nm.

7. The semiconductor device according to claim 6, wherein, The contact layer includes a metal material; The first groove extends from the surface of the epitaxial layer on the side facing away from the semiconductor substrate to the inside of the barrier layer; A part of the contact layer is located inside the first groove, and another part protrudes from the surface of the epitaxial layer on the side facing away from the semiconductor substrate, and the contact layer has a second groove on the surface facing away from the semiconductor substrate; A part of the metal isolation layer is located inside the second groove, and another part protrudes from the surface of the contact layer on the side facing away from the semiconductor substrate, and the metal isolation layer has a third groove on the surface facing away from the semiconductor substrate; A part of the antioxidant metal layer is located inside the third groove, and another part protrudes from the surface of the metal isolation layer on the side facing away from the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein The contact layer includes Ti material, and the thickness of the contact layer is in the range of 4 nm to 20 nm; The metal isolation layer includes at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and the thickness of the metal isolation layer is in the range of 20 nm to 100 nm.

9. The semiconductor device according to claim 7 or 8, wherein The first electrode further includes a first metal layer located between the contact layer and the metal isolation layer. The first metal layer includes an Al material, and the thickness of the first metal layer is between 80 nm and 200 nm.

10. The semiconductor device according to claim 6, wherein, The contact layer includes a semiconductor doped layer and a second metal layer; The semiconductor doped layer includes a semiconductor material doped with impurities. The semiconductor doped layer fills the first groove, and the second metal layer is located on the side of the semiconductor doped layer facing away from the semiconductor substrate; The first groove extends from the surface of the epitaxial layer on the side facing away from the semiconductor substrate into the interior of the channel layer.

11. The semiconductor device according to claim 10, wherein, The semiconductor doped layer includes a GaN material doped with N-type impurities, and the second metal layer includes a Ti material; the metal isolation layer includes a Pt material.

12. The semiconductor device according to any one of claims 6 to 11, characterized in that, The epitaxial layer further includes a cap layer located on the side of the barrier layer facing away from the semiconductor substrate; The first groove penetrates the cap layer in a direction perpendicular to the surface of the semiconductor substrate; The cap layer includes a GaN material, and the thickness of the cap layer is in the range of 1 nm to 5 nm.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, The epitaxial layer further includes a nucleation layer located between the semiconductor substrate and the channel layer, a transition layer located between the nucleation layer and the channel layer, and a buffer layer between the transition layer and the channel layer; The nucleation layer includes an AlN material, and the thickness of the nucleation layer is in the range of 100 nm to 300 nm; The transition layer includes an AlGaN material, and the thickness of the transition layer is in the range of 100 nm to 500 nm; The buffer layer includes a GaN material; the buffer layer is doped with carbon elements having a concentration greater than 1e 17 ~2e 19 ; alternatively, the buffer layer is doped with iron elements having a concentration greater than 1e 17 ; the thickness of the buffer layer is in the range of 0.5 um to 2 um.

14. The semiconductor device according to any one of claims 1 to 13, characterized in that, The semiconductor substrate includes Si material with a resistivity greater than 5000 Ω.cm; alternatively, the semiconductor substrate includes SiC material with a resistivity greater than 1e 6 Ω.cm; alternatively, the semiconductor substrate includes GaN material with a resistivity greater than 1e4 Ω.cm; alternatively, the semiconductor substrate includes sapphire material with a resistivity greater than 1e11 Ω.cm.

15. A manufacturing method of a semiconductor device, characterized in that, including: forming an epitaxial layer on the semiconductor substrate, and patterning the epitaxial layer to form a first groove on the surface of the epitaxial layer on the side facing away from the semiconductor substrate; wherein, the epitaxial layer includes a channel layer; forming a first electrode with a part located inside the first groove and another part protruding from the surface of the epitaxial layer on the side facing away from the semiconductor substrate; wherein, the first electrode is a source electrode or a drain electrode, and the first electrode includes a contact layer, a metal isolation layer, and an antioxidant metal layer. The contact layer contacts the epitaxial layer on the inner wall of the first groove, the antioxidant metal layer is located on the side of the contact layer facing away from the semiconductor substrate, and the metal isolation layer is located between the contact layer and the antioxidant metal layer; the thickness of the antioxidant metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer; annealing the structure after forming the antioxidant metal layer to obtain the semiconductor device.

16. The manufacturing method according to claim 15, wherein, The forming an epitaxial layer on the semiconductor substrate and patterning the epitaxial layer to form a first groove on the surface of the epitaxial layer on the side facing away from the semiconductor substrate specifically includes: forming the channel layer with a thickness in the range of 100 nm to 400 nm on the semiconductor substrate; forming a barrier layer having a thickness in the range of 4 nm to 35 nm on the channel layer; Performing patterning on the epitaxial layer to form the first groove extending from a surface of the epitaxial layer facing away from the semiconductor substrate to an interior of the barrier layer; The forming of the first electrode having a portion located inside the first groove and another portion protruding from a surface of the epitaxial layer facing away from the semiconductor substrate specifically includes: A contact layer is formed using a metal material, with a portion of the contact layer located inside the first groove and another portion extending to a region of the surface of the epitaxial layer excluding the first groove, and a second groove is formed on a surface of the contact layer facing away from the semiconductor substrate; A metal isolation layer is formed using a metal material, with a portion of the metal isolation layer being located within the second groove and another portion extending to an area above the contact layer excluding the second groove, and a third groove being provided on a surface of the metal isolation layer facing away from the semiconductor substrate; forming an anti-oxidation metal layer using a metal material, with a portion of the anti-oxidation metal layer being located within the third groove and another portion protruding from a surface of the metal isolation layer facing away from the semiconductor substrate; The annealing treatment of the structure after forming the anti-oxidation metal layer specifically includes: The structure after forming the anti-oxidation metal layer is annealed at a temperature within a range of 500° C. to 1000° C.

17. The manufacturing method according to claim 15, characterized in that, The step of forming an epitaxial layer on a semiconductor substrate and patterning the epitaxial layer to form a first groove on a surface of the epitaxial layer facing away from the semiconductor substrate specifically includes: forming the channel layer with a thickness ranging from 100 nm to 400 nm on the semiconductor substrate; forming a barrier layer having a thickness in the range of 4 nm to 35 nm on the channel layer; Performing patterning on the epitaxial layer to form the first groove extending from a surface of the epitaxial layer facing away from the semiconductor substrate to an interior of the channel layer; The contact layer includes: a semiconductor doping layer and a second metal layer; the first electrode formed with a portion located inside the first groove and another portion protruding from the surface of the epitaxial layer facing away from the semiconductor substrate specifically includes: forming the semiconductor doping layer using a semiconductor material doped with impurities, so that the semiconductor doping layer fills the first groove; forming the second metal layer, the metal isolation layer and the anti-oxidation metal layer in sequence on the semiconductor doping layer; The annealing treatment of the structure after forming the anti-oxidation metal layer specifically includes: The structure after forming the anti-oxidation metal layer is annealed at a temperature within a range of 200° C. to 500° C.

18. The manufacturing method according to any one of claims 15 to 17, characterized in that, The forming of the first electrode having a portion located inside the first groove and another portion protruding from a surface of the epitaxial layer facing away from the semiconductor substrate further includes: forming an etch stop layer on the anti-oxidation metal layer; After the structure after forming the anti-oxidation metal layer is annealed, the method further includes: An interconnection structure in contact with the etch stop layer is formed.

19. A power amplifier chip, characterized in that, include: The semiconductor device according to any one of claims 1 to 14, or the semiconductor device manufactured by the manufacturing method according to any one of claims 15 to 18.

20. An electronic device, characterized in that, Including a power amplifier chip according to claim 19, and the electronic device is a terminal portable device.

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