Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. According to an embodiment, a semiconductor device may include a substrate including a base substrate and a buried oxide layer on the base substrate; the channel layer is arranged on the buried oxide layer and has stress; an isolation layer between the channel layer and the buried oxide layer; a gate stack on the channel layer; and the source / drain layers are arranged on two opposite sides of the channel layer.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor technology, and more particularly, to a semiconductor device with improved performance and a method for manufacturing the same. Background Art

[0002] Planar semiconductor-on-insulator (SOI) devices are inferior to other device architectures such as fin field-effect transistors (FinFETs) and multi-nanosheet or nanowire devices in terms of area scaling. Therefore, it is desirable to improve other device performances of SOI devices, such as improving carrier mobility, stress application, etc. Summary of the Invention

[0003] An object of the present disclosure is to provide, at least in part, a semiconductor device with improved performance and a method for manufacturing the same.

[0004] According to one aspect of the present disclosure, there is provided a semiconductor device, comprising: a substrate including a base substrate and a buried oxide layer on the base substrate; a channel layer on the buried oxide layer, wherein the channel layer has stress; an isolation layer between the channel layer and the buried oxide layer; a gate stack on the channel layer; and source / drain layers on opposite sides of the channel layer.

[0005] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: sequentially disposing a sacrificial layer and a preliminary channel layer on a substrate, wherein the substrate includes a base substrate and a buried oxide layer on the base substrate, and the sacrificial layer induces stress in the preliminary channel layer; patterning the sacrificial layer and the preliminary channel layer into a fin structure extending in a first direction; forming a sacrificial gate extending in a second direction intersecting the first direction and intersecting the fin structure and forming sidewalls on sidewalls of the sacrificial gate; patterning the fin structure using the sacrificial gate and the sidewalls as masks; forming source / drain layers on sidewalls of the patterned fin structure; removing the sacrificial gate to expose sidewalls of the sacrificial layer inside the sidewalls; removing the sacrificial layer via the exposed sidewalls of the sacrificial layer, and forming an isolation layer in a space released due to the removal of the sacrificial layer; and forming a gate stack on the preliminary channel layer inside the sidewalls.

[0006] According to an embodiment of the present disclosure, by providing the sacrificial layer, stress can be introduced into the channel layer to improve device performance. Additionally, the sacrificial layer is ultimately replaced by the isolation layer, so that the semiconductor-on-insulator (SOI) structure can be maintained and the advantages of the SOI device can be retained. Brief Description of the Drawings

[0007] According to the following description in conjunction with the drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure may be more apparent. In the drawings:

[0008] Figure 1(a) and 1(b)A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is schematically shown;

[0009] Figures 2 to 15(b) Some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown. Detailed implementation manners

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0011] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0012] Figure 1(a) and 1(b) A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0013] As shown in FIG. 1(a), a semiconductor device according to an embodiment may include a substrate, which may include a base substrate 101 and a buried oxide layer 103 on the base substrate 101. Such a substrate can be provided, for example, by a semiconductor-on-insulator (SOI) substrate, as will be described in further detail below. The semiconductor device may further include a channel layer 107 on the buried oxide layer 103 and an isolation layer 121 between the channel layer 107 and the buried oxide layer 103. The channel layer 107 may include a suitable semiconductor material such as silicon (Si), etc., and may be in the form of nanosheets. The isolation layer 121 may include a suitable dielectric material such as an oxide (e.g., silicon oxide). The lower surface of the isolation layer 121 may be adjacent to the buried oxide layer 103, and the upper surface may be adjacent to the channel layer 107.

[0014] As described in further detail below, the isolation layer 121 can be formed by replacing a sacrificial layer below the channel layer 107 and can be self-aligned with the channel layer 107. For example, in a top view, the isolation layer 121 and the channel layer 107 can substantially completely overlap. Additionally, such a sacrificial layer can cause stress in the channel layer 107, for example due to differences in lattice constants. For an n-type semiconductor device, tensile stress can be present in the channel layer 107 to enhance the mobility of carriers (electrons); while for a p-type semiconductor device, compressive stress can be present in the channel layer 107 to enhance the mobility of carriers (holes). For example, for an n-type semiconductor device, the sacrificial layer can include SiGe while the channel layer can include Si, which can cause tensile stress in the Si channel layer. On the other hand, for a p-type semiconductor device, the sacrificial layer can include Si while the channel layer can include SiGe, which can cause compressive stress in the SiGe channel layer.

[0015] The semiconductor device can further include a gate stack on the channel layer 107. The gate stack can include a gate dielectric layer 123 and a gate electrode layer 125 on the gate dielectric layer 123. The gate stack can include a metal gate stack. For example, the gate dielectric layer 123 can include a high-K gate dielectric such as hafnium oxide (HfO2), and the gate electrode layer 125 can include a work function layer such as a conductive metal nitride like titanium nitride (TiN) and a gate conductor layer on the work function layer such as a metal like tungsten (W).

[0016] The semiconductor device can further include source / drain layers 117 on opposite sides of the channel layer 107. The source / drain layers 117 can be disposed on the buried oxide layer 103 and extend on the sidewalls of the isolation layer 121. The source / drain layers 117 can include a suitably doped semiconductor material. For example, for an n-type semiconductor device, the source / drain layers 117 can be doped n-type; or, for a p-type semiconductor device, the source / drain layers 117 can be doped p-type. The source / drain layers 117 can include the same semiconductor material as the channel layer 107 such as Si, or can include a semiconductor material different from the channel layer 107. In the case of including different materials, the source / drain layers 117 can also apply stress to the channel layer 107 to further enhance device performance.

[0017] FIG. 1(b) shows a semiconductor device according to another embodiment. The semiconductor device shown in FIG. 1(b) can have substantially the same structure as the semiconductor device shown in FIG. 1(a), except for the channel layer. The channel layer of the semiconductor device according to this embodiment can include a multi-layer structure. Hereinafter, the differences between these two embodiments will be mainly described.

[0018] As shown in FIG. 1(b), the channel layer may include a first semiconductor layer 107' and a second semiconductor layer 127 on the first semiconductor layer 107'. The first semiconductor layer 107' may be adjacent to the isolation layer 121 and may include a portion extending on the bottom surface of the second semiconductor layer 127 and a portion extending on the sidewalls of the second semiconductor layer. As described above, due to the sacrificial layer (replaced by the isolation layer 121), the first semiconductor layer 107' may have stress. Generally, the first semiconductor layer 107' has one type of stress, i.e., tensile stress or compressive stress. This single type of stress may be suitable for optimizing one type of device (e.g., tensile stress is suitable for optimizing n-type semiconductor devices while compressive stress is suitable for optimizing p-type semiconductor devices). If another type of device is to be formed, then different stress needs to be generated in the channel layer. This can be achieved by providing the second semiconductor layer 127 on the first semiconductor layer 107'. For example, due to the difference in lattice constants between the first semiconductor layer 107' and the second semiconductor layer 127, another type of stress may be induced in the second semiconductor layer 127. In one example, the first semiconductor layer 107' may include Si (e.g., having tensile stress due to a SiGe sacrificial layer), the second semiconductor layer 127 may include SiGe (having compressive stress due to the first semiconductor layer 107' of Si), and thus it is beneficial for p-type semiconductor devices. In this example, the channel layer may further include a third semiconductor layer 129 such as Si on the second semiconductor layer 127 to improve the interface quality. In another example, the first semiconductor layer 107' may include SiGe (e.g., having compressive stress due to a Si sacrificial layer), the second semiconductor layer 127 may include Si (having tensile stress due to the first semiconductor layer 107' of SiGe), and thus it is beneficial for n-type semiconductor devices.

[0019] Although Figure 1(a) and 1(b) show semiconductor devices of different configurations respectively, the two configurations of semiconductor devices can be integrated on a substrate, where some devices may have the configuration shown in FIG. 1(a) while some devices may have the configuration shown in FIG. 1(b). For example, among the devices integrated on the substrate, the n-type semiconductor devices may have the configuration shown in FIG. 1(a), while the p-type semiconductor devices may have the configuration shown in FIG. 1(b); vice versa. In this case, the channel layer 107 in the configuration shown in FIG. 1(a) and the first semiconductor layer 107' in the configuration shown in FIG. 1(b) may include the same semiconductor material, and they may be obtained from the same preliminary channel layer as described below.

[0020] Such a semiconductor device can be manufactured as follows.

[0021] For example, a sacrificial layer and a preparatory channel layer can be sequentially disposed on a substrate. As described above, the substrate can include a base substrate and a buried oxide layer on the base substrate. The sacrificial layer can induce stress in the preparatory channel layer, for example, due to the difference in lattice constants between the two. In one example, an SOI substrate can be provided, which includes a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer. The SOI layer can be used as the sacrificial layer.

[0022] The sacrificial layer and the preparatory channel layer can be patterned into a fin structure extending in a first direction. Additionally, a sacrificial gate extending in a second direction intersecting (e.g., perpendicular to) the first direction and intersecting the fin structure can be formed. On the sidewalls of the sacrificial gate, spacers can be formed. Using the sacrificial gate and the spacers as masks, the fin structure can be patterned. In this way, the opposite sidewalls of the sacrificial layer and the preparatory channel layer in the first direction can be exposed. Source / drain layers can be formed on the sidewalls of the patterned sacrificial layer and preparatory channel layer. These processes can be compatible with the manufacturing processes of (SOI) nanosheet devices.

[0023] After that, an alternative gate process can be performed. For example, the sacrificial gate can be removed to expose the sidewall of the sacrificial layer inside the spacers. The sacrificial layer can be removed via the exposed sidewall of the sacrificial layer, and an isolation layer can be formed in the space released due to the removal of the sacrificial layer. A gate stack can be formed on the preparatory channel layer inside the spacers.

[0024] According to an embodiment of the present disclosure, stress can be introduced into the channel layer through the sacrificial layer. The sacrificial layer is replaced by the isolation layer in the final device, maintaining the SOI structure without the need to consider the bottom isolation problem as in nanosheet devices. The semiconductor device according to an embodiment of the present disclosure can be a fully depleted (FD) SOI device.

[0025] The present disclosure can be presented in various forms, and some examples will be described below. In the following description, the selection of various materials is involved. In addition to considering its function (e.g., semiconductor materials are used to form active regions, and dielectric materials are used to form electrical isolation), the etching selectivity is also considered when selecting materials. In the following description, the required etching selectivity may or may not be indicated. Those skilled in the art should be aware that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or other layers are not shown as being etched in the figure, then this etching can be selective, and this material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0026] Figures 2 to 15(b) Some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0027] As Figure 2As shown, an SOI substrate 100 can be provided. The SOI substrate 100 can include a base substrate 1001, a buried oxide layer 1003 on the base substrate 1001, and an SOI layer 1005 on the buried oxide layer 1003. The base substrate 1001 can include a semiconductor material such as silicon (Si), the buried oxide layer 1003 can include an oxide (such as silicon oxide), and the SOI layer 1005 can include a suitable semiconductor material such as SiGe. The SOI layer 1005 can be used as the sacrificial layer described above.

[0028] SOI substrates with an SOI layer of SiGe can be provided by different methods. For example, an insulator-on-SiGe (SGOI) substrate can be formed by bonding a SiGe layer to a base substrate through a smart-cut process. Alternatively, a conventional SOI substrate with an SOI layer of Si can be converted into an SOI layer of SiGe through a germanium enrichment process.

[0029] As Figure 3 shown, on the SOI substrate 100, specifically on the SOI layer 1005, a preliminary channel layer 1007 can be formed, for example, by epitaxial growth. The preliminary channel layer 1007 can include a semiconductor material different from the SOI layer 1005 to have an etching selectivity with respect to the SOI layer 1005 on the one hand and a strain or stress generated due to a difference in lattice constant on the other hand. For example, the preliminary channel layer 1007 can include Si.

[0030] In this example, the SOI layer 1005 includes SiGe and the preliminary channel layer 1007 includes Si, so tensile stress can be generated in the preliminary channel layer 1007. However, the present disclosure is not limited thereto. For example, the SOI layer 1005 can include Si and the preliminary channel layer 1007 can include SiGe, so compressive stress can be generated in the preliminary channel layer 1007. Additionally, Si-based materials are used as an example for description herein. However, the present disclosure is not limited thereto, and other suitable semiconductor materials are equally applicable.

[0031] For example, as Figure 4(a) 、 4(b) and 4(c) (the positions of the AA' section and the BB' section are shown in the top view of Fig. 4(a)) shown, the SOI layer 1005 and the preliminary channel layer 1007 can be patterned into strips extending in a first direction (for example, Figure 4(a) and 4(b) the horizontal direction in the plane of the paper, the direction perpendicular to the plane of the paper in Fig. 4(c)). As shown in Fig. 4(c), the patterned SOI layer 1005 and preliminary channel layer 1007 protrude relatively to form a fin structure. The patterning of the SOI layer 1005 and the preliminary channel layer 1007 can penetrate into the base substrate 1001. Between each fin structure (in Figure 4(a) 、 4(b)In FIGS. 4(c), only a single fin structure is shown; however, those skilled in the art will understand that multiple fin structures can be formed), shallow trench isolation (STI) can be formed, as can be seen in 1011 in FIG. 5(c). The STI can include an oxide, and the top surface can be between the top and bottom surfaces of the buried oxide layer 1003.

[0032] As Figure 5(a) , 5(b) and as shown in FIGS. 5(c), a sacrificial gate 1013 can be formed extending in a second direction (e.g., the vertical direction in the plane of the paper in FIG. 5(a), the direction perpendicular to the plane of the paper in FIG. 5(b), the horizontal direction in the plane of the paper in FIG. 5(c)) intersecting (e.g., perpendicular) to the first direction so as to intersect the fin structure. On the sidewalls of the sacrificial gate 1013, spacers 1015 can be formed. For example, the sacrificial gate 1013 can include a stack of an oxide and polysilicon (with a hard mask layer on top for assisting in patterning), and the spacers 1015 can include a nitride (e.g., silicon nitride). Although the spacers 1015 are shown as a single-layer structure in this example, the present disclosure is not limited thereto. The spacers 1015 can also have a multi-layer structure.

[0033] On opposite sides of the sacrificial gate, source / drain layers can be formed.

[0034] For example, as Figure 6 shown, the sacrificial gate 1013 and the spacers 1015 can be used as an etching mask to anisotropically etch the SOI layer 1005 and the pre-channel layer 1007, such as reactive ion etching (RIE) in the vertical direction. The sidewalls of the SOI layer 1005 and the pre-channel layer 1007 in the first direction can be exposed. Figure 6 An example is shown where the etching stops at the buried oxide layer 1003. However, the present disclosure is not limited thereto. For example, the etching can also stop at the SOI layer 1005, so that the SOI layer 1005 can also be used as a seed in a subsequent source / drain epitaxial growth process to improve the crystal quality of the source / drain layers.

[0035] As Figure 7 shown, source / drain layers 1017 can be formed, for example, by selective epitaxial growth using the so-exposed sidewalls as seeds. The source / drain portions 101 layers can be doped to the desired conduction type, for example, by in-situ doping during growth or ion implantation after growth. Regarding the source / drain layers 1017, reference can be made to the detailed description of the source / drain layers in conjunction with FIG. 1 above.

[0036] Next, an alternative gate process can be performed.

[0037] For example, as Figure 8As shown, an interlayer dielectric layer 1019 can be formed. For example, an oxide layer can be formed by deposition such as chemical vapor deposition (CVD) and planarized such as by chemical mechanical polishing (CMP), and the CMP can be performed until the sacrificial gate 1013 is exposed, thereby forming the interlayer dielectric layer 1019.

[0038] As Figure 9(a) and 9(b) shown, the sacrificial gate 1013 can be removed by selective etching, thereby releasing space for the gate stack inside the sidewall 1015. In the space thus released, the sidewalls of the SOI layer 1005 (in the second direction) can be exposed.

[0039] As Figure 10(a) and 10(b) shown, the SOI layer 1005 can be removed by selective etching via the exposed sidewalls of the SOI layer 1005. Due to the structures around the pre-channel layer 1007 (e.g., the source / drain layer 1017, the interlayer dielectric layer 1019, etc.), even though the SOI layer 1005 is removed, the stress in the pre-channel layer 1007 caused by the SOI layer 1005 can be maintained. The process of removing the SOI layer 1005 is similar to the process of releasing the channel layer in a nanosheet device, and thus can be compatible with the process of manufacturing a nanosheet device.

[0040] In the space released due to the removal of the SOI layer 1005, an isolation layer can be formed. For example, as Figure 11(a) and 11(b) shown, an oxide layer can be formed by deposition such as CVD, the deposited oxide layer can be planarized such as by CMP, and the planarized oxide layer can be etched back to form the isolation layer 1021. To facilitate controlling the stop point of the etch back, the STI 1011 can include, for example, a high density plasma (HDP) oxide, and thus the etch back of the oxide can stop at the HDP oxide.

[0041] After that, as Figure 12(a) and 12(b) shown, a gate stack can be formed on the pre-channel layer 1007 inside the sidewall 1015. The gate stack can include a gate dielectric layer 1023 and a gate electrode layer 1025. Regarding the gate stack, reference can be made to the detailed description of the gate stack in conjunction with FIG. 1 above.

[0042] The portion of the pre-channel layer 1007 remaining in the final device can serve as the channel layer. As described above, the channel layer can have a single type of stress. In the example where the above SOI layer 1005 is SiGe and the pre-channel layer 1007 is Si, the final channel layer can have tensile stress. Alternatively, for example, if the SOI layer 1005 is Si and the pre-channel layer 1007 is SiGe, the final channel layer can have compressive stress.

[0043] Therefore, the formation of the gate stack directly on the preliminary channel layer 1007 as described above in combination with Figure 12(a) and 12(b) can be applicable to one type of device (for example, in the case where the preliminary channel layer 1007 has tensile stress, it is applicable to n-type semiconductor devices; in the case where the preliminary channel layer 1007 has compressive stress, it is applicable to p-type semiconductor devices). If another type of device is to be formed on the substrate, the two types of devices can be processed separately. For example, when processing the region of one type of device as described above in combination with Figure 12(a) and 12(b) , the region of the other type of device can be masked; after the processing is completed, the processed region can be masked while exposing the region of the other type of device that was previously masked for further processing.

[0044] For example, as shown in Figure 13(a) and 13(b) , after forming the isolation layer as shown above, instead of directly forming the gate stack on the preliminary channel layer 1007, the preliminary channel layer 1007 can be etched back by selective etching to make the preliminary channel layer 1007 recessed by a certain depth. As shown in Figure 14(a) and 14(b) , taking the remaining preliminary channel layer 1007 as a seed, a semiconductor layer 1027 can be formed on the preliminary channel layer 1007 by, for example, selective epitaxial growth. The semiconductor layer 1027 can include a semiconductor material different from that of the preliminary channel layer 1007 to generate strain or stress due to a difference in lattice constant with respect to the preliminary channel layer 1007. For example, in an example where the preliminary channel layer 1007 includes Si, the semiconductor layer 1027 can include SiGe and thus can have compressive stress. Or, in an example where the preliminary channel layer 1007 includes SiGe, the semiconductor layer 1027 can include Si and thus can have tensile stress. Additionally, in an example where the semiconductor layer 1027 includes SiGe, in order to improve the interface characteristics, a covering layer 1029 such as Si can be further formed on the semiconductor layer 1027 by, for example, selective epitaxial growth.

[0045] After that, as shown in Figure 15(a) and 15(b) , a gate stack can be formed inside the sidewall 1015. The gate stack can include a gate dielectric layer 1023' and a gate electrode layer 1025'. Regarding the gate stack, refer to the detailed description of the gate stack in combination with FIG. 1 above. The gate stacks of n-type semiconductor devices and p-type semiconductor devices can have different configurations, for example, having different equivalent work functions to optimize the performance of n-type semiconductor devices and p-type semiconductor devices respectively.

[0046] The semiconductor device according to an embodiment of the present disclosure can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such a semiconductor device, and an electronic device can be constructed therefrom. Such an electronic device may also include components such as a display screen that cooperates with the integrated circuit and a wireless transceiver that cooperates with the integrated circuit. Such electronic devices include, for example, smart phones, computers, tablet computers, wearable smart devices, artificial intelligence devices, mobile power supplies, and the like.

[0047] In the above description, technical details such as the layout and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used in combination advantageously.

[0048] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate including a base substrate and a buried oxide layer on the base substrate; a channel layer on the buried oxide layer, wherein the channel layer has stress; an isolation layer between the channel layer and the buried oxide layer; a gate stack on the channel layer; and source / drain layers on opposite sides of the channel layer.

2. The semiconductor device according to claim 1, including an n-type semiconductor device and a p-type semiconductor device, Among them, wherein a channel layer of one of the n-type semiconductor device and the p-type semiconductor device includes a semiconductor layer of a first semiconductor material, wherein a channel layer of the other of the n-type semiconductor device and the p-type semiconductor device includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer includes the first semiconductor material, and the second semiconductor layer includes a second semiconductor material different from the first semiconductor material.

3. The semiconductor device according to claim 2, wherein, The first semiconductor layer includes a portion extending on a bottom surface of the second semiconductor layer and a portion extending on a sidewall of the second semiconductor layer.

4. The semiconductor device according to claim 1, wherein, The isolation layer is self-aligned with the channel layer.

5. The semiconductor device according to claim 1, wherein, A lower surface of the isolation layer abuts the buried oxide layer, and an upper surface abuts the channel layer.

6. The semiconductor device according to claim 1, wherein, The semiconductor device is an n-type semiconductor device, and the channel layer has tensile stress.

7. The semiconductor device according to claim 6, wherein, The channel layer of the n-type semiconductor device includes Si having tensile stress, and the source / drain layers include Si.

8. The semiconductor device according to claim 1, wherein, The semiconductor device is a p-type semiconductor device, and the channel layer has compressive stress.

9. The semiconductor device according to claim 8, wherein, The channel layer of the p-type semiconductor device includes: a first Si layer on the isolation layer; a SiGe layer on the first Si layer; and a second Si layer on the SiGe layer.

10. The semiconductor device according to claim 1, wherein, The source / drain layers are disposed on the buried oxide layer and extend on sidewalls of the isolation layer.

11. A method of manufacturing a semiconductor device, comprising: sequentially disposing a sacrificial layer and a preliminary channel layer on a substrate, wherein the substrate includes a base substrate and a buried oxide layer on the base substrate, and the sacrificial layer induces stress in the preliminary channel layer; patterning the sacrificial layer and the preliminary channel layer into a fin structure extending in a first direction; forming a sacrificial gate extending in a second direction intersecting the first direction and intersecting the fin structure and forming sidewalls on sidewalls of the sacrificial gate; patterning the fin structure using the sacrificial gate and the sidewalls as a mask; forming source / drain layers on sidewalls of the patterned fin structure; removing the sacrificial gate to expose sidewalls of the sacrificial layer inside the sidewalls; removing the sacrificial layer via the exposed sidewalls of the sacrificial layer and forming an isolation layer in a space released due to the removal of the sacrificial layer; and forming a gate stack on the preliminary channel layer inside the sidewalls.

12. The method according to claim 11, wherein, Forming a gate stack on the preliminary channel layer further includes: etching back the preliminary channel layer; growing a semiconductor layer on the etched-back preliminary channel layer, wherein the preliminary channel layer induces stress in the semiconductor layer.

13. The method according to claim 12, wherein Forming a gate stack on the preliminary channel layer further includes: growing a capping layer on the semiconductor layer.

14. The method according to claim 13, wherein, The said preliminary channel layer includes Si, the semiconductor layer includes SiGe, the covering layer includes Si, and the preliminary channel layer induces compressive stress in the semiconductor layer.

15. The method according to claim 11, wherein, The said sacrificial layer includes SiGe, the preliminary channel layer includes Si, and the sacrificial layer induces tensile stress in the preliminary channel layer.

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