Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. According to the embodiment, the semiconductor device comprises a substrate, a buried oxide layer on the substrate, a channel part comprising a semiconductor layer, a source part / drain part and a gate stack. The semiconductor layer comprises a shell part and a core part which are separated from each other at an interval and are distributed in an overlapping manner in the projection direction, and the shell part and the core part are respectively subjected to one of p-type doping and n-type doping. The semiconductor layer of the channel portion is formed to include a protruding semiconductor portion such that at least a portion of an interface between the channel portion and the gate stack protrudes toward the gate stack away from a surface of the semiconductor layer.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a channel portion including a shell portion and a core portion and a method of manufacturing the same. Background Art

[0002] Fully depleted (FD) SOI semiconductor devices, especially oxide semiconductor field effect transistors (MOSFETs), can well control short channel effects and enable further miniaturization of devices. However, the process of manufacturing FDSOI MOSFETs is complex and costly, and the performance needs to be further improved. Summary of the Invention

[0003] In view of this, at least part of the object of the present disclosure is to provide a semiconductor device having a channel portion including a metal sulfide layer and a method of manufacturing the same.

[0004] According to one aspect of the present disclosure, there is provided a semiconductor device, including:

[0005] A substrate;

[0006] A buried oxide layer on the substrate;

[0007] A channel portion including a semiconductor layer stacked above the substrate, the semiconductor layer having a planar semiconductor layer surface;

[0008] Source / drain portions disposed above the buried oxide layer and connected to opposite ends of the channel portion; and

[0009] A gate stack between the source / drain portions, disposed on the channel portion;

[0010] Wherein the semiconductor layer includes a shell portion and a core portion stacked and distributed in a projection direction, the shell portion having a doping type opposite to that of the source / drain portions, and the core portion having the same doping type as the source / drain portions,

[0011] Wherein the shell portion and the core portion are parts of the semiconductor layer, respectively having opposite doping types;

[0012] Wherein the semiconductor layer of the channel portion is formed to include a protruding semiconductor portion such that at least part of an interface between the channel portion and the gate stack departs from the semiconductor layer surface and protrudes toward the gate stack.

[0013] According to one embodiment, the interface between the channel portion and the gate stack includes a planar first surface portion and an inclined second surface portion of the protruding semiconductor portion, and the second surface portion extends from the first surface portion to the semiconductor layer surface.

[0014] According to one embodiment, the second surface portion of the protruding semiconductor portion and the source / drain portion define a bottom corner of the gate stack with improved sharpness.

[0015] According to one embodiment, the included angle between the second surface portion and the source / drain portion is between 25 and 45 degrees.

[0016] According to one embodiment, the semiconductor layer is a silicon layer or a silicon-germanium layer, the first surface portion is oriented along the (100) crystal plane, and the second surface portion is oriented along the (111) crystal plane.

[0017] According to one embodiment, the doping concentration of the shell portion is greater than that of the core portion.

[0018] According to one embodiment, the shell portion is located on the core portion, or the core portion is located on the shell portion; and

[0019] The shell portion and the core portion are both distributed adjacently or spaced apart.

[0020] According to one embodiment, the shell portion and the core portion are obtained by a process of performing ion implantation on the semiconductor layer and an annealing process.

[0021] According to one embodiment, the gate stack includes gate metal.

[0022] According to one embodiment, the semiconductor device is provided as a plurality of semiconductor devices, the plurality of semiconductor devices including n-type semiconductor devices and / or p-type semiconductor devices,

[0023] wherein, the channel portion of the n-type semiconductor device includes a p-type doped shell portion and an n-type doped core portion, and / or the channel portion of the p-type semiconductor device includes an n-type doped shell portion and a p-type doped core portion.

[0024] According to one embodiment, the semiconductor device is an n-type semiconductor device,

[0025] When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core portion is balanced by the space charge of the shell portion to become fully depleted; and

[0026] When the absolute value of the gate voltage gradually becomes greater than the absolute value of the threshold voltage, the core portion first forms a charge accumulation mode to start conducting, and then a larger gate voltage value causes the shell portion to form an inversion mode to jointly participate in conduction.

[0027] According to one embodiment, the semiconductor device is a p-type semiconductor device,

[0028] When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core portion is balanced by the space charge of the shell portion to become fully depleted; and

[0029] When the gate voltage value gradually becomes greater than the absolute value of the threshold voltage, a hole accumulation mode is first formed in the core part to start conducting, and then a greater absolute value of the gate voltage causes the shell part to form an inversion mode and jointly participate in conduction.

[0030] According to one embodiment, the semiconductor device further includes a buried oxide layer, the buried oxide layer is located on the substrate, and the semiconductor layer of the channel part is stacked above the buried oxide layer.

[0031] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including:

[0032] Forming a buried oxide layer on a substrate;

[0033] Forming a semiconductor layer on the buried oxide layer;

[0034] Forming a sacrificial gate on the semiconductor layer, and forming a sacrificial gate sidewall on the sidewall of the sacrificial gate;

[0035] Forming source / drain parts on opposite sides of the sacrificial gate sidewall, and the source / drain parts overlap with the sacrificial gate in the channel extension direction;

[0036] Removing the sacrificial gate and optionally removing the sidewall of the sacrificial gate to release the space between the source / drain parts;

[0037] Etching a recess in the semiconductor layer in the space, and forming a semiconductor part protruding out of the surface of the semiconductor layer by an epitaxial method in the recess, forming a core part and a shell part overlapping and distributed in the projection direction in the semiconductor layer, wherein the doping type in the shell part is opposite to the doping type in the semiconductor layer; and

[0038] Forming a gate stack on the semiconductor layer including the semiconductor part protruding out of the surface of the semiconductor layer in the space.

[0039] According to one embodiment, at least one core part and a shell part are formed in the semiconductor layer by ion implantation.

[0040] According to one embodiment, the semiconductor part protruding out of the surface of the semiconductor layer includes a planar first surface part and an inclined second surface part, and the second surface part extends from the first surface part to the surface of the semiconductor layer.

[0041] According to one embodiment, the second surface part of the protruding semiconductor part and the source / drain part define a bottom corner of the gate stack with improved sharpness, and the inner included angle between the second surface part and the source / drain part is between 25 and 45 degrees.

[0042] According to one embodiment, the method includes, for an n-type semiconductor device, forming a p-type doped shell portion and an n-type doped core portion; and / or

[0043] For a p-type semiconductor device, forming an n-type doped shell portion and a p-type doped core portion.

[0044] According to one embodiment, the doping concentration of the shell portion is greater than that of the core portion.

[0045] According to one embodiment, in the space, by selectively etching the semiconductor layer, the surface of the etched recess is along the (100) plane, and the first surface portion of the epitaxial growth is along the (100) plane, and the second surface portion is along the (111) plane.

[0046] According to an embodiment of the present disclosure, the channel portion may include a shell portion and a core portion. Thus, by changing the absolute value of the gate voltage, the charges of the shell portion and the core portion can be changed, and they can jointly participate in conduction. Therefore, the electrical characteristics of the semiconductor device can be improved. The sharpness of the gate stack of the present invention, which has an improved bottom corner of the gate stack, can increase the driving voltage of the semiconductor device and reduce the leakage current. In addition, the method for manufacturing a semiconductor device according to an embodiment of the present disclosure can be simpler and have lower costs. Description of the Drawings

[0047] According to the following description in conjunction with the drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure can be more clearly understood. In the drawings:

[0048] Figures 1 to 9 Some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown, where Figure 9 A part of a semiconductor device having a shell portion, a corner portion, a protruding semiconductor portion, and an improved bottom corner of the gate stack with increased sharpness is schematically shown. Detailed Description

[0049] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0050] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, certain details are enlarged and certain details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0051] The present disclosure can be presented in various forms, and some examples will be described below. In the following description, the selection of various materials is involved. In addition to considering its function (for example, semiconductor materials are used to form active regions, and dielectric materials are used to form electrical isolation), the etching selectivity is also considered when selecting materials. In the following description, the required etching selectivity may or may not be indicated. Those skilled in the art should be clear that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or other layers are not shown as being etched in the figures, then this etching can be selective, and the material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0052] The FDSOI technology enables great improvement in the performance of devices. The application of field-effect transistors on FDSOI has been greatly developed. The junctionless field-effect transistors on FDSOI in the prior art exhibit excellent advantages. And the present inventor has found that devices on FDSOI including a shell part and a core part have further improved performance, exceeding the performance of devices in the prior art, and can be combined with the current process flow at the 10nm node and below. Furthermore, it is expected to carry out the integration and innovation of device structures, materials, and processes, and has great development space.

[0053] The inventors have found that the semiconductor layer of the channel portion can be prepared by an epitaxial growth technique. The semiconductor layer of the channel portion can include a shell portion and a core portion. As an example, for an n-channel field effect transistor, the shell portion in the semiconductor layer of the channel portion is limited to p-type doping, and the core portion can be an n-type doped layer; or for a p-channel field effect transistor, the shell portion in the semiconductor layer of the channel portion is limited to n-type doping, and the core portion can be a p-type doped layer, and the thickness of the shell portion is comparable to the thickness of the core portion (e.g., the same order of magnitude), but the doping concentration of the shell portion is higher than that of the core portion; the positional relationship between the shell portion and the core portion can be that the shell portion is stacked on the core portion, or the core portion is stacked on the shell portion, and the two can be adjacent or spaced apart; the core portion can be one or two. The manufacturing methods of the shell portion and the core portion have high reliability. For example, it can be achieved by an ion implantation process after forming the semiconductor layer. The FDSOI planar technology has the opportunity to achieve or exceed the performance of the same-node Fin field effect transistor and has market competitiveness.

[0054] The present inventors have also found that by forming a protruding semiconductor portion in the semiconductor layer of the channel portion in a semiconductor device, a gate stack bottom corner with improved sharpness can be obtained in the gate stack, thereby increasing the drive voltage of the semiconductor device and reducing the leakage current.

[0055] According to an embodiment of the present disclosure, a semiconductor device is provided. Specifically, the semiconductor device may include a channel portion, a gate stack disposed on the channel portion, and source / drain portions 1011 disposed on opposite sides of the gate stack. The channel portion may extend in a first direction, and opposite ends in the first direction may be connected to the source / drain portions 1011. In one implementation, there may be no gate sidewalls between the gate stack and the source / drain portions 1011.

[0056] The channel portion may include a semiconductor layer, such as Si; in one implementation, the channel portion may also include a semiconductor layer 1005 with high mobility, such as SiGe; in other implementations, a part of the semiconductor layer 1005 may be Si and another part may be SiGe. The semiconductor layer 1005 includes a shell portion 1005-1 and a core portion 1005-2. The shell portion 1005-1 is a partially doped region within the semiconductor layer 1005, and the core portion 1005-2 is a partially doped region within the semiconductor layer 1005, and the doping concentration of the shell portion is higher than that of the core portion.

[0057] The doping concentrations of the shell portion and the core portion and the arrangement between the shell portion and the core portion can be set according to the required performance. For example, in one implementation, the shell portion is on the core portion. In one implementation, the core portion is disposed above the shell portion (not shown). In one implementation, the shell portion and the core portion are substantially adjacent; in another implementation, the shell portion and the core portion are spaced apart.

[0058] The channel part having a core-shell structure or morphology is a method that can be used to adjust the Vt value and achieve multiple Vt values. The present invention can advantageously implement a scheme for fine-tuning multiple Vt values of an FDSOI device by setting the shell-core method, which is extremely beneficial for FDSOI devices because traditional / existing FDSOI devices with multiple Vt values are achieved through backside wells and biasing methods, and the existing process and circuit design of this method are extremely complex. The design of the present invention allows a transistor with a planar structure to have a shell-core structure, so as to make full use of the charge balance effect and achieve common conduction of the shell and the core when conducting. The additional doping in the shell can determine the Vt of the FDSOI transistor, that is, ΔVT = ΔQ / Cox.

[0059] In the present invention, due to the existence of the shell, the additional doping concentration of the shell can be selectively adjusted by adjusting the doping of the shell, so that fine-tuning of Vt can be achieved.

[0060] In the present invention, since the doping of the shell-core can affect the thickness of the channel layer, the thickness of the channel layer can be proportionally thinned or thickened. Under the condition of a high doping level, the mobility of carriers will be reduced, so by optimizing the doping level, the final leakage current can be optimized to the greatest extent.

[0061] In Figure 9 In the illustrated implementation, by way of example only, the semiconductor device includes source / drain parts 1011 and a channel part between the source / drain parts 1011, wherein the channel part includes a semiconductor layer 1005, and the semiconductor layer 1005 includes a shell part 1005-1 and a core part 1005-2. In other implementations, the semiconductor layer 1005 may include one shell part and two core parts. Compared with one layer of core parts, the configuration of one layer of shell part 1005-1 and two layers of core parts 1005-2 has better uniformity and greater current under the same conditions. In this implementation, a gate stack is formed between the source and drain and above the channel part. Figure 9 The dashed line in shows the shell part 1005-1 and the core part 1005-2, but actually this dashed line does not exist.

[0062] In the implementation of the present invention, the semiconductor layer 1005 of the channel part includes a shell part 1005-1 and a core part 1005-2. In a projection direction (for example, a direction perpendicular to the semiconductor layer), one layer of the shell part 1005-1 is substantially stacked on one layer of the core part 1005-2. In the horizontal direction shown in the figure, the spans of the shell part 1005-1 and the core part 1005-2 are substantially similar to the span of the channel part. However, it should be noted that the characteristics of ion implantation determine that the ion distribution morphology of the shell part 1005-1 and the core part 1005-2 is not necessarily rectangular, but generally oval, and other shapes can be achieved by changing the implantation process.

[0063] In the implementation of the present invention, the semiconductor layer of the channel portion includes a protruding semiconductor portion that protrudes from the interface between the channel portion and the gate stack away from the surface of the semiconductor layer toward the gate stack. Here, the surface of the semiconductor layer refers to the surface portion of the semiconductor surface shown in the figure excluding the surface of the protruding semiconductor portion, as Figures 7 - 9 shown.

[0064] As can be seen from Figures 6 - 9 it, the semiconductor layer is first selectively etched to form a recess, and then an epitaxial method is used in the recess to form a protruding semiconductor portion that protrudes out of the surface of the semiconductor layer. The shell portion and the core portion can be part of the semiconductor layer. Ions are doped in the portion of the semiconductor layer where the core portion is formed to obtain the core portion, and ions are doped in the portion of the semiconductor layer where the shell portion is formed to obtain the shell portion, where the doping type in the shell portion is opposite to the doping type in the semiconductor layer. The doping type of the shell portion is opposite to the type of the source / drain portion of the semiconductor device.

[0065] The semiconductor layer is selectively etched to form a recess, and the bottom surface of the recess can be a (100) plane; semiconductor, such as silicon or germanium, is epitaxially grown on the recess to form a protruding semiconductor portion. The protruding semiconductor portion has a first surface portion, such as the top surface shown in the figure, and a second surface portion. The second surface portion is inclined relative to the top surface. Since the epitaxial growth of the semiconductor grows along the slowest growth direction on one side of the edge, the first surface portion can be a (100) plane, and the second surface portion can be a (111) plane. The included angle between the two crystal planes is as Figure 9 shown by α in

[0066] As Figure 9 shown, the core portion is located in the portion of the semiconductor layer below the recess shown in the figure, and the shell portion is located in the protruding semiconductor portion above the recess.

[0067] In the present invention, it should be noted that after the epitaxial formation of the protruding semiconductor portion has grown and formed, as part of the semiconductor layer, the shell portion and the core portion can be the previously formed semiconductor layer and the subsequently epitaxially formed protruding semiconductor portion inside and outside the recess. In the implementation of the present invention, the core portion can be partially disposed in the previously formed semiconductor layer or at least partially disposed in the protruding semiconductor portion shown in the figure; in other implementations of the present invention, the shell portion can be partially located below the protruding semiconductor portion or disposed in the protruding semiconductor portion shown in the figure, depending on the performance requirements of the semiconductor device and the sizes of the recess and the protruding semiconductor layer.

[0068] As Figure 9As shown, since the semiconductor layer has a protruding semiconductor portion at this time, the subsequently formed gate is defined to have a bottom corner of the gate stack with increased sharpness. Specifically, the second surface portion of the protruding semiconductor portion along the (111) plane and both of the source / drain portions define the bottom corner of the gate stack with increased sharpness. In the implementation of the present invention, the bottom corner of the gate stack may have an internal included angle β between 25° and 45°. Ideally, the included angle α between the (100) plane and the (111) plane is about 54°, and the included angle β of the bottom corner of the gate stack is the complementary angle of the included angle between the (100) plane and the (111) plane. However, in actual formation, affected by many other factors, the plane formed during the epitaxial process is not strictly the (111) plane, and the included angle α between the formed plane and the (100) plane is not 54°, but an angle range, approximately between 40° and 70°. Moreover, there are more factors affecting the formation of the bottom corner of the gate stack, and the angle β of the bottom corner of the gate stack is within a range of 25° to 45°.

[0069] Through the process of selective etching - epitaxy, the present invention obtains a protruding semiconductor portion in the semiconductor layer of the channel portion according to the characteristics of the lattice structure of silicon and / or germanium or germanium - silicon semiconductors, and further obtains a bottom corner of the gate stack with increased sharpness, without the need for additional masks or other etching processes, simplifying the process and improving reliability and compatibility.

[0070] It is advantageous that the semiconductor device of the present invention has a bottom corner of the gate stack with increased sharpness. Specifically, when the gate turn - on voltage (positive voltage for n - type semiconductor devices and negative voltage for p - type semiconductor devices) turns on the channel, the bottom corner of the gate stack with increased sharpness can cause an increase in the electric field around it, so that there are more attracted carriers at the channel edge, and thus the drive current of the transistor is increased. When the gate turn - on voltage (negative voltage for n - type semiconductor devices and positive voltage for p - type semiconductor devices) cuts off the channel, the bottom corner of the gate stack with increased sharpness can cause an increase in the electric field around it, so that the doped depletion charges around the corner and along the channel are strengthened, and thus the leakage current of the transistor is reduced. That is to say, due to the inclusion of the bottom corner of the gate stack with increased sharpness, the on - and - off performance of the semiconductor device is greatly improved, the drive current is increased, and the leakage current is reduced.

[0071] The bottom corner of the gate stack with increased sharpness of the semiconductor device of the present invention can be formed by epitaxially growing a protruding semiconductor portion from the semiconductor layer, without the need to add additional complex processes, with high reliability and no increase in process complexity.

[0072] The method of the present invention for setting the shell-core part in the channel part in a very simple manner through the existing injection technology can advantageously implement the multi-Vt scheme of the FDSOI device. Compared with the traditional / existing methods for manufacturing FDSOI devices with multi-Vt, the process is extremely simple, without the need for additional circuit design and corresponding process settings, and the complexity is greatly reduced.

[0073] Those skilled in the art know that the energy of ion implantation can determine the depth of implanted ions, and the dose of ion implantation can determine the concentration of implanted ions. The combination of the energy and dose of ion implantation can determine the depth and amplitude of the distribution of ions in the semiconductor through calculation. Therefore, the formation of the protruding semiconductor part in the manufacturing process of the present invention and the subsequent doping process are fully compatible with the conventional planar FDSOI, and thus have strong adaptability.

[0074] Through the shell-core junctionless channel technology of the p-channel, the carrier mobility is greatly enhanced, for example, increased by 5 times, so that the silicon-germanium p-channel of the FDSOI can be formed without further or additional process simplification.

[0075] It should be noted that the technology provided by the present invention for forming the protruding semiconductor part and the shell-core part in the channel is not limited to FDSOI, but can be applied to field-effect transistors in general, such as field-effect transistors (non-FDSOI) in integrated circuits on traditional bulk silicon wafers. Of course, it has better effects in FDSOI with a buried oxide layer and a thin channel layer.

[0076] According to an embodiment, the above semiconductor device can be set as a plurality of semiconductor devices, and the plurality of semiconductor devices can include n-type semiconductor devices and p-type semiconductor devices. Among them, the shell 1005-1 in the semiconductor layer 1005 of the channel part of the n-type semiconductor device is a partially p-type doped region, and the core 1005-2 is a partially n-type doped region in the semiconductor layer 1005; the shell 1005-1 in the semiconductor layer 1005 of the channel part of the p-type semiconductor device is a partially n-type doped region, and the core 1005-2 is a partially p-type doped region in the semiconductor layer 1005. The doping concentration of the shell is higher than that of the core.

[0077] For example, in one implementation of the present invention, for example, in an n-type semiconductor device, the doping concentration of the p-type shell is higher than that of the n-type core, which makes the core completely depleted in the cut-off state. The core doping concentration can have a wide concentration range, for example, between 10 17 to 10 19 cm -3 magnitudes.

[0078] According to an embodiment, the contact resistance between the channel portion and the source / drain portion 1011 of the semiconductor device may be lower in the on state of the semiconductor device than in the off state of the semiconductor device.

[0079] According to an embodiment, the semiconductor device described above may be an n-type semiconductor device. In this case, the absolute value of the gate voltage is less than the absolute value of the threshold voltage (positive voltage), and the space charge in the core portion 1005-2 is balanced by the space charge in the shell portion 1005-1 to become fully depleted. When the absolute value of the gate voltage gradually becomes greater than the absolute value of the threshold voltage, an electron accumulation mode is first formed in the core portion 1005-2 to start conducting, and then a larger gate voltage value causes the shell portion 1005-1 to form an inversion mode and jointly participate in conduction.

[0080] According to an embodiment, the semiconductor device described above may be a p-type semiconductor device. In this case, the absolute value of the gate voltage is less than the absolute value of the threshold voltage (negative voltage), and the space charge in the core portion 1005-2 is balanced by the space charge in the shell portion 1005-1 to become fully depleted. When the absolute value of the gate voltage gradually increases and becomes greater than the absolute value of the threshold voltage, a hole accumulation mode is first formed in the core portion 1005-2 to start conducting. Then a larger gate voltage value causes the shell portion 1005-1 to form an inversion mode and jointly participate in conduction.

[0081] A method for manufacturing a transistor device according to an implementation of the present invention will be described below.

[0082] Figures 1 to 7 Some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0083] As Figure 1 shown, a buried oxide layer 1003 may be formed on a substrate 1001 (such as Si), or a finished silicon-on-insulator (SOI) substrate may be directly used. A semiconductor layer 1005 is formed on the buried oxide layer 1003. In this embodiment, the SOI substrate may be formed by, for example, an SOI preparation process such as a smart cut process. The substrate 1001 may include an elemental semiconductor material such as Si or Ge, or a compound semiconductor material such as SiGe, etc. Here, taking a silicon wafer as an example, the substrate 1001 is described. The buried oxide layer 1003 may include an oxide (such as silicon oxide). The semiconductor layer 1005 may include an elemental semiconductor material such as Si or Ge, or a compound semiconductor material such as SiGe, etc. The thickness of the semiconductor layer 1005 may be set as needed, and the semiconductor layer 1005 may be directly grown by epitaxy. It should be noted here that the upper surface of the semiconductor layer 1005 shown in the figure is a plane, and the semiconductor layer surface mentioned in this application refers to this upper surface. However, in subsequent processes, a convex semiconductor portion may be formed on a part of the planar semiconductor layer surface.

[0084] Next, asFigure 2 As shown, a sacrificial gate 1007 can be formed on the semiconductor layer 1005. Here, the channel extension direction is taken as the first direction (for example, Figure 2 the horizontal direction in the plane of the paper in [a certain figure]), and the direction intersecting (for example, perpendicular) the first direction is taken as the second direction (for example, Figure 2 the direction perpendicular to the plane of the paper in [a certain figure]). The sacrificial gate 1007 extends in the second direction. The sacrificial gate 1007 can include polysilicon. For convenience, the hard mask that may exist on the sacrificial gate 1007 is not shown. On the sidewalls of the sacrificial gate 1007, sidewalls 1009 of the sacrificial gate 1007 can be formed through a spacer formation process. For example, the sidewalls 1009 can include a nitride (such as silicon nitride). As Figure 2 shown, in the third direction ( Figure 2 the vertical direction in the plane of the paper in [a certain figure]), the portion of the upper surface of the semiconductor layer 1005 not covered by the sacrificial gate 1007 and the sidewalls 1009 is exposed.

[0085] As Figure 3 shown, using the exposed portion of the upper surface of the semiconductor layer 1005 as a seed, source / drain portions 1011 extending in the third direction can be formed, for example, by selective epitaxial growth. The source / drain portions 1011 can be formed on opposite sides of the sidewalls 1009 of the sacrificial gate 1007 and can be formed to overlap the sacrificial gate 1007 in the first direction. The source / drain portions 1011 can include various suitable semiconductor materials. For example, it is Si for an n-type field effect transistor and SiGe for a p-type field effect transistor. The source / drain portions 1011 can be doped to the desired conductivity type (n-type doping for an n-type field effect transistor and p-type doping for a p-type field effect transistor) through, for example, in-situ doping or ion implantation. Here, advantageously, the height of the source / drain portions 1011 can be less than the height of the sacrificial gate 1007.

[0086] Next, an alternative gate process can be performed.

[0087] For example, as Figure 4 shown, an interlayer dielectric layer 1013 can be formed on the semiconductor layer 1005. The interlayer dielectric layer can be an oxide layer. For example, the interlayer dielectric layer 1013 can be formed by depositing an oxide and then planarizing the deposited oxide such as by CMP. The CMP can be performed until the sacrificial gate 1007 inside the inner side of the sacrificial gate sidewalls 1009 is exposed.

[0088] As Figure 5As shown, the sacrificial gate 1007 and the sacrificial gate sidewall 1009 can be removed by selective etching to release the space 1015 between the source / drain portions 1011, forming an opening pattern that exposes the surface of the semiconductor layer 1005. Since the sacrificial gate sidewall 1009 is removed in addition to the sacrificial gate 1007, there can be no gate sidewall between the gate stack formed subsequently in the released space 1015 and the source / drain portions 1011. In another embodiment, the gate sidewall can be retained.

[0089] It should be noted here that Figure 5 For convenience, the space 1015 is shown as having a substantially uniform width in the vertical direction. However, considering the topography of the sacrificial gate sidewall 1009, the space 1015 may have a shape with a lower width greater than the upper width.

[0090] Thereafter, as Figure 6 shown, the surface of the semiconductor layer 1005 exposed by the selective etching of the opening pattern (space 1015) is etched. A trapezoidal recess is formed on the surface of the semiconductor layer 1005 exposed in the opening pattern (space 1015) as schematically shown, where the surface of the semiconductor layer 1005, such as a silicon layer, in the horizontal direction of the paper surface is the (100) plane, and the inclined surface of the semiconductor layer 1005 that forms an angle with the horizontal surface can be the (111) plane (the actually formed inclined surface may not be an ideal flat inclined surface, such as having a curvature or other irregular shapes).

[0091] Subsequently, silicon is epitaxially grown in the trapezoidal recess on the surface of the exposed semiconductor layer 1005. The epitaxial silicon fills the recess as Figure 6 shown, and a protruding semiconductor portion, such as silicon, is formed, such that the planar semiconductor layer surface has a protruding semiconductor portion. The planar semiconductor layer surface herein does not exclude having a protruding semiconductor portion.

[0092] Here, the protruding semiconductor portion protrudes relative to the planar semiconductor surface (the upper surface mentioned above) to the outside of the planar upper surface or the semiconductor surface.

[0093] As Figure 7 shown, the protruding semiconductor portion on the semiconductor layer surface has a planar (upper surface) first surface portion and an inclined second surface portion that extends from the first surface portion to the semiconductor layer surface. Figure 7 Schematically shown as the protruding semiconductor portion being trapezoidal.

[0094] In one implementation, as Figure 7The included angle between the shown first surface portion and the inclined second surface portion is the included angle between the (100) and (111) planes, which is ideally about 54 degrees. The actually formed included angle between the first surface portion and the inclined second surface portion is between 40 and 70 degrees.

[0095] According to the present invention, ions can be implanted into the semiconductor layer 1005 with the opening pattern facing, and the shell portion 1005-1 and the core portion 1005-2 can be formed through the annealing process after implantation; the process parameters of multiple ion implantation processes can be set according to the number, respective depths, and concentrations of the shell portion 1005-1 and the core portion 1005-2, so as to form ion implantation regions with different depths and concentrations in the semiconductor layer 1005, thereby providing the shell portion 1005-1 and at least one core portion 1005-2 (such as one core portion or two core portions). The distribution of the doped ions in the shell portion 1005-1 and the core portion 1005-2 formed through this process can be Figure 8 shown as Figure 8 the distribution is schematic.

[0096] The process of using ion implantation is advantageous. Through the ion implantation process, the distribution ranges of the shell portion 1005-1 and the core portion 1005-2, including the depth and the distribution amplitude, can be precisely controlled. For example, the shell portion can be adjacent to the core portion or spaced apart; the ion concentrations, that is, the doping concentrations, of the shell portion 1005-1 and the core portion 1005-2 can also be precisely controlled. The ion implantation process is a mature process in semiconductor production, so it can be realized by using the existing semiconductor process flow and has a low cost. Since the ion implantation process can penetrate multiple layers and the implantation depth can be controlled by the implantation energy, the ion implantation process can allow ions to be directly implanted on the surface of the semiconductor layer 1005 to form the shell portion 1005-1 and the core portion 1005-2 in different depth regions of the semiconductor layer 1005, or ion implantation can be performed after other dielectric layers are formed on the semiconductor layer 1005. For example, ions can be implanted through the opening in the step shown in Figure 6 before epitaxial growth, or ions can be implanted through the opening and the dielectric layer in the opening in the step shown in Figure 8 after the semiconductor part of epitaxial growth. The annealing process of the present invention can be realized through the laser nanosecond annealing process, which has a low thermal cost and is fast.

[0097] For example, for an n-type field effect transistor, n-type ions are first implanted at a predetermined energy to provide an ion distribution in the core 1005-2, and then the implantation energy is adjusted to implant p-type ions to provide an ion distribution in the shell 1005-1. In another implementation, for an n-type field effect transistor, n-type ions are first implanted at a predetermined energy to provide an ion distribution in the core 1005-2, and then the implantation energy is reduced to implant n-type ions to provide an ion distribution in a second core 1005-2, and then the implantation energy is adjusted to implant p-type ions to provide an ion distribution in the shell 1005-1. In this implementation, the ion doping concentration of the shell 1005-1 can be higher than the ion doping concentration of the core 1005-2, that is, the ion dose implanted into the shell 1005-1 is slightly higher than the ion dose implanted into the core 1005-2.

[0098] For a p-type field-effect transistor, p-type ions are first implanted at a predetermined energy to provide an ion distribution in the core 1005-2. Then, the implantation energy is adjusted to implant n-type ions to provide an ion distribution in the shell 1005-1. The dose of n-type ions implanted in the shell 1005-1 is slightly higher than the dose of p-type ions implanted in the core 1005-2.

[0099] In the present invention, when performing ion implantation, the presence of the opening pattern allows the ions to be implanted into the portion of the semiconductor layer 1005 exposed in the opening. The entire SOI substrate is covered with the interlayer dielectric layer 1013, and the ions are implanted and blocked in the interlayer dielectric layer 1013. Therefore, there is no need to provide a separate hard mask and alignment process to perform the ion implantation process, thereby simplifying the manufacturing process and ensuring accurate implantation.

[0100] Afterwards, if Figure 9 As shown, a gate stack may be formed in the space 1015, for example, by deposition. The gate stack may include metal.

[0101] Due to the protruding semiconductor portion, the deposited gate stack forms a sharper bottom corner under the influence of the protruding semiconductor portion. Because the sidewalls of the space between the source / drain may not be ideal and vertical, the internal angle between the second surface portion and the source / drain is between 25 and 45 degrees. However, compared to a case without the protruding semiconductor portion, the bottom corner of the gate stack becomes sharper. Figure 9 This angle is schematically shown as β in FIG.

[0102] For the n-type field effect transistor and the p-type field effect transistor, the corresponding shell portions 1005-1 and core portions 1005-2 can be formed respectively as described above, and the n-type and p-type work function layers can be formed respectively. In one implementation, the threshold voltage of the n-type field effect transistor and the threshold voltage of the p-type field effect transistor can be set to be substantially symmetric. In this case, the manufacturing process of the semiconductor device can be simplified and the manufacturing cost can be reduced.

[0103] The semiconductor device according to an embodiment of the present disclosure can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such a semiconductor device, and an electronic device can be constructed therefrom. Such an electronic device may also include components such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit. Such electronic devices include, for example, smart phones, computers, tablet computers, wearable smart devices, artificial intelligence devices, mobile power supplies, etc.

[0104] In the above description, technical details such as the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0105] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate; a buried oxide layer on the substrate; a channel portion including a semiconductor layer stacked above the substrate, the semiconductor layer having a planar semiconductor layer surface; source / drain portions disposed above the buried oxide layer and connected to opposite ends of the channel portion; and a gate stack between the source / drain portions, disposed on the channel portion; wherein the semiconductor layer includes a shell portion and a core portion stacked and distributed in a projection direction, the shell portion having a doping type opposite to that of the source / drain portions, and the core portion having the same doping type as the source / drain portions, wherein the shell portion and the core portion are parts of the semiconductor layer, respectively having opposite doping types; wherein the semiconductor layer of the channel portion is formed to include a protruding semiconductor portion such that at least a part of the interface between the channel portion and the gate stack protrudes away from the semiconductor layer surface toward the gate stack.

2. The semiconductor device according to claim 1, wherein the interface between the channel portion and the gate stack includes a planar first surface portion of the protruding semiconductor portion and an inclined second surface portion, and the second surface portion extends from the first surface portion to the semiconductor layer surface.

3. The semiconductor device according to claim 2, wherein the second surface portion of the protruding semiconductor portion and the source / drain portions define a gate stack bottom corner with an improved sharpness of the gate stack.

4. The semiconductor device according to claim 3, wherein the inner included angle between the second surface portion and the source / drain portions is between 25 and 45 degrees.

5. The semiconductor device according to claim 1, wherein the semiconductor layer is a silicon layer or a silicon-germanium layer, the first surface portion is oriented along the (100) crystal plane, and the second surface portion is oriented along the (111) crystal plane.

6. The semiconductor device according to claim 1, wherein the doping concentration of the shell portion is greater than that of the core portion.

7. The semiconductor device according to claim 1, wherein the shell portion is located on the core portion, or the core portion is located on the shell portion; and both the shell portion and the core portion are closely distributed or spaced apart.

8. The semiconductor device according to claim 1, wherein the shell portion and the core portion are obtained by a process of performing ion implantation on the semiconductor layer and an annealing process.

9. The semiconductor device according to claim 1, wherein the gate stack includes a gate metal.

10. The semiconductor device according to claim 1, wherein, The semiconductor device is provided as a plurality of semiconductor devices, the plurality of semiconductor devices including n-type semiconductor devices and / or p-type semiconductor devices, wherein the channel portion of the n-type semiconductor device includes a p-type doped shell portion and an n-type doped core portion, and / or the channel portion of the p-type semiconductor device includes an n-type doped shell portion and a p-type doped core portion.

11. The semiconductor device according to claim 10, wherein the semiconductor device is an n-type semiconductor device, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core portion is balanced by the space charge of the shell portion to become fully depleted; and When the absolute value of the gate voltage gradually becomes greater than the absolute value of the threshold voltage, a charge accumulation mode is first formed in the core to start conduction, and then a larger gate voltage value causes an inversion mode to be formed in the shell to jointly participate in conduction.

12. The semiconductor device according to claim 10, wherein the semiconductor device is a p-type semiconductor device, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell to become fully depleted; and when the gate voltage value gradually becomes greater than the absolute value of the threshold voltage, a hole accumulation mode is first formed in the core to start conduction, and then a larger absolute value of the gate voltage causes an inversion mode to be formed in the shell to jointly participate in conduction.

13. The semiconductor device according to claim 1, further comprising a buried oxide layer, the buried oxide layer being located on the substrate, and the semiconductor layer of the channel portion being stacked above the buried oxide layer.

14. A method of manufacturing a semiconductor device, comprising: forming a buried oxide layer on a substrate; forming a semiconductor layer on the buried oxide layer; forming a sacrificial gate on the semiconductor layer, and forming sacrificial gate sidewalls on sidewalls of the sacrificial gate; forming source / drain portions on opposite sides of the sacrificial gate sidewalls, the source / drain portions overlapping with the sacrificial gate in a channel extension direction; removing the sacrificial gate and optionally removing sidewalls of the sacrificial gate to release a space between the source / drain portions; etching a recess in the semiconductor layer in the space, and forming a semiconductor portion protruding out of the surface of the semiconductor layer by an epitaxial method in the recess, forming a core and a shell overlapping in a projection direction in the semiconductor layer, wherein a doping type in the shell is opposite to a doping type in the semiconductor layer; and forming a gate stack on the semiconductor layer including the semiconductor portion protruding out of the surface of the semiconductor layer in the space.

15. The method according to claim 14, wherein, forming at least one core and shell in the semiconductor layer by ion implantation.

16. The method according to claim 14, wherein, The semiconductor portion protruding out of the surface of the semiconductor layer includes a planar first surface portion and an inclined second surface portion, the second surface portion extending from the first surface portion to the surface of the semiconductor layer.

17. The method according to claim 16, wherein, The second surface portion of the protruding semiconductor portion and the source / drain portion define a gate stack bottom corner with improved sharpness of the gate stack, wherein an included angle between the second surface portion and the source / drain portion is between 25 and 45 degrees.

18. The method according to claim 14, comprising: For an n-type semiconductor device, forming a p-type doped shell and an n-type doped core; and / or For a p-type semiconductor device, forming an n-type doped shell and a p-type doped core.

19. The method according to claim 18, wherein a doping concentration of the shell is greater than a doping concentration of the core.

20. The method according to claim 14, wherein in the space, the semiconductor layer is selectively etched such that a surface of the etched recess is along a (100) plane, and a first surface portion of the epitaxial growth is along a (100) plane and a second surface portion is along a (111) plane.

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