Thin film transistor, pixel array substrate, display device and manufacturing method thereof

Abstract

The invention relates to a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. The manufacturing method of the thin film transistor comprises the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor film on the insulating layer; carrying out ion implantation on the amorphous semiconductor thin film so as to implant 3A group ions into the amorphous semiconductor thin film; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing interface removal processing on the first semiconductor material layer; forming a second semiconductor material layer and a third semiconductor material layer on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching treatment to divide the second metal layer into a source electrode and a drain electrode.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. Background Art

[0002] A thin film transistor (TFT) is a device used as a switching element to control the operation of pixels in a general display screen. The thin film transistor can be generally classified into two types, namely an amorphous silicon (a-Si) thin film transistor and a polycrystalline silicon (poly-Si) thin film transistor, according to the material composition of its active layer.

[0003] The amorphous silicon thin film transistor has the advantages of low cost and relatively simple manufacturing process, and thus becomes the mainstream design for large-size panels. In addition, compared with polycrystalline silicon, amorphous silicon can be manufactured at a lower temperature, making it more suitable for some portable devices. However, the current amorphous silicon thin film transistor has a low carrier mobility, usually only 0.2 - 0.5 cm 2 / V×S, and such device characteristics will lead to limitations in product applications. Summary of the Invention

[0004] The purpose of the present invention is to provide a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof to solve the above problems.

[0005] The present invention provides a thin film transistor, including a gate, an insulating layer, an active layer, a source electrode and a drain electrode. The insulating layer is formed on the gate. The active layer is formed on the insulating layer. The source electrode is formed on one of the two end portions of the active layer. The drain electrode is formed on the other of the two end portions of the active layer. The active layer includes a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer which are sequentially stacked. The first semiconductor material layer is formed on the insulating layer and has an ordered lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure and is doped with N-type ions. There is substantially no semiconductor oxide at the interface between the first semiconductor material layer and the second semiconductor material layer.

[0006] The present invention provides a thin film transistor, which includes a gate electrode, an insulating layer, an active layer, a source electrode, and a drain electrode. The insulating layer is formed on the gate electrode. The active layer is formed on the insulating layer. The source electrode is formed on one of the two end portions of the active layer. The drain electrode is formed on the other of the two end portions of the active layer. The active layer includes a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer that are sequentially stacked. The first semiconductor material layer is formed on the insulating layer and has an orderly arranged lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disorderly arranged lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disorderly arranged lattice structure and is doped with N-type ions. The first semiconductor material layer is doped with group 3A ions.

[0007] The present invention provides a method for manufacturing a thin film transistor, which includes the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor thin film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing an interface cleaning process on the first semiconductor material layer to remove the native semiconductor oxide on the surface of the first semiconductor material layer; forming a second and a third semiconductor material layer on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing an etching process to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source electrode and a drain electrode.

[0008] In some embodiments of the present invention, the manufacturing method further includes the following step: before performing the heat treatment, performing ion implantation on the amorphous semiconductor thin film to implant group 3A ions into the amorphous semiconductor thin film.

[0009] The present invention provides a pixel array substrate, which includes a thin film transistor manufactured by the method for manufacturing a thin film transistor as described above.

[0010] The present invention provides a display device, which includes the pixel array substrate as described above.

[0011] The present invention provides a method for manufacturing a thin film transistor, comprising the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor thin film on the insulating layer; performing ion implantation on the amorphous semiconductor thin film to implant group 3A ions into the amorphous semiconductor thin film; performing heat treatment on the amorphous semiconductor thin film implanted with the group 3A ions to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching treatment to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source electrode and a drain electrode.

[0012] Through the technical solution of the present invention, the thin film transistor, pixel array substrate, display device and their manufacturing methods provided by the embodiments of the present invention can, through specific interface cleaning treatment in the manufacturing process of the thin film transistor, make there be substantially no semiconductor oxides that are likely to cause bonding defects between the microcrystalline or polycrystalline silicon layer and the amorphous silicon layer in the active layer, so that the thin film layers in the active layer can be well bonded without the problem of film layer peeling, and the device characteristics such as the carrier mobility and on-off ratio of the thin film transistor can be effectively improved. In addition, the embodiments of the present invention also propose to improve the threshold voltage of the thin film transistor by performing ion implantation on the active layer before the heat treatment step, so that the finished product can have better device characteristics. Description of the Drawings

[0013] Figure 1A and Figure 1B is a schematic diagram of a display device according to an embodiment of the present invention;

[0014] Figure 2 is a schematic cross-sectional structure diagram of a thin film transistor according to an embodiment of the present invention;

[0015] Figures 3A to 3C is a flowchart of the steps of a method for manufacturing a thin film transistor according to different embodiments of the present invention;

[0016] Figures 4A to 4F is Figure 3A a flowchart of a method for manufacturing a thin film transistor;

[0017] Figures 5A to 5F is Figure 3B a flowchart of a method for manufacturing a thin film transistor;

[0018] Figure 6 is a SEM photo of a thin film transistor manufactured by the manufacturing method of the embodiment of the present invention and a comparative example;

[0019] Figure 7Schematic diagrams of the on-state current of the thin-film transistors manufactured by the manufacturing method of the embodiments of the present invention and the comparative example; and

[0020] Figure 8 Schematic diagram of the current-voltage characteristic curves of the thin-film transistors manufactured by the manufacturing method of the embodiments of the present invention at different ion implantation concentrations. Detailed implementation manners

[0021] To make the above objects, features, and advantages of the technical solution more obvious and understandable, the following will describe in detail the specific embodiments of the proposed technical solution with reference to the accompanying drawings. The descriptions of the embodiments of the technical solution of the present invention below are only for illustration and are not intended to represent all embodiments of the present invention or limit the present invention to specific embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0022] It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right", "upper", "lower" and similar expressions used herein are only for indicating the relative positional relationship based on the drawings and do not limit the elements using the said terms to be implemented only in the indicated manner. When the absolute position of the described object changes, the relative position description may also change accordingly.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the description of the present invention herein are only for the purpose of describing specific implementation manners and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0024] Figure 1A and Figure 1B Schematic diagram of a display device according to an embodiment of the present invention, where Figure 1A is a top view configuration schematic diagram of the display device 100, and Figure 1B is a side view configuration schematic diagram of the display device 100. For ease of explanation, Figure 1A is represented in a manner that the internal components of the display device 100 are unfolded in the x-y plane, Figure 1B while presenting the configuration state of the internal components of the display device 100 in the housing.

[0025] Please refer to in conjunction with Figure 1A andFigure 1B The display device 100 can be any electronic device with a display function, such as a television, a screen, a laptop, or a mobile phone. It may include a display panel 110, a scan driving circuit 120, a data driving circuit 130, a connection module 140, and a control circuit 150. In this embodiment, the display panel 110 has a display area DR and a non-display area SR. The display area DR is the area for displaying images; while the non-display area SR is the area where the display panel 110 does not display images. The non-display area SR usually surrounds the display area DR and can also be regarded as the border area of the display device 100. The scan driving circuit 120 and the data driving circuit 130 are disposed in the non-display area SR of the display panel 110. In the illustration, the scan driving circuit 120 is taken as an example of being disposed in the non-display areas SR on the left and right sides of the display panel 110, and the data driving circuit 130 is taken as an example of being disposed in the non-display area SR at the lower side of the display panel 110, but the present invention is not limited thereto. One end of the connection module 140 is disposed on the side of the non-display area SR close to the data driving circuit 130, and the control circuit 150 is coupled to the other end of the connection module 140.

[0026] From the perspective of the electrical relationship between components, the scan driving circuit 120 is electrically connected to the display panel 110 through traces on the substrate 112. The data driving circuit 130 is electrically connected to the display panel 110 through a first transmission portion WR1 and is electrically connected to the flexible circuit board 140 through a second transmission portion WR2. On the other hand, the control circuit 150 is electrically connected to the data driving circuit 130 through the connection module 140 and the second transmission portion WR2. Among them, the first transmission portion WR1 and the second transmission portion WR2 can be transmission lines formed on the substrate 112.

[0027] Specifically, the display panel 110 may include a substrate 112 and a pixel array 114 located in the display area DR. The pixel array 114 is disposed on the substrate 112 and is arranged in an m×n array, that is, m columns (rows) and n rows (columns), where m and n can be natural numbers selected according to design requirements, and the present invention does not limit this. The pixels in the same column of the pixel array 114 correspond to the same scan line, and the pixels in the same row correspond to the same data line of the pixel array 114. In this embodiment, the pixel array 114 can be electrically connected to the scan driving circuit 120 through the scan line to receive the scan signal, and is electrically connected to the data driving circuit 130 through the data line and the first transmission unit WR1 to receive the data driving signal provided by the data driving circuit 130. The data driving circuit 130 provides the data driving signal in coordination with the turn-on timing of the pixel array 114, so that the pixel array 114 adjusts the passing light according to the data driving signal to present a corresponding image in the display area DR. In this embodiment, the display panel 110 can be various types of display panels, such as LCD, LED, OLED, mini-LED, or micro-LED, etc., and the present invention is not limited thereto.

[0028] The scan driving circuit 120 is used to generate a scan signal for sequentially turning on / enabling the pixels row by row according to the timing control signal. In this embodiment, the scan driving circuit 120 is illustrated as an example of two configurations respectively for enabling odd-row pixels and even-row pixels. Among them, the scan driving circuit 120 on the left is exemplified by including scan units 121_1, 121_3,..., 121_m-1 respectively connected to odd-numbered scan lines, and the scan driving circuit 120 on the right is exemplified by including scan units 121_2, 121_4, 121_m respectively connected to even-numbered scan lines, but the present invention is not limited thereto. In this embodiment, the scan unit 121_x represents any one of the left scan units 121_1, 121_3,..., 121_m-1, and the scan unit 121_y represents any one of the right scan units 121_2, 121_4, 121_m. In other words, x can be any odd number less than m, and y can be any even number less than or equal to m, where m is an even number, but the present invention is not limited thereto.

[0029] The data driving circuit 130 is used to generate a driving signal for driving the pixel array 114 according to the data control signal. Although the drawings of this embodiment illustrate a single data driving circuit 130 for illustration, the present invention is not limited thereto. In some embodiments, the data driving circuit 130 can be integrated into multiple driving chips, and the multiple driving chips can cooperate to drive the pixels in different parts / regions of the pixel array 114.

[0030] The connection module 140 is used to provide a signal transmission path between the data driving circuit 130 and the control circuit 150, so that the data control signal generated by the control circuit 150 can be transmitted to the data driving circuit 130 through the connection module 140 and the second transmission part WR2.

[0031] In the pixel array 114 of the display panel 110, there are a plurality of thin film transistors. The plurality of thin film transistors are turned on or off in response to the received signals, and are used to control the operation of corresponding pixels, so as to achieve the effect of adjusting the passing light according to the data driving signal and presenting a corresponding image in the display area DR.

[0032] In some embodiments, the structural configuration of the thin film transistor may be as Figure 2 shown, where Figure 2 is a schematic cross-sectional structure diagram of a thin film transistor according to an embodiment of the present invention. Please refer to Figure 2 , the thin film transistor 200 includes a gate 210, an insulating layer 220, an active layer 230, a source electrode 240S and a drain electrode 240D. The gate 210, the insulating layer 220 and the active layer 230 are stacked in sequence from bottom to top (based on the illustrated direction). Source electrode 240S and drain electrode 240D are respectively formed at both ends of the active layer 230, and the middle region of the active layer 230 is etched to form a channel region CHA.

[0033] The gate 210, the source electrode 240S and the drain electrode 240D may be composed of metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), copper (Cu), etc. or a stacked combination of the above metals, but the present invention is not limited thereto. The insulating layer 220 may be a non-metallic dielectric material, such as silicon dioxide (SiOx), silicon nitride (SiNx), or a stacked combination of the above materials, but the present invention is also not limited thereto.

[0034] The active layer 230 of this embodiment has a three-layer stacked structure at both ends, which includes a first semiconductor material layer 231, a second semiconductor material layer 232, and a third semiconductor material layer stacked in sequence from bottom to top. The first semiconductor material layer 231 is formed on the insulating layer 220 and has an orderly arranged lattice structure, such as microcrystalline silicon or polycrystalline silicon. The second semiconductor material layer 232 is formed on the first semiconductor material layer 231 and has a disorderly arranged lattice structure, such as amorphous silicon (a-Si). The third semiconductor material layer 233 is formed on both sides of the second semiconductor material layer 232, where the third semiconductor material layer 233 has a disorderly arranged lattice structure and is doped with N-type ions. In other words, at both ends of the active layer 230, the second semiconductor material layer 232 and the third semiconductor material layer 233 can both be made of amorphous silicon, and the difference is that the N-type ion concentration of the third semiconductor material layer 233 is higher than that of the second semiconductor material layer 232.

[0035] On the other hand, the thickness of the active layer 230 in the channel region CHA is less than the thickness outside the channel region CHA (i.e., both ends), and the third semiconductor material layer 233 is removed by etching the active layer 230 in the channel region CHA, and the second semiconductor material layer 232 is exposed. In other words, there will only be a two-layer structure of the first semiconductor material layer 231 and the second semiconductor material layer 232 in the channel region CHA.

[0036] The thin-film transistor 200 having the active layer 230 composed of the above-mentioned first to third semiconductor material layers 231-233 has a higher carrier mobility compared to a conventional amorphous silicon thin-film transistor. Under the structure of this embodiment, the carrier mobility can be increased to 6-8 cm 2 / V×SM, which is more than 10 times that of a conventional amorphous silicon thin-film transistor.

[0037] In addition, in this embodiment, most of the native semiconductor oxide (such as SiOx) between the first semiconductor material layer 231 and the second semiconductor material layer 232 is removed so that there is substantially no semiconductor oxide at the interface between the first semiconductor material layer 231 and the second semiconductor material layer 232. Therefore, the first semiconductor material layer 231 and the second semiconductor material layer 232 can be basically well joined without the problem of film peeling, and the device characteristics such as the carrier mobility and on-off ratio of the thin-film transistor 200 can be effectively improved.

[0038] It should be noted here that although the carrier mobility of the thin film transistor 200 is significantly improved compared to traditional amorphous silicon thin film transistors, the critical voltage may be relatively low. In some embodiments, in order to further optimize the electrical properties of the thin film transistor 200, the first semiconductor material layer 231 may also be doped with group 3A (ⅢA) ions (i.e., the boron group) by ion implantation during the manufacturing process. The doped group 3A ions form covalent bonds with the semiconductor material in the first semiconductor material layer 231 and then provide holes, so that the current-voltage characteristic curve of the thin film transistor moves to the right, thereby increasing the critical voltage and effectively improving the problem of low critical voltage.

[0039] In some embodiments, the ion concentration of the group 3A ions implanted into the first semiconductor material layer 231 may be between 10 12 ~10 13 ions / cm 3 However, the present invention is not limited thereto. In the embodiment of implanting boron ions, the ion concentration may be, for example, 2×10 12 、4×10 12 or 6×10 12 , and the implantation energy is, for example, 10 - 20 keV, and the chamber is, for example, at room temperature. However, the present invention is equally not limited thereto.

[0040] The source electrode 240S and the drain electrode 240D are respectively formed at both ends of the active layer 230, and extend from the side surface of the active layer 230 to cover a part of the insulating layer 220. More specifically, the source electrode 240S and the drain electrode 240D respectively contact the top of the third semiconductor material layer 233 (i.e., the side away from the second semiconductor material layer 232) and the side walls of the first semiconductor material layer 231, the second semiconductor material layer 232, and the third semiconductor material layer 233 (i.e., the side of the active layer 230 away from the channel region CHA), and extend through the side walls to contact the top of the insulating layer 220 (i.e., the side away from the gate 210).

[0041] In some embodiments, the thin film transistor 200 may further include a functional layer 250 covering the surface of the device, and the functional layer 250 may be formed, for example, on some or all of the exposed surfaces of the source electrode 240S, the drain electrode 240D, and the active layer 230. In some embodiments, the functional layer 250 may be, for example, a protective film implemented with silicon nitride (SiN), etc., but the present invention is not limited thereto. Figure 3A It is a flowchart of the steps of the manufacturing method of a thin film transistor according to an embodiment of the present invention, where Figure 3A the manufacturing method can be used to manufacture the thin film transistor 200 as described in Figure 2 the embodiment. The following is combined with Figures 4A to 4F to illustrate the manufacturing process of the thin film transistor 200, whereFigures 4A to 4F is a schematic flow chart of a method for manufacturing a thin film transistor in accordance with Figure 3A .

[0042] Please refer to Figure 3A and Figure 4A . First, a first metal layer 210 is formed on a substrate SUB, and an insulating layer 220 covering the first metal layer 210 is formed (step S110), wherein the first metal layer 210 is used as a gate of the thin film transistor 200.

[0043] Next, please refer to Figure 3A , Figure 4B and Figure 4C . An amorphous semiconductor thin film 231p is formed on the insulating layer 220 (step S120), and the amorphous semiconductor thin film 231p is heat-treated to convert the amorphous semiconductor thin film 231p into a first semiconductor material layer 231 having an orderly arranged lattice structure (step S130).

[0044] In some embodiments, the amorphous semiconductor thin film 231p is, for example, amorphous silicon. The heat treatment may be, for example, an Excimer Laser Annealing (ELA) technique of irradiating amorphous silicon with an excimer laser to implement a manufacturing process of converting amorphous silicon into microcrystalline silicon or polycrystalline silicon (i.e., the first semiconductor material layer 231) having an orderly arranged lattice structure, but the present invention is not limited thereto.

[0045] After the amorphous semiconductor thin film 231p is converted into the first semiconductor material layer 231, in this embodiment, an interface cleaning process is further performed on the first semiconductor material layer 231 to remove a native semiconductor oxide SO on the surface of the first semiconductor material layer 231 (step S140).

[0046] In some embodiments, the interface cleaning process may be implemented by surface treatment manufacturing processes such as wet etching (e.g., chemical agent treatment), dry etching (e.g., plasma treatment), etc. In the interface cleaning process using wet etching, it can be implemented by using a chemical liquid corrosive to the semiconductor oxide SO, for example, a diluted Buffered Oxide Etch (BOE), a diluted hydrofluoric acid (HF), or a chemical liquid mixing hydrofluoric acid and ammonium fluoride (NH4F), but the present invention is not limited thereto.

[0047] In an embodiment of performing the interface cleaning process using a corrosive chemical liquid, the chemical liquid may be diluted to an etching rate of 5 to / sec, and the interface cleaning process is maintained for 5 to 30 seconds to avoid corrosion of the insulating layer 220 and / or the first semiconductor material layer 231 when removing the semiconductor oxide SO. In some embodiments, if the chemical solution is HF or BOE, the dilution concentration can be, for example, 1% to 2%, but the present invention is not limited thereto.

[0048] Please continue to refer to Figure 3A and Figure 4D , after the interface cleaning process is completed, a second semiconductor material layer 232 and a third semiconductor material layer 233 are formed on the first semiconductor material layer 231 (step S150), where the first to third semiconductor material layers 231 to 233 stacked in sequence from bottom to top form the active layer 230 of the thin film transistor 200. In this embodiment, the second semiconductor material layer 232 is composed of, for example, amorphous silicon, and the third semiconductor material layer 233 is composed of, for example, n-doped amorphous silicon, but the present invention is not limited thereto.

[0049] In some embodiments, in order to ensure that the semiconductor oxide SO removed in step S140 will not be formed again during the manufacturing process, the execution time interval between step S140 and step S150 needs to be set to less than 1 hour. That is, the steps of forming the second and third semiconductor material layers 232 to 233 need to be performed within one hour after the interface cleaning process is completed.

[0050] Please continue to refer to Figure 3A and Figure 4E , after the active layer 230 is formed, the active layer 230 can be patterned, and a second metal layer 240 is formed on the patterned active layer 230 (step S160).

[0051] Please continue to refer to Figure 3A and Figure 4F , after the second metal layer 240 is formed, the device is etched to expose the second semiconductor material layer 232 in the channel region CHA, and the second metal layer 240 is separated into left and right parts by the channel region CHA (step S170), where the left second metal layer 240 serves as the source electrode 240S of the thin film transistor 200, and the right second metal layer 240 serves as the drain electrode 240D of the thin film transistor 200.

[0052] In some embodiments, after step S170, a functional layer 250 covering the surfaces of the source electrode 240S, the drain electrode 240D, and the channel region CHA can be further formed on the device according to the design or device requirements.

[0053] Figure 3B is a flowchart of the steps of a manufacturing method of a thin film transistor according to another embodiment of the present invention, where Figure 3BThe manufacturing method can be used to manufacture a thin film transistor 200 as described in Figure 2 the embodiment. The following is combined with Figures 5A to 5F to illustrate the manufacturing process of the thin film transistor 200, where Figures 5A to 5F is a schematic flow chart of the manufacturing method of the thin film transistor according to Figure 3B .

[0054] Please refer to Figure 3B and Figure 5A . First, a first metal layer 210 is formed on a substrate SUB, and an insulating layer 220 covering the first metal layer 210 is formed (step S110), where the first metal layer 210 is used as the gate of the thin film transistor 200.

[0055] Please refer to Figure 3B and Figure 5B . An amorphous semiconductor thin film 231p is formed on the insulating layer 220 (step S220), and ion implantation is performed on the amorphous semiconductor thin film 231p (step S230) to implant group 3A ions into the amorphous semiconductor thin film 231p.

[0056] Next, please refer to Figure 3B and Figure 5C . The amorphous semiconductor thin film 231p implanted with group 3A ions is heat-treated to convert the amorphous semiconductor thin film 231p into a first semiconductor material layer 231 (step S240).

[0057] In other words, before the heat treatment in the manufacturing method of this embodiment, the main difference from the foregoing Figure 3A embodiment is that in this embodiment, through step S230 of ion implantation of the amorphous semiconductor thin film, group 3A ions are doped into the amorphous semiconductor thin film 231p.

[0058] In some embodiments, the amorphous semiconductor thin film 231p is, for example, amorphous silicon, and the ions implanted into the amorphous semiconductor thin film 231p can be, for example, boron ions (B+). The heat treatment can be, for example, an excimer laser annealing (ELA) technique of irradiating the boron ion-doped amorphous silicon with an excimer laser to realize the manufacturing process of converting the amorphous silicon into microcrystalline silicon or polycrystalline silicon with an orderly arranged lattice structure (i.e., the first semiconductor material layer 231), but the present invention is not limited thereto.

[0059] Please then refer to Figure 3B and Figure 5D, after the heat treatment is completed, a second semiconductor material layer 232 and a third semiconductor material layer 233 are formed on the first semiconductor material layer 231 (step S250), wherein the first to third semiconductor material layers 231 to 233 stacked in sequence from bottom to top constitute the active layer 230 of the thin film transistor 200. In this embodiment, the second semiconductor material layer 232 is made of amorphous silicon, for example, and the third semiconductor material layer 233 is made of n-doped amorphous silicon, for example, but the present invention is not limited thereto.

[0060] Please then refer to Figure 3B and Figure 5E , after the active layer 230 is formed, the active layer 230 can be patterned, and a second metal layer 240 is formed on the patterned active layer 230 (step S260).

[0061] Please then refer to Figure 3B and Figure 5F , after the second metal layer 240 is formed, the device is etched to expose the second semiconductor material layer 232 in the channel region CHA, and the second metal layer 240 is separated into left and right parts by the channel region CHA (step S270), wherein the left second metal layer 240 serves as the source electrode 240S of the thin film transistor 200, and the right second metal layer 240 serves as the drain electrode 240D of the thin film transistor 200.

[0062] In some embodiments, after step S270, a functional layer 250 covering the surfaces of the source electrode 240S, the drain electrode 240D, and the channel region CHA can be further formed on the device according to design or device requirements.

[0063] Compared with the traditional thin film transistor manufacturing process, the purpose of step S230 in this embodiment is to adjust the threshold voltage value, rather than to configure the source / drain region, so the ion concentration injected / doped does not need to be too high, and subsequent rapid thermal annealing (RTA) manufacturing process for the first semiconductor layer 231 is not required to activate the ions again, effectively simplifying the complexity of the manufacturing process.

[0064] Figure 3C is a flowchart of the steps of a manufacturing method of a thin film transistor according to another embodiment of the present invention, wherein Figure 3C the manufacturing method can be used to manufacture the thin film transistor 200 as described in Figure 2 the embodiment.

[0065] Please refer to Figure 3C , this embodiment is substantially the same as the foregoing Figure 3A and / or Figure 3B embodiments, and it is the same as Figure 3AThe difference in this embodiment is that before the heat treatment step S340, an ion implantation operation as described in step S230 of Figure 3B is performed, so that the first semiconductor material layer is doped with group 3A ions. From another perspective, the difference between this embodiment and Figure 3B the embodiment is that after the heat treatment step S340, an interface cleaning process as described in step S140 of Figure 3A is performed, so that the native semiconductor oxide on the first semiconductor material layer is removed.

[0066] In addition, the relevant description of step S310 in this embodiment can refer to step S110 of the foregoing Figure 3A and step S210 of Figure 3B . The relevant description of step S320 in this embodiment can refer to step S120 of the foregoing Figure 3A and step S220 of Figure 3B . The relevant description of step S330 in this embodiment can refer to step S230 of the foregoing Figure 3B . The relevant description of step S340 in this embodiment can refer to step S130 of the foregoing Figure 3A and step S240 of Figure 3B . The relevant description of step S350 in this embodiment can refer to step S140 of the foregoing Figure 3A . The relevant description of steps S360 - S380 in this embodiment can refer to steps S150 - S170 of the foregoing Figure 3A and steps S250 - S270 of Figure 3B , so the repeated parts will not be elaborated here.

[0067] More specifically, compared with the manufacturing method flow of the foregoing Figure 3A and Figure 3B , in addition to performing the ion implantation manufacturing process (step S330) to improve the threshold voltage characteristics, after the amorphous semiconductor thin film (231p) doped with group 3A ions is converted into the first semiconductor material layer (231) in polycrystalline or microcrystalline state, an interface cleaning process (step S350) is further performed on it to improve the bonding strength between the first semiconductor material layer and the second semiconductor material layer, making the overall device characteristics of the thin film transistor better. Figure 6 SEM photos of the thin film transistor manufactured by the manufacturing method according to the embodiment of the present invention and the comparative example are shown. Please refer to Figure 6 . It can be seen from the experimental comparison result photos that for the thin film transistor manufactured by the above Figure 3A manufacturing method, there is no film layer peeling between the first semiconductor material layer and the second semiconductor material layer compared with the comparative example.

[0068] Figure 7 Schematic diagrams of the on-currents of thin-film transistors manufactured by the manufacturing method according to an embodiment of the present invention and a comparative example. Please refer to Figure 7 , it can be seen from the experimental result data in the figure that through Figure 3A the step process, the switching ratio of the manufactured thin-film transistor is significantly higher than that of the comparative example without the interface cleaning process (step S140).

[0069] In addition, in some experimental examples, through Figure 3A the step process, the carrier mobility of the manufactured thin-film transistor can reach 11.12 cm 2 / V×S. In contrast, in the comparative example without the interface cleaning process (step S140), its carrier mobility may be affected by defects and only about 1.29 cm 2 / V×S.

[0070] Figure 8 Current-voltage characteristic curves of thin-film transistors manufactured by the manufacturing method according to an embodiment of the present invention at different ion implantation concentrations. From Figure 8 the characteristic curves, it can be seen that as the concentration of Group 3A ions implanted in step S230 / S330 of the above manufacturing method increases, the threshold voltage of the thin-film transistor also increases. In summary, the thin-film transistor, pixel array substrate, display device, and manufacturing method thereof proposed in the embodiments of the present invention can, through a specific interface cleaning process in the manufacturing process of the thin-film transistor, make there be substantially no semiconductor oxides that are likely to cause bonding defects between the microcrystals or polysilicon layer (such as the first semiconductor material layer) and the amorphous silicon layer (such as the second semiconductor material layer) in the active layer, so that the thin films in the active layer can be well bonded without the problem of film peeling, and the carrier mobility and switching ratio and other device characteristics of the thin-film transistor 200 can be effectively improved. In addition, the embodiments of the present invention also propose to increase the threshold voltage of the thin-film transistor by ion implanting the active layer before the heat treatment step, so that the finished product can have better device characteristics.

[0071] Although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications to the above embodiments without departing from the spirit and scope of the present invention, and these still belong to the technical scope protected by the present invention. Therefore, the protection scope of the present invention should be defined by the claims.

Claims

1. A thin film transistor, characterized in that, Comprising: a gate electrode; an insulating layer formed on the gate electrode; an active layer formed on the insulating layer; a source electrode formed on one of the two end portions of the active layer; and a drain electrode formed on the other of the two end portions of the active layer, wherein the active layer comprises a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer stacked in sequence, the first semiconductor material layer is formed on the insulating layer and has an ordered lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure and is doped with N-type ions, wherein the first semiconductor material layer is doped with group 3A ions.

2. A method for manufacturing a thin film transistor, characterized in that, Comprising: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor thin film on the insulating layer; performing ion implantation on the amorphous semiconductor thin film to implant group 3A ions into the amorphous semiconductor thin film; performing heat treatment on the amorphous semiconductor thin film implanted with the group 3A ions to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming a second and a third semiconductor material layer on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing an etching process to expose the second semiconductor material layer in a channel region and separate the second metal layer into a source electrode and a drain electrode.

3. A pixel array substrate, characterized in that Comprising: a thin film transistor fabricated by the manufacturing method according to claim 2.

4. A display device, characterized in that, Comprising: a pixel array substrate as claimed in claim 3.

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