Mitigating thermal shock on adjacent stacked semiconductor devices

Abstract

The invention relates to mitigating thermal shock on adjacent stacked semiconductor devices. A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to opposite sides of the first set of stacked semiconductor devices; and (5) a temperature regulation assembly on the second side and aligned with the second set of stacked semiconductor devices. The temperature regulation assembly is positioned to absorb thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application of a Chinese patent application with the invention title "Reducing Thermal Shock on Adjacent Stacked Semiconductor Devices", application number 202110479153.9, and filing date April 30, 2021. Technical Field

[0003] The present technology relates to an apparatus and method for eliminating or at least reducing the thermal shock of heat treatment on stacked semiconductor devices. More specifically, some embodiments of the present technology relate to an apparatus and method for reducing the thermal shock to adjacent stacked semiconductor devices generated during a thermal bonding process. Background Art

[0004] Encapsulated and stacked semiconductor dies including memory chips, microprocessor chips, logic chips, and imager chips typically include semiconductor dies mounted on a substrate and encapsulated in a plastic protective cover. Individual semiconductor dies may include functional features such as memory cells, processor circuits, imager devices, and other circuitry, as well as bonding pads electrically connected to the functional features. Semiconductor manufacturers are constantly reducing the size of die packages to accommodate the space limitations of electronic devices. One method for increasing the processing power of semiconductor packages is to vertically stack multiple semiconductor dies on top of each other in a single package. A thermal bonding process can be used to connect the multiple semiconductor dies, the thermal bonding process including (i) positioning a film between two of the semiconductor dies, and (ii) thermally curing the film. Summary of the Invention

[0005] In one aspect, the present application provides a semiconductor device assembly, comprising: a substrate having a first side and a second side opposite the first side; a first set of stacked semiconductor devices on the first side of the substrate; a second set of stacked semiconductor devices adjacent to the first set of stacked semiconductor devices; and wherein a temperature regulation component is located on the second side of the substrate and at least partially aligned with the second set of stacked semiconductor devices, and wherein the temperature regulation component is configured to absorb at least a portion of the thermal energy applied to the first set of stacked semiconductor devices, and thereby inhibit the thermal energy from heating the second set of stacked semiconductor devices.

[0006] In another aspect, the present application further provides a method for managing thermal energy, comprising: applying thermal energy from a separate heat component to a first set of stacked semiconductor devices of a semiconductor device assembly; and absorbing at least a portion of the thermal energy generated by the heat component through the temperature regulation component of the semiconductor device assembly, such that the portion of the thermal energy is inhibited from increasing the temperature of the second set of stacked semiconductor devices.

[0007] In yet another aspect, the present application further provides a semiconductor device assembly, comprising: a substrate having a first side and a second side opposite to the first side; a first group of stacked semiconductor devices on the first side of the substrate; a second group of stacked semiconductor devices adjacent to one side of the first group of stacked semiconductor devices; a third group of stacked semiconductor devices adjacent to the opposite side of the first group of stacked semiconductor devices; and a temperature regulation component located on the second side of the substrate and at least partially aligned with the second group of stacked semiconductor devices, the temperature regulation component being positioned relative to the second group of stacked semiconductor devices to absorb at least a portion of the thermal energy and thereby thermally isolate the second group of stacked semiconductor devices from the first group of stacked semiconductor devices at least partially. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale. Instead, the emphasis is on illustrating the principles of the present technology.

[0009] Figure 1A is a schematic cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology.

[0010] Figure 1B is a schematic bottom view of a semiconductor device assembly according to an embodiment of the present technology.

[0011] Figures 2A to 2C is a schematic bottom view of a semiconductor device packaging assembly according to an embodiment of the present technology.

[0012] Figure 3 is a schematic isometric view of a temperature regulation component according to an embodiment of the present technology.

[0013] Figure 4A and 4B is a schematic cross-sectional view of a semiconductor device packaging assembly according to an embodiment of the present technology.

[0014] Figure 5 is a block diagram showing a system incorporating a semiconductor assembly according to an embodiment of the present technology.

[0015] Figure 6 is a flowchart showing a method according to an embodiment of the present technology. DETAILED DESCRIPTION

[0016] Details of several embodiments of a stacked semiconductor die package and methods of fabricating such die packages are described below. The term "semiconductor device" generally refers to a solid-state device that includes one or more semiconductor materials. A semiconductor device may include, for example, a semiconductor substrate, a wafer, or a die diced from a wafer or substrate. Throughout the disclosure, semiconductor dies are generally described in the context of semiconductor devices, but are not limited thereto.

[0017] The term "semiconductor device package" may refer to an arrangement having one or more semiconductor devices bonded to a common package. A semiconductor device package may include a housing or enclosure that partially or fully encapsulates at least one semiconductor device. A semiconductor device package may also include an interposer substrate that carries one or more semiconductor devices and is attached to or otherwise bonded to the enclosure. The term "semiconductor device assembly" may refer to an assembly that includes a plurality of stacked semiconductor devices. As used herein, the terms "vertical," "lateral," "upper," and "lower" may refer to the relative direction or position of features in a semiconductor device or package in view of the orientation shown in the figures. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations.

[0018] When using thermal energy to cure two adjacent semiconductor device packages that are close to each other, the thermal energy applied to the first package can adversely affect the second package. For example, excessive thermal energy can further harden or otherwise impact the film of the second film such that it cannot properly deform and / or adhere to the connecting semiconductor die. The present technology provides a solution to this problem.

[0019] Figure 1A is a schematic cross-sectional view of a semiconductor device assembly 100 according to an embodiment of the present technology. The semiconductor device assembly 100 includes a base substrate 101, a first set of stacked semiconductor devices 103, and a second set of stacked semiconductor devices 105. The first and second sets of semiconductor devices 103, 105 are adjacent to each other and are carried by the base substrate 101. The semiconductor device assembly 100 may also include more than two semiconductor device packages. The first and second sets of stacked semiconductor devices 103, 105 will be encapsulated or covered by a suitable material (such as a dielectric material, an epoxy resin, etc.). The encapsulated first and second sets of stacked semiconductor devices 103, 105 may be referred to as the first and second semiconductor device packages, respectively.

[0020] The first set of stacked semiconductor devices 103 respectively includes a plurality of semiconductor devices 1031 and a plurality of curable layers 1033 between or on the semiconductor devices 1031. Figure 1AIn the illustrated embodiment, the first set of stacked semiconductor devices 103 includes eight semiconductor devices 1031 and eight curable layers 1033. However, it should be understood that the first set of stacked semiconductor devices 103 may have different numbers of semiconductor devices 1031 and curable layers 1033.

[0021] The second set of stacked semiconductor devices 105 may also include a plurality of semiconductor devices 1051 and a plurality of curable layers 1053 between or on the semiconductor devices 1031, respectively. Figure 1A The illustrated embodiment of the second set of stacked semiconductor devices 105 has eight semiconductor devices 1051 and eight curable layers 1053, but in other embodiments, the second set of stacked semiconductor devices 105 may include different numbers of semiconductor devices 1051 and curable layers 1053.

[0022] The curable layers 1033, 1053 may include die attach materials for bonding the semiconductor devices 1031, 1051 to each other or to the substrate 101. The curable layers 1033, 1053 may be non-conductive films (NCF), non-conductive pastes (NCP), etc. The curable layers 1033, 1053 may also include thermosensitive or temperature-sensitive materials such that the stiffness or flexibility of the curable layers 1033, 1053 can be manipulated by adjusting the temperature or thermal energy.

[0023] The curable layer 1033 can be cured by applying thermal energy from the thermal assembly 109 of the bonding head 107. In some embodiments, the thermal assembly 109 may be an external assembly attached to the bonding head 107. As Figure 1A shown, the heat generated by the thermal assembly 109 flows through the first semiconductor die package 103 in the direction D1 towards the substrate 101, thereby curing the curable layer 1033. A portion of the thermal energy may also flow towards the second set of stacked semiconductor devices 105, as shown in the direction D2, and then upwards towards one or more of the curable layers 1053, as shown in the direction D3. This may adversely affect one or more of the curable layers 1053.

[0024] The semiconductor device assembly 100 of the present technology can be manufactured by using a temperature regulation assembly 111 configured to inhibit or prevent the thermal energy generated by the thermal assembly 109 from reaching the curable layer 1053 of the second set of stacked semiconductor devices 105. The temperature regulation assembly 111 is thus configured to at least partially thermally isolate the second set of stacked semiconductor devices 105 from the first set of stacked semiconductor devices 103. As Figure 1AAs shown, the temperature regulation component 111 can be adjacent to the base substrate 101 and opposite to the second group of stacked semiconductor devices 105. The temperature regulation component 111 can be located in the region A1 defined by the side surface 103a of the first group of stacked semiconductor devices 103 and the second side surface 105b of the second group of stacked semiconductor devices 105. For example, as Figure 1A shown, the temperature regulation component 111 is positioned such that the edge 111a of the temperature regulation component 111 is aligned with the first side 105a of the second group of stacked semiconductor devices 105. In some embodiments, the temperature regulation component 111 can be shaped or formed to cover most of the region A1. For example, in various embodiments, the "most" can mean greater than 90%, 75%, or 50%.

[0025] The temperature regulation component 111 can also be or alternatively in the region A2 and / or the region A3. When the temperature regulation component 111 is in the region A2, the temperature regulation component 111 absorbs the heat transferred through the base substrate 101 from both sides of the second group of stacked semiconductor devices 105. When the temperature regulation component 111 is in the region A3, the temperature regulation component 111 directly absorbs the excessive heat directly below the first group of stacked semiconductor devices 103.

[0026] The temperature regulation component 111 can be a cooling unit or a heat sink, which is configured to absorb the thermal energy from the heat component 109 to maintain the temperature of the base substrate 101 within a desired range. The temperature regulation component 111 can be, for example, a "passive" cooling unit, which only absorbs the thermal energy transferred to it and cools by conduction and convection to the environment. Alternatively, the temperature regulation component 111 can be an "active" cooling unit that actively cools other components (e.g., the second group of stacked semiconductor devices 105). In these embodiments, the temperature regulation component 111 can be a thermoelectric component, such as a thermoelectric cooler, a Peltier device, a solid-state refrigerator, etc.

[0027] Figure 1B is Figure 1A a schematic bottom view of the semiconductor device assembly 100 shown. The second group of stacked semiconductor devices 105 has a first lateral dimension X1 and a second lateral dimension Y1. The first group of stacked semiconductor devices 103 generally has the same lateral dimensions as the second group of stacked semiconductor devices 105. The temperature regulation component 111 has a first lateral dimension X2 and a second lateral dimension Y2. In Figure 1B the embodiment shown, the first lateral dimension X2 of the temperature regulation component 111 is smaller than the first lateral dimension X1 of the second group of stacked semiconductor devices 105, while the second lateral dimension Y2 of the temperature regulation component 111 is larger than the second lateral dimension Y1 of the second group of stacked semiconductor devices 105. The temperature regulation component 111 can have a linear shape, such as a square, a rectangle (as Figure 1B shown), etc.

[0028] Figures 2A to 2C is a schematic bottom view of a semiconductor device package assembly 100 according to an embodiment of the present technology. In Figure 2A the illustrated embodiment, the first lateral dimension X2 of the temperature regulation component 111 is greater than the first lateral dimension X1 of the second set of stacked semiconductor devices 105, and the second lateral dimension Y2 of the temperature regulation component 111 is also greater than the second lateral dimension Y1 of the second set of stacked semiconductor devices 105. In Figure 2B the illustrated embodiment, the first lateral dimension X2 of the temperature regulation component 111 is greater than the first lateral dimension X1 of the second set of stacked semiconductor devices 105, and the second lateral dimension Y2 of the temperature regulation component 111 is substantially the same as the second lateral dimension Y1 of the second set of stacked semiconductor devices 105. In Figure 2C the embodiment illustrated, the first lateral dimension X2 of the temperature regulation component 111 is substantially the same as the first lateral dimension X1 of the second set of stacked semiconductor devices 105, and the second lateral dimension Y2 of the temperature regulation component 111 is also substantially the same as the second lateral dimension Y1 of the second set of stacked semiconductor devices 105.

[0029] Figure 3 is a schematic isometric view of a temperature regulation component 311 according to an embodiment of the present technology. The temperature regulation component 311 is a rectangular ring. As shown, the temperature regulation component 311 has a first outer dimension X3 and a second outer dimension Y3. The temperature regulation component 311 also has a first inner dimension X4 and a second inner dimension Y4. The first outer dimension X3 is greater than the first inner dimension X4. The second outer dimension Y3 is greater than the second inner dimension Y4. In various embodiments, the difference between the first outer dimension X3 and the first inner dimension X4 (or the difference between the second outer dimension Y3 and the second inner dimension Y4) may vary depending on factors such as the size of the second set of stacked semiconductor devices 105, the target temperature for curing the curable layer 1033 of the first set of stacked semiconductor devices 103, the material types of the curable layers 1033, 1053, the distance or gap between the first and second sets of semiconductor devices 103, 105, etc.

[0030] Figure 4AFIG. 0 is a schematic cross-sectional view of a semiconductor device assembly 400 according to an embodiment of the present technology. The semiconductor device assembly 400 includes a base substrate 401, a first set of stacked semiconductor devices 403, a second set of stacked semiconductor devices 405, and a third set of stacked semiconductor devices 406. The second and third sets of stacked semiconductor devices 405 and 406 are on opposite sides of the first set of stacked semiconductor devices 403. The semiconductor device packages 403, 405, and 406 are attached to the front face 401a of the base substrate 401, and the base substrate 401 has a back face 401b. In some embodiments, the semiconductor device assembly 400 may include more than three semiconductor device packages.

[0031] As Figure 4A shown, the thermal assembly 409 of the bonding head 407 is used to heat the first set of stacked semiconductor devices 403 to bond the semiconductor devices 4031 in the first set of stacked semiconductor devices 403 together. The semiconductor devices 4031 may be bonded by curing films 4033 that are respectively attached to the semiconductor devices 4031. The heat generated by the thermal assembly 409 flows to the base substrate 401, as shown by the direction D4.

[0032] The semiconductor device assembly 400 also has a cooling unit 411 attached to the back face 401b of the base substrate 401. The backside cooling unit 411 is configured to inhibit or prevent the heat generated by the thermal assembly 409 from being transferred through the base substrate 401 to the second set of stacked semiconductor devices 405 or the third set of stacked semiconductor devices 406. In some embodiments, the backside cooling unit 411 may be formed with a recess 413 that can effectively prevent the backside cooling unit 411 from absorbing too much heat from the base substrate 401. This may be useful because absorbing too much heat may affect the curing process of the curing film 4033. With this arrangement, the curing process of the film 4033 (e.g., especially the lowest one in FIG. 4) of the first set of stacked semiconductor devices 403 is not affected by the backside cooling unit 411.

[0033] In some embodiments, the backside cooling unit 411 may be shaped or formed according to the shape, material, and / or properties of the base substrate 401. The size of the recess 413 may be determined, for example, based on the thermal conductivity of the base substrate 401 and the load provided by the thermal assembly 409. For example, in embodiments where the base substrate 401 has a relatively high thermal conductivity, the size of the recess 413 may be relatively small. Conversely, when the base substrate 401 has a relatively low thermal conductivity, the size of the recess 413 may be relatively large. As Figure 4AAs shown, the recess 413 may have a lateral dimension extending from the side surface 4055 of the second set of stacked semiconductor devices 405 to the side surface 4065 of the third set of stacked semiconductor devices 406. In some embodiments, the recess 413 may have the same lateral dimension as the lateral dimension of the first set of stacked semiconductor devices 403 (e.g., from the first side surface 4035 to the second side surface 4037 opposite the first side surface 4035). In some embodiments, the recess 413 may have a lateral dimension somewhere between Figure 4A the lateral dimension shown and the lateral dimension of the first set of stacked semiconductor devices 403.

[0034] Figure 4B Another structure is shown in which Figure 4B the substrate 401 in Figure 4A is carried by the chuck table 402, and the backside cooling unit 411 is attached to the chuck table 402. Thus, the backside cooling unit 411 is not part of the semiconductor device assembly 400 (

[0035] Figure 5 is a block diagram of a system incorporating a semiconductor assembly in accordance with an embodiment of the present technology. Any of the semiconductor devices having the features described above with reference to Figures 1A to 4B can be incorporated into any of countless larger and / or more complex systems, a representative example of which is Figure 5 the system 500 schematically shown in Figure 5in any of the elements shown. The resulting system 500 can be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Thus, representative examples of system 500 include, but are not limited to, computers and / or other data processors such as desktop computers, laptop computers, Internet devices, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Other representative examples of system 500 include lights, cameras, vehicles, etc. With respect to these and other examples, system 500 can be housed in a single unit or distributed, for example, over multiple interconnected units via a communication network. Thus, the components of system 500 can include local and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0036] Figure 6 is a flow chart showing a method 600 for managing thermal energy in a semiconductor device assembly according to an embodiment of the present technology. At block 601, method 600 begins by positioning a thermal component adjacent to a first set of stacked semiconductor devices of the semiconductor device assembly. At block 603, method 600 continues by providing a temperature regulation component relative to the thermal component and adjacent to a second set of stacked semiconductor devices of the semiconductor device assembly. At block 605, method 600 continues by absorbing at least a portion of the thermal energy generated by the thermal component via the temperature regulation component such that the temperature of the second set of stacked semiconductor devices is maintained within a desired range (e.g., increasing by no more than 1 to 5 degrees Celsius).

[0037] For example, method 600 can include transferring at least a portion of the thermal energy generated by the thermal component to the first set of stacked semiconductor devices such that the temperature of the first set of stacked semiconductor devices increases. In some embodiments, method 600 includes measuring the temperature of the first and / or second set of stacked semiconductor devices and adjusting the temperature of the temperature regulation component or the temperature of the thermal component in response to a change in the measured temperature. For example, reducing the thermal energy when the temperature of the first set of stacked semiconductor devices (e.g., 103 or 403) has been at a temperature sufficient to cure a curable layer or film for a sufficient time or when the temperature of the first and / or second set of stacked semiconductor devices exceeds a corresponding threshold temperature.

[0038] In some embodiments, a method for managing thermal energy according to the present technology may include: (1) applying thermal energy from a separate thermal component to a first set of stacked semiconductor devices of a semiconductor device assembly; and (2) absorbing at least a portion of the thermal energy generated by the thermal component through a temperature regulation component of the semiconductor device assembly. With this arrangement, an increase in the temperature of a second set of stacked semiconductor devices by that portion of the thermal energy can be inhibited. In other words, the second set of stacked semiconductor devices can be at least partially thermally isolated from the first set of stacked semiconductor devices. In some embodiments, the method may further include measuring the temperature of the first and / or second set of stacked semiconductor devices. In some embodiments, the method may further include adjusting the temperature of the temperature regulation component in response to a change in the measured temperature. In some embodiments, the method may further include adjusting the temperature of the thermal component in response to a change in the measured temperature.

[0039] The present disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. While specific embodiments are disclosed herein for illustrative purposes, as will be recognized by those of ordinary skill in the relevant art, various equivalent modifications are possible without departing from the present technology. In some instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the present technology. While the steps of a method may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments may be combined or eliminated in other embodiments. Additionally, while advantages associated with certain embodiments of the present technology have been disclosed in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments must exhibit such advantages or other advantages disclosed herein that fall within the scope of the present technology. Accordingly, the present disclosure and the associated technology may include other embodiments not expressly shown or described herein.

[0040] Throughout this disclosure, unless the context clearly indicates otherwise, the singular terms "a," "an," and "the" include plural referents. Similarly, unless the word "or" in reference to a list of two or more items is explicitly limited to mean only a single item exclusive of the other items in the list, "or" as used in such a list will be interpreted to include (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Additionally, the term "comprising" is used throughout to mean including at least the recited feature such that no greater number of the same feature and / or additional types of other features are excluded. References herein to "one embodiment," "some embodiments," or the like mean that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the technology. Thus, the appearances of such phrases or statements herein do not necessarily all refer to the same embodiment. Moreover, the various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0041] From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but various modifications may be made without departing from the scope of the invention. The technology is not limited except as by the appended claims.

Claims

1. A semiconductor assembly, comprising: A first semiconductor package; A second semiconductor package adjacent to the first semiconductor package; And A temperature regulation component that is at least partially vertically aligned with the second semiconductor package and is configured to at least partially suppress an increase in a second temperature of the second semiconductor package based on a first temperature of the first semiconductor package.

2. The semiconductor assembly according to claim 1, further comprising: A substrate including a first side and a second side opposite the first side, Wherein the first semiconductor package and the second semiconductor package are bonded to the first side of the substrate, and the temperature regulation component contacts the second side of the substrate.

3. The semiconductor assembly according to claim 1, further comprising: A thermal component configured to apply thermal energy to the first semiconductor package, the second semiconductor package, or a combination thereof.

4. The semiconductor assembly according to claim 3, wherein the thermal component is configured to apply the thermal energy to the first semiconductor package, the second semiconductor package, or a combination thereof via a first side of the first semiconductor package and the second semiconductor package opposite a second side of the first semiconductor package, the second side being associated with coupling the first semiconductor package and the second semiconductor package to a substrate.

5. The semiconductor assembly according to claim 3, wherein the temperature regulation component is configured to at least partially suppress an increase in the second temperature of the second semiconductor package based on an increase in the first temperature of the first semiconductor package by the thermal component.

6. The semiconductor assembly according to claim 1, wherein: The first semiconductor package includes a first set of stacked semiconductor devices; and The second semiconductor package includes a second set of stacked semiconductor devices.

7. The semiconductor assembly according to claim 1, wherein the temperature regulation component is not vertically aligned with the first semiconductor package.

8. The semiconductor assembly according to claim 1, wherein the temperature regulation component is positioned relative to the first semiconductor package and the second semiconductor package to at least partially thermally isolate the first semiconductor package and the second semiconductor package.

9. The semiconductor assembly according to claim 1, wherein an edge of the temperature regulation component is vertically aligned with an edge of the second semiconductor package.

10. The semiconductor assembly according to claim 1, wherein the temperature regulation component includes an active cooling unit.

11. The semiconductor assembly according to claim 1, wherein the temperature regulation component includes a passive cooling unit.

12. A semiconductor assembly, comprising: A substrate; A first semiconductor package coupled to a first side of the substrate; A second semiconductor package adjacent to the first semiconductor package and coupled to the first side of the substrate; And A temperature regulation component that is coupled to a second side of the substrate in a region that is at least partially vertically aligned with the second semiconductor package and is configured to at least partially suppress an increase in a second temperature of the second semiconductor package based on a first temperature of the first semiconductor package.

13. The semiconductor assembly according to claim 12, further comprising: A thermal component configured to apply thermal energy to the first semiconductor package, the second semiconductor package, or a combination thereof.

14. The semiconductor assembly according to claim 12, wherein the temperature regulation component is configured to at least partially suppress an increase in a third temperature of the substrate based on the first temperature of the first semiconductor package.

15. The semiconductor assembly according to claim 14, wherein the temperature regulation component is configured to maintain the third temperature of the substrate within a range based at least in part on an increase in the first temperature of the first semiconductor package.

16. The semiconductor assembly according to claim 12, wherein the temperature regulation component is configured to maintain the second temperature of the second semiconductor package within a range based at least in part on an increase in the first temperature of the first semiconductor package.

17. The semiconductor assembly according to claim 12, wherein the second side of the substrate is opposite the first side of the substrate.

18. The semiconductor assembly according to claim 12, wherein the temperature regulation component is configured to at least partially suppress an increase in the second temperature of the second semiconductor package based on identifying an increase in the first temperature of the first semiconductor package.

19. The semiconductor assembly according to claim 12, wherein the temperature regulation component is configured to at least partially suppress an increase in the second temperature of the second semiconductor package based on absorbing thermal energy from the first semiconductor package via the substrate.

20. The semiconductor assembly according to claim 12, wherein the temperature regulation component includes a thermoelectric cooler, a Peltier device, or a solid-state refrigerator.

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