Semiconductor device, preparation method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises an N-drift layer; the N + substrate is positioned on one side of the N-drift layer; the groove penetrates through the N + substrate; the N-buffer layer is positioned on one side, close to the N-drift layer, of the groove; the P + anode is wrapped by the N-buffer layer on one side, close to the N-drift layer, of the groove; the anode conducting layer is in contact with the surface, far away from the N-drift layer, of the P + anode in the groove and is in contact with the surface, far away from one side of the N-drift layer, of the N + substrate outside the groove; the N-layer is in contact with the surface, facing the N-drift layer, of the N + substrate and the surface, facing the N + substrate, of the N-drift layer, the thickness TNL of the N-layer between the bottom face of the groove and the surface, facing the N-drift layer, of the N + substrate is larger than or equal to 0, and at least when the TNL is equal to 0, the doping concentration of the N-layer is smaller than that of the N-drift layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] By integrating a freewheeling diode and a bipolar device on a single chip, a reverse-conducting power device has the ability to conduct reverse current. This can not only reduce the parasitic inductance and parasitic resistance caused by the conventional external parallel diode method, but also improve the device power density, device performance, and reduce the system volume by saving the terminal area. However, in a conventional reverse-conducting device such as a reverse-conducting IGBT, an N+ collector region short-circuited with the P+ collector region is introduced into the device collector, thereby forming a PiN diode structure in the device to achieve the reverse-conducting function. However, the presence of the N+ collector region causes the device to enter the unipolar conduction mode first during forward conduction. As the anode voltage gradually increases, the P+ collector region gradually participates in conduction, and the device enters the bipolar conduction mode. The switching from the unipolar conduction mode to the bipolar conduction mode easily causes a sharp drop in the device conduction resistance and a voltage snapback phenomenon in the device collector voltage. This easily leads to uneven current distribution inside the device and is not conducive to device parallel connection, which needs to be further optimized and improved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and an electronic device to improve the voltage snapback phenomenon existing in the prior art.

[0004] The semiconductor device, the manufacturing method thereof, and the electronic device provided by the embodiments of the present disclosure are specifically as follows: On the one hand, an embodiment of the present disclosure provides a semiconductor device, including: An N- drift layer; An N+ substrate located on one side of the N- drift layer; A trench penetrating the N+ substrate; An N- buffer layer located on the side of the trench close to the N- drift layer; A P+ anode wrapped by the N- buffer layer on the side of the trench close to the N- drift layer; An anode conductive layer contacting the surface of the P+ anode away from the N- drift layer in the trench and contacting the surface of the N+ substrate away from the N- drift layer outside the trench; An N- layer contacting the surface of the N+ substrate facing the N- drift layer and the surface of the N- drift layer facing the N+ substrate. The thickness T of the N- layer between the bottom surface of the trench and the surface of the N+ substrate facing the N- drift layer , NLGreater than or equal to 0, and at least at T NL When it is equal to 0, the doping concentration of the N-layer is less than the doping concentration of the N-drift layer.

[0005] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N-buffer layer is wrapped by the N-layer.

[0006] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N-buffer layer is wrapped by the N-drift layer, T NL Greater than 0.

[0007] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the surface of the N-buffer layer away from the trench contacts the N-drift layer, and the side surface of the N-buffer layer contacts the N-layer; or, the surface of the N-buffer layer away from the trench and part of the side surface are embedded in the N-drift layer, and the non-embedded side surface contacts the N-layer.

[0008] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the trench extends into the N-layer, T NL Greater than 0.

[0009] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, an anode dielectric layer is further disposed in the trench, and the N-layer is separated from the anode conductive layer in the trench by the anode dielectric layer.

[0010] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N+ substrate is separated from the anode conductive layer in the trench by the anode dielectric layer.

[0011] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N-layer contacts the anode conductive layer in the trench.

[0012] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the P+ anode and the N-buffer layer are further disposed between the side surface of the trench and the N-layer.

[0013] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N-buffer layer and the P+ anode contact the N+ substrate outside the trench.

[0014] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N+ substrate contacts the anode conductive layer in the trench.

[0015] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the trench is strip-shaped, and a plurality of strip-shaped trenches are arranged side by side in the orthographic projection on the N-drift layer.

[0016] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the orthographic projection of the trench on the N-drift layer is a mesh shape.

[0017] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the trench is closed-shaped, and a plurality of closed-shaped trenches are concentrically arranged in the orthographic projection on the N-drift layer.

[0018] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, it further includes a P-type well region, an N+ cathode region, a P+ cathode region, a cathode conductive layer, a gate dielectric layer, a gate conductive layer, and an isolation dielectric layer. Among them, the P-type well region is wrapped by the N-drift layer, the N+ cathode region and the P+ cathode region are disposed in the P-type well region, the cathode conductive layer is in contact with the N+ cathode region and the P+ cathode region, the gate dielectric layer is in contact with the N+ cathode region, the P-type well region, and the gate conductive layer, and the isolation dielectric layer separates the gate conductive layer from the cathode conductive layer.

[0019] On the other hand, the embodiments of the present disclosure provide a method for manufacturing the above semiconductor device, including: Providing an N+ substrate; Epitaxially growing an N-layer and an N-drift layer on the N+ substrate in sequence; After thinning the N+ substrate to a target thickness, forming a first hard mask on the back surface of the N+ substrate, and then performing selective etching to form a trench penetrating the N+ substrate; While maintaining the state of the first hard mask, implanting N-type impurities on the back surface of the N+ substrate to form an N-buffer layer at the bottom of the trench; Depositing a second hard mask on the side where the first hard mask is located, and etching the second hard mask by using a reactive ion etching method, leaving only the second hard mask on the side surface of the trench; Implanting P-type impurities on the back surface of the N+ substrate to form a P+ anode wrapped by the N-buffer layer; Stripping and removing the first hard mask and the second hard mask, and annealing to activate the implanted ions and repair lattice damage.

[0020] On the other hand, the embodiments of the present disclosure provide an electronic device, including the above semiconductor device provided by the embodiments of the present disclosure.

[0021] The beneficial effects of the present disclosure are as follows: The semiconductor device, its manufacturing method and electronic device provided by the embodiments of the present disclosure include an N-drift layer; an N+ substrate located on one side of the N-drift layer; a trench penetrating the N+ substrate; an N-buffer layer located on the side of the trench close to the N-drift layer; a P+ anode wrapped by the N-buffer layer on the side of the trench close to the N-drift layer; an anode conductive layer contacting the surface of the P+ anode away from the N-drift layer in the trench and contacting the surface of the N+ substrate away from the N-drift layer outside the trench; an N-layer contacting the surface of the N+ substrate facing the N-drift layer and the surface of the N-drift layer facing the N+ substrate; the thickness of the N-layer between the bottom surface of the trench and the surface of the N+ substrate facing the N-drift layer is greater than or equal to 0, and at least when it is 0, the doping concentration of the N-layer is less than that of the N-drift layer. The doping concentration of the N-layer is lower than that of the N-drift layer, thereby increasing the resistance from the N-buffer layer on the P+ anode to the N+ substrate. Therefore, under the same forward conduction current, the potential difference from the N-buffer layer on the P+ anode of the present disclosure to the N+ substrate is greater, so that the PN junction of the P+ anode / N-buffer layer of the present disclosure is easier to turn on, which is beneficial to suppressing the voltage bounce phenomenon. The vertical thickening of the N-layer (i.e., T is greater than 0) further increases the resistance between the N-buffer layer on the P+ anode and the N+ substrate, so that the P+ anode / N-layer is easier to turn on, and the voltage bounce phenomenon can be further improved. NL is greater than or equal to 0, and at least when it is 0, the doping concentration of the N-layer is less than that of the N-drift layer. NL When the doping concentration of the N-layer is lower than that of the N-drift layer, the resistance from the N-buffer layer on the P+ anode to the N+ substrate is increased. Therefore, under the same forward conduction current, the potential difference from the N-buffer layer on the P+ anode of the present disclosure to the N+ substrate is greater, so that the PN junction of the P+ anode / N-buffer layer of the present disclosure is easier to turn on, which is beneficial to suppressing the voltage bounce phenomenon. The vertical thickening of the N-layer (i.e., T NL is greater than 0) further increases the resistance between the N-buffer layer on the P+ anode and the N+ substrate, so that the P+ anode / N-layer is easier to turn on, and the voltage bounce phenomenon can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 2 is Figure 1 a schematic diagram of the principle for the semiconductor device shown to improve voltage bounce; Figure 3 is Figure 1 an equivalent circuit diagram of the semiconductor device shown; Figure 4 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 5 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 6 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 7 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 8 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 9 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 10 A schematic diagram of the trench distribution provided by an embodiment of the present disclosure; Figure 11 Another schematic diagram of the trench distribution provided by an embodiment of the present disclosure; Figure 12 Another schematic diagram of the trench distribution provided by an embodiment of the present disclosure; Figure 13 is Figure 1 A schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 14 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 15 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 16 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 17 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 18 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 19 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 20 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 21 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 22 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 23 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown; Figure 24 is Figure 1 Another schematic diagram of a structure during the preparation of the semiconductor device shown. Detailed implementation manners

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the various figures in the accompanying drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of the present disclosure. Also, the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of known functions and known components are omitted.

[0024] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "comprising", "including", or similar terms mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms "inside", "outside", "above", "below", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0025] The embodiments of the present disclosure provide a semiconductor device, which can be fabricated based on semiconductor materials such as silicon, silicon carbide, gallium nitride, etc. through processes such as epitaxy and ion implantation. In some embodiments, as Figure 1 shown, the semiconductor device provided by the present disclosure may include: an N-drift layer 101, an N+ substrate 102, an N-buffer layer 103, a P+ anode 104, an anode conductive layer 105, an N-layer 106, and a trench V; wherein, the N+ substrate 102 is located on one side of the N-drift layer 101; the trench V penetrates the N+ substrate 102. Optionally, the trench V may only penetrate the N+ substrate 102, or may extend into the N-layer 106 while penetrating the N+ substrate 102; the N-buffer layer 103 is located on the side of the trench V close to the N-drift layer 101; the P+ anode 104 is wrapped by the N-buffer layer 103 on the side of the trench V close to the N-drift layer 101, that is, the N-buffer layer 103 is in contact with the upper surface and side surfaces of the P+ anode 104; the anode conductive layer 105 is in contact with the surface of the P+ anode 104 away from the N-drift layer 101 inside the trench V and is in contact with the surface of the N+ substrate 102 away from the N-drift layer 101 outside the trench V. The anode conductive layer 105 can be led out as the anode of the device; the N-layer 106 is in contact with the surface of the N+ substrate 102 facing the N-drift layer 101 and the surface of the N-drift layer 101 facing the N+ substrate 102, and the N-layer 106 may also wrap the N-buffer layer 103. In some embodiments, it is also possible to arrange for the N-drift layer 101 to wrap the N-buffer layer 103 (asFigure 4 as shown), or the surface of the N-buffer layer 103 away from the trench V can also be in contact with the N-drift layer 101, and the side surface of the N-buffer layer 103 is in contact with the N-layer 106 (as Figure 5 shown); alternatively, the surface of the N-buffer layer 103 away from the trench V and a part of the side surface are embedded in the N-drift layer 101, and the side surface of the N-buffer layer 103 not embedded in the N-drift layer 101 is in contact with the N-layer 106 (as Figure 6 shown). The thickness T of the N-layer 106 between the bottom surface of the trench V and the surface of the N+-substrate 102 facing the N-drift layer 101 NL can be greater than or equal to 0, and at least when T NL is equal to 0, the doping concentration of the N-layer 106 is less than the doping concentration of the N-drift layer 101.

[0026] Continuing to refer to Figure 1 it can be seen that the semiconductor device of the present disclosure may further include: a P-type well region 107, an N+ cathode region 108, a P+ cathode region 109, a cathode conductive layer 110, a gate dielectric layer 111, a gate conductive layer 112, and an isolation dielectric layer 113. Among them, the P-type well region 107 is located in the N-drift layer 101, the N+ cathode region 108 is located in the P-type well region 107, the P+ cathode region 109 is in contact with the P-type well region 107 and is in contact with the N+ cathode region 108, the cathode conductive layer 110 is simultaneously in contact with the N+ cathode region 108 and the P+ cathode region 109, the lower surface of the gate dielectric layer 111 is in contact with the upper surface of the P-type well region 107, the upper surface of the N+ cathode region 108, and the upper surface of the N-drift layer 101, the gate conductive layer 112 is located on the upper surface of the gate dielectric layer 111, the upper surface and the side surface of the gate conductive layer 112 are in contact with the isolation dielectric layer 113, the upper surface and the side surface of the isolation dielectric layer 113 are in contact with the cathode conductive layer 110, and the isolation dielectric layer 113 and the gate dielectric layer 111 completely wrap the gate conductive layer 112. The gate conductive layer 112 is led out as the device gate, and the cathode conductive layer 110 is led out as the device cathode.

[0027] Figure 3 is Figure 1 the equivalent circuit diagram of the semiconductor device shown. It can be seen from the equivalent circuit diagram that the parasitic resistance R between the P+ anode 104 and the N+-substrate 102 PN will affect the switching of the device from unipolar conduction to bipolar conduction. Increasing the parasitic resistance R PNIt can make the device easier to enter the bipolar conduction mode. Device working principle: When the cathode of the device is connected to a low potential and the anode of the device is connected to a high potential, when the gate voltage changes from 0 potential or negative potential to positive potential and an electron channel is formed by the inversion of the surface of the P-type well region 107 under the gate dielectric layer 111, the device first operates in the unipolar forward conduction mode. Electrons sequentially pass through the electron channel, the N-drift layer 101, the N-layer 106, the N-buffer layer 103 from the N+ cathode region 108, and finally enter the N+ substrate 102. The N-layer 106 is a high-resistance region with a doping concentration lower than that of the N-drift layer 101, increasing the parasitic resistance R from the N-buffer layer 103 on the P+ anode 104 to the N+ substrate 102 PN ; in addition, Figure 2 T of NL is greater than 0, increasing the Figure 2 distance from point B to point A1 or point A2 as shown, making the corresponding parasitic resistance R PN increase further. At the same current, the larger the parasitic resistance R PN is, the greater the voltage drop across the parasitic resistance R PN . Since the N+ substrate 102 and the P+ anode 104 are at the same potential, the greater the voltage drop across the parasitic resistance R PN from point B to point A1 or from point B to point A2, the greater the voltage difference between the P+ anode 104 near point B and the N-buffer layer 103, and the easier it is to reach the turn-on voltage of the PN junction of the P+ anode 104 / N-buffer layer 103, thereby turning on the PN junction of the P+ anode 104 / N-buffer layer 103 and the device entering the bipolar conduction mode. Thus, it can be seen that the present disclosure can make the device easier to enter the bipolar conduction mode from the unipolar conduction mode by extending the longitudinal distance between the N+ substrate 102 and the P+ anode 104, and / or reducing the doping concentration of the N-layer 106, thereby effectively improving the voltage snapback phenomenon

[0028] In some embodiments, Figure 7 Another semiconductor device structure provided by the embodiments of the present disclosure is given. As Figure 1 and Figure 7 shown, the semiconductor device provided by the embodiments of the present disclosure may further include an anode dielectric layer 114 disposed in the trench V. The N-layer 106 and the anode conductive layer 105 in the trench V can be separated by the anode dielectric layer 114, and the N+ substrate 102 can be separated from the anode conductive layer 105 in the trench V by the anode dielectric layer 114 (as Figure 1 shown), or the N+ substrate 102 is in contact with the anode conductive layer 105 in the trench V (as Figure 7 shown). Since the doping concentration of the N+ substrate 102 is often very high, the lateral contact between the anode conductive layer 105 and the N+ substrate 102 has an impact on the parasitic resistance R from the N+ substrate 102 to the N-buffer layer 103 above the P+ anode 104PN The influence is relatively small. In other words, Figure 1 and Figure 7 the improvement effects of the two embodiments on voltage bounce are quite similar.

[0029] In some embodiments, Figure 8 Another structural schematic diagram of the semiconductor device provided by the embodiments of the present disclosure is given. As Figure 8 shown, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the anode dielectric layer 114 may not be provided. At this time, both the N-layer 106 and the N+ substrate 102 can be in contact with the anode conductive layer 105 in the trench V. Since the anode conductive layer 105 is directly in contact with the N-layer 106, the parasitic resistance R from the N+ substrate 102 to the N-buffer layer 103 above the P+ anode 104 is reduced PN , and the voltage bounce suppression effect is relatively Figure 1 worse than that of the embodiment shown.

[0030] In some embodiments, Figure 9 Another structural schematic diagram of the semiconductor device provided by the embodiments of the present disclosure is given. As Figure 9 shown, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the P+ anode 104 and the N-buffer layer 103 can also be provided between the side surface of the trench V and the N-layer 106. The N-buffer layer 103 and the P+ anode 104 are in contact with the N+ substrate 102 outside the trench V. That is to say, the anode conductive layer 105 is not in contact with the N-layer 106, and the two are separated by the P+ anode 104 and the N-buffer layer 103. Compared with Figure 1 the embodiment shown, Figure 9 the area of the P+ anode region 104 in the embodiment shown is larger, and the injection efficiency is relatively higher.

[0031] It should be understood that in some embodiments, the N-buffer layer 103 and the P+ anode 104 can also extend downward to cover a part of the side surface of the trench V, so that a part of the side surface of the anode conductive layer 105 close to the N-drift layer 101 is separated from the N-layer 106 by the P+ anode 104 and the N-buffer layer 103, and another part of the side surface of the anode conductive layer 105 close to the N+ substrate 102 is in contact with the N-layer 106, which is equivalent to Figure 7 the combination of the embodiment shown in Figure 9 and the embodiment shown in Figure 9 . In this embodiment, it is still possible to ensure Figure 7 the technical effects of the large area of the P+ anode region 104 and high injection efficiency in the embodiment shown; at the same time, since only part of the side surface of the anode conductive layer 105 is directly in contact with the N-layer 106, compared with PN the embodiment shown, the parasitic resistance R from the N+ substrate 102 to the N-buffer layer 103 above the P+ anode 104 is increased Figure 7The illustrated embodiment is better.

[0032] In some embodiments, the P-type well region 107, P+ cathode region 109, N+ cathode region 108, and cathode conductive layer 110 of the present disclosure may belong to the cathode region, the gate dielectric layer 111, gate conductive layer 112, and isolation dielectric layer 113 may belong to the gate region, the N-drift layer 101 may belong to the drift region, and the N+ substrate 102, N-buffer layer 103, P+ anode 104, N-layer 106, anode conductive layer 105, and anode dielectric layer 114 (optional) may belong to the anode region. Figure 1 , Figures 4 to 9 One drift region, one cathode region, and one gate region are respectively shown disposed on one anode region. In some embodiments, multiple repeated drift regions, cathode regions, and gate regions may be disposed on one anode region according to process capabilities and required device performance; wherein, the N-drift layers 101 of adjacent drift regions are integrally disposed, the adjacent P-type well regions 107, adjacent P+ cathode regions 109, and cathode conductive layer 110 in adjacent cathode regions are integrally disposed, and adjacent gate regions are spaced apart by the cathode conductive layer 110.

[0033] In some embodiments, as Figure 10 shown, the trench V may be strip-shaped, and the orthographic projections of multiple strip-shaped trenches V on the N-drift layer 101 may be arranged side by side. The transverse cross-sectional structure of any trench V (for example, the cross-sectional structure along the I-I' line) may refer to Figure 1 , Figures 4 to 9 , which will not be elaborated herein.

[0034] In some embodiments, as Figure 11 shown, the orthographic projection of the trench V of the present disclosure on the N-drift layer 101 may also be a mesh shape, and the shape defined by the mesh-shaped trench V may be the square shown in Figure 11 , may also be circular or other shapes, which are not specifically limited in the present disclosure; and the cross-sectional views on the horizontal and vertical grid lines of the trench V (for example, the positions shown by the II-II' line and III-III' line) may all refer to Figure 1 , Figures 4 to 9 , which will not be elaborated herein.

[0035] In some embodiments, as Figure 12 shown, the trench V of the present disclosure may also be closed (such as a square, circle, etc., closed figure), and the orthographic projections of multiple closed trenches V on the N-drift layer 101 may be concentrically arranged; the cross-sectional views of any side of the trench V (for example, the cross-sectional views at the IV-IV' line and VI-VI' line) may all refer to Figure 1 , Figures 4 to 9 , which will not be elaborated herein.

[0036] As can be seen from the above, the doping concentration of the N-layer 106 in the present disclosure is lower than that of the N-drift layer 101, thereby increasing the parasitic resistance from the N-buffer layer 103 on the P+ anode 104 to the N+ substrate 102. Therefore, under the same forward conduction current, the potential difference from the N-buffer layer 103 on the P+ anode 104 to the N+ substrate 102 is greater, making the PN junction of the P+ anode 104 / N-buffer layer 103 easier to turn on, which is beneficial to suppressing the voltage snapback phenomenon. The vertical thickening of the N-layer 106 further increases the parasitic resistance between the N-buffer layer 103 on the P+ anode 104 and the N+ substrate 102, making the P+ anode 104 / N-layer 106 easier to turn on, and the voltage snapback phenomenon can be further improved, and the device cell size can be further reduced. It is preferable that there is no contact between the anode conductive layer 105 and the N-layer 106, and they are separated by the anode dielectric layer 114, so as to increase the parasitic resistance between the N-buffer layer 103 on the P+ anode 104 and the N+ substrate 102 as much as possible. If there is contact, the contact can be a Schottky contact or an Ohmic contact. Among them, the Schottky contact has a better improvement effect on the voltage snapback phenomenon than the Ohmic contact.

[0037] Based on the same inventive concept, an embodiment of the present disclosure further provides a method for manufacturing the above semiconductor device, which may include the following steps: Provide an N+ substrate; Epitaxially grow an N-layer and an N-drift layer on the N+ substrate in sequence; After thinning the N+ substrate to a target thickness, form a first hard mask on the back of the N+ substrate, and then perform selective etching to form a trench penetrating the N+ substrate; While maintaining the state of the first hard mask, inject N-type impurities into the back of the N+ substrate to form an N-buffer layer at the bottom of the trench; Deposit a second hard mask on the side where the first hard mask is located, and use a reactive ion etching method to etch the second hard mask, leaving only the second hard mask on the side of the trench; Inject P-type impurities into the back of the N+ substrate to form a P+ anode wrapped by the N-buffer layer; Strip and remove the first hard mask and the second hard mask, and anneal to activate the implanted ions and repair the lattice damage.

[0038] For a better understanding of the technical solution of the manufacturing method provided by the present disclosure, the following takes Figure 1 the manufacturing of the semiconductor device shown as an example for detailed description.

[0039] In some embodiments, an embodiment of the present disclosure further provides Figure 1 the manufacturing process of the semiconductor device shown, which may specifically include the following steps: (1) As shown in Figure 13As shown, an N- layer 106 is epitaxially grown on an N+ substrate 102.

[0040] (2) As Figure 14 shown, an N- drift layer 101 is grown on the surface of the N- layer 106.

[0041] (3) As Figure 15 shown, a P- type well region 107, an N+ cathode region 108, and a P+ cathode region 109 are formed by selective implantation on the surface of the N- drift layer 101 using a hard mask and ion implantation.

[0042] (4) As Figure 16 shown, after thinning the N+ substrate 102 to the target thickness, a first hard mask HM1 is formed on the back surface of the N+ substrate 102. Subsequently, selective etching is performed, and the N+ substrate 102 is etched using dry etching until at least the N- layer 106 is exposed.

[0043] (5) As Figure 17 shown, while maintaining the state of the first hard mask HM1, N- type impurities are implanted on the back surface of the N+ substrate 102, thereby forming an N- buffer layer 103.

[0044] (6) As Figure 18 shown, a second hard mask HM2 is deposited on the back surface of the device.

[0045] (7) As Figure 19 shown, on the back surface of the device, using a reactive ion etching method, the second hard mask HM2 in the middle region of the lower surface of the N+ substrate 102 and the lower surface of the N- buffer layer 103 is etched away, leaving only the second hard mask HM2 on the side of the trench V.

[0046] (8) As Figure 20 shown, P- type impurities are implanted on the back surface of the N+ substrate 102, thereby forming a P+ anode 104.

[0047] (9) As Figure 21 shown, the first hard mask HM1 and the second hard mask HM2 are stripped. Then, an annealing process is performed to activate the implanted ions and repair lattice damage.

[0048] (10) As Figure 22 shown, a chip surface structure is formed: including a gate dielectric layer 111, a gate conductive layer 112, an isolation dielectric layer 113, forming source contact holes, gate contact holes (not shown in the figure), a cathode conductive layer 110, and a gate lead layer (not shown in the figure).

[0049] (11) As Figure 23 shown, an anode dielectric layer 114 is deposited on the back surface of the device.

[0050] (12) As Figure 24As shown, reactive ion etching is used on the back of the device to etch away the anode dielectric layer 114 in the middle area of the lower surface of the N+ substrate 102 and the lower surface of the P+ anode 104, leaving only the anode dielectric layer 114 on the side of the trench V.

[0051] (13) Figure 1 As shown, the anode conductive layer 105 is filled and formed on the back side of the device by using a sputtering method.

[0052] So far, it is completed Figure 1 Preparation of the semiconductor device shown.

[0053] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device including the aforementioned semiconductor device provided in embodiments of the present disclosure. Because the principles underlying the problems solved by the electronic device are similar to those of the aforementioned semiconductor device, the implementation of the electronic device provided in embodiments of the present disclosure can refer to the implementation of the aforementioned semiconductor device provided in embodiments of the present disclosure, and any repetitions will not be repeated.

[0054] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, and household appliances. Of course, the electronic devices provided by the present disclosure may include not only semiconductor devices but also other structures. For example, when the electronic device is a radar, it may also include structures such as a transmitter, antenna, and receiver; when the electronic device is a mixer, it may also include structures such as input ports, output ports, and other structures.

[0055] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0056] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A semiconductor device, characterized in that, Comprising: N-drift layer; N+ substrate, located on one side of the N-drift layer; Groove, penetrating through the N+ substrate; N-buffer layer, located on the side of the groove close to the N-drift layer; P+ anode, wrapped by the N-buffer layer on the side of the groove close to the N-drift layer; Anode conductive layer, contacting the surface of the P+ anode away from the N-drift layer in the groove and contacting the surface of the N+ substrate away from the N-drift layer on the outside of the groove; The N-layer, on the surface of the N+ substrate facing the N-drift layer and on the surface of the N-drift layer facing the N+ substrate; the thickness T of the N-layer between the bottom surface of the trench and the surface of the N+ substrate facing the N-drift layer NL is greater than or equal to 0, and at least when T NL equals 0, the doping concentration of the N-layer is less than the doping concentration of the N-drift layer.

2. The semiconductor device according to claim 1, wherein The N-buffer layer is wrapped by the N-layer.

3. The semiconductor device according to claim 1, wherein The N-buffer layer is wrapped by the N-drift layer, T NL is greater than 0.

4. The semiconductor device according to claim 1, characterized in that, The surface of the N-buffer layer away from the groove contacts the N-drift layer, and the side surface of the N-buffer layer contacts the N-layer; or, the surface and part of the side surface of the N-buffer layer away from the groove are embedded in the N-drift layer, and the non-embedded side surface contacts the N-layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The groove extends into the N-layer, T NL is greater than 0.

6. The semiconductor device according to claim 5, characterized in that, It further includes an anode dielectric layer provided in the groove, and the N-layer and the anode conductive layer in the groove are separated by the anode dielectric layer.

7. The semiconductor device according to claim 6, characterized in that, The N+ substrate and the anode conductive layer in the groove are separated by the anode dielectric layer.

8. The semiconductor device according to claim 5, wherein The N-layer contacts the anode conductive layer in the groove.

9. The semiconductor device according to claim 5, characterized in that, The P+ anode and the N-buffer layer are also provided between the side surface of the groove and the N-layer.

10. The semiconductor device according to claim 9, wherein, The N-buffer layer and the P+ anode contact the N+ substrate outside the groove.

11. The semiconductor device according to any one of claims 6, 8 to 10, characterized in that, The N+ substrate contacts the anode conductive layer in the groove.

12. The semiconductor device according to any one of claims 1 to 4, 6 to 10, characterized in that, The groove is strip-shaped, and the positive projections of multiple strip-shaped grooves are arranged side by side on the N-drift layer.

13. The semiconductor device according to any one of claims 1 to 4, 6 to 10, characterized in that, The positive projection of the groove on the N-drift layer is reticular.

14. The semiconductor device according to any one of claims 1 to 4, 6 to 10, characterized in that, The groove is closed, and the positive projections of multiple closed grooves are concentrically arranged on the N-drift layer.

15. The semiconductor device according to any one of claims 1 to 4 and 6 to 10, characterized in that, It further includes a P-type well region, an N+ cathode region, a P+ cathode region, a cathode conductive layer, a gate dielectric layer, a gate conductive layer, and an isolation dielectric layer. Among them, the P-type well region is wrapped by the N-drift layer, the N+ cathode region and the P+ cathode region are provided in the P-type well region, the cathode conductive layer contacts the N+ cathode region and the P+ cathode region, the gate dielectric layer contacts the N+ cathode region, the P-type well region, and the gate conductive layer, and the isolation dielectric layer separates the gate conductive layer and the cathode conductive layer.

16. A method for manufacturing a semiconductor device according to any one of claims 1 to 15, characterized in that, Comprising: Providing an N+ substrate; Epitaxially growing an N-layer and an N-drift layer on the N+ substrate in sequence; After thinning the N+ substrate to a target thickness, forming a first hard mask on the back surface of the N+ substrate, and then performing selective etching to form a groove penetrating through the N+ substrate; Keeping the state of the first hard mask, injecting N-type impurities on the back surface of the N+ substrate to form an N-buffer layer located at the bottom of the groove; Depositing a second hard mask on the side where the first hard mask is located, and etching the second hard mask by using a reactive ion etching method, only leaving the second hard mask on the side surface of the groove; Injecting P-type impurities on the back surface of the N+ substrate to form a P+ anode wrapped by the N-buffer layer; Stripping and removing the first hard mask and the second hard mask, and annealing to activate the implanted ions and repair the lattice damage.

17. An electronic device, characterized in that, Including the semiconductor device according to any one of claims 1 to 15.

Images