Semiconductor device, preparation method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises an N-drift layer; the N + substrate is arranged on one side of the N-drift layer; the groove penetrates through the N + substrate; the surface, facing the N + substrate, of the N-drift layer is in contact with the N-buffer layer; the P + anode is arranged on one side, facing the N-buffer layer, of the groove; the anode conducting layer is in contact with the surface, far away from the N-drift layer, of the P + anode in the groove and is in contact with the surface, far away from one side of the N-drift layer, of the N + substrate outside the groove; the N-layer is in contact with the surface, facing the N + substrate, of the N-buffer layer and the surface, facing the N-buffer layer, of the N + substrate; the thickness TNL1 of the N-layer between the bottom surface of the groove and the surface, facing the N-buffer layer, of the N + substrate is larger than or equal to 0, and / or the thickness TNL2 of the N-layer between the surface, facing the N-buffer layer, of the P + anode and the surface, facing the P + anode, of the N-buffer layer is larger than or equal to 0, and at least when TNL1 and TNL2 are 0, the doping concentration of the N-layer is smaller than that of the N-drift layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and particularly to a semiconductor device, a preparation method thereof, and an electronic device. Background Art

[0002] For bipolar power semiconductor devices such as IGBTs, GTOs, etc., both holes and electrons participate in conduction when they are turned on. The concentration of minority carriers in the drift region is much higher than the doping concentration of the drift region. Therefore, the conductivity modulation effect will occur in the drift region, and the on-resistance of the drift region can be greatly reduced. This characteristic enables bipolar power semiconductor devices to be widely used in application fields that require high voltage and large current. For conventional bipolar devices such as IGBTs, because there is a PN junction in the anode region, when a reverse bias voltage is applied between the anode and cathode of the device, this PN junction is in a reverse bias withstand voltage state. Therefore, the device has no reverse conduction current ability, and a freewheeling diode often needs to be anti-parallel connected to freewheel the reverse current in practical applications. Integrating the freewheeling diode with a bipolar device single chip can not only reduce the parasitic inductance and parasitic resistance of the connection leads, but also improve the device power density by saving the terminal area, improve the device performance, and reduce the system volume. In order to integrate the freewheeling diode inside the bipolar device, reverse-conducting devices such as reverse-conducting IGBTs, reverse-conducting GTOs, etc. have been proposed. A conventional reverse-conducting IGBT introduces an N+ anode region short-circuited with the P+ anode region at the anode of the device, thereby forming a PiN diode structure inside the device to achieve the freewheeling function. However, the introduction of the N+ anode region makes it easy for the conventional reverse-conducting device to exhibit a voltage snapback phenomenon when it is forward-conducted, and there is a serious contradiction between its forward-conducting characteristics and reverse-conducting performance, which needs to be further optimized and improved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device, a preparation method thereof, and an electronic device to improve the voltage snapback phenomenon existing in the prior art.

[0004] The semiconductor device, the preparation method thereof, and the electronic device provided by the embodiments of the present disclosure are specifically as follows: On the one hand, an embodiment of the present disclosure provides a semiconductor device, including: An N-drift layer; An N+ substrate, located on one side of the N-drift layer; A trench, penetrating through the N+ substrate; An N-buffer layer, in contact with the surface of the N-drift layer facing the N+ substrate; A P+ anode, on the side of the trench facing the N-buffer layer; An anode conductive layer, which contacts the surface of the P+ anode away from the N- drift layer within the trench and contacts the surface of the N+ substrate away from the N- drift layer on one side outside the trench; An N- layer, which contacts the surface of the N- buffer layer facing the N+ substrate and the surface of the N+ substrate facing the N- buffer layer; the thickness T of the N- layer between the bottom surface of the trench and the surface of the N+ substrate facing the N- buffer layer NL1 is greater than or equal to 0, and / or, the thickness T of the N- layer between the surface of the P+ anode facing the N- buffer layer and the surface of the N- buffer layer facing the P+ anode NL2 is greater than or equal to 0, at least when T NL1 and T NL2 are both 0, the doping concentration of the N- layer is less than that of the N- drift layer.

[0005] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the surface of the N- buffer layer away from the N- drift layer is a plane; the N- layer wraps the P+ anode, or the surface of the P+ anode facing the N- buffer layer contacts the N- buffer layer and the side surface of the P+ anode contacts the N- layer.

[0006] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the surface and part of the side surface of the P+ anode facing the N- buffer layer are embedded in the N- buffer layer, and the unembedded side surface contacts the N- layer.

[0007] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the trench extends into the N- layer, and T NL1 is greater than 0.

[0008] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, an anode dielectric layer is further provided in the trench, and the N- layer is separated from the anode conductive layer in the trench by the anode dielectric layer.

[0009] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N+ substrate is separated from the anode conductive layer in the trench by the anode dielectric layer.

[0010] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N- layer contacts the anode conductive layer in the trench.

[0011] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the P+ anode is further disposed between the anode conductive layer on the side wall of the trench and the N- layer.

[0012] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the P+ anode is further disposed between the anode conductive layer on the sidewall of the trench and the N+ substrate.

[0013] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the N+ substrate is in contact with the anode conductive layer in the trench.

[0014] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the trench is strip-shaped, and a plurality of strip-shaped trenches are arranged side by side in the positive projection on the N- drift layer.

[0015] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the positive projection of the trench on the N- drift layer is a mesh shape.

[0016] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the trench is closed, and a plurality of closed trenches are concentrically arranged in the positive projection on the N- drift layer.

[0017] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, it further includes a P- well region, an N+ cathode region, a P+ cathode region, a cathode conductive layer, a gate dielectric layer, a gate conductive layer, and an isolation dielectric layer. Among them, the P- well region is wrapped by the N- drift layer, the N+ cathode region and the P+ cathode region are disposed in the P- well region, the cathode conductive layer is in contact with the N+ cathode region and the P+ cathode region, the gate dielectric layer is in contact with the N+ cathode region, the P- well region, and the gate conductive layer, and the isolation dielectric layer separates the gate conductive layer and the cathode conductive layer.

[0018] On the other hand, the embodiments of the present disclosure provide a method for manufacturing the above semiconductor device, including: Providing an N+ substrate; Epitaxially growing an N- layer, an N- buffer layer, and an N- drift layer on the N+ substrate in sequence; After thinning the N+ substrate to a target thickness, forming a hard mask on the back surface of the N+ substrate, and then performing selective etching to form a trench penetrating the N+ substrate; Maintaining the state of the hard mask, implanting P-type impurities on the back surface of the N+ substrate to form a P+ anode; Removing the hard mask by stripping, and annealing to activate the implanted ions and repair lattice damage.

[0019] On the other hand, the embodiments of the present disclosure provide an electronic device including the above semiconductor device provided by the embodiments of the present disclosure.

[0020] The beneficial effects of the present disclosure are as follows: The semiconductor device, its manufacturing method and the electronic device provided by the embodiments of the present disclosure include an N-drift layer; an N+ substrate located on one side of the N-drift layer; a trench penetrating through the N+ substrate; an N-buffer layer contacting the surface of the N-drift layer facing the N+ substrate; a P+ anode on the side of the trench facing the N-buffer layer; an anode conductive layer contacting the surface of the P+ anode away from the N-drift layer in the trench and contacting the surface of the N+ substrate away from the N-drift layer on the outside of the trench; an N-layer contacting the surface of the N-buffer layer facing the N+ substrate and the surface of the N+ substrate facing the N-buffer layer; the thickness T of the N-layer between the bottom surface of the trench and the surface of the N+ substrate facing the N-buffer layer NL1 is greater than or equal to 0, and / or the thickness T of the N-layer between the surface of the P+ anode facing the N-buffer layer and the surface of the N-buffer layer facing the P+ anode NL2 is greater than or equal to 0, at least when T NL1 and T NL2 are both equal to 0, the doping concentration of the N-layer is less than that of the N-drift layer. Introducing an N-layer with a low doping concentration between the N-buffer layer and the N+ substrate can increase the parasitic resistance between the N-buffer layer and the N+ substrate, increase the potential difference between the potential of the N-layer on the upper surface of the P+ anode and the potential of the N+ substrate, so that the PN junction formed by the P+ anode / N-layer is easier to turn on; thickening the N-layer in the vertical direction (i.e., T NL1 and / or T NL2 is greater than 0) can further increase the parasitic resistance between the N+ substrate and the N-buffer layer, and the voltage jump phenomenon can be further improved. Description of the Drawings

[0021] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 2 is Figure 1 the schematic diagram of improving the voltage jump of the semiconductor device shown; Figure 3 is Figure 1 the equivalent circuit diagram of the semiconductor device shown; Figure 4 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 5 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 6 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 7 Another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 8Another structural schematic diagram of the semiconductor device provided by the embodiment of the present disclosure; Figure 9 Another structural schematic diagram of the semiconductor device provided by the embodiment of the present disclosure; Figure 10 A schematic diagram of the trench distribution provided by the embodiment of the present disclosure; Figure 11 Another schematic diagram of the trench distribution provided by the embodiment of the present disclosure; Figure 12 Another schematic diagram of the trench distribution provided by the embodiment of the present disclosure; Figure 13 is Figure 1 A structural schematic diagram during the preparation process of the semiconductor device shown; Figure 14 is Figure 1 Another structural schematic diagram during the preparation process of the semiconductor device shown; Figure 15 is Figure 1 Another structural schematic diagram during the preparation process of the semiconductor device shown; Figure 16 is Figure 1 Another structural schematic diagram during the preparation process of the semiconductor device shown; Figure 17 is Figure 1 Another structural schematic diagram during the preparation process of the semiconductor device shown; Figure 18 is Figure 1 Another structural schematic diagram during the preparation process of the semiconductor device shown; Figure 19 is Figure 1 Another structural schematic diagram during the preparation process of the semiconductor device shown; Figure 20 is Figure 1 Another structural schematic diagram during the preparation process of the semiconductor device shown. Detailed implementation manners

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the content of the present disclosure schematically. Also, the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0023] Unless otherwise defined, technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in the specification and claims of this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. "Inside", "outside", "above", "below", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0024] Embodiments of the present disclosure provide a semiconductor device, which can be prepared based on semiconductor materials such as silicon, silicon carbide, gallium nitride, etc. through processes such as epitaxy and ion implantation. In some embodiments, as Figure 1 shown, the semiconductor device provided by the present disclosure may include: an N-drift layer 101, an N+ substrate 102, an N-buffer layer 103, a P+ anode 104, an anode conductive layer 105, an N-layer 106, and a trench V; wherein, the N+ substrate 102 is located on one side of the N-drift layer 101; the trench V penetrates the N+ substrate 102, optionally, the trench V may only penetrate the N+ substrate 102, or may extend into the N-layer 106 while penetrating the N+ substrate 102; the N-buffer layer 103 is in contact with the surface of the N-drift layer 101 facing the N+ substrate 102; the P+ anode 104 is on the side of the trench V facing the N-buffer layer 103; the anode conductive layer 105 is in contact with the surface of the P+ anode 104 away from the N-drift layer 101 inside the trench V and is in contact with the surface of the N+ substrate 102 away from the N-drift layer 101 outside the trench V, and the anode conductive layer 105 is led out as the device anode; the N-layer 106 is in contact with the surface of the N-buffer layer 103 facing the N+ substrate 102 and the surface of the N+ substrate 102 facing the N-buffer layer 103; from Figure 1 which it can be seen that the N-layer 106 can also wrap the P+ anode 104 (that is, the N-layer 106 is in contact with the upper surface and the side surfaces of the P+ anode); or, as Figure 4 shown, the N-layer 106 is in contact with the side surface of the P+ anode 104, and the N-buffer layer 103 is in contact with the upper surface of the P+ anode 104; or, as Figure 5 shown, the upper surface and part of the side surfaces of the P+ anode 104 are embedded in the N-buffer layer 103, and the side surfaces of the P+ anode 104 not embedded in the N-buffer layer 103 are in contact with the N-layer 106; the thickness T of the N-layer 106 between the surface of the P+ anode 104 away from the N-buffer layer 103 and the surface of the N+ substrate 102 facing the N-buffer layer 103 NL1 is greater than or equal to 0, T NL1When greater than 0, the surface of the N+ substrate 102 facing the N- buffer layer 103 is only in contact with the N- layer 106, T NL1 When equal to 0, the surface of the N+ substrate 102 facing the N- buffer layer 103 is in contact with both the N- layer 106 and the P+ anode 104; and / or, the thickness T of the N- layer 106 between the surface of the P+ anode 104 facing the N- buffer layer 103 and the surface of the N- buffer layer 103 facing the P+ anode 104 NL2 is greater than or equal to 0, where T NL2 When greater than 0, the surface of the P+ anode 104 facing the N- buffer layer 103 is in contact with the N- layer 106, T NL2 When equal to 0, the surface of the P+ anode 104 facing the N- buffer layer 103 is in contact with the N- buffer layer 103; at least when T NL1 and T NL2 are both equal to 0, the doping concentration of the N- layer 106 is less than that of the N- drift layer 101.

[0025] Continuing to refer to Figure 1 it can be seen that the semiconductor device of the present disclosure may further include: a P-type well region 107, an N+ cathode region 108, a P+ cathode region 109, a cathode conductive layer 110, a gate dielectric layer 111, a gate conductive layer 112, and an isolation dielectric layer 113. Among them, the P-type well region 107 is located in the N- drift layer 101, the N+ cathode region 108 is located in the P-type well region 107, the P+ cathode region 109 is in contact with the P-type well region 107 and is in contact with the N+ cathode region 108, the cathode conductive layer 110 is in contact with both the N+ cathode region 108 and the P+ cathode region 109, the lower surface of the gate dielectric layer 111 is in contact with the upper surface of the P-type well region 107, the upper surface of the N+ cathode region 108, and the upper surface of the N- drift layer 101, the gate conductive layer 112 is located on the upper surface of the gate dielectric layer 111, the upper surface and the side surface of the gate conductive layer 112 are in contact with the isolation dielectric layer 113, the upper surface and the side surface of the isolation dielectric layer 113 are in contact with the cathode conductive layer 110, and the isolation dielectric layer 113 and the gate dielectric layer 111 completely wrap the gate conductive layer 112. The gate conductive layer 112 is led out as the device gate, and the cathode conductive layer 110 is led out as the device cathode.

[0026] Figure 3 is Figure 1 the equivalent circuit diagram of the semiconductor device shown. It can be seen from the equivalent circuit diagram that the parasitic resistance R between the P+ anode 104 and the N+ substrate 102 PN will affect the switching of the device from unipolar conduction to bipolar conduction. Increasing the parasitic resistance R PNIt can make the device easier to enter the bipolar conduction mode. Device working principle: When the cathode of the device is connected to a low potential and the anode of the device is connected to a high potential, when the gate voltage changes from 0 potential or negative potential to positive potential and an electron channel is formed by the inversion of the surface of the P-type well region 107 under the gate dielectric layer 111, the device first operates in the unipolar forward conduction mode. Electrons sequentially pass through the electron channel, N-drift layer 101, N-buffer layer 103, N-layer 106 from the N+ cathode region 108, and finally enter the N+ substrate 102. Since the N-layer 106 is lightly doped, the contact formed between it and the anode conductive layer 105 is a Schottky contact or an Ohmic contact with a high contact resistance. Therefore, electrons tend to flow away through the N+ substrate 102, the N+ substrate 102 / anode conductive layer 105 interface with a low contact resistance, and the anode conductive layer 105, rather than flowing away from the interface between the high-resistance N-layer 106 and the anode conductive layer 105. Additionally, T NL1 and / or T NL2 When greater than 0, it increases the Figure 2 distance from point B to point A1 or point A2 as shown, that is, the corresponding parasitic resistance R PN increases. At the same current, the greater the parasitic resistance R PN is, the greater the voltage drop across the parasitic resistance R PN . Since the N+ substrate 102 and the P+ anode 104 are at the same potential, the greater the voltage drop across the parasitic resistance R PN from point B to point A1 or from point B to point A2, the greater the voltage difference between the P+ anode 104 near point B and the N-layer 106, and the easier it is to reach the turn-on voltage of the PN junction of P+ anode 104 / N-layer 106, thereby turning on the PN junction and the device entering the bipolar conduction mode. Therefore, the present disclosure makes the device easier to enter the bipolar conduction mode from the unipolar conduction mode by extending the longitudinal distance between the N+ substrate 102 and the P+ anode 104, and / or reducing the doping concentration of the N-layer 106, thereby improving the voltage snapback phenomenon.

[0027] In some embodiments, Figure 6 and Figure 7 respectively show another semiconductor device structure provided by the embodiments of the present disclosure. Different from the Figure 1 shown contact between the N-layer 106 and the anode conductive layer 105 in the trench V. As shown in Figure 6 and Figure 7 , the present disclosure can also provide an anode dielectric layer 114 in the trench V, and the N-layer 106 and the anode conductive layer 105 in the trench V can be separated by the anode dielectric layer 114. The anode conductive layer 105 is not in direct contact with the N-layer 106, which can increase the parasitic resistance of the N-layer 106 directly above the midpoint between the N+ substrate 102 and the P+ anode 104, and is more conducive to alleviating the voltage snapback.

[0028] Continue to refer to Figure 6It can be seen that in the present disclosure, the N+ substrate 102 and the anode conductive layer 105 in the trench V can be separated by the anode dielectric layer 114. Alternatively, as Figure 1 and Figure 7 shown, the N+ substrate 102 and the anode conductive layer 105 in the trench V can also be in direct contact. Since the doping concentration of the N+ substrate 102 is often very high, the side contact between the anode conductive layer 105 and the N+ substrate 102 has little influence on the parasitic resistance from the N+ substrate 102 to the N- layer 106 above the P+ anode 104. In other words, the improvement effect on voltage snapback is quite the same whether the N+ substrate 102 is in direct contact with the anode conductive layer 105 in the trench V or separated by the anode dielectric layer 114.

[0029] In some embodiments, Figure 8 and Figure 9 respectively show another semiconductor device structure provided by the embodiments of the present disclosure. As can be seen from Figure 8 and Figure 9 , the P+ anode 104 can also be disposed between the anode conductive layer 105 on the sidewall of the trench V and the N- layer 106. Compared with the embodiment shown in Figure 1 , the area of the P+ anode 104 is increased in the embodiments shown in Figure 8 and Figure 9 , the injection efficiency is higher, and the conduction characteristics are better. Optionally, in Figure 8 , the N+ substrate 102 is in direct contact with the anode conductive layer 105 in the trench V, and in Figure 9 , the N+ substrate 102 is separated from the anode conductive layer 105 on the sidewall of the trench V by the P+ anode 104. Compared with the embodiment shown in Figure 8 , in the embodiment shown in Figure 9 , the contact area between the anode conductive layer 105 and the N+ substrate 102 is narrower, so the parasitic resistance from the N+ substrate 102 to the N- layer 106 directly above the middle of the P+ anode 104 can be further increased, which is more beneficial to alleviating voltage snapback.

[0030] In some embodiments, the P-type well region 107, N+ cathode region 108, P+ cathode region 109, and cathode conductive layer 110 of the present disclosure may belong to the cathode region, the gate dielectric layer 111, gate conductive layer 112, and isolation dielectric layer 113 may belong to the gate region, and the N- drift layer 101 may belong to the drift region. The N+ substrate 102, N- buffer layer 103, P+ anode 104, anode conductive layer 105, N- layer 106, and anode dielectric layer 114 (optional) may belong to the anode region. Figure 1 , Figures 4 to 9One drift region, one cathode region, and one gate region are respectively shown on an anode region. In some embodiments, multiple repeated drift regions, cathode regions, and gate regions may be provided on one anode region according to process capabilities and required device performance; wherein, the N-drift layers 101 of adjacent drift regions are integrally provided, the adjacent P-well regions 107 in adjacent cathode regions are integrally provided, the adjacent P+cathode regions 109 are integrally provided, and the cathode conductive layer 110 is integrally provided, and adjacent gate regions are spaced apart by the cathode conductive layer 110.

[0031] In some embodiments, as Figure 10 shown, trench V may be strip-shaped, and the positive projections of multiple strip-shaped trenches V on the N-drift layer 101 may be arranged side by side. The transverse cross-sectional structure of any trench V (for example, the cross-sectional structure along the I-I' line) may all refer to Figure 1 , Figures 4 to 9 , and will not be elaborated here.

[0032] In some embodiments, as Figure 11 shown, the positive projection of the trench V of the present disclosure on the N-drift layer 101 may also be a mesh shape, and the shape defined by the mesh-shaped trench V may be the square shown in Figure 11 , may also be a circle or other shapes, which are not specifically limited in the present disclosure; and the cross-sectional views of the horizontal and vertical grid lines of the trench V (for example, the positions shown by the II-II' line and the III-III' line) may all refer to Figure 1 , Figures 4 to 9 , and will not be elaborated here.

[0033] In some embodiments, as Figure 12 shown, the trench V of the present disclosure may also be in a closed shape (such as a square, a circle, etc., a closed figure), and the positive projections of multiple closed-shaped trenches V on the N-drift layer 101 may be concentrically arranged; the cross-sectional views of any side of the trench V (for example, the cross-sectional views at the IV-IV' line and the VI-VI' line) may all refer to Figure 1 , Figures 4 to 9 , and will not be elaborated here.

[0034] As can be seen from the above, in the present disclosure, a low-doped N-layer 106 is introduced between the N-buffer layer 103 and the N+ substrate 102, thereby increasing the parasitic resistance between the N-buffer layer 103 and the N+ substrate 102, increasing the potential difference between the potential of the N-layer 106 on the upper surface of the P+ anode 104 and the potential of the N+ substrate 102, so that the P+ anode 104 / N-layer 106 is more easily turned on; thickening the N-layer 106 in the vertical direction can further increase the parasitic resistance between the N+ substrate 102 and the N-buffer layer 103, the voltage snapback phenomenon can be further improved, and the device cell size can be further reduced. The contact between the P+ anode 104 and the N-layer 106 can be a Schottky contact or an ohmic contact. If it is a Schottky contact, the improvement effect on the voltage snapback phenomenon will be better. Preferably, the N-layer 106 does not contact the anode conductive layer 105, and it can be blocked by the P+ anode 104 or blocked by using the anode dielectric layer 114, so that the parasitic resistance between the N+ substrate 102 and the N-buffer layer 103 can be maximized, which is more conducive to improving the voltage snapback phenomenon.

[0035] Based on the same inventive concept, an embodiment of the present disclosure further provides a method for manufacturing the above semiconductor device, which may include the following steps: Provide an N+ substrate; Epitaxially grow an N-layer, an N-buffer layer, and an N-drift layer on the N+ substrate in sequence; After thinning the N+ substrate to a target thickness, form a hard mask on the back surface of the N+ substrate, and then perform selective etching to form a trench penetrating the N+ substrate; While maintaining the hard mask state, implant P-type impurities on the back surface of the N+ substrate to form a P+ anode; Strip and remove the hard mask, and anneal to activate the implanted ions and repair lattice damage.

[0036] For a better understanding of the technical solution of the manufacturing method provided by the present disclosure, the following takes Figure 1 the manufacturing of the semiconductor device shown as an example for detailed description.

[0037] In some embodiments, an embodiment of the present disclosure further provides Figure 1 the manufacturing process of the semiconductor device shown, which may specifically include the following steps: (1) As Figure 13 shown, epitaxially grow an N-layer 106 on the N+ substrate 102.

[0038] (2) As Figure 14 shown, epitaxially form an N-buffer layer 103 and an N-drift layer 101 on the surface of the N-layer 106 in sequence.

[0039] (3) As Figure 15As shown, a P-type well region 107, an N+ cathode region 108, and a P+ cathode region 109 are formed by selective implantation on the surface of the N-drift region layer using a hard mask and ion implantation.

[0040] (4)As Figure 16 shown, the N+ substrate 102 is thinned to a target thickness.

[0041] (5)As Figure 17 shown, a hard mask HM is formed on the back surface of the N+ substrate 102, and then selective etching is performed. The N+ substrate 102 is etched using dry etching until at least the N-layer 106 is exposed.

[0042] (6)As Figure 18 shown, while maintaining the hard mask HM, P-type impurities are implanted on the back surface of the N+ substrate 102 to form a P+ anode 104.

[0043] (7)As Figure 19 shown, the hard mask HM is removed. Then annealing treatment is performed to activate the implanted ions and repair lattice damage.

[0044] (8)As Figure 20 shown, a device surface structure is formed: including a gate dielectric layer 111, a gate conductive layer 112, an isolation dielectric layer 113, forming a source contact hole, and a gate contact hole (the gate contact hole is not shown in the figure), a cathode conductive layer 110, and a gate lead layer (not shown in the figure).

[0045] (9)As Figure 1 shown, on the back surface of the device, an anode conductive layer 105 is formed by filling using a method such as sputtering.

[0046] Thus far, the fabrication of the Figure 1 semiconductor device shown is completed.

[0047] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device including the above semiconductor device provided by the embodiments of the present disclosure. Since the principle of the electronic device for solving problems is similar to that of the above semiconductor device for solving problems, therefore, the implementation of the electronic device provided by the embodiments of the present disclosure can refer to the implementation of the above semiconductor device provided by the embodiments of the present disclosure, and the repeated parts will not be described again.

[0048] In some embodiments, the above electronic device provided by the embodiments of the present disclosure may include but is not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, in addition to including semiconductor devices, the electronic devices provided by the present disclosure may also include other structures. For example, when the electronic device is a radar, it further includes: a transmitter, an antenna, a receiver, etc. structures; when the electronic device is a mixer, it may further include: input ports and output ports, etc. structures.

[0049] Although the preferred embodiments of the present disclosure have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they learn the basic inventive concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present disclosure.

[0050] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: N-drift layer; An N+ substrate, located on one side of the N-drift layer; A trench extending through the N+ substrate; An N-buffer layer, in contact with a surface of the N-drift layer facing the N+ substrate; A P+ anode, located on a side of the trench facing the N-buffer layer; an anode conductive layer, contacting a surface of the P+ anode away from the N-drift layer within the trench, and contacting a surface of the N+ substrate away from the N-drift layer outside the trench; N-layer, and the surface of the N-buffer layer facing the N+ substrate, and the surface of the N+ substrate facing the N-buffer layer; the thickness T of the N-layer between the bottom surface of the trench and the surface of the N+ substrate facing the N-buffer layer NL1 is greater than or equal to 0, and / or the thickness T of the N-layer between the surface of the P+ anode facing the N-buffer layer and the surface of the N-buffer layer facing the P+ anode ... NL2 Greater than or equal to 0, at least in T NL1 and T NL2 When both are 0, the doping concentration of the N-layer is lower than the doping concentration of the N-drift layer.

2. The semiconductor device according to claim 1, wherein The surface of the N-buffer layer away from the N-drift layer is flat; the N-layer wraps the P+ anode, or the surface of the P+ anode facing the N-buffer layer contacts the N-buffer layer, and the side of the P+ anode contacts the N-layer.

3. The semiconductor device according to claim 1, wherein The P+ anode is embedded in the N-buffer layer toward a surface and a portion of a side surface of the N-buffer layer, and the unembedded side surface is in contact with the N-layer.

4. The semiconductor device according to claim 2 or 3, characterized in that, The trench extends into the N-layer, T NL1 Greater than 0.

5. The semiconductor device according to claim 4, wherein, The invention also includes an anode dielectric layer disposed in the trench, wherein the N-layer and the anode conductive layer in the trench are separated by the anode dielectric layer.

6. The semiconductor device according to claim 5, wherein, The N+ substrate is separated from the anode conductive layer in the trench by the anode dielectric layer.

7. The semiconductor device according to claim 4, wherein The N-layer contacts the anode conductive layer in the trench.

8. The semiconductor device according to claim 4, wherein, The P+ anode is also disposed between the anode conductive layer and the N-layer on the sidewall of the trench.

9. The semiconductor device according to claim 8, characterized in that, The P+ anode is also provided between the anode conductive layer and the N+ substrate on the sidewall of the trench.

10. The semiconductor device according to claim 5 or 8, wherein The N+ substrate contacts the anode conductive layer in the trench.

11. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, wherein: The trenches are strip-shaped, and the orthographic projections of a plurality of strip-shaped trenches on the N-drift layer are arranged side by side.

12. The semiconductor device according to any one of claims 1 to 3, 5 to 9, characterized in that, The orthographic projection of the trench on the N-drift layer is in a mesh shape.

13. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, characterized in that, The trench is closed, and a plurality of closed trenches are concentrically arranged on the orthographic projection of the N-drift layer.

14. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, characterized in that, It also includes a P-well region, an N+ cathode region, a P+ cathode region, a cathode conductive layer, a gate dielectric layer, a gate conductive layer, and an isolation dielectric layer, wherein the P-well region is wrapped by the N-drift layer, the N+ cathode region and the P+ cathode region are arranged in the P-well region, the cathode conductive layer is in contact with the N+ cathode region and the P+ cathode region, the gate dielectric layer is in contact with the N+ cathode region, the P-well region, and the gate conductive layer, and the isolation dielectric layer separates the gate conductive layer from the cathode conductive layer.

15. A method for manufacturing a semiconductor device according to any one of claims 1 to 14, characterized in that, include: Providing an N+ substrate; Epitaxially growing an N-layer, an N-buffer layer and an N-drift layer in sequence on the N+ substrate; After thinning the N+ substrate to a target thickness, forming a hard mask on the back side of the N+ substrate, and then selectively etching to form a trench penetrating the N+ substrate; Keeping the hard mask in a state, implanting P-type impurities on the back side of the N+ substrate to form a P+ anode; The hard mask is removed by stripping, and annealing is performed to activate the implanted ions and repair lattice damage.

16. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 14.

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