Method for forming side wall of MOS (Metal Oxide Semiconductor) tube
By setting an etching buffer layer between the two layers of silicon nitride in the MOS tube and selective etching is performed using the difference in etching rate, the overetching problem caused by the thickness difference of NMOS and PMOS side walls is solved, protecting the gate, simplifying the etching process and reducing damage.
Patent Information
- Application Number
- CN202510389880.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-29
AI Technical Summary
In the multi-layer side wall structure on both sides of the MOS tube gate, the difference in the thickness of the side wall film layer between NMOS and PMOS leads to overetching in the thinning process, damaging the polysilicon gate.
By providing an etching buffer layer between the two layers of silicon nitride, selective etching is performed using the difference in etching rate between the etching buffer layer and the silicon nitride to protect the gate from being overetched. The specific steps include forming a first side wall and an etching buffer layer on the gate side wall, then forming a second side wall, and selective etching is performed after a high temperature annealing process.
It effectively avoids overetching of the gate side wall of the MOS tube, protects the gate from damage, simplifies the formation process of the etching buffer layer, and reduces the risk of photoresist edge peeling.
Smart Images
Figure CN120390441A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for forming sidewalls of a MOS transistor. Background Art
[0002] With the development of CMOS (Complementary Metal - Oxide - Semiconductor) semiconductor device processes, the smaller the critical dimension (CD) of the MOS transistor, the more sensitive the thermal budget is to the junction depth and lateral diffusion. Among them, different implanted elements have different reactions to the same thermal process. In order to achieve the same lateral diffusion length, NMOS and PMOS use sidewall processes with different widths.
[0003] There are often multiple sidewall structures on both sides of the MOS transistor gate, which are often formed by depositing multiple dielectric layers and using anisotropic re - etching. Due to the difference in the thickness of the NMOS and PMOS sidewall film layers, during the sidewall thinning process, over - etching may occur in the thin sidewall area, causing damage to the polysilicon gate.
[0004] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background art of the present invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of the present invention is to provide a method for forming sidewalls of a MOS transistor to solve the problem of over - etching of the gate sidewalls.
[0006] To solve the above - mentioned technical problems, the present invention provides a method for forming sidewalls of a MOS transistor, including the following steps:
[0007] Provide a substrate, on the surface of which several gates are formed to constitute MOS transistors;
[0008] Form a first sidewall, an etch buffer layer, and a second sidewall stacked in sequence on the sidewalls of the gates. Both the first sidewall and the second sidewall are silicon nitride, and the etch buffer layer is formed by passivating the first sidewall;
[0009] Re - etch the second sidewall of the NMOS transistor gate until the film layer on the sidewall of the NMOS transistor gate has the required thickness, wherein the etch selectivity between the silicon nitride and the etch buffer layer is greater than 1.
[0010] Preferably, perform a high - temperature annealing treatment on the first sidewall, so as to form an etch buffer layer with a certain thickness on the outer side of the first sidewall.
[0011] Preferably, the first sidewall is subjected to high-temperature annealing treatment at a temperature of 600-800 °C.
[0012] Preferably, the thickness of the first sidewall is
[0013] Preferably, the first sidewall and the second sidewall are respectively formed by deposition and etching. The deposition methods include low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, ultra-high vacuum chemical vapor deposition, rapid thermal chemical vapor deposition, physical vapor deposition, atomic layer deposition or molecular beam epitaxy.
[0014] Preferably, the thickness of the second sidewall is
[0015] Preferably, the second sidewall of the NMOS transistor gate is etched back until the second sidewall of the NMOS transistor gate is removed.
[0016] Preferably, the etching back of the second sidewall of the NMOS transistor gate includes: when etching back the second sidewalls of the NMOS transistor and the PMOS transistor simultaneously, until the film layer on the PMOS transistor gate has the required thickness, covering a protective layer on the PMOS transistor gate, and then etching the second sidewall of the NMOS transistor.
[0017] Preferably, the thickness of the film layer on the sidewall of the PMOS transistor gate is The thickness of the film layer on the sidewall of the NMOS transistor gate is
[0018] Preferably, a phosphoric acid solution is used to etch back the second sidewalls of the PMOS transistor and the NMOS transistor.
[0019] In the method for forming the sidewalls of the MOS transistors provided by the present invention, by providing an etching buffer layer between two layers of silicon nitride, selective etching is performed by utilizing the difference in etching rates between the etching buffer layer and the silicon nitride, protecting the gate during the etching process, and avoiding over-etching of the sidewalls of the MOS transistor gates. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:
[0021] Figure 1 is a schematic diagram of the structure of a MOS transistor in the prior art;
[0022] Figure 2 is a schematic diagram of the structure of the first sidewall according to an embodiment of the present invention;
[0023] Figure 3Schematic diagram of an etch stop layer structure according to an embodiment of the present invention;
[0024] Figure 4 Schematic diagram of a second sidewall structure according to an embodiment of the present invention;
[0025] Figure 5 Flowchart according to an embodiment of the present invention;
[0026] Figure 6 Graph showing the relationship between the loss amount of the silicon nitride layer and the usage duration of the phosphoric acid solution.
[0027] In the drawings:
[0028] 100, substrate; 200, N-type well region; 300, P-type well region; 400, gate; 500, silicon oxide; 600, first sidewall; 700, etch buffer layer; 800, second sidewall; 900, isolation structure. Detailed implementation manners
[0029] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in very simplified forms and not drawn to scale, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the emphasis to be shown in each drawing is different, and sometimes different scales are used.
[0030] As used in the present invention, the singular forms "a", "an" and "the" include plural referents. The term "or" is generally used in the sense of including "and / or". The term "several" is generally used in the sense of including "at least one". The term "at least two" is generally used in the sense of including "two or more". In addition, the terms "first", "second", "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end close to the operator, and the term "distal end" generally refers to the end close to the patient. "One end" and "the other end", as well as "proximal end" and "distal end", generally refer to corresponding two parts, which include not only the endpoints. The terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. In addition, as used in the present invention, one element being disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and should not be construed as indicating or implying the spatial position relationship between the two elements, that is, one element may be inside, outside, above, below or on one side of the other element, etc. in any orientation, unless otherwise explicitly specified in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0031] It is found that, as Figure 1 shown, the substrate 100 has an N-type well region 200 and a P-type well region 300. A gate 400 is disposed above the well regions. Sidewalls with different thicknesses are disposed on the sidewalls of the gate 400 to form MOS transistors of corresponding conductive types. Since the gate sidewalls of NMOS transistors and PMOS transistors have different thicknesses, during formation, a relatively thick film layer is often formed on the gate sidewalls, and then a sidewall thinning process is performed to achieve the required thickness. During the thinning process, over-etching may occur in the thin sidewall region, causing damage to the polysilicon gate.
[0032] Based on this, the core idea of the present invention is to protect the gate during etching and avoid over-etching of the MOS transistor gate sidewalls by disposing an etching buffer layer between two layers of silicon nitride and performing selective etching using the difference in etching rates between the etching buffer layer and the silicon nitride.
[0033] Specifically, please refer to Figures 2 - 6 , which is a schematic diagram of an embodiment of the present invention. AsFigure 2 As shown, a method for forming sidewalls of a MOS transistor includes the following steps:
[0034] S1. Provide a substrate 100, on the surface of which several gate electrodes 400 are formed to constitute MOS transistors. The substrate 100 has multiple well regions, such as an N-type well region 200 and a P-type well region 300. As Figure 2 shown, the N-type well region 200 is used to form a PMOS transistor with the top gate electrode 400, and the P-type well region 300 forms an NMOS transistor with the top gate electrode 400. The top of the gate electrode 400 is also covered with silicon oxide 500. The P-type well region 300 and the N-type well region 200 can also be separated by an isolation structure 900, such as a shallow trench isolation (STI) structure.
[0035] Among them, the material of the substrate 100 can include semiconductor materials, insulating materials, conductive materials, or any combination thereof; and the substrate 100 can be a single-layer structure or a multi-layer structure. For example, the substrate 100 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. And, the substrate 100 is, for example, a layered substrate such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0036] S2. Form a first sidewall 600, an etching buffer layer 700, and a second sidewall 800 that are sequentially stacked on the sidewalls of the gate electrode 400. Both the first sidewall 600 and the second sidewall 800 are silicon nitride, and the etching buffer layer 700 is formed by passivating the first sidewall 600. Form the first sidewall 600 on the sidewalls of the gate electrode 400, and dispose the etching buffer layer 700 outside the first sidewall 600. Then continue to form the second sidewall 800 outside the etching buffer layer 700. Both the first sidewall 600 and the second sidewall 800 are silicon nitride.
[0037] Exemplarily, the first sidewall 600 and the second sidewall 800 are formed by deposition and etching respectively. The deposition methods include low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, ultra-high vacuum chemical vapor deposition, rapid thermal chemical vapor deposition, physical vapor deposition, atomic layer deposition or molecular beam epitaxy. By depositing a silicon nitride layer on the gate 400 and the substrate 100 and anisotropically etching the silicon nitride layer, the first sidewall 600 is formed on the sidewalls of the gate 400. After performing a high-temperature annealing process on the first sidewall 600, the second sidewall 800 is formed using the same process. The deposition methods of the first sidewall 600 and the second sidewall 800 can be the same or different. Alternatively, a silicon nitride layer is first deposited on the gate 400 and the substrate 100, directly subjected to a high-temperature annealing process, and then another silicon nitride layer is formed thereon. By anisotropically etching the two silicon nitride layers, the first sidewall 600, the etch buffer layer 700 and the second sidewall 800 are formed on the sidewalls of the gate 400. Here, there is no specific limitation on the methods for forming the first sidewall 600 and the second sidewall 800. The etch buffer layer 700 is formed by high-temperature treatment of silicon nitride, without introducing new media and without the need for re-deposition and etching, thus simplifying the formation process of the etch buffer layer 700.
[0038] As Figure 3 shown, a high-temperature annealing process is performed on the first sidewall 600, so as to form an etch buffer layer 700 with a certain thickness on the outer side of the first sidewall 600. After the silicon nitride on the surface of the first sidewall 600 is heated, the physical and chemical properties of the surface film structure change, forming an etch buffer layer 700. Under the same etching conditions, the etching rate of the etch buffer layer 700 is much lower than that of silicon nitride, increasing the difficulty of etching the first sidewall 600. Selective etching is performed using the etching rate difference between the two sidewalls and the etch buffer layer 700 to avoid damaging the gate 400 due to over-etching.
[0039] Specifically, a phosphoric acid solution is used to etch back the second sidewalls 800 of the PMOS transistor and the NMOS transistor.
[0040] After the deposition of the first sidewall 600, a thermal annealing process is performed in an atmospheric pressure diffusion furnace tube. After the high-temperature process, the physical and chemical properties of the silicon nitride surface layer change, thus forming a structure similar to a "hard film" on the surface. This increases the etching difficulty of the silicon nitride after the high-temperature process, and the etching rate of phosphoric acid on it is greatly reduced, that is, the original two-layer homogeneous silicon nitride structure forms a three-layer structure similar to a sandwich.
[0041] When removing the outer second sidewall 800, since the etching rate of the "hard film" is smaller, this middle layer of "hard film" can serve as the etch buffer layer 700 for phosphoric acid. As Figure 6As shown, for the silicon nitride layer that has undergone a high-temperature process, the loss of the silicon nitride layer is proportional to the cleaning duration using the phosphoric acid solution only after the cleaning duration reaches 9 minutes. Among them is the film thickness of the etching buffer layer 700. It can be found that when the etching time is 9 minutes, the etching amount of the etching buffer layer 700 is while normal silicon nitride can be etched away The etching rates differ by a factor of 10. For the silicon nitride layer that has not undergone a high-temperature process, its etching amount is proportional to the cleaning duration.
[0042] Among them, the first sidewall 600 is subjected to a high-temperature annealing treatment under the condition of 600-800 °C to avoid the problem that the silicon nitride may crack and generate cracks at a relatively high temperature.
[0043] Specifically, the overall thickness of the first sidewall 600 can be the same as or slightly greater than the final required film thickness of the sidewall of the NMOS transistor gate 400. The thickness of the first sidewall 600 is The thickness of the second sidewall 800 can be determined according to the film thickness of the sidewall of the PMOS transistor gate 400, and it is often greater than the film thickness of the sidewall of the PMOS transistor gate 400. The thickness of the second sidewall 800 is
[0044] S3, back-etch the second sidewall 800 of the NMOS transistor gate 400 until the film layer on the sidewall of the NMOS transistor gate 400 has the required thickness. Among them, the etching selectivity of the silicon nitride and the etching buffer layer 700 is greater than 1. Under the same etching conditions, such as using hot phosphoric acid wet etching, the etching rate of silicon nitride is much greater than that of the etching buffer layer 700. Exemplarily, the etching selectivity of the silicon nitride and the etching buffer layer 700 is greater than 10:1.
[0045] In one embodiment, back-etching the second sidewall 800 of the NMOS transistor gate 400 includes: simultaneously back-etching the second sidewalls 800 of the NMOS transistor and the PMOS transistor until the film layer on the PMOS transistor gate 400 has the required thickness, covering a protective layer on the PMOS transistor gate 400, and then etching the second sidewall 800 of the NMOS transistor.
[0046] It can be understood that the material of the protective layer is, for example, photoresist (PR). After the film layer on the gate 400 of the PMOS transistor has the required thickness, a protective layer is covered on the gate 400 of the PMOS transistor to prevent the sidewall from being further etched. In addition, since the first sidewalls 600 on both the PMOS transistor and the NMOS transistor are subjected to high-temperature treatment simultaneously, an etching buffer layer 700 is also present on the gate 400 of the PMOS transistor to prevent the edge of the photoresist from peeling off during subsequent etching and continuously laterally etching the bottom of the gate 400 of the PMOS transistor. The photoresist can be polyimide (PI), bis-benzocyclobutene (BCB), or p-phenylene-2,6-benzobisoxazole (PBO).
[0047] Similarly, after thinning the film layer on the gate 400 of the PMOS transistor to the required thickness, silicon nitride can be heat-treated at a high temperature to form a protective layer, and then the etching process for the film layer on the gate 400 of the NMOS transistor can be controlled to thin the second sidewall 800 of the NMOS transistor.
[0048] Exemplarily, the second sidewall 800 of the NMOS transistor gate 400 is etched back until the second sidewall 800 of the NMOS transistor gate 400 is removed. Or as Figure 4 shown, a part of the second sidewall 800 is still retained, or the second sidewall 800 and a part of the first sidewall 600 are completely removed. Here, the degree of etching back of the second sidewall 800 can be determined according to the thicknesses of the first sidewall 600 and the second sidewall 800 until the film layers with the required thicknesses are present on the sidewalls of the gates 400 of both the PMOS transistor and the NMOS transistor. Among them, the thickness of the film layer on the sidewall of the PMOS transistor gate 400 is The thickness of the film layer on the sidewall of the NMOS transistor gate 400 is
[0049] In other embodiments, the total thickness of the deposited first sidewall 600 and second sidewall 800 is exactly the required thickness of the PMOS transistor gate 400. A protective layer can be directly covered on the PMOS transistor gate 400, and the second sidewall 800 on the NMOS transistor gate 400 is etched back, which has the same processing flow as the above embodiments and will not be specifically described here.
[0050] The second sidewall 800 is etched back using a hot phosphoric acid solution, and the time for the hot phosphoric acid treatment is 30 - 60 s to completely remove the second sidewall 800 and thereby remove a part of the first sidewall 600.
[0051] In the method for forming the sidewall of the MOS transistor provided by the present invention, an etching buffer layer 700 is provided between two layers of silicon nitride, and selective etching is performed by utilizing the difference in etching rates between the etching buffer layer 700 and the silicon nitride to protect the gate 400 during the etching process and avoid over-etching of the sidewall of the MOS transistor gate 400. Further, by performing a high-temperature annealing treatment on the first sidewall 600, after the silicon nitride is heated, the physical and chemical properties of the surface film structure will change to form an etching buffer layer 700. Under the same etching conditions, the etching rate of the etching buffer layer 700 is much lower than that of the silicon nitride, increasing the difficulty of etching the first sidewall 600 and avoiding damage to the gate 400 caused by over-etching the sidewall of the gate 400 during the back-etching and thinning process. Moreover, the etching buffer layer 700 is formed by high-temperature treatment of silicon nitride, without introducing new media and without the need for re-deposition and etching, simplifying the formation process of the etching buffer layer 700. Also, during the process of back-etching the second sidewall 800, it is possible to avoid the peeling of the edge of the photoresist and continuously laterally etch the bottom of the PMOS transistor gate 400.
[0052] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for forming sidewalls of a MOS transistor, characterized in that, It includes the following steps: Provide a substrate, on the surface of which several gates are formed to constitute MOS transistors; Form a first sidewall, an etching buffer layer and a second sidewall which are stacked in sequence on the sidewalls of the gates. Both the first sidewall and the second sidewall are silicon nitride, and the etching buffer layer is formed by passivating the first sidewall; Etch back the second sidewall of the NMOS transistor gate until the film layer on the sidewall of the NMOS transistor gate has a required thickness, wherein the etching selectivity between the silicon nitride and the etching buffer layer is greater than 1.
2. The method for forming the sidewall of the MOS transistor according to claim 1, wherein Perform a high-temperature annealing treatment on the first sidewall, so as to form an etching buffer layer with a certain thickness on the outer side of the first sidewall.
3. The method for forming the sidewall of the MOS transistor according to claim 2, wherein Perform a high-temperature annealing treatment on the first sidewall under the condition of 600-800 °C.
4. The method for forming the sidewall of the MOS transistor according to claim 1, wherein The thickness of the first side wall is 5. The method for forming a sidewall of the MOS transistor according to claim 1, wherein Form the first sidewall and the second sidewall by deposition and etching respectively. The deposition method is low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, ultra-high vacuum chemical vapor deposition, rapid thermal chemical vapor deposition, physical vapor deposition, atomic layer deposition or molecular beam epitaxy.
6. The method for forming the sidewall of the MOS transistor according to claim 1, characterized in that, The thickness of the second side wall is 7. The method for forming a sidewall of a MOS transistor according to claim 1, wherein Etch back the second sidewall of the NMOS transistor gate until the second sidewall of the NMOS transistor gate is removed.
8. The method for forming a sidewall of the MOS transistor according to claim 7, wherein Etching back the second sidewall of the NMOS transistor gate includes: simultaneously etching back the second sidewalls of the NMOS transistor and the PMOS transistor until the film layer on the PMOS transistor gate has a required thickness, covering a protective layer on the PMOS transistor gate, and then etching the second sidewall of the NMOS transistor.
9. The method for forming the sidewall of the MOS transistor according to claim 8, wherein The thickness of the film layer on the sidewall of the PMOS transistor gate is The thickness of the film layer on the sidewall of the NMOS transistor gate is 10. The method for forming the sidewall of the MOS transistor according to claim 8, wherein Use a phosphoric acid solution to etch back the second sidewalls of the PMOS transistor and the NMOS transistor.