Systems, circuits, and methods for reducing transients during mode changes in multilevel converters

Abstract

The present disclosure relates to systems, circuits, and methods for reducing transients during mode changes in multilevel converters. In one embodiment, the multilevel converter is capable of operating in a charge pump mode by open-loop control and in a regulated mode by closed-loop control. A control circuit for controlling a pulse width modulation (PWM) signal of a multilevel converter includes: a compensation signal generation circuit configured to generate a compensation signal; and a PWM circuit configured to generate a PWM signal having a target duty cycle based on the compensation signal when the multilevel converter is operated in the charge pump mode. A PWM signal having a target duty cycle is used to control a multilevel converter in a mode change from a charge pump mode to a regulation mode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of U.S. Provisional Application No. 63 / 387,986, filed on Dec. 19, 2022, the entire content of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to switched - capacitor circuit multilevel buck converters, and more particularly, to systems, circuits, and methods for reducing transients during mode changes in multilevel converters. Background art

[0004] Many electronic products, especially mobile computing and / or communication products and components (e.g., laptop computers, ultra - book computers, tablet devices, LCD and LED displays) require multiple voltage levels. For example, a power amplifier for a radio - frequency transmitter may require a relatively high voltage (e.g., 12 volts (V) or higher), and a logic circuit system may require a low voltage level (e.g., 1V to 2V). Some other circuits may require intermediate voltage levels (e.g., 5V to 10V). Various configurations of switched - capacitor power - conversion circuits (sometimes also referred to as “charge pumps”) provide voltage conversion (i.e., boost, buck, or bidirectional) between a high - side voltage and a low - side voltage through a controlled charge transfer between capacitors in the circuit. Summary of the invention

[0005] Embodiments of the present disclosure may provide systems, circuits, and methods for reducing transients during mode changes in multilevel converters. In one embodiment, a multilevel converter is capable of operating in a charge - pump mode by open - loop control and in a regulation mode by closed - loop control. A control circuit for controlling a pulse - width modulation (PWM) signal for the multilevel converter includes a compensation - signal generation circuit configured to generate a compensation signal, and a PWM circuit configured to generate a PWM signal with a target duty cycle based on the compensation signal when the multilevel converter is operating in the charge - pump mode. The PWM signal with the target duty cycle is used to control the multilevel converter during a mode change from the charge - pump mode to the regulation mode.

[0006] In another embodiment, a method for controlling a multilevel converter includes determining a duty cycle of a pulse width modulation (PWM) signal, the PWM signal being configured to control the multilevel converter. The method further includes determining at least one of the following: whether the duty cycle of the PWM signal is decreasing, increasing, or remaining unchanged, or whether the duty cycle of the PWM signal is less than or greater than a target duty cycle. The method further includes increasing a parameter to increase the duty cycle of the PWM signal in response to determining that the duty cycle of the PWM signal is decreasing or determining that the duty cycle of the PWM signal is less than the target duty cycle. The method further includes decreasing a parameter to decrease the duty cycle of the PWM signal in response to determining that the duty cycle of the PWM signal is increasing or determining that the duty cycle of the PWM signal is greater than the target duty cycle.

[0007] In another embodiment, a system for reducing transients during a power conversion mode change includes a multilevel converter configured to operate in a charge pump mode or a regulation mode to provide an output voltage signal. The system further includes a control circuit configured to control the multilevel converter to operate at a 50% duty cycle in the charge pump mode by open-loop control or at a variable duty cycle in the regulation mode by closed-loop control; and to generate a pulse width modulation (PWM) signal having a target duty cycle when the multilevel converter is operating in the charge pump mode. The PWM signal having the target duty cycle is used to control the multilevel converter during a mode change from the charge pump mode to the regulation mode.

[0008] In yet another embodiment, a system for reducing transients during a mode change in a switched capacitor circuit multilevel buck converter is disclosed. The system includes a switched capacitor-based buck converter and a control circuit for controlling the switched capacitor-based buck converter. The control circuit is capable of open-loop and closed-loop control of the switched capacitor-based buck converter. During open-loop control, the control circuit is configured to control the duty cycle of one or more control signals of the switched capacitor-based buck converter at, for example, approximately 33.3% or 66.6% using feedback from the output of the switched capacitor-based buck converter.

[0009] It should be understood that the foregoing general description and the following detailed description are merely exemplary and explanatory and are not restrictive of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a circuit diagram of an example switched capacitor circuit multilevel buck converter consistent with the disclosed embodiments.

[0011] Figure 2 is a block diagram showing example aspects of a switched capacitor circuit multilevel buck converter operating in an open-loop mode consistent with the disclosed embodiments.

[0012] Figure 3A is a block diagram showing exemplary aspects of a switched capacitor circuit multilevel buck converter operating in a closed-loop voltage mode consistent with the disclosed embodiments.

[0013] Figure 3B is a circuit diagram showing exemplary aspects of a controller for a switched capacitor circuit multilevel buck converter operating in a closed-loop voltage mode consistent with the disclosed embodiments.

[0014] Figure 4A is a block diagram showing exemplary aspects of a switched capacitor circuit multilevel buck converter operating in a closed-loop current mode consistent with the disclosed embodiments.

[0015] Figure 4B is a circuit diagram showing exemplary aspects of a controller for a switched capacitor circuit multilevel buck converter operating in a closed-loop current mode consistent with the disclosed embodiments.

[0016] Figures 5A to 5B is a block diagram showing exemplary aspects of changing an operating mode in a switched capacitor circuit multilevel buck converter consistent with the disclosed embodiments.

[0017] Figure 6 is a state flow diagram showing exemplary aspects of controlling a switched capacitor circuit multilevel buck converter consistent with the disclosed embodiments. Detailed Description

[0018] The following disclosure provides many different exemplary embodiments or examples for implementing different features of the provided subject matter. Specific simplified examples of components and arrangements are described below to explain the present disclosure. Of course, these are merely examples and are not intended to be limiting. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0019] Many electronic products, particularly mobile computing and / or communication products and components (e.g., laptop computers, ultrabook computers, tablet devices, LCD and LED displays) require multiple voltage levels. For example, a power amplifier for a radio frequency transmitter may require a relatively high voltage (e.g., 12 volts (V) or higher), and logic circuitry may require a low voltage level (e.g., 1V to 2V). Some other circuits may require intermediate voltage levels (e.g., 5V to 10V). Power converters are typically used to generate lower or higher voltages from a common power source (e.g., a battery) to meet the power requirements of different components in an electronic product.

[0020] Figure 1 FIG. 100 is a circuit diagram of an exemplary switched capacitor circuit multilevel buck conversion circuit that is consistent with the disclosed embodiments. Various embodiments of the switched capacitor power conversion circuit provide a high-side voltage (e.g., input voltage V IN 101) and a low-side voltage (e.g., output voltage V OUT 108) through controlled charge transfer between flying capacitors (e.g., 103a-b) in the circuit (e.g., buck conversion). The charge pump steps down the input voltage by storing a portion of the input voltage on each flying capacitor (e.g., 103a-b). Switches (e.g., 102a-f) coupled to the two terminals of each flying capacitor are typically used to perform charge transfer and configure the charge pump to provide a desired voltage conversion ratio. The control of the charge transfer between flying capacitors 103a-b typically utilizes circuit elements that act as "switches", such as diodes or FET transistors. The switched capacitor circuit multilevel buck conversion circuit 100 may include an inductor 104, and the inductor 104 is configured such that the circuit 100 operates as a buck converter. It should be understood that the principles of the present disclosure can be applied to any other type of buck DC-DC converter, such as boost, buck-boost, or cuk converters. Finally, the switched capacitor circuit multilevel buck conversion circuit 100 may include a controller 105 to control the operation of switches 102a-f. For example, the controller 105 may provide control signals, such as IN1, IN2, and IN3, to control the timing of the opening and closing of switches 102a-f, thereby controlling the charge transfer between flying capacitors 103a-b. Thus, the controller 105 can control the output voltage V OUT 108 and the voltage buck conversion ratio (V OUT 108 / V IN 101).

[0021] Figure 2 FIG. 200 is a block diagram showing exemplary aspects of a switched capacitor circuit multilevel buck converter operating in open-loop mode that is consistent with the disclosed embodiments. In various embodiments, the controller 105 of the switched capacitor circuit multilevel buck conversion circuit 100 may operate in open-loop mode (sometimes referred to as "charge pump" mode) or closed-loop mode (sometimes referred to as "regulation" mode). For example, in open-loop mode, the controller 105 may not utilize feedback from the output voltage V OUT 108 to determine the timing of the opening and closing of switches 102a-f to control the charge transfer between flying capacitors 103a-b. Instead, the controller 105 may provide control signals IN1, IN2, and IN3 to close and open switches 102a-f with a fixed duty cycle (on-off ratio) (e.g., 33.3% or 66.6%) (see, for exampleFigure 2 component 210). For example, referring to Figure 1 the four-level buck converter shown, the control signals IN1, IN2, and IN3 can each be provided with a duty cycle of 33.3% (on) (and 120° out of phase with each other) to obtain 1 / 3*V IN of the output voltage V OUT 108, or each be provided with a duty cycle of 33.3% (off) (i.e., a duty cycle of 66.6% (on)) (and 120° out of phase with each other) to obtain 2 / 3*V IN of the output voltage V OUT 108. In such a scenario, Figure 1 the voltage V indicated in LX will experience a 50% duty cycle, indicating a 50% duty cycle for the switching state transition. Those of ordinary skill in the art will understand how to set the duty cycle and phase of the control signals of the N-level converter to achieve each of the N levels in open-loop mode.

[0022] Referring to Figure 1 , in some embodiments of the switched capacitor circuit multi-level buck converter circuit 100, the capacitors 103a-b and the output capacitor C OUT 106 can be sized such that when the controller 105 provides the control signals IN1, IN2, and IN3 with a fixed duty cycle, the voltages V C1 and V C2 across the flying capacitors 103a and 103b respectively during operation are approximately 1 / 3*V IN 101 and 2 / 3*V IN 101.

[0023] Additionally, in open-loop mode, the controller 105 can control the phase of the control signals IN1, IN2, and IN3 such that the output voltage V OUT 108 is approximately 1 / 3*V IN 101 or 2 / 3*V IN 101. For example, as shown in Figure 2 Table 220 of, to achieve an output voltage V IN 108 of approximately 1 / 3*V OUT 101 (with 0V, 1 / 3*V IN 101, 2 / 3*V IN 101, and V INFor the 4-level converter of the output voltage of 101, at level 2), in open-loop mode, the controller 105 can close one of the switches 102a, 102b, or 102c (i.e., the switch coupled to one terminal of the flying capacitor 103a-b) at a time, and simultaneously open the corresponding switch 102d, 102e, or 102f (i.e., the switch coupled to the other terminal of the flying capacitor 103a-b).

[0024] As an example, the controller 105 can assert IN1 and IN2 as low (logic "0"), while asserting IN3 as high (logic "1"). When the controller asserts the {IN1 IN2 IN3} code {0 0 1}, the switch 102a can be closed, while the switches 102b and 102c can be opened. At the other terminals of the flying capacitors 103a and 103b, the switch 102f can be opened, while the switches 102d and 102e can be closed. In this configuration, the output voltage V OUT 108 can be approximately 1 / 3 * V IN 101 (i.e., a conversion ratio of 1 / 3 (level 2)).

[0025] Similarly, the controller 105 can assert IN1 and IN3 as low (logic "0"), while asserting IN2 as high (logic "1"). When the controller asserts the {IN1 IN2 IN3} code {0 1 0}, the switch 102b can be closed, while the switches 102a and 102c can be opened. At the other terminals of the flying capacitors 103a and 103b, the switch 102e can be opened, while the switches 102d and 102f can be closed. In this configuration, the output voltage V OUT 108 can be approximately 1 / 3 * V IN 101 (i.e., a conversion ratio of 1 / 3 (level 2)).

[0026] Similarly, the controller 105 can assert IN2 and IN3 as low (logic "0"), while asserting IN1 as high (logic "1"). When the controller asserts the {IN1 IN2 IN3} code {1 0 0}, the switch 102c can be closed, while the switches 102a and 102b can be opened. At the other terminals of the flying capacitors 103a and 103b, the switch 102d can be opened, while the switches 102e and 102f can be closed. In this configuration, the output voltage V OUT 108 can be approximately 1 / 3 * V IN 101 (i.e., a conversion ratio of 1 / 3 (level 2)). In some embodiments, the controller 105 can sequentially cycle through the level 2 codes {0 01}, {0 1 0}, and {1 0 0} at a duty cycle of 33% respectively to achieve an output voltage V of approximately 1 / 3 * V IN 101OUT 108 (i.e., a conversion ratio of 1 / 3 (level 2)).

[0027] Additionally, in the open-loop mode, the controller 105 can control the phases of the control signals IN1, IN2, and IN3 such that the output voltage V OUT 108 is approximately 2 / 3 * V IN 101. For example, as Figure 2 shown in Table 230, to achieve an output voltage V IN 108 of approximately 2 / 3 * V OUT 101 (output voltage levels 0V, 1 / 3 * V IN 101, 2 / 3 * V IN 101, and V IN 101 for a 4-level converter at level 3), in the open-loop mode, the controller 105 can close two of the switches 102a, 102b, or 102c (i.e., the switches coupled to one terminal of the flying capacitor 103a-b) at a time and simultaneously open the two corresponding switches 102d, 102e, or 102f (i.e., the switches coupled to the other terminal of the flying capacitor 103a-b).

[0028] As an example, the controller 105 can assert IN1 as low (logic "0") while asserting IN2 and IN3 as high (logic "1"). When the controller asserts the {IN1 IN2 IN3} code {0 1 1}, switch 102c can open while switches 102a and 102b can close. At the other terminal of the flying capacitors 103a and 103b, switch 102d can close while switches 102e and 102f can open. In this configuration, the output voltage V OUT 108 can be approximately 2 / 3 * V IN 101 (i.e., a conversion ratio of 2 / 3 (level 3)).

[0029] Similarly, the controller 105 can assert IN2 as low (logic "0") while asserting IN1 and IN3 as high (logic "1"). When the controller asserts the {IN1 IN2 IN3} code {1 0 1}, switch 102b can open while switches 102a and 102c can close. At the other terminal of the flying capacitors 103a and 103b, switch 102e can close while switches 102d and 102f can open. In this configuration, the output voltage V OUT 108 can be approximately 2 / 3 * V IN 101 (i.e., a conversion ratio of 2 / 3 (level 3)).

[0030] Similarly, the controller 105 can assert IN3 low (logic "0") while asserting IN1 and IN2 high (logic "1"). When the controller asserts the {IN1 IN2 IN3} code {1 1 0}, switch 102a can be opened, while switches 102b and 102c can be closed. At the other terminals of flying capacitors 103a and 103b, switch 102f can be closed, while switches 102d and 102e can be opened. In this configuration, the output voltage V OUT 108 can be approximately 2 / 3 * V IN 101 (i.e., a conversion ratio (level 3) of 2 / 3). In some embodiments, the controller 105 can sequentially cycle through the level 3 codes {0 1 1}, {1 0 1}, and {1 1 0} with a 33% duty cycle (off) (i.e., a 66.6% duty cycle (on)) respectively to achieve an output voltage V IN 108 of approximately 2 / 3 * V OUT 101 (i.e., a conversion ratio (level 3) of 2 / 3).

[0031] Figure 3A is a block diagram showing example aspects of a switched-capacitor circuit multilevel buck converter operating in closed-loop voltage mode consistent with the disclosed embodiments. In various embodiments, the controller 105 of the switched-capacitor circuit multilevel buck conversion circuit 100 can operate in an open-loop mode (sometimes referred to as a "charge pump" mode) or a closed-loop mode (sometimes referred to as a "regulation" mode). For example, in the closed-loop mode, the controller 105 can utilize feedback from the output voltage V OUT 108 to determine the timing of opening and closing of switches 102a-f to control the charge transfer between flying capacitors 103a-b. Thus, in some embodiments, the controller 105 can provide control signals IN1, IN2, and IN3 with a variable duty cycle (on-off ratio) to open and close switches 102a-f to maintain a constant output voltage V OUT 108.

[0032] Referring to Figure 3A , in some embodiments of the switched-capacitor circuit multilevel buck conversion circuit 100, the controller 105 operating in closed-loop voltage mode can utilize pulse-width modulation techniques to vary the duty cycle of control signals IN1, IN2, and IN3 to open and close switches 102a-f. For example, as Figure 3AAs shown (see, e.g., element 310), the controller 105 may include a comparator that compares the voltage sawtooth waveform 306 with the COMP signal (representing the target output voltage) to modulate the width of the generated pulses provided to the logic AND PWM to level converter 340, which may provide control signals to generate an output voltage V that is maintained at a constant voltage OUT 108. When operating in this closed-loop voltage mode, the switched capacitor circuit multilevel buck conversion circuit 100 may generate an output voltage V in the range of approximately 0V to approximately V IN 101 OUT 108.

[0033] Figure 3B FIG. 300 is a circuit diagram showing an example aspect of a controller for a switched capacitor circuit multilevel buck converter operating in a closed-loop voltage mode in accordance with the disclosed embodiments. In some embodiments, the controller 105 operating in the closed-loop voltage mode may include a comparator 305 (i.e., a PWM circuit) to modulate the width of the generated pulses (e.g., a PWM signal) provided to the logic AND PWM to level converter 340, which may provide control signals to generate an output voltage V that is maintained at a constant voltage OUT 108. The comparator 305 may compare the voltage sawtooth waveform 306 with the COMP signal to modulate the width of the generated pulses. As discussed further below, various techniques may be used to manipulate / control the COMP signal.

[0034] Figure 4A FIG. is a block diagram showing an example aspect of operating a switched capacitor circuit multilevel buck converter in a closed-loop current mode in accordance with the disclosed embodiments. As described above, in various embodiments, the controller 105 of the switched capacitor circuit multilevel buck conversion circuit 100 may operate in an open-loop mode (sometimes referred to as a "charge pump" mode) or a closed-loop mode (sometimes referred to as a "regulation" mode). For example, in the closed-loop mode, the controller 105 may utilize feedback from the output voltage V OUT 108 as well as the output current to determine the timing of opening and closing of the switches 102a-f to control the charge transfer between the flying capacitors 103a-b. Thus, in some embodiments, the controller 105 may provide control signals IN1, IN2, and IN3 with a variable duty cycle (on-off ratio) to close and open the switches 102a-f to maintain a constant output voltage V OUT 108.

[0035] Refer to Figure 4A, in some embodiments of the switched capacitor circuit multi-level buck conversion circuit 100, the controller 105 operating in closed-loop current mode can utilize pulse width modulation techniques to change the duty cycles of the control signals IN1, IN2, and IN3 to turn on and off the switches 102a-f. For example, as Figure 4A shown (see, for example, element 410), the controller 105 can include a comparator that compares the current I of the inductor 104 L sawtooth waveform 406 with the COMP signal to modulate the width of the generated pulse provided to the logic AND PWM to level converter 440, which can provide control signals to maintain a constant output voltage V OUT 108. When operating in this closed-loop current mode, the switched capacitor circuit multi-level buck conversion circuit 100 can generate an output voltage V IN within a range between approximately 0V and approximately V OUT 101.

[0036] Figure 4B FIG. 400 is a circuit diagram showing example aspects of a controller for a switched capacitor circuit multi-level buck converter operating in closed-loop current mode consistent with the disclosed embodiments. In some embodiments, the controller 105 operating in closed-loop current mode can include a comparator 405 (i.e., a PWM modulator) to modulate the width of the generated pulse (e.g., a PWM signal) provided to the logic AND PWM to level converter 440, which can provide control signals to generate a constant output voltage V OUT 108. The comparator 405 can compare the current I L sawtooth (or triangular) waveform 406 with the COMP signal to modulate the width of the generated pulse. As discussed further below, various techniques can be used to control the COMP signal.

[0037] As discussed above with reference to Figure 2 , Figure 3A -B, and Figure 4A -B, in a switched capacitor circuit multi-level buck converter, the input voltage V IN 101 can be stepped down using a closed-loop "regulation" mode to regulate the output voltage V OUT 108 to a desired level using voltage mode or current mode control, or the input voltage V IN101 can use an open-loop "charge pump" mode to step down the voltage. Depending on the specific application, sometimes it is desirable to operate the switched capacitor circuit multilevel step-down converter in the "charge pump" mode, sometimes in the "regulation" mode, and sometimes to switch between the two operating modes. However, the inventors have recognized herein that the transition from one operating mode to another (e.g., from the "charge pump" mode to the "regulation" mode) may cause a transient in the output voltage V OUT 108, which may take an undesirably long time to recover (depending on the system bandwidth), and may also cause an overvoltage fault with respect to the output voltage V OUT 108.

[0038] In particular, with respect to Figure 2 , the controller 105 operating in the open-loop "charge pump" mode may not utilize feedback from the output voltage V OUT 108 to determine the timing of opening and closing of the switches 102a-f to control the charge transfer between the flying capacitors 103a-b. Thus, the controller 105 operating in the "charge pump" mode may not utilize any pulse width modulation techniques (such as Figure 3A -B and Figure 4A -B) to change the duty cycle of the control signals IN1, IN2, and IN3 to close and open the switches 102a-f. However, in order for the controller 105 to quickly transition from the "charge pump" mode to the "regulation" mode (closed-loop current or voltage mode), the circuit system may need to operate even though the pulse width modulation circuitry is not used in the open-loop "charge pump" mode. Thus, in some embodiments, the pulse width modulation circuit system may continue to operate even when the pulse width modulation circuit is not used to change the duty cycle of the control signals IN1, IN2, and IN3 in the open-loop "charge pump" mode.

[0039] During such operation in the open-loop "charge pump" mode, the pulse width modulation circuit system may be undesirably pre-conditioned to provide an extreme COMP signal to modulate the width of the generated pulses. This is because during open-loop "charge pump" mode operation, the output voltage V OUT 108 can decrease as the load current increases. For example, with respect to Figure 3B the pulse width modulation circuit system shown, this decrease in the output voltage V OUT 108 can cause the transconductance amplifier Gm 303 to output a COMP signal when comparing the decreased output voltage V OUT 108 with the reference voltage VREF 301 to compensate for the output voltage V OUT108. For example, Gm 303 may output a current signal proportional to the difference in voltage input to it, which may be converted to a voltage signal using an output resistor and capacitor. However, since controller 105 operates in an open-loop "charge pump" mode, the COMP signal may not be used to change the duty cycle of control signals IN1, IN2, and IN3 (see Figure 1 ), and therefore the output voltage V OUT 108 can remain lowered, even though the COMP signal attempts to compensate for the lowered output voltage V OUT 108. This may result in the COMP signal railing high in open loop "charge pump" mode. Similarly, for example, Figure 4B The pulse width modulation circuit system shown in FIG, the output voltage V OUT This reduction in 108 can allow the transconductance amplifier Gm 403 to reduce the output voltage V OUT 108 outputs a COMP signal when compared with the reference voltage VREF 401 to compensate the output voltage V OUT 108. For example, Gm 403 may output a current signal proportional to the difference in voltage input to it, which may be converted to a voltage signal using an output resistor and capacitor. However, since controller 105 operates in an open-loop "charge pump" mode, the COMP signal may not be used to change the duty cycle of control signals IN1, IN2, and IN3 (see Figure 1 ), and therefore the output voltage V OUT 108 can keep decreasing, even though the COMP signal attempts to compensate for the reduced output voltage V OUT 108. This can cause the COMP signal to go high in open loop "charge pump" mode.

[0040] Because the COMP signal has been compensated to the maximum extent possible during the open-loop "charge pump" mode of operation, e.g., the COMP signal has been raised, the operational effect of the operating pulse width modulation circuitry, even when the operating pulse width modulation circuitry is not used in the open-loop "charge pump" mode, can be to bias or pre-condition the pulse width modulation circuitry so that high duty cycle values of the control signals IN1, IN2, and IN3 are set when the switched capacitor circuit multi-level buck converter transitions from the "charge pump" mode to the "regulation" mode. In various embodiments, this can bias or pre-condition the pulse width modulation circuitry so that a high duty cycle state is set in the "regulation" closed-loop voltage mode control or a high current state is set in the "regulation" closed-loop peak or average current mode control when transitioning from the open-loop "charge pump" mode. Such biasing or pre-conditioning can cause the output voltage V OUT108, which may take an undesirably long time to recover (depending on the system bandwidth) and may also cause a voltage drop relative to the output voltage V OUT 108 An overvoltage fault occurred.

[0041] Embodiments of the present disclosure can mitigate and / or prevent the pulse width modulation circuitry from driving the COMP signal to extreme or undesirable levels during open-loop "charge pump" mode operation. For example, during open-loop "charge pump" mode operation, the controller 105 can set the COMP voltage to a voltage close to the voltage at which the switched capacitor circuit multi-level buck converter needs to be when it transitions from "charge pump" mode to "regulation" mode. For example, to transition from "charge pump" mode to "regulation" closed-loop voltage mode, the controller 105 can set the COMP voltage such that V LX The duty cycle of the signal is approximately 50%. As another example, to transition from "charge pump" mode to "regulate" closed-loop peak or average current mode, the controller 105 may set the COMP voltage so that V LX The duty cycle of the signal is less than about 50%, for example, preferably with a linear range of COMP voltage versus duty cycle and a slope compensation of less than one.

[0042] Reference Figure 3B and Figure 4B To achieve the desired COMP voltage, the controller 105 may use a digitally controlled potentiometer (DCP) 302 / 402 (i.e., an adjustable resistor whose resistance is controlled by a digital code (e.g., a series of bits)) to adjust the resistance of the feedback resistor divider so that the feedback voltage V at node FB of Gm 303 / 403 is FB At or near the reference voltage V REF 301 / 401, or so that the desired target COMP voltage is achieved. Once the desired target COMP is approached, adjacent DCP codes may be generated to maintain the desired target COMP voltage and duty cycle (e.g., 33.3%). This approach may be advantageously employed in an example embodiment using a field programmable gate array. Alternatively, the controller 105 may adjust the reference voltage V REF 301 / 401, so that the desired target COMP voltage is achieved. In some alternatives, the digitally controlled V REF 301 / 401 directly with the output voltage V OUT 108 compares the voltage without using a resistor divider circuit. Such a scheme can be advantageously employed in example integrated circuit implementations.

[0043] In yet another alternative, the controller 105 may include analog circuitry 307 / 407 that compares the target COMP voltage 308 / 408 with the current COMP signal and adjusts the current COMP signal to a desired target level. In some embodiments, the analog circuitry 307 / 407 may be coupled to the COMP terminal, for example, by closing switches 309 / 409, while other components of the pulse width modulation circuitry may be disconnected, for example, by opening switches 304 / 404. For example, to transition from a "charge pump" mode to a "regulation" closed-loop voltage mode, the controller 105 may set the COMP voltage to the midpoint of the voltage sawtooth waveform 306. Similarly, to transition from a "charge pump" mode to a "regulation" closed-loop current mode, the controller 105 may measure the load current and accordingly determine the target COMP voltage, and then may provide this target COMP voltage as target COMP 408. It should be understood that any combination of the above techniques may be used to achieve a desired target COMP voltage during operation in the open-loop "charge pump" mode.

[0044] Figures 5A to 5B FIG. 500 is a block diagram illustrating an example aspect of changing an operating mode in a switched capacitor circuit multilevel buck converter consistent with the disclosed embodiments. Referring Figure 5A thereto, in some embodiments, a controller 105 of an exemplary four-level switched capacitor circuit buck converter circuit 100 may operate in an open-loop "charge pump" mode or a closed-loop mode (voltage or current control) "regulation" mode. As Figure 5A shown, the four-level switched capacitor circuit buck converter circuit 100 may be capable of accepting an input voltage V IN 101 and providing four fixed output voltages V OUT 108 levels, for example, 0 (level 1), 1 / 3*V IN 101 (level 2), 2 / 3*V IN 101 (level 3), and V IN 101 (level 4) in an open-loop "charge pump" mode. Specifically, when providing a level 2 or level 3 output voltage V OUT 108, the switched capacitor circuit buck converter circuit 100 may operate in an open-loop (OL) "charge pump" mode, using a fixed duty cycle of 33.3% or 66.6% for the control signals IN1, IN2, and IN3. As described above with reference to Figure 2 thereto, in some embodiments, the controller 105 may sequentially cycle through the level 2 codes {0 0 1}, {0 1 0}, and {1 0 0} to achieve an output voltage V IN 108 of approximately 1 / 3*V OUT108 (i.e., a conversion ratio of 1 / 3 (level 2)). Similarly, in some embodiments, the controller 105 may sequentially cycle through the level 3 codes {0 1 1}, {1 0 1}, and {1 1 0} to achieve an output voltage V of approximately 2 / 3*V IN of 101 OUT 108 (i.e., a conversion ratio of 2 / 3 (level 3)).

[0045] Additionally, as Figure 5A shown, the switched capacitor circuit buck converter 100 may provide a variable output voltage V between fixed levels using a closed-loop mode (voltage or current control) "regulation" mode OUT of 108. For example, between 0 (level 1) and 1 / 3*V IN of 101 (level 2), the switched capacitor circuit buck converter 100 may operate in a closed-loop "regulation" mode, using varying duty cycles (minimum to maximum) for the control signals IN1, IN2, and IN3, to continuously control the output voltage V IN of 108 between 0 and 1 / 3*V OUT of 101 - Δ, where Δ is the voltage boundary zone window of V OUT 108. Similarly, between 1 / 3*V IN of 101 (level 2) and 2 / 3*V IN of 101 (level 3), the switched capacitor circuit buck converter 100 may operate in a closed-loop "regulation" mode, using varying duty cycles (minimum to maximum) for the control signals IN1, IN2, and IN3, to continuously control the output voltage V OUT of 108 between 1 / 3*V IN of 101 + Δ and 1 / 3*V IN of 101 - Δ, where Δ is the voltage boundary zone window of V OUT 108. Additionally, between 2 / 3*V IN of 101 (level 3) and V IN of 101 (level 4), the switched capacitor circuit buck converter 100 may operate in a closed-loop "regulation" mode, using varying duty cycles (minimum to maximum) for the control signals IN1, IN2, and IN3, to continuously control the output voltage V OUT of 108 between 2 / 3*V IN of 101 + Δ and V IN of 101.

[0046] Referring to Figure 5B , at level 2 (1 / 3*V IN of 101) or level 3 (2 / 3*V INDuring open-loop “charge pump” mode operation of (101), the controller 105 may set the COMP voltage close to the voltage at which the switched capacitor circuit multilevel buck converter needs to be when transitioning from “charge pump” mode to “regulation” mode. For example, in order to transition from “charge pump” mode to “regulation” closed-loop voltage mode near level 2 (1 / 3*V IN 101 ± Δ) or level 3 (2 / 3*V IN 101 ± Δ), the controller 105 may set the COMP voltage such that the duty cycle of the switching state transition (e.g., the duty cycle of the V LX signal) is approximately 50% (e.g., 50% ± Σ, where Σ is the boundary zone window of the equivalent duty cycle). As another example, in order to transition from “charge pump” mode to “regulation” closed-loop peak or average current mode near level 2 (1 / 3*V IN 101 ± Δ) or level 3 (2 / 3*V IN 101 ± Δ), the controller 105 may set the COMP voltage such that the duty cycle of the V LX signal is less than approximately 50% (e.g., 50% - Σ, where Σ is the boundary zone window of the equivalent duty cycle), for example preferably having a linear range of the COMP voltage with respect to the duty cycle and slope compensation less than one.

[0047] As explained above with reference to Figure 3B and Figure 4B To achieve the desired COMP voltage, the controller 105 may use the digital control potentiometer DCP 302 / 402 to adjust the resistance of the feedback resistor divider such that the feedback voltage V FB at the node FB of the Gm 303 / 403 is at or near the reference voltage V REF 301 / 401, or such that the desired target COMP voltage is achieved. Once near the desired target COMP, adjacent DCP codes may be switched to maintain the desired target COMP voltage and the V LX signal duty cycle (e.g., 50%). Such a scheme may be advantageously employed in an example implementation using a field programmable gate array. Alternatively, the digitally controlled V REF 301 / 401 may also be used with a fixed resistor divider. As another alternative, the digitally controlled V REF 301 / 401 may be directly compared with the output voltage V OUT 108 without using a resistor divider circuit. Such a scheme may be advantageously used in an example integrated circuit implementation.

[0048] Figure 6is a state flow diagram 600 of an example aspect showing selection of a DCP code to control the resistance of a feedback resistor divider (or digital ground selection of V REF 301 / 401 to control the output of transconductance amplifiers Gm 303 / 403) and to achieve a desired target COMP voltage. At state 602, the "charge pump" mode may be inactive (see 610), and thus control of the DCP code may not be performed. Once the "charge pump" mode has been activated, the duty cycle generated by pulse width modulation (PWMDC) may be measured (e.g., twice, to detect movement of the PWM DC) (see 620). The regulated PWM DC may be measured by oversampling the PWM signal and may be averaged over 1, 2, 4, 8, or N PWM cycles, where N is an integer (odd or even). For example, in an FPGA implementation, the division operation to perform the averaging may be carried out by using a right shift operation, advantageously averaging the PWM signal over 2 k cycles.

[0049] Then, the state of controller 105 may transition to state 604, where the PWM DC remains unchanged (see 630). Controller 105 may determine whether the PWM DC should be decreased or increased to achieve the desired target COMP voltage and V LX signal duty cycle (e.g., 50%). If the PWM DC has decreased, or the PWM DC is less than the target PWM DC (taking into account any hysteresis in the measurement) (see 632), then the state of controller 105 may transition to state 608, in which controller 105 increments the DCP code to increase the PWM DC. If the PWM DC is decreasing or stuck below the target PWM DC, controller 105 may also increment the DCP code (see 637). If the PWM DC has increased, or the PWM DC is greater than the target PWM DC (taking into account any hysteresis in the measurement) (see 634), then the state of controller 105 may transition to state 606, in which controller 105 decrements the DCP code to decrease the PWM DC. If the PWM DC is increasing or stuck above the target PWM DC, controller 105 may also decrement the DCP code (see 639). Depending on whether the PWM DC is greater than the target PWM DC (taking into account any hysteresis in the measurement) (see 636), or whether the PWMDC is less than the target PWM DC (taking into account any hysteresis in the measurement) (see 638), the state of controller 105 may also transition between states 606 and 608. Once approaching the desired target COMP, the state of controller 105 may switch between states 606 and 608 as controller 105 switches between adjacent DCP codes to maintain the desired target COMP voltage and V LXSignal duty cycle (e.g., 50%).

[0050] The embodiments can be further described using the following clauses:

[0051] 1. A control circuit for controlling a pulse width modulation (PWM) signal of a multilevel converter, wherein the multilevel converter is capable of operating in a charge pump mode through open-loop control and operating in a regulation mode through closed-loop control, the control circuit comprising:

[0052] A compensation signal generation circuit configured to generate a compensation signal; and

[0053] A PWM circuit configured to: when the multilevel converter operates in the charge pump mode, generate a PWM signal with a target duty cycle based on the compensation signal, and the PWM signal with the target duty cycle is used to control the multilevel converter during a mode change from the charge pump mode to the regulation mode.

[0054] 2. The control circuit according to clause 1, wherein the compensation signal generation circuit comprises:

[0055] A resistor divider circuit configured to receive an output voltage signal from the multilevel converter, receive a digital code, and divide the output voltage signal to obtain a feedback signal of a voltage based on the digital code; and

[0056] A transconductance amplifier having a first input receiving a reference voltage signal and a second input receiving the feedback signal from the resistor divider circuit, and the transconductance amplifier is configured to generate the compensation signal based on the feedback signal.

[0057] 3. The control circuit according to clause 1, wherein the compensation signal generation circuit comprises:

[0058] A resistor divider circuit configured to receive an output voltage signal from the multilevel converter and divide the output voltage signal to obtain a feedback signal; and

[0059] A transconductance amplifier having a first input receiving a signal of an adjustable voltage and a second input receiving the feedback signal, and the transconductance amplifier is configured to generate the compensation signal based on the adjustable voltage signal.

[0060] 4. A control circuit according to claim 1, wherein the compensation signal generating circuit includes an analog circuit for providing the compensation signal at a target voltage, the analog circuit having a first input for receiving a signal of the target voltage and a second input for receiving a loopback signal from an output of the analog circuit, and the analog circuit is configured to generate the compensation signal based on the signal of the target voltage.

[0061] 5. The control circuit of any one of clauses 1 to 4, wherein, when the multilevel converter operates in a voltage regulation mode, the PWM circuit is configured to generate a PWM signal having the target duty cycle based on a sawtooth wave signal and the compensation signal.

[0062] 6. The control circuit of any one of clauses 1 to 4, wherein, when the multilevel converter operates in a current regulation mode, the PWM circuit is configured to generate a PWM signal having the target duty cycle through slope compensation based on a triangular wave signal and the compensation signal.

[0063] 7. The control circuit according to any one of clauses 1 to 6, further comprising:

[0064] A voltage level control circuit, the voltage level control circuit being configured to:

[0065] receiving the PWM signal from the PWM circuit; and

[0066] Based on the PWM signal, a plurality of level control signals are generated for controlling the multi-level converter to:

[0067] operating in the charge pump mode through open loop control and providing an output voltage signal at one of a plurality of voltage levels; or

[0068] The device operates in the regulation mode through closed-loop control and provides the output voltage signal of a variable voltage.

[0069] 8. The control circuit of clause 7, wherein:

[0070] The multilevel converter operates at a 50% duty cycle in the charge pump mode to provide the output voltage signal; or

[0071] The multi-level converter operates with an adjustable duty cycle in the regulation mode to provide the output voltage signal.

[0072] 9. The control circuit according to clause 7, wherein the voltage level control circuit is configured to generate the plurality of level control signals having a fixed duty cycle for controlling the multilevel converter in the charge pump mode to provide the output voltage signal of one of the plurality of voltage levels, and a first level control signal among the level control signals has a phase shift relative to a second level control signal among the level control signals.

[0073] 10. The control circuit according to clause 7, wherein the voltage level control circuit is configured to generate the plurality of level control signals for controlling the multilevel converter in the regulation mode to provide the output voltage signal having the variable voltage, and the variable voltage is between a first voltage level among the plurality of voltage levels minus a voltage boundary region window value and the first voltage level plus the voltage boundary region window value.

[0074] 11. The control circuit according to clause 10, wherein the multilevel converter operates at a duty cycle between 50% minus a duty cycle boundary region window value and 50% plus the duty cycle boundary region window value.

[0075] 12. A method for controlling a multilevel converter, the method comprising:

[0076] determining a duty cycle of a pulse width modulation (PWM) signal configured to control the multilevel converter;

[0077] determining at least one of the following: whether the duty cycle of the PWM signal decreases, increases, or remains unchanged; or whether the duty cycle of the PWM signal is less than or greater than a target duty cycle;

[0078] in response to determining that the duty cycle of the PWM signal decreases or determining that the duty cycle of the PWM signal is less than the target duty cycle, increasing a parameter to increase the duty cycle of the PWM signal; and

[0079] in response to determining that the duty cycle of the PWM signal increases or determining that the duty cycle of the PWM signal is greater than the target duty cycle, decreasing the parameter to decrease the duty cycle of the PWM signal.

[0080] 13. The method according to clause 12, wherein determining the duty cycle of the PWM signal comprises:

[0081] measuring the PWM signal to obtain a first duty cycle at a first time and a second duty cycle at a second time, the first time and the second time being times when the multilevel converter is in the charge pump mode; and

[0082] The duty cycle of the PWM signal is determined based on the first duty cycle and the second duty cycle.

[0083] 14. A method according to clause 12 or 13, wherein:

[0084] Determining whether the duty cycle of the PWM signal is less than the target duty cycle includes determining whether the duty cycle of the PWM signal is less than the target duty cycle minus a hysteresis value; and

[0085] Determining whether the duty cycle of the PWM signal is greater than the target duty cycle includes determining whether the duty cycle of the PWM signal is greater than the target duty cycle plus the hysteresis value.

[0086] 15. The method of clause 12, wherein the duty cycle of the PWM signal is the first duty cycle of the PWM signal, the method further comprising:

[0087] After determining at least one of whether the first duty cycle of the PWM signal is decreased, increased, or unchanged, or whether the first duty cycle of the PWM signal is less than a target duty cycle or greater than the target duty cycle:

[0088] determining a second duty cycle of the PWM signal;

[0089] determining at least one of: whether the second duty cycle of the PWM signal decreases, increases, or remains unchanged, or whether the second duty cycle of the PWM signal is less than the target duty cycle or greater than the target duty cycle;

[0090] In response to determining that the second duty cycle of the PWM signal is reduced or determining that the second duty cycle of the PWM signal is less than the target duty cycle, increasing the parameter to increase the duty cycle of the PWM signal; and

[0091] In response to determining that the second duty cycle of the PWM signal increases or determining that the second duty cycle of the PWM signal is greater than the target duty cycle, the parameter is decreased to reduce the duty cycle of the PWM signal.

[0092] 16. The method of any of clauses 12 to 15, wherein the target duty cycle is 50%.

[0093] 17. A system for reducing transients during a change in power conversion mode, the system comprising:

[0094] a multilevel converter configured to operate in a charge pump mode or a regulation mode to provide an output voltage signal; and

[0095] A control circuit, the control circuit being configured to:

[0096] control the multilevel converter to operate in the charge pump mode with a 50% duty cycle through open-loop control, or control it to operate with a variable duty cycle in the regulation mode through closed-loop control; and

[0097] when the multilevel converter operates in the charge pump mode, generate a pulse width modulation (PWM) signal with a target duty cycle, and the PWM signal with the target duty cycle is used to control the multilevel converter during a mode change from the charge pump mode to the regulation mode.

[0098] 18. The system according to clause 17, wherein the control circuit includes:

[0099] a compensation signal generation circuit configured to generate a compensation signal for generating the PWM signal; and

[0100] a PWM circuit configured to generate the PWM signal with the target duty cycle based on the compensation signal.

[0101] 19. The system according to clause 18, wherein the compensation signal generation circuit includes:

[0102] a resistor divider circuit configured to receive the output voltage signal from the multilevel converter, receive a digital code, and divide the output voltage signal to obtain a feedback signal with a voltage based on the digital code; and

[0103] a transconductance amplifier having a first input for receiving a signal of a reference voltage and a second input for receiving the feedback signal from the resistor divider circuit, and the transconductance amplifier being configured to generate the compensation signal based on the feedback signal.

[0104] 20. The system according to clause 18, wherein the compensation signal generation circuit includes:

[0105] a resistor divider circuit configured to receive the output voltage signal from the multilevel converter and divide the output voltage signal to obtain a feedback signal; and

[0106] a transconductance amplifier having a first input for receiving a signal of an adjustable voltage and a second input for receiving the feedback signal, and the transconductance amplifier being configured to generate the compensation signal based on the signal of the adjustable voltage.

[0107] 21. A system for reducing transients during mode changes in a multilevel converter of a switched capacitor circuit, comprising:

[0108] A switched capacitor-based converter;

[0109] A control circuit for controlling the switched capacitor-based converter, the control circuit being capable of open-loop and closed-loop control of the switched capacitor-based converter;

[0110] Wherein, during open-loop control, the control circuit is configured to control the duty cycle of the switching state transition at about 50% by using feedback from the output of the switched capacitor-based converter.

[0111] The terms used in this specification generally have their ordinary meanings in the art and in the particular context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely illustrative and in no way limits the scope and meaning of the present disclosure or any exemplary term. Similarly, the present disclosure is not limited to the various embodiments given herein.

[0112] Although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0113] For ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0114] In the present disclosure, the term "coupled" may also be referred to as "electrically coupled", and the term "connected" may be referred to as "electrically connected". "Coupled" and "connected" may also be used to indicate that two or more elements cooperate or interact with each other.

[0115] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will recognize that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A control circuit for controlling a pulse width modulation (PWM) signal of a multilevel converter, wherein, The multilevel converter is capable of operating in a charge pump mode through open-loop control and in a regulation mode through closed-loop control. The control circuit includes: a compensation signal generation circuit configured to generate a compensation signal; and a PWM circuit configured to: when the multilevel converter operates in the charge pump mode, generate a PWM signal with a target duty cycle based on the compensation signal, and the PWM signal with the target duty cycle is used to control the multilevel converter during a mode change from the charge pump mode to the regulation mode.

2. The control circuit according to claim 1, wherein, The compensation signal generation circuit includes: a resistor divider circuit configured to: receive an output voltage signal from the multilevel converter, receive a digital code, and divide the output voltage signal to obtain a feedback signal having a voltage based on the digital code; and a transconductance amplifier that has a first input receiving a reference voltage signal and a second input receiving the feedback signal from the resistor divider circuit, and is configured to generate the compensation signal based on the feedback signal.

3. The control circuit according to claim 1, wherein, The compensation signal generation circuit includes: a resistor divider circuit configured to: receive an output voltage signal from the multilevel converter, and divide the output voltage signal to obtain a feedback signal; and a transconductance amplifier that has a first input receiving a signal of an adjustable voltage and a second input receiving the feedback signal, and is configured to generate the compensation signal based on the signal of the adjustable voltage.

4. The control circuit according to claim 1, wherein, The compensation signal generation circuit includes: an analog circuit for providing the compensation signal at a target voltage, the analog circuit has a first input for receiving a signal of the target voltage and a second input for receiving a loopback signal from the output of the analog circuit, and is configured to generate the compensation signal based on the signal of the target voltage.

5. The control circuit according to any one of claims 1 to 4, wherein, When the multilevel converter operates in a voltage regulation mode, the PWM circuit is configured to generate a PWM signal with the target duty cycle based on a sawtooth wave signal and the compensation signal.

6. The control circuit according to any one of claims 1 to 4, wherein, When the multilevel converter operates in a current regulation mode, the PWM circuit is configured to generate a PWM signal with the target duty cycle based on a triangular wave signal and the compensation signal through slope compensation.

7. The control circuit according to any one of claims 1 to 6, further comprising: a voltage level control circuit configured to: receive the PWM signal from the PWM circuit; and generate a plurality of level control signals based on the PWM signal, for controlling the multilevel converter to: operate in the charge pump mode through open-loop control and provide an output voltage signal of one of a plurality of voltage levels; or operate in the regulation mode through closed-loop control and provide the output voltage signal of a variable voltage.

8. The control circuit according to claim 7, wherein: The multi-level converter operates at a 50% duty cycle in the charge pump mode to provide the output voltage signal; or The multi-level converter operates at an adjustable duty cycle in the regulation mode to provide the output voltage signal.

9. The control circuit according to claim 7, wherein, The voltage level control circuit is configured to generate the plurality of level control signals having a fixed duty cycle for controlling the multi-level converter in the charge pump mode to provide the output voltage signal of one voltage level among the plurality of voltage levels, and a first level control signal among the level control signals has a phase shift relative to a second level control signal among the level control signals.

10. The control circuit according to claim 7, wherein, The voltage level control circuit is configured to generate the plurality of level control signals for controlling the multi-level converter in the regulation mode to provide the output voltage signal having the variable voltage, and the variable voltage is between a first voltage level among the plurality of voltage levels minus a voltage boundary zone window value and the first voltage level plus the voltage boundary zone window value.

11. The control circuit according to claim 10, wherein, The multi-level converter operates at a duty cycle between 50% minus a duty cycle boundary zone window value and 50% plus the duty cycle boundary zone window value.

12. A method for controlling a multi-level converter, the method comprising: Determining a duty cycle of a pulse width modulation (PWM) signal configured to control the multi-level converter; Determining at least one of the following: Whether the duty cycle of the PWM signal decreases, increases, or remains unchanged; or Whether the duty cycle of the PWM signal is less than or greater than a target duty cycle; In response to determining that the duty cycle of the PWM signal decreases or determining that the duty cycle of the PWM signal is less than the target duty cycle, increasing a parameter to increase the duty cycle of the PWM signal; and In response to determining that the duty cycle of the PWM signal increases or determining that the duty cycle of the PWM signal is greater than the target duty cycle, decreasing the parameter to decrease the duty cycle of the PWM signal.

13. The method according to claim 12, wherein Determining the duty cycle of the PWM signal includes: Measuring the PWM signal to obtain a first duty cycle at a first time and a second duty cycle at a second time, where the first time and the second time are times when the multi-level converter is in the charge pump mode; and Determining the duty cycle of the PWM signal based on the first duty cycle and the second duty cycle.

14. The method according to claim 12 or 13, wherein: Determining whether the duty cycle of the PWM signal is less than the target duty cycle includes determining whether the duty cycle of the PWM signal is less than the target duty cycle minus a hysteresis value; and Determining whether the duty cycle of the PWM signal is greater than the target duty cycle includes determining whether the duty cycle of the PWM signal is greater than the target duty cycle plus the hysteresis value.

15. The method according to claim 12, wherein The duty cycle of the PWM signal is a first duty cycle of the PWM signal, and the method further includes: After determining whether the first duty cycle of the PWM signal is decreasing, increasing, or remaining unchanged, or whether the first duty cycle of the PWM signal is less than or greater than a target duty cycle by at least one of the following: Determine the second duty cycle of the PWM signal; Determine at least one of the following: Whether the second duty cycle of the PWM signal is decreasing, increasing, or remaining unchanged, or Whether the second duty cycle of the PWM signal is less than or greater than the target duty cycle; In response to determining that the second duty cycle of the PWM signal is decreasing or determining that the second duty cycle of the PWM signal is less than the target duty cycle, increase the parameter to increase the duty cycle of the PWM signal; and In response to determining that the second duty cycle of the PWM signal is increasing or determining that the second duty cycle of the PWM signal is greater than the target duty cycle, decrease the parameter to decrease the duty cycle of the PWM signal.

16. The method according to any one of claims 12 to 15, wherein, The target duty cycle is 50%.

17. A system for reducing transients during a change in power conversion mode, the system comprising: A multilevel converter configured to operate in a charge pump mode or a regulation mode to provide an output voltage signal; And A control circuit configured to: Control the multilevel converter to operate in the charge pump mode at a 50% duty cycle by open-loop control or at a variable duty cycle in the regulation mode by closed-loop control; And When the multilevel converter is operating in the charge pump mode, generate a pulse width modulation (PWM) signal having a target duty cycle, and the PWM signal having the target duty cycle is used to control the multilevel converter during a mode change from the charge pump mode to the regulation mode.

18. The system according to claim 17, wherein, The control circuit includes: A compensation signal generation circuit configured to generate a compensation signal for generating the PWM signal; and A PWM circuit configured to generate the PWM signal having the target duty cycle based on the compensation signal.

19. The system according to claim 18, wherein, The compensation signal generation circuit includes: A resistor divider circuit configured to: Receive the output voltage signal from the multilevel converter, Receive a digital code, and Divide the output voltage signal to obtain a feedback signal having a voltage based on the digital code; and A transconductance amplifier Having a first input for receiving a signal of a reference voltage and a second input for receiving the feedback signal from the resistor divider circuit, and Configured to generate the compensation signal based on the feedback signal.

20. The system according to claim 18, wherein The compensation signal generation circuit includes: A resistor divider circuit configured to: Receive the output voltage signal from the multilevel converter, and Divide the output voltage signal to obtain a feedback signal; and A transconductance amplifier Having a first input for receiving a signal of an adjustable voltage and a second input for receiving the feedback signal, and configured to generate the compensation signal based on the signal of the adjustable voltage.

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